Semiconductor device and method of manufacturing the same
By designing semiconductor devices with active regions and trenches within the substrate, the gate structure is located within the trench, increasing the channel length/width. This solves the problem of excessively large transistor area, improves chip integration, and reduces parasitic capacitance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-02-05
- Publication Date
- 2026-07-24
AI Technical Summary
In the existing technology, long/wide channel transistors occupy most of the area on the chip, which limits the chip integration and makes it impossible to reduce the area of the transistor while ensuring the channel length/width.
An active region and a trench are formed in the substrate. The gate structure is located in the trench and extends upward to above the top surface of the trench. The gate sidewalls are located on the steps. The source and drain regions are located in the active regions on both sides of the gate structure. The inclined trench design increases the channel length/width and reduces the device area.
While maintaining the channel length/width, the device area was reduced, the chip integration was improved, and the parasitic capacitance was decreased.
Smart Images
Figure CN121665621B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its fabrication method. Background Technology
[0002] As computing power demands increase, the number of transistors required in chips also increases. Therefore, it becomes increasingly important to fit more transistors into a limited chip area, which necessitates further miniaturization of transistors.
[0003] For chips used in specific applications, long / wide channel transistors are used for driving. These transistors occupy most of the chip area, which poses a challenge to chip integration. How to reduce the area of the transistor while ensuring the length / width of the channel is an urgent problem to be solved. Summary of the Invention
[0004] In view of this, the embodiments of this application aim to provide a semiconductor device and a method for fabricating the same, so as to solve the problem in the prior art that it is impossible to reduce the area of the transistor while ensuring the length / width of the channel.
[0005] This application provides a semiconductor device, including:
[0006] A substrate having an active region and a trench therein, the active region extending from the surface of the substrate into the substrate, and the trench extending from the surface of the active region into the active region;
[0007] A gate structure includes a gate oxide layer, a gate conductive layer, and a gate sidewall. The gate conductive layer is located on the gate oxide layer. The gate oxide layer covers the sidewalls and bottom surface of the gate conductive layer. The gate oxide layer and the gate conductive layer fill the trench and extend upward to a surface higher than the top surface of the trench. The portion of the sidewall of the gate oxide layer above the trench has a step, and the gate sidewall is located at least on the step.
[0008] The source / drain regions are located within the active regions on both sides of the gate structure.
[0009] In some embodiments, the trench is part of a sigma trench, and the width of the trench gradually decreases in the direction close to the active region so that the sidewalls of the trench are inclined.
[0010] In some embodiments, the inclination angle of the sidewalls of the trench is 45°C to 52°C.
[0011] In some embodiments, the sidewalls of the gate conductive layer are tilted, and the tilt angle of the sidewalls of the gate conductive layer is the same as the tilt angle of the sidewalls of the trench.
[0012] In some embodiments, the bottom surface of the step is flush with the top surface of the substrate, the top surface of the step is flush with the top surface of the gate conductive layer, and the top surface of the gate sidewall is in direct contact with the top surface of the gate conductive layer.
[0013] In some embodiments, the gate sidewall is located on the step and extends laterally from the step to the substrate.
[0014] This application also provides a method for fabricating a semiconductor device, comprising:
[0015] A trench and an active region are formed within a substrate, the active region extending from the surface of the substrate into the substrate, and the trench extending from the surface of the active region into the active region;
[0016] A gate structure is formed on the substrate. The gate structure includes a gate oxide layer, a gate conductive layer, and gate sidewalls. The gate conductive layer is located on the gate oxide layer. The gate oxide layer covers the sidewalls and bottom surface of the gate conductive layer. The gate oxide layer and the gate conductive layer fill the trench and extend upward to a point above the top surface of the trench. The portion of the sidewall of the gate oxide layer above the trench has a step, and the gate sidewall is located at least on the step.
[0017] Source and drain regions are formed in the active regions on both sides of the gate structure.
[0018] In some embodiments, the step of forming the trench and the active region within the substrate includes:
[0019] The substrate is etched to form sigma trenches within the substrate;
[0020] A sacrificial layer is filled within the sigma groove;
[0021] The sacrificial layer is etched back until the top surface of the sacrificial layer is flush with the inflection point of the sidewall of the sigma groove;
[0022] Perform a planarization process until the top surface of the substrate is flush with the top surface of the sacrificial layer, and the remaining portion of the sigma trench forms the trench.
[0023] Remove the sacrificial layer; and,
[0024] Ion implantation is performed on the substrate to form the active region within the substrate.
[0025] In some embodiments, after the sacrificial layer is filled into the sigma groove and before the sacrificial layer is etched back, the fabrication method further includes:
[0026] A planarization process is performed to remove a portion of the thickness of the substrate and the sacrificial layer, and the top surface of the substrate and the sacrificial layer is controlled to be higher than the inflection point of the sidewall of the sigma trench.
[0027] In some embodiments, the step of forming the gate structure on the substrate includes:
[0028] The gate oxide layer and the gate conductive layer are sequentially formed on the substrate, and the gate oxide layer and the gate conductive layer sequentially cover the substrate and fill the trench;
[0029] A planarization process is performed to remove a portion of the thickness of the gate conductive layer until a portion of the surface of the gate oxide layer is exposed.
[0030] Etching to remove the exposed portion of the gate oxide layer, and forming a step on the portion of the gate oxide layer's sidewalls above the trench; and,
[0031] The gate sidewall is formed on the step.
[0032] This application provides a semiconductor device and a method for fabricating the same, comprising: a substrate having an active region and a trench therein, the active region extending from the surface of the substrate into the substrate, and the trench extending from the surface of the active region into the active region; a gate structure including a gate oxide layer, a gate conductive layer, and a gate sidewall, the gate conductive layer being located on the gate oxide layer, the gate oxide layer enclosing the sidewalls and bottom surface of the gate conductive layer, the gate oxide layer and the gate conductive layer filling the trench and extending upward to a surface higher than the top surface of the trench, the sidewall of the gate oxide layer having a step at the portion above the trench, and the gate sidewall being located at least on the step; and source / drain regions located within the active regions on both sides of the gate structure. An unexpected effect of this application is that by placing the gate structure within the trench, the length / width of the channel can be increased, thereby increasing the control capability of the gate structure over the channel, while not excessively increasing the device area. This reduces the device area and improves chip integration while maintaining the channel length / width. Furthermore, placing the gate sidewall on the step serves two purposes: firstly, the gate sidewall protects the gate oxide layer, preventing direct bombardment of the gate oxide layer during source / drain ion implantation; secondly, the gate sidewall increases the distance between the source / drain region and the gate conductive layer, thereby reducing parasitic capacitance. Attached Figure Description
[0033] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.
[0034] Figure 2This is a schematic diagram of an etched substrate provided in an embodiment of the present application to form sigma trenches within the substrate.
[0035] Figure 3 This is a schematic diagram of a structure in which a sacrificial layer is filled in a sigma trench, according to an embodiment of this application.
[0036] Figure 4 This is a schematic diagram of a structure with a portion of the thickness of the substrate and sacrificial layer removed, provided in an embodiment of this application.
[0037] Figure 5 This is a schematic diagram of the structure of the etch-back sacrificial layer provided in an embodiment of this application.
[0038] Figure 6 This is a schematic diagram of the structure provided in an embodiment of the present application, showing the top surface of the polishing substrate until the top surface of the substrate is flush with the top surface of the sacrificial layer.
[0039] Figure 7 This is a schematic diagram of the structure after removing the sacrificial layer according to an embodiment of this application.
[0040] Figure 8 This is a schematic diagram of an active region formed in a substrate according to an embodiment of this application.
[0041] Figure 9 This is a schematic diagram of a structure in which a gate oxide layer and a gate conductive layer are sequentially formed on a substrate, according to an embodiment of this application.
[0042] Figure 10 This is a schematic diagram of a structure provided in an embodiment of the present application for grinding the gate conductive layer to remove part of the thickness of the gate conductive layer.
[0043] Figure 11 This is a schematic diagram of a structure provided in an embodiment of the present application for etching to remove the exposed portion of the gate oxide layer.
[0044] Figure 12 This is a schematic diagram of a structure in which a first sub-sidewall and a second sub-sidewall are sequentially formed on a substrate, according to an embodiment of this application.
[0045] Figure 13 This is a schematic diagram of the structure of etching the first sub-sidewall and the second sub-sidewall provided in an embodiment of this application.
[0046] Figure 14 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.
[0047] Figure 15 This is a schematic diagram of the outline of three channels provided in one embodiment of this application.
[0048] The attached figures are labeled as follows:
[0049] 100 - Substrate; 101 - Active region; 101a - sigma trench; 101b - Trench; 111 - Source / drain region; 200 - Mask layer; 300 - Sacrificial layer; 400 - Gate structure; 401 - Gate oxide layer; 402 - Gate conductive layer; 411 - Step; 403 - Gate sidewall; 413 - First sub-sidewall; 423 - Second sub-sidewall. Detailed Implementation
[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0051] This application provides a semiconductor device. Figure 14 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application, as shown below. Figure 14 As shown, the semiconductor device includes a substrate 100, a gate structure 400, and source / drain regions 111.
[0052] Specifically, the substrate 100 can be made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc., and can also be an organic semiconductor material or other semiconductor materials known in the art. The substrate 100 has an active region 101 and a trench 101b. The active region 101 extends from the surface of the substrate 100 into the interior of the substrate 100, and the trench 101b extends from the surface of the active region 101 into the interior of the active region 101. A trench isolation structure can be formed in the substrate 100. Figure 14 (Not shown in the diagram) A trench isolation structure extends from the substrate 100 into the substrate 100 to define an active region 101 within the substrate 100, such that adjacent active regions 101 are isolated by the trench isolation structure. The top of the trench isolation structure may be higher than or flush with the surface of the substrate 100. The material of the trench isolation structure is silicon oxide, but this is not a limitation. In other embodiments, the trench isolation structure may also be other dielectric materials, such as high-k dielectrics like metal oxides.
[0053] In some embodiments, the thickness of the active region 101 is equal at all locations, that is, the morphology of the active region 101 is consistent with the morphology of the substrate 100 surface, so that the depth of the active region 101 below the trench 101b is also deep enough to reduce the probability of leakage.
[0054] Further, the gate structure 400 includes a gate oxide layer 401, a gate conductive layer 402, and a gate sidewall 403. The gate conductive layer 402 is located on the gate oxide layer 401, and the gate oxide layer 401 covers the sidewalls and bottom surface of the gate conductive layer 402. The gate oxide layer 401 and the gate conductive layer 402 together fill the trench 101b and extend upwards to a surface higher than the top surface of the trench 101b. Figure 14 As can be seen, the gate oxide layer 401 is roughly U-shaped and covers the inner wall of the trench 101b. The gate oxide layer 401 is located entirely within the trench 101b, but its two ends extend upwards to a height above the top surface of the trench 101b. The gate conductive layer 402 fills the U-shaped opening of the gate oxide layer 401. The gate oxide layer 401 and the gate conductive layer 402 together fill the trench 101b, and both are higher than the top surface of the trench 101b.
[0055] It should be noted that, Figure 14 The illustration shows an embodiment in which the gate oxide layer 401 fills the trench 101b and the gate conductive layer 402 is located above the trench 101b. In other embodiments, the gate oxide layer 401 may not completely fill the trench 101b. In this case, the gate conductive layer 402 may be partially located inside the trench 101b and partially located above the trench 101b.
[0056] It is understood that in this application, the area at the junction of the active region 101 and the trench 101b is the channel. The length / width of the channel depends on the length of the junction between the trench 101b and the active region 101, that is, the sum of the length L1 of the bottom surface of the trench 101b and the length L2 of the two sidewalls of the trench 101b. By placing the gate structure 400 in the trench 101b, the length / width of the channel can be increased, thereby increasing the control capability of the gate structure 400 over the channel, while not increasing the area of the device too much. Thus, the area of the device is reduced while ensuring the length / width of the channel, and the chip integration is improved.
[0057] In some embodiments, the gate oxide layer may be made of dielectric materials such as silicon oxide or silicon oxynitride, and its thickness may be 300 angstroms to 500 angstroms, but should not be limited thereto; the gate conductive layer 402 may be made of conductive materials such as polysilicon or metal, and its thickness may be 300 angstroms to 500 angstroms, but should not be limited thereto.
[0058] Please continue reading. Figure 14The sidewall of the gate oxide layer 401 above the trench 101b has a step 411, and the gate sidewall 403 is located at least on the step 411. Specifically, since the gate oxide layer 401 is generally U-shaped and extends upward at both ends above the top surface of the trench 101b, the portion of the gate oxide layer 401 above the trench 101b is actually the portion of the sidewall of the gate oxide layer 401 outside the trench 101b. The presence of the step 411 makes the outer contour of the portion of the sidewall of the gate oxide layer 401 above the trench 101b L-shaped. The gate sidewall 403 is located on the step 411 and covers the bottom surface and sidewall of the step 411. Understandably, by placing the gate sidewall 403 on the step 411, on the one hand, the gate sidewall 403 can protect the gate oxide layer 401 and prevent the gate oxide layer 401 from being directly bombarded during source / drain ion implantation; on the other hand, the gate sidewall 403 can increase the distance between the source / drain region 111 and the gate conductive layer 402, thereby reducing parasitic capacitance.
[0059] In some embodiments, the gate sidewall 403 is located on step 411 and extends laterally from step 411 onto substrate 100. This can further increase the distance between source / drain regions 111 and gate conductive layer 402, thereby further reducing parasitic capacitance.
[0060] In some embodiments, the bottom surface of step 411 may be flush with the top surface of substrate 100, and the top surface of step 411 may be flush with the top surface of gate conductive layer 402. Furthermore, the top surface of gate sidewall 403 is in direct contact with the top surface of gate conductive layer 402. Figure 14 As can be seen, the gate sidewall 403 can completely cover the gate oxide layer 401, preventing the gate oxide layer 401 from being exposed, thereby achieving a better protection effect for the gate oxide layer 401.
[0061] Further, the gate sidewall 403 includes a first sub-sidewall 413 and a second sub-sidewall 423. The first sub-sidewall 413 has the same shape as the step 411, both being L-shaped, to conformally cover the bottom surface and sidewalls of the step 411. The second sub-sidewall 423 is located on the first sub-sidewall 413. In some embodiments, the material of the first sub-sidewall 413 can be a dielectric material such as silicon oxide, silicon oxynitride, or silicon oxycarbide, and the thickness can be 50 angstroms to 100 angstroms; the material of the second sub-sidewall 423 can be a dielectric material such as silicon nitride, and the thickness can be 100 angstroms to 150 angstroms.
[0062] Please continue reading. Figure 14The source / drain regions 111 are located within the active regions 101 on both sides of the gate structure 400. The type of doped ions in the source / drain regions 111 can be consistent with the type of transistor to be formed. For example, when the semiconductor device is an NMOS transistor, the doped ions in the source / drain regions 111 can be one or more N-type ions selected from P, As, or Sb; when the semiconductor device is a PMOS transistor, the doped ions in the source / drain regions 111 can be one or more P-type ions selected from B, Ga, or In.
[0063] In some embodiments, trench 101b is a portion of a sigma trench (specifically, the portion below the inflection point of the sidewall of the sigma trench), and the width of trench 101b gradually decreases along the direction approaching the active region 101, so that the sidewall of trench 101b is inclined, from Figure 14 As can be seen, trench 101b has an inverted trapezoidal structure that is wider at the top and narrower at the bottom. When the sidewalls of trench 101b are tilted, the sidewalls of gate conductive layer 402 also tilt accordingly, and the tilt angle of gate conductive layer 402 is the same as the tilt angle of the sidewalls of trench 101b. The increased length L2 of the sidewalls of trench 101b increases the length / width of the channel without significantly increasing the device area. This allows for increased control of the channel by gate structure 400 (or reduced device area while maintaining the same control capability of gate structure 400 over the channel), thus improving chip integration.
[0064] In some embodiments, the inclination angle α of the sidewall of the trench 101b can be 45°~52°, the length L1 of the bottom surface of the trench 101b can be 400nm~500nm, the length L2 of the sidewall of the trench 101b can be 40nm~50nm, and the depth of the trench 101b can be 300nm~500nm, but should not be limited thereto.
[0065] Figure 15 This is a schematic diagram showing the outlines of three types of channels provided in one embodiment of this application. For example... Figure 15 As shown, when the sidewalls of trench 101b are inclined, compared to not having trench 101b or having the sidewalls of trench 101b vertically (vertical sidewalls are extremely difficult to form and are rarely used in actual products), the thickness and area of the device are more balanced, and the overall device size is more advantageous. Assuming the inclination angle α of the sidewalls of trench 101b is 45°, L1 = 600nm, and L2 = 50nm, approximately 5% of the area can be saved compared to not having trench 101b.
[0066] Based on this, one embodiment of this application also provides a method for fabricating a semiconductor device. Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application is shown below. Figure 1 As shown, the method for fabricating a semiconductor device includes:
[0067] Step S100: A trench 101b and an active region 101 are formed in the substrate 100. The active region 101 extends from the surface of the substrate 100 into the substrate 100, and the trench 101b extends from the surface of the active region 101 into the active region 101.
[0068] Step S200: A gate structure 400 is formed on the substrate 100. The gate structure 400 includes a gate oxide layer 401, a gate conductive layer 402, and a gate sidewall 403. The gate conductive layer 402 is located on the gate oxide layer 401. The gate oxide layer 401 covers the sidewalls and bottom surface of the gate conductive layer 402. The gate oxide layer 401 and the gate conductive layer 402 fill the trench 101b and extend upward to a surface higher than the top surface of the trench 101b. The portion of the sidewall of the gate oxide layer 401 above the trench 101b has a step 411. The gate sidewall 403 is located at least on the step 411.
[0069] Step S300: Source and drain regions 111 are formed in the active regions 101 on both sides of the gate structure 400.
[0070] Figures 2-14 This is a schematic diagram of the structure corresponding to the respective steps of the method for fabricating a semiconductor device according to an embodiment of this application. Next, we will combine... Figures 2-14 The method for fabricating the semiconductor device provided in this application is described in detail.
[0071] like Figure 2 As shown, step S100 is first performed to provide a substrate 100. The material of the substrate 100 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc., or it can be an organic semiconductor material or other semiconductor materials known in the art.
[0072] like Figures 2-7 As shown, a trench 101b is formed in the substrate 100.
[0073] Specifically, such as Figure 2 As shown, a mask layer 200 is formed on the substrate 100, and the mask layer 200 is patterned using photolithography and etching processes. The material of the mask layer 200 can be silicon nitride, and the thickness can be 200 angstroms to 500 angstroms.
[0074] Next, the patterned mask layer 200 is used as a mask to etch the substrate 100 to form a sigma trench 101a in the substrate 100. The sigma trench 101a extends downward from the surface of the substrate 100 into the substrate 100. Specifically, a dry etching process can be used to etch the substrate 100 first to form the initial shape of the sigma groove 101a. The initial shape of the sigma groove 101a can be U-shaped, bowl-shaped, saucer-shaped, rectangular, or inverted trapezoidal, etc. Then, a wet etching process is used to continue etching downwards along the bottom of the sigma groove 101a. The etchant in the wet etching process flows into the sigma groove 101a, continuing to etch the substrate 100 within the sigma groove 101a. Because the etchant in the wet etching process is selective for crystal orientation, the shape and size of the sigma groove 101a will change after etching, forming the final shape of the sigma groove 101a, which is a sigma shape (also known as a Σ shape or diamond shape). In some embodiments, the etchant used in the wet etching process on the substrate 100 can be tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH). <111> The etching rate of the crystal orientation is lower than that of other crystal orientations. After etching is completed, the sigma groove 101a forms its final shape.
[0075] Please continue reading. Figure 2 After forming the sigma groove 101a, the length L1 of the bottom of the sigma groove 101a can be 400nm~600nm, the depth of the sigma groove 101a can be 500 angstroms~700 angstroms, the sidewall of the sigma groove 101a has an inflection point at a height position H, and the part of the sidewall of the sigma groove 101a below the inflection point is inclined, and the inclination angle α is 45°~52°.
[0076] like Figure 3 As shown, a sacrificial layer 300 is filled within the sigma trench 101a. Specifically, the sacrificial layer 300 is deposited within the mask layer 200 and the sigma trench 101a, at which point the sacrificial layer 300 covers the mask layer 200 and fills the sigma trench 101a.
[0077] It should be noted that the sacrificial layer 300 needs to serve as a grinding stop layer in subsequent processes. Therefore, the material of the sacrificial layer 300 can be a material with high hardness, such as silicon nitride. Furthermore, the thickness of the sacrificial layer 300 is preferably greater than the depth of the sigma groove 101a. Thus, after the sacrificial layer 300 is formed, it can fill the sigma groove 101a, which is convenient for subsequent processes. The thickness of the sacrificial layer 300 can be, for example, 900 angstroms to 1200 angstroms.
[0078] like Figure 4As shown, a planarization process is performed to remove a portion of the thickness of the substrate 100 and the sacrificial layer 300, and the top surface of the substrate 100 and the sacrificial layer 300 is controlled to be higher than the inflection point of the sidewall of the sigma trench 101a. Preferably, the planarization process can be stopped only after the mask layer 200 is removed (this can be achieved by controlling the time of the planarization process), thereby removing as much of the sacrificial layer 300 as possible and improving the efficiency of subsequent etching of the sacrificial layer 300.
[0079] from Figure 4 As can be seen, after the planarization process, the top surfaces of the substrate 100 and the sacrificial layer 300 are flush, and both are higher than the height H. It is understood that this step removes a portion of the thickness of the sacrificial layer 300, which can reduce the amount of subsequent etching of the sacrificial layer 300, thereby reducing the process difficulty. In some embodiments, the step of performing the planarization process to remove a portion of the thickness of the substrate 100 and the sacrificial layer 300 can be omitted.
[0080] like Figure 5 As shown, the sacrificial layer 300 is etched back until its top surface is flush with the inflection point of the sidewall of the sigma groove 101a. From Figure 5 As can be seen, after the sacrificial layer 300 is etched back, its top surface is located at height H. It is understandable that, compared to directly using a planarization process to grind the top surface of the sacrificial layer 300 to be flush with the inflection point of the sidewall of the sigma groove 101a, using an etching process allows for precise etching of the sacrificial layer 300 until its top surface is flush with the inflection point of the sidewall of the sigma groove 101a, making the process easier to control.
[0081] It should be noted that when etching back the sacrificial layer 300, the etching amount can be precisely controlled to avoid abnormal morphology of the sidewalls of the subsequently formed trench 101b due to insufficient etching amount. At the same time, excessive etching amount should be avoided to prevent the sidewalls of the subsequently formed trench 101b from becoming shorter.
[0082] like Figure 6 As shown, the planarization process is performed again, grinding the top surface of the substrate 100 until the top surface of the substrate 100 is flush with the top surface of the sacrificial layer 300. At this time, the sacrificial layer 300 can be used as a grinding stop layer, and grinding can stop on the surface of the sacrificial layer 300. After the planarization process is performed, the top surface of the substrate 100 and the top surface of the sacrificial layer 300 are both located at height H. The remaining part of the sigma groove 101a can form the trench 101b. At this time, the trench 101b is still filled by the sacrificial layer 300.
[0083] Understandably, the trench 101b, as part of the sigma trench 101a, has inclined sidewalls. Compared to directly etching the substrate 100 to form a trench 101b with inclined sidewalls, forming the trench 101b by means of the sigma trench 101a can automatically form a trench 101b with inclined sidewalls. The inclination angle α of the sidewall of the trench 101b can be automatically controlled between 45°C and 52°C. The angle α of the sidewall of the trench 101b is easier to control, the process is simpler, and no additional photomask is required, thus saving costs.
[0084] like Figure 7 As shown, the sacrificial layer 300 is removed using a process such as wet etching.
[0085] like Figure 8 As shown, ions are implanted into the substrate 100 using an ion implantation process to form an active region 101 within the substrate 100. The active region 101 extends from the surface of the substrate 100 into the substrate 100, and naturally surrounds the periphery of the trench 101b. When ions are implanted into the substrate 100 using the ion implantation process, the depth of the implanted ions is consistent throughout the entire substrate 100; therefore, the thickness of the active region 101 is equal at all points.
[0086] In some embodiments, the thickness of the active region 101 may be 1500 angstroms to 2000 angstroms, but should not be limited thereto.
[0087] like Figures 9-13 As shown, step S200 is performed to form a gate structure 400 on the substrate 100.
[0088] Specifically, such as Figure 9 As shown, a gate oxide layer 401 and a gate conductive layer 402 are sequentially formed on a substrate 100. The gate oxide layer 401 and the gate conductive layer 402 sequentially cover the substrate 100 and together fill the trench 101b. The thickness of the gate oxide layer 401 and the gate conductive layer 402 needs to be greater than the depth of the trench 101b, so that the top surface of the gate conductive layer 402 is higher than the top surface of the trench 101b. In some embodiments, the semiconductor device can be a high-voltage device, in which case the thickness of the gate oxide layer 401 is relatively thick, which can be 400 angstroms to 600 angstroms, and the thickness of the gate conductive layer 402 can also be 400 angstroms to 600 angstroms.
[0089] like Figure 10 As shown, a planarization process is performed, grinding the gate conductive layer 402 to remove a portion of its thickness until a portion of the surface of the gate oxide layer 401 is exposed. From Figure 10As can be seen, the gate oxide layer 401 at this time has a planar portion and a recessed portion. The recessed portion is recessed relative to the planar portion in the direction toward the substrate 100. After performing the planarization process, the gate conductive layer 402 above the planar portion of the gate oxide layer 401 is removed, while the gate conductive layer 402 in the recessed portion is retained.
[0090] like Figure 11 As shown, etching is used to remove the exposed portion of the gate oxide layer 401, and to form a step 411 on the portion of the sidewall of the gate oxide layer 401 above the trench 101b. Specifically, an anisotropic etching process can be used to etch downwards the planar portion of the gate oxide layer 401 and the recessed portion connected to the planar portion. Due to the strong directionality of the anisotropic etching process, the gate oxide layer 401 will be etched downwards to form the step 411.
[0091] like Figure 12 and Figure 13 As shown, a gate sidewall 403 is formed on step 411.
[0092] Specifically, such as Figure 12 As shown, a first sub-sidewall 413 and a second sub-sidewall 423 are sequentially formed on the substrate 100. The first sub-sidewall 413 and the second sub-sidewall 423 conformally cover the top surface of the substrate 100, the surface of the step 411, and the top surface of the gate conductive layer 402. In some embodiments, the material of the first sub-sidewall 413 may be a dielectric material such as silicon oxide, silicon oxynitride, or silicon oxycarbide, and the thickness may be 50 angstroms to 100 angstroms; the material of the second sub-sidewall 423 may be a dielectric material such as silicon nitride, and the thickness may be 100 angstroms to 150 angstroms.
[0093] like Figure 13 As shown, the first sub-sidewall 413 and the second sub-sidewall 423 are etched to remove the first sub-sidewall 413 and the second sub-sidewall 423 on the gate conductive layer 402 and at least part of the substrate 100, while retaining the first sub-sidewall 413 and the second sub-sidewall 423 on the step 411 to form the gate sidewall 403.
[0094] like Figure 14 As shown, step S300 is performed to implant ions into the active regions 101 on both sides of the gate structure 400 to form source / drain regions 111 within the active regions 101 on both sides of the gate structure 400. From Figure 14As can be seen, the gate sidewall 403 covers the gate oxide layer 401. During ion implantation, the gate sidewall 403 can protect the gate oxide layer 401 and prevent the source and drain ions from directly bombarding the gate oxide layer 401. At the same time, with the barrier of the gate sidewall 403, the source and drain doped ions will not be implanted into the film layer below the gate sidewall 403, and the formed source and drain regions 111 can be further away from the gate structure 400. Therefore, the gate sidewall 403 can increase the distance between the source and drain regions 111 and the gate conductive layer 402, thereby reducing parasitic capacitance.
[0095] In summary, this embodiment provides a semiconductor device and its fabrication method, comprising: a substrate 100 having an active region 101 and a trench 101b therein, the active region 101 extending from the surface of the substrate 100 into the substrate 100, and the trench 101b extending from the surface of the active region 101 into the active region 101; a gate structure 400 including a gate oxide layer 401, a gate conductive layer 402, and a gate sidewall 403, the gate conductive layer 402 being located on the gate oxide layer 401, the gate oxide layer 401 enclosing the sidewalls and bottom surface of the gate conductive layer 402, the gate oxide layer 401 and the gate conductive layer 402 filling the trench 101b and extending upward to a top surface higher than the trench 101b, the portion of the sidewall of the gate oxide layer 401 above the trench 101b having a step 411, and the gate sidewall 403 being located at least on the step 411; and source / drain regions 111 located within the active regions 101 on both sides of the gate structure 400. An unexpected effect of this application is that by placing the gate structure 400 within the trench 101b, the length / width of the channel can be increased, thereby increasing the control capability of the gate structure 400 over the channel, while not excessively increasing the device area. This reduces the device area and improves chip integration while maintaining the length / width of the channel. Furthermore, by placing the gate sidewall 403 on the step 411, on the one hand, the gate sidewall 403 can protect the gate oxide layer 401 and prevent direct bombardment of the gate oxide layer 401 during source / drain ion implantation; on the other hand, the gate sidewall 403 can increase the distance between the source / drain region 111 and the gate conductive layer 402, thereby reducing parasitic capacitance.
[0096] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0097] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.
[0098] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.
[0099] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A trench and an active region are formed within a substrate, the active region extending from the surface of the substrate into the substrate, and the trench extending from the surface of the active region into the active region. The trench is part of a sigma trench, and the width of the trench gradually decreases in the direction close to the active region so that the sidewalls of the trench are inclined. A gate structure is formed on the substrate. The gate structure includes a gate oxide layer, a gate conductive layer, and a gate sidewall. The gate conductive layer is located on the gate oxide layer. The gate oxide layer covers the sidewall and bottom surface of the gate conductive layer. The gate oxide layer and the gate conductive layer fill the trench and extend upward to a surface higher than the top surface of the trench. The portion of the sidewall of the gate oxide layer above the trench has a step. The gate sidewall is located at least on the step. as well as, Source and drain regions are formed in the active regions on both sides of the gate structure; The steps of forming the trench and the active region within the substrate include: The substrate is etched to form sigma trenches within the substrate; A sacrificial layer is filled within the sigma groove; The sacrificial layer is etched back until the top surface of the sacrificial layer is flush with the inflection point of the sidewall of the sigma groove; Perform a planarization process until the top surface of the substrate is flush with the top surface of the sacrificial layer, and the remaining portion of the sigma trench forms the trench. Remove the sacrificial layer; and, Ion implantation is performed on the substrate to form the active region within the substrate.
2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After the sacrificial layer is filled into the sigma groove and before the sacrificial layer is etched back, the preparation method further includes: A planarization process is performed to remove a portion of the thickness of the substrate and the sacrificial layer, and the top surface of the substrate and the sacrificial layer is controlled to be higher than the inflection point of the sidewall of the sigma trench.
3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of forming the gate structure on the substrate includes: The gate oxide layer and the gate conductive layer are sequentially formed on the substrate, and the gate oxide layer and the gate conductive layer sequentially cover the substrate and fill the trench; A planarization process is performed to remove a portion of the thickness of the gate conductive layer until a portion of the surface of the gate oxide layer is exposed. Etching to remove the exposed portion of the gate oxide layer, and forming a step on the portion of the gate oxide layer's sidewalls above the trench; and, The gate sidewall is formed on the step.