Semiconductor device

Abstract

A semiconductor device includes: an active pattern including a plurality of channel patterns in a first region; a gate electrode surrounding the plurality of channel patterns; a doped bottom pattern including a first well region and a second well region in the second region, the first well region having the first conductivity type, the second well region being at the same height as the first well region and having a second conductivity type; a device isolation layer between the active pattern and the doped bottom pattern; a first doped region in the first well region having a dopant concentration of the first conductivity type greater than the dopant concentration of the first conductivity type within the first well region; and a second doped region in the second well region having a dopant concentration of the second conductivity type greater than the dopant concentration of the second conductivity type within the second well region, in which the first doped region and the second doped region are positioned higher than a bottom surface of the device isolation layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are key components in electronic devices used to control or amplify electrical signals, and various types of semiconductor devices can be manufactured. For example, memory devices are primarily used for storing and retrieving data, while non-memory devices can be used to control or amplify electrical signals. As core components of electronic devices, semiconductor devices play a vital role in various fields, such as computers, communication equipment, and consumer electronics.

[0003] With industrial development, the demands for the performance and functionality of electronic devices have increased, thus requiring high-performance semiconductor devices. To meet these requirements, the integration level of semiconductor devices has been increased. Various methods for forming semiconductor devices with excellent performance and improved integration have been investigated. Summary of the Invention

[0004] To address one or more problems (e.g., the problems mentioned above and / or other problems not explicitly described herein), this disclosure provides a semiconductor device with improved electrical characteristics and reliability.

[0005] In order to address one or more problems (e.g., the problems mentioned above and / or other problems not explicitly described herein), this disclosure also provides a semiconductor device with improved design and process freedom.

[0006] According to some example embodiments of this disclosure for solving the above-mentioned technical problems, a semiconductor device may include: an active pattern including a plurality of channel patterns stacked and spaced apart from each other in a first region in a first region; a gate electrode surrounding the plurality of channel patterns; a doped bottom pattern including a first well and a second well region in a second region, the first well having a first conductivity type, and the second well region being at the same height as the first well region and having a second conductivity type; a device isolation layer between the active pattern and the doped bottom pattern in a second direction intersecting the first direction; a first doped region formed in the first well region and having a dopant concentration of a first conductivity type greater than that in the first well region; and a second doped region formed in the second well region and having a dopant concentration of a second conductivity type greater than that in the second well region, wherein the bottom surface of the device isolation layer is positioned at a height corresponding to the bottom surface of the doped bottom pattern, and the first doped region and the second doped region are respectively positioned at a height above the bottom surface of the device isolation layer.

[0007] According to some example embodiments of this disclosure for solving the above-mentioned technical problems, a semiconductor device may include: a lower insulating layer and a lower barrier layer, the lower insulating layer in a first region and the lower barrier layer in a second region; an active pattern including a plurality of channel patterns stacked on the lower insulating layer and spaced apart from each other in a first direction; a gate electrode surrounding the plurality of channel patterns; a source / drain pattern on one side of the plurality of channel patterns; a doped bottom pattern including a first well region and a second well region positioned side by side in a second direction intersecting the first direction on the lower barrier layer; a first doped region formed in the first well region; and a second doped region formed in the second well region, wherein the bottom surface of the lower barrier layer is coplanar with the bottom surface of the lower insulating layer.

[0008] According to some example embodiments of this disclosure for solving the above-mentioned technical problems, a semiconductor device may include: a lower insulating layer and a lower barrier layer, the lower insulating layer in a first region and the lower barrier layer in a second region; an active pattern including a plurality of channel patterns stacked on the lower insulating layer and spaced apart from each other in a first direction; a gate electrode surrounding the plurality of channel patterns; a source / drain pattern on one side of the plurality of channel patterns; a doped bottom pattern including a first well region and a second well region stacked in a second direction intersecting the first direction on the lower barrier layer; a device isolation layer between the active pattern and the doped bottom pattern in the second direction; and a first doped region formed therein. Above the first well region; a second doped region, formed above the second well region and positioned at a height corresponding to the first direction; a first upper contact extending in the first direction on the first doped region; a second upper contact extending in the first direction on the second doped region; an upper wiring and a lower wiring, the upper wiring being at a height higher than the active pattern and the doped bottom pattern, and the lower wiring being at a height lower than the lower insulating layer and the lower barrier layer; a lower source / drain contact positioned on the source / drain pattern through the lower insulating layer and electrically connecting the source / drain pattern and the lower wiring; and a conductive post extending in the first direction and connecting between the upper wiring and the lower wiring.

[0009] According to some example embodiments of this disclosure, the electrical characteristics and reliability of semiconductor devices can be improved.

[0010] According to some example embodiments of this disclosure, design freedom and process freedom in semiconductor devices can be improved. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0012] Figures 2 to 19 This is a cross-sectional view showing an intermediate stage, provided to explain a method for manufacturing a semiconductor device according to some example embodiments.

[0013] Figure 20 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0014] Figure 21 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0015] Figure 22 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0016] Figure 23 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0017] Figure 24 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure. Detailed Implementation

[0018] In the following, semiconductor devices according to some exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0019] Figure 1 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0020] Reference Figure 1 A semiconductor device according to some example embodiments may include a first element disposed in a first region R1 and a second element disposed in a second region R2. The first element and the second element may include active elements that are different from each other. For example, the first element may be a transistor and the second element may be a diode. However, the example embodiments are not limited thereto, and the first element may be disposed in the second region R2 and the second element may be disposed in the first region R1. In some example embodiments, the second element may include a passive element (such as an inductor and a capacitor).

[0021] The semiconductor device according to some example embodiments may include a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, the semiconductor device may include a three-dimensional (3D) multi-stacked semiconductor device referred to as a gate-all-around FET (GAAFET) and a multi-bridge channel FET (MBCFET).

[0022] The semiconductor device may include a lower insulating layer 110, an active pattern AP, a doped bottom pattern DBP, a lower barrier layer 111, a device isolation layer 105, a gate electrode 120, a gate insulating layer 130, a source / drain pattern 150, a gate spacer 170, a first well region WR1, and a second well region WR2.

[0023] A lower insulating layer 110 may be disposed in the first region R1. The lower insulating layer 110 may include oxides, nitrides, oxynitrides, or combinations thereof. For clarity, the lower insulating layer 110 is shown as a single layer, but the example embodiment is not limited thereto. For example, the lower insulating layer 110 may be formed of multiple layers.

[0024] An active pattern AP may be disposed on the lower insulating layer 110. The active pattern AP may include multiple channel patterns stacked in a first direction D1. The first direction D1 may be a direction perpendicular to the top surface of the lower insulating layer 110. The active pattern AP may be disposed spaced apart from adjacent active pattern APs in a second direction D2. The active pattern AP may extend in a third direction D3. The first direction D1 may be a direction intersecting the second direction D2. The third direction D3 may be a direction intersecting the first direction D1 and the second direction D2. In some example embodiments, the active pattern AP may be disposed in a region where a P-type metal-oxide-semiconductor (PMOS) device will be formed. In other example embodiments, the active pattern AP may be disposed in a region where an N-type metal-oxide-semiconductor (NMOS) device will be formed.

[0025] The active pattern AP can be a multi-channel active pattern. The active pattern AP may include multiple channel patterns CP. The multiple channel patterns CP may be disposed on a lower insulating layer 110. For example, the lower insulating layer 110 may be disposed at a height lower than the active pattern AP. The channel patterns CP may be spaced apart from each other in a first direction D1. The first direction D1 may be the thickness direction of the lower insulating layer 110. In some example embodiments, the channel patterns CP may have a nanosheet shape. Figure 1 Four channel patterns CP are shown, but the example embodiment is not limited to this.

[0026] The channel pattern CP may include one of the following as elemental semiconductor materials: silicon (Si), group IV-IV compound semiconductors (e.g., silicon germanium (SiGe)), and group III-V compound semiconductors.

[0027] Gate electrode 120 may extend on lower insulating layer 110 in a third direction D3. Gate electrode 120 may intersect with active pattern AP. Gate electrode 120 may be disposed on lower insulating layer 110. Gate electrode 120 may be spaced apart from adjacent gate electrodes 120 in a second direction D2. Gate electrode 120 may surround a plurality of channel patterns CP. Gate electrode 120 may surround four surfaces of channel pattern CP. For example, gate electrode 120 may surround the top surface, bottom surface, and two side surfaces of channel pattern CP. In this example, the top and bottom surfaces of channel pattern CP may refer to surfaces perpendicular to the first direction D1, and the two side surfaces of channel pattern CP may refer to surfaces perpendicular to the third direction D3.

[0028] The gate electrode 120 may include an upper gate electrode 120_U and a lower gate electrode 120_B. The lower gate electrode 120_B may be disposed between adjacent channel patterns CP in the first direction D1. The lower gate electrode 120_B may be disposed between multiple channel patterns CP, and may be disposed between the lower insulating layer 110 and the lowermost channel pattern CP among the multiple channel patterns CP. The upper gate electrode 120_U may be disposed on the uppermost channel pattern CP among the multiple channel patterns CP.

[0029] According to some example embodiments, the active pattern AP may include multiple channel patterns CP, and the gate electrode 120 may include multiple lower gate electrodes 120_B. For example, the number of lower gate electrodes 120_B may be proportional to the number of channel patterns CP included in the active pattern AP. In this example, the number of lower gate electrodes 120_B may be the same as the number of channel patterns CP. Figure 2 As shown, the number of lower gate electrodes 120_B can be, for example, four, the same as the number of channel patterns CP. However, the example embodiment is not limited to this.

[0030] The gate electrode 120 may include at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and conductive metal oxide nitride. For example, the gate electrode 120 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), aluminum tantalum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), and tungsten (W). Materials including aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but the exemplary embodiments are not limited thereto. Conductive metal oxides and conductive metal nitrides may include the oxidation forms of the above-mentioned materials, but the exemplary embodiments are not limited thereto.

[0031] The top surface of the lower insulating layer 110 may contact the lower surface of the gate insulating layer 130 disposed on the lowermost gate electrode 120_B. In some example embodiments, the top surface of the lower insulating layer 110 may have a facet structure. A portion of the substrate may be disposed on the top surface of the lower insulating layer 110.

[0032] The gate insulating layer 130 may be disposed between the gate electrode 120 and the plurality of channel patterns CP, between the gate electrode 120 and the lower insulating layer 110, and between the gate electrode 120 and the source / drain pattern 150. For example, the gate insulating layer 130 may be disposed between the upper gate electrode 120_U and the uppermost channel pattern CP among the plurality of channel patterns CP. The gate insulating layer 130 may be disposed between the lower gate electrode 120_B and the channel pattern CP.

[0033] The gate spacer 170 may be disposed on the side surface of the upper gate electrode 120_U. For example, the gate spacer 170 may extend along the side surface of the upper gate electrode 120_U. The gate spacer 170 may not be disposed between adjacent channel patterns CP in the first direction D1.

[0034] The gate spacer 170 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. For clarity, the gate spacer 170 is shown as a single layer, but the example embodiment is not limited thereto.

[0035] In some example embodiments, the gate insulating layer 130 may be disposed between the upper gate electrode 120_U and the channel pattern CP, and may not be disposed on the gate spacer 170. In some example embodiments, the gate insulating layer 130 (e.g., the upper gate insulating layer 130_U) may be disposed between the gate spacer 170 and the upper gate electrode 120_U. For example, the gate insulating layer 130 may not be disposed between the gate spacer 170 and the upper gate electrode 120_U, nor between the gate spacer 170 and the gate cap pattern 165, but the example embodiments are not limited thereto.

[0036] A gate cap pattern 165 may be disposed on the upper gate electrode 120_U and the gate spacer 170. The gate cap pattern 165 may cover the top surface of the upper gate electrode 120_U. The gate cap pattern 165 may be stacked with the upper gate electrode 120_U in the first direction D1. The top surface of the gate cap pattern 165 may be disposed in the same plane as the top surface of the first interlayer insulating layer 180, but the example embodiment is not limited thereto. The width of the gate cap pattern 165 in the first direction D1 may be greater than the width of the upper gate electrode 120_U in the first direction D1.

[0037] In some example embodiments, the gate cap pattern 165 may be disposed between the gate spacers 170. For example, the width of the gate cap pattern 165 in the first direction D1 may correspond to the width of the upper gate electrode 120_U in the first direction D1.

[0038] The gate cover pattern 165 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. The gate cover pattern 165 may include a material that has etch selectivity for the first interlayer insulating layer 180.

[0039] Source / drain pattern 150 may be disposed on lower insulating layer 110. Source / drain pattern 150 may be connected to channel pattern CP. Some portions of the sidewalls of source / drain pattern 150 may contact channel pattern CP. Other portions of the sidewalls of source / drain pattern 150 may contact gate insulating layer 130. Source / drain pattern 150 may be connected to channel patterns CP spaced apart in a first direction D1. Source / drain pattern 150 may be disposed between channel patterns CP spaced apart in a second direction D2.

[0040] The source / drain pattern 150 may be disposed on at least one side of the gate electrode 120. The source / drain pattern 150 may be disposed between adjacent gate electrodes 120 in the second direction D2. For example, the source / drain pattern 150 may be disposed on both sides of the lower gate electrode 120_B. The source / drain pattern 150 may be disposed on one side of the gate electrode 120, and may not be disposed on the other side of the gate electrode 120.

[0041] The source / drain pattern 150 may include a first source / drain pattern 151 and a second source / drain pattern 152. The first source / drain pattern 151 and the second source / drain pattern 152 may be spaced apart from each other in the second direction D2. Each of the first source / drain pattern 151 and the second source / drain pattern 152 may be disposed between channel patterns CP spaced apart in the second direction D2 and between lower gate electrodes 120_B spaced apart in the second direction D2.

[0042] The source / drain pattern 150 can be an epitaxial pattern formed by a selective epitaxial growth process using an active pattern AP or a substrate as a seed. The source / drain pattern 150 can be used as the source / drain of a transistor using a channel pattern CP as the channel region.

[0043] The source / drain pattern 150 may include a semiconductor material. The source / drain pattern 150 may include, for example, silicon (Si) or germanium (Ge) as an elemental semiconductor material. The source / drain pattern 150 may include, for example, a binary or ternary compound comprising at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound wherein a group IV element is doped in the binary or ternary compound. For example, the source / drain pattern 150 may include silicon (Si), silicon-germanium (SiGe), germanium (Ge), silicon carbide (SiC), etc., but the exemplary embodiments are not limited thereto.

[0044] The source / drain pattern 150 may include impurities doped in the semiconductor material. The doped impurities may include at least one of boron (B), phosphorus (P), carbon (C), arsenic (As), antimony (Sb), bismuth (Bi), and oxygen (O), but the example embodiments are not limited thereto.

[0045] For clarity, the source / drain pattern 150 is shown as a single layer, but the example embodiments are not limited thereto. In some example embodiments, the source / drain pattern 150 may include multiple layers comprising materials that are different from each other. In other example embodiments, the source / drain pattern 150 may include multiple layers comprising the same material but having different concentrations of the constituent materials.

[0046] The first interlayer insulating layer 180 can be disposed on the source / drain pattern 150. The first interlayer insulating layer 180 can be disposed on one side of the upper gate electrode 120_U. The first interlayer insulating layer 180 can be disposed between the upper gate electrodes 120_U.

[0047] The first interlayer insulating layer 180 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and low-k materials. For example, low-k materials may include tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonnen silazene (TOSZ), fluorinated silicate glass (FSG), nanofoams (such as polypropylene oxide or polyimide), carbon-doped silica (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica degel, mesoporous silica, or combinations thereof, but the exemplary embodiments are not limited thereto.

[0048] Source / drain contacts 250 may be disposed on source / drain pattern 150. Source / drain contacts 250 may pass through a portion of source / drain pattern 150 and the first interlayer insulation layer 180. Source / drain contacts 250 may be connected to source / drain pattern 150. For example, a lower source / drain contact 251 may be disposed on the first source / drain pattern 151, and an upper source / drain contact 252 and sacrificial contact pattern PLH may be disposed on the second source / drain pattern 152. However, the example embodiments may be merely exemplary, and the upper source / drain contact may be disposed on the first source / drain pattern 151, and the lower source / drain contact may be disposed on the second source / drain pattern 152. In some example embodiments, both the upper and lower source / drain contacts may be disposed on the first source / drain pattern 151 or the second source / drain pattern 152.

[0049] A metal-semiconductor compound layer (e.g., a silicide layer) may be disposed between the source / drain contact 250 and the source / drain pattern 150. The source / drain contact 250 may be electrically connected to the source / drain pattern 150 via the silicide layer. For example, the silicide layer may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0050] The source / drain contact 250 may include a conductive material. For example, the source / drain contact 250 may include at least one of a metal, a metal nitride, a metal carbonitride, a two-dimensional (2D) material, and a conductive semiconductor material. The source / drain contact 250 may include a barrier layer surrounding the conductive material. The barrier layer may include a metal layer / metal nitride layer. The metal layer may include at least one of Ti, Ta, W, Ni, Co, and Pt. The metal nitride layer may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0051] The lower barrier layer 111 may be disposed in the second region R2. The lower barrier layer 111 may contact the lower insulating layer 110 in the second direction D2. The bottom surface of the lower insulating layer 110 may be coplanar with the bottom surface of the lower barrier layer 111.

[0052] The lower barrier layer 111 may comprise oxides, nitrides, oxynitrides, or combinations thereof. For clarity, the lower barrier layer 111 is shown as a single layer, but the example embodiment is not limited thereto. For example, the lower barrier layer 111 may be formed of multiple layers.

[0053] A doped bottom pattern (DBP) may be disposed on a lower barrier layer 111. For example, the lower barrier layer 111 may be disposed at a height lower than the doped bottom pattern (DBP). The doped bottom pattern (DBP) may extend in the third direction (D3). The doped bottom pattern (DBP) may be formed by etching a portion of the substrate, but the example embodiments are not limited thereto. For example, the doped bottom pattern (DBP) may include an epitaxial layer grown from the substrate. The doped bottom pattern (DBP) may include Si or Ge as an elemental semiconductor material. The doped bottom pattern (DBP) may include a compound semiconductor. For example, the doped bottom pattern (DBP) may include a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0054] IV-IV compound semiconductors can be binary or ternary compounds including at least two or more of C, Si, Ge and Sn.

[0055] III-V compound semiconductors can be, for example, binary, ternary, and quaternary compounds formed by combining at least one of Al, Ga, and indium (In), which are group III elements, with at least one of P, As, and Sb, which are group V elements.

[0056] In some example embodiments, the doped bottom pattern DBP and the multiple channel patterns CP may comprise Si. In other example embodiments, the doped bottom pattern DBP and the multiple channel patterns CP may comprise SiGe. In even further example embodiments, the doped bottom pattern DBP may comprise Si, and the multiple channel patterns CP may comprise SiGe.

[0057] The doped bottom pattern (DBP) may include a first well region WR1 and a second well region WR2. The first well region WR1 and the second well region WR2 may be positioned at the same height. The first well region WR1 and the second well region WR2 may be arranged side-by-side in a second direction D2. The first well region WR1 and the second well region WR2 may be arranged to be stacked in the second direction D2.

[0058] The first well region WR1 and the second well region WR2 can be regions in which the substrate is doped with impurities. The first well region WR1 and the second well region WR2 can be doped with impurities having opposite conductivity types. The first well region WR1 can be doped with an impurity having a first conductivity type, and the second well region WR2 can be doped with an impurity having a second conductivity type. For example, the first well region WR1 can be a region doped with p-type impurities, and the second well region WR2 can be a region doped with N-type impurities. When the well region is an N-type region, the well region can include dopants such as P, As, and Sb, and when the well region is a p-type region, the well region can include dopants such as B. The first well region WR1 and the second well region WR2 can form a PN junction to form a PN diode.

[0059] A first doped region DR1 may be formed in a first well region WR1, and a second doped region DR2 may be formed in a second well region WR2. The first doped region DR1 may be doped with impurities having the same conductivity type as the first well region WR1. The first doped region DR1 may include the same dopant as the first well region WR1. The first doped region DR1 may be a region with a higher impurity concentration than the first well region WR1 (e.g., the portion of the first well region WR1 excluding the first doped region DR1). The second doped region DR2 may be doped with impurities having the same conductivity type as the second well region WR2. The second doped region DR2 may include the same dopant as the second well region WR2. The second doped region DR2 may be a region with a higher impurity concentration than the second well region WR2 (e.g., the portion of the second well region WR2 excluding the second doped region DR2).

[0060] In some exemplary embodiments of this disclosure, the first doped region DR1 and the second doped region DR2 may be spaced apart from the lower barrier layer 111 in the first direction D1. The first doped region DR1 and the second doped region DR2 may be disposed on the upper side of the doped bottom pattern DBP. The first doped region DR1 may be disposed on the upper side of the first well region WR1, and the second doped region DR2 may be disposed on the upper side of the second well region WR2. The top surfaces of the first doped region DR1, the second doped region DR2, the first well region WR1, and the second well region WR2 may be coplanar with each other.

[0061] The doped bottom patterned DBP can be separated from the lower insulating layer 110 via the device isolation layer 105. The device isolation layer 105 can be disposed on the side surface of the doped bottom patterned DBP. A portion of the side surface and the top surface of the device isolation layer 105 can contact the first interlayer insulating layer 180. The device isolation layer 105 can be disposed in the boundary between the first region R1 and the second region R2. For example, the device isolation layer 105 can be disposed on the boundary between the lower insulating layer 110 and the lower barrier layer 111.

[0062] The top surface of the doped bottom pattern DBP can be positioned at a height corresponding to the top surface of the lower insulating layer 110. The top surface of the doped bottom pattern DBP can be positioned at the same height as the bottom surface of the gate insulating layer 130 disposed on the lowest gate electrode 120_B.

[0063] Device isolation layer 105 may comprise, for example, oxides, nitrides, oxynitrides, or combinations thereof. For clarity, device isolation layer 105 is shown as a single layer, but the example embodiment is not limited thereto. For example, device isolation layer 105 may be formed of multiple layers. Device isolation layer 105 may be an insulating layer for electrically isolating the active pattern from the doped bottom pattern, and may comprise the same material as the lower insulating layer 110, so the boundary between device isolation layer 105 and lower insulating layer 110 may not be distinguishable.

[0064] The top surface of the device isolation layer 105 can be positioned at the same height as the top surface of the uppermost channel pattern CP. The side surface of the device isolation layer 105 can contact the side surface of the active pattern AP. The bottom surface of the device isolation layer 105 can be positioned at a height corresponding to the bottom surface of the doped bottom pattern DBP. The bottom surface of the device isolation layer 105 can be positioned at the same height as the bottom surface of the doped bottom pattern DBP. The bottom surface of the device isolation layer 105 can be coplanar with the bottom surface of the doped bottom pattern DBP. The first doped region DR1 and the second doped region DR2 formed in the doped bottom pattern DBP can be positioned at a height higher than the bottom surface of the device isolation layer 105.

[0065] An upper etch stop layer 161 may be disposed on the first interlayer insulating layer 180. The upper etch stop layer 161 may extend along the contour of the top surface of the first interlayer insulating layer 180 and the contour of the top surface of the gate cap pattern 165.

[0066] The upper etch stop layer 161 may include a material that is etch-selective to the first interlayer insulating layer 180. For example, the upper etch stop layer 161 may include at least one of SiN, SiO, SiON, SiOCN, SiBN, SiOBN, SiOC, and combinations thereof.

[0067] The second interlayer insulating layer 181 may be disposed on the upper etch stop layer 161. For example, the second interlayer insulating layer 181 may include at least one of SiO, SiN, SiON and low-k materials. The upper wiring insulating layer 182 may be disposed on the second interlayer insulating layer 181.

[0068] The upper wiring 210 may be disposed within the upper wiring insulating layer 182. The upper wiring 210 may be disposed at a height higher than the active pattern AP and the doped bottom pattern DBP. The upper wiring 210 may be electrically connected to at least one of the source / drain pattern 150, the first well region WR1, and the second well region WR2. At least one of the first doped region DR1 and the second doped region DR2 may be electrically connected to the upper wiring 210.

[0069] A second upper via 262 may be disposed on the upper source / drain contact 252. The source / drain pattern 150 may be electrically connected to the upper wiring 210. The second upper via 262 may pass through the upper etch stop layer 161 and the second interlayer insulating layer 181. The second upper via 262 may electrically connect the source / drain pattern 150 and the upper wiring 210. The second upper via 262 may be electrically connected to the first upper wiring 211. The first upper wiring 211 may extend in the third direction D3. The top surface of the second upper via 262 may contact the bottom surface of the first upper wiring 211, and the bottom surface of the second upper via 262 may contact the top surface of the upper source / drain contact 252.

[0070] Upper contacts 231 and 232 may extend in a first direction D1. The first upper contact 231 may be disposed on a first doped region DR1, which is located above a first well region WR1. The second upper contact 232 may be disposed on a second doped region DR2, which is located above a second well region WR2. The first upper contact 231 and the second upper contact 232 may extend in the first direction D1, respectively.

[0071] The bottom surface of the first upper contact 231 may contact the top surface of the first doped region DR1, and the bottom surface of the second upper contact 232 may contact the top surface of the second doped region DR2. In some example embodiments, a silicide layer may be disposed between the first upper contact 231 and the first doped region DR1, and a silicide layer may be disposed between the second upper contact 232 and the second doped region DR2. The bottom surfaces of the upper contacts 231 and 232 may be positioned at a height corresponding to the bottom surface of the gate electrode 120. For example, the bottom surfaces of the upper contacts 231 and 232 may be positioned at a height corresponding to the bottom surface of the bottommost lower gate electrode in the lower gate electrode 120_B. In another example, the bottom surfaces of the upper contacts 231 and 232 may be positioned at the same height as the bottom surface of the gate insulating layer 130 disposed on the bottommost lower gate electrode 120_B in the lower gate electrode 120_B.

[0072] The top surfaces of the upper contacts 231 and 232 may be coplanar with the top surface of the upper source / drain contact 252. The first upper contact 231 and the second upper contact 232 may be disposed on the top surface of the doped bottom pattern DBP, so the length of each of the first upper contact 231 and the second upper contact 232 in the first direction D1 may be greater than the length of the upper source / drain contact 252 disposed on the second upper source / drain pattern 152 in the first direction D1.

[0073] Upper vias 241 and 242 may be disposed on the first upper contact 231 and the second upper contact 232, respectively. Upper vias 241 and 242 may electrically connect the upper contacts 231 and 232 and the upper wiring 210, respectively. Upper vias 241 and 242 may pass through the upper etch stop layer 161 and the second interlayer insulating layer 181. Upper vias 241 and 242 may electrically connect the first well region WR1, the second well region WR2, and the upper wiring 210, respectively. For example, the first well region WR1 may be electrically connected to the second upper wiring 212, and the second well region WR2 may be electrically connected to the third upper wiring 213. However, the connection structure may be merely exemplary, and other connection structures may be provided.

[0074] The lower wiring 220 may be disposed on the bottom surface of the lower insulating layer 110 and the lower barrier layer 111. For example, the lower wiring 220 may be disposed at a height lower than the lower insulating layer 110 and the lower barrier layer 111. At least one of the first doped region DR1 and the second doped region DR2 may be electrically connected to the lower wiring 220.

[0075] The lower wiring 220 may include a first power line 221 and a second power line 222. For example, the first power line 221 and the second power line 222 may extend in a third direction D3, respectively. A lower etch stop layer 162 and a lower wiring insulating layer 183 may be disposed between the first power line 221 and the second power line 222. The lower wiring insulating layer 183 may be disposed on the bottom surface of the lower etch stop layer 162. The lower etch stop layer 162 may be disposed on the boundary between the lower insulating layer 110 and the lower barrier layer 111. The lower etch stop layer 162 may be disposed above the first region R1 and the second region R2.

[0076] The lower etch stop layer 162 may be constructed of the same material as the upper etch stop layer 161. The lower wiring insulating layer 183 may be constructed of the same material as the first interlayer insulating layer 180.

[0077] The lower source / drain contact 251 may be disposed on the top surface of the first power line 221. The first source / drain pattern 151 may be electrically connected to the first power line 221. The lower source / drain contact 251 may be disposed on the top surface of the first power line 221 such that power may be supplied from the first power line 221 to the first source / drain pattern 151.

[0078] In some example embodiments, the conductive post 190 may be disposed on the top surface of the second power line 222. The conductive post 190 may electrically connect the upper wiring 210 and the lower wiring 220. The conductive post 190 may connect between the upper wiring 210 and the lower wiring 220. The conductive post 190 may electrically connect the second power line 222 and the third upper wiring 213. The conductive post 190 may extend in a first direction D1. The conductive post 190 may supply power from the second power line 222 to the second well region WR2 via the third upper wiring 213. The first doped region DR1 and the second doped region DR2 may be electrically connected to the second power line 222 via the conductive post 190. The conductive post 190 may have a length in the first direction D1 greater than the length of the first upper contact 231 and the second upper contact 232. The conductive post 190 may pass through the second interlayer insulating layer 181, the upper etch stop layer 161, the first interlayer insulating layer 180, the device isolation layer 105, and the lower barrier layer 111 in the first direction D1. Figure 1 The conductive pillar 190 is shown as a single layer, but the structure of the conductive pillar 190 is merely exemplary. In other example embodiments, the conductive pillar 190 may have a structure in which multiple conductive layers are stacked.

[0079] The conductive pillar 190 may include at least one or a combination thereof, such as W, Mo, Co, Cu, Al, Ti, Ta and Ti / TiN.

[0080] Figures 2 to 19The diagram illustrates intermediate stages and is provided to explain a method for manufacturing a semiconductor device according to some example embodiments.

[0081] Reference Figure 2 A method for manufacturing a semiconductor device according to some example embodiments may include forming a first element on a substrate 100 including a bottom pattern BP, a device isolation layer 105, a doped bottom pattern DBP, a stacked structure S_ST, a first interlayer insulating layer 180, etc.

[0082] The stacked structure S_ST can be formed by alternately stacking a sacrificial semiconductor layer SC_L and an active semiconductor layer ACT_L on a substrate 100. The substrate 100 can be a silicon substrate. The substrate 100 may include another material (e.g., silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), or gallium antimonide (GaSb)), but the example embodiments are not limited thereto.

[0083] The stacked structure S_ST may include alternating stacked sacrificial semiconductor layers SC_L and active semiconductor layers ACT_L. The sacrificial semiconductor layer SC_L may be disposed in the bottommost layer of the stacked structure S_ST. The active semiconductor layer ACT_L may be disposed in the topmost layer of the stacked structure S_ST. The active semiconductor layer ACT_L and the sacrificial semiconductor layer SC_L may be constructed of materials having different etch selectivity to each other.

[0084] A mask pattern can be formed on the stacked structure S_ST, and a portion of the stacked structure S_ST can be patterned. For example, a portion of the stacked structure S_ST can be selectively removed. The stacked structure S_ST can be patterned to form trenches, a bottom pattern BP, and a doped bottom pattern DBP. A device isolation layer 105 can be formed within the trenches. The trenches can be filled with the device isolation layer 105. The device isolation layer 105 is shown as a single layer, but the example embodiment is not limited thereto.

[0085] The doped bottom pattern DBP may be doped with impurities. A portion of the doped bottom pattern DBP may be doped with impurities of a first conductivity type to form a first well region WR1, and the remaining portion of the doped bottom pattern DBP may be doped with impurities of a second conductivity type to form a second well region WR2. The first well region WR1 and the second well region WR2 may be formed at the same height as each other. The first well region WR1 and the second well region WR2 may be stacked in a second direction D2.

[0086] Based on the device isolation layer 105, the first region and the second region can be separated. A mask can be placed in the second region, and then a first element can be formed in the first region. A first interlayer insulating layer 180 can be formed in the first region and the second region. For example, the first interlayer insulating layer 180 can be formed on the first element, the device isolation layer 105, and the stacked structure S_ST.

[0087] Reference Figure 3 A mask can be placed on the first component, and then an etching process can be performed on the second region. The etching process removes a portion of the first interlayer insulating layer 180 and the stacked structure (see...). Figure 2 (S_ST in the original text). With the removal of the stacked structure, the top surface of the doped bottom pattern DBP can be exposed. For example, the top surface of the first well region WR1 and the top surface of the second well region WR2 can be exposed in the first direction D1.

[0088] In some example embodiments, the device isolation layer 105 and the first interlayer insulating layer 180 can be isotropically etched using a wet etching process, such that a portion of the device isolation layer 105 can be removed.

[0089] Reference Figure 4 Each of the first well region WR1 and the second well region WR2 can be subjected to a separate ion implantation process. Impurities having a concentration greater than that of the first well region WR1 and the second well region WR2 can be implanted into the first well region WR1 and the second well region WR2, respectively. A first conductivity type dopant can be implanted into the first well region WR1, and a second conductivity type dopant can be implanted into the second well region WR2. Therefore, a first doped region DR1 can be formed on the upper side of the first well region WR1, and a second doped region DR2 can be formed on the upper side of the second well region WR2.

[0090] Reference Figures 5 to 7 An insulating layer can be formed on the doped bottom pattern DBP. Therefore, the device isolation layer 105 and the first interlayer insulating layer 180 can be refilled on the doped bottom pattern DBP.

[0091] A mask pattern may be formed on the first interlayer insulating layer 180. The mask pattern may expose a portion of the first interlayer insulating layer 180. For example, portions of the first interlayer insulating layer 180 corresponding to the first doped region DR1 and the second doped region DR2 may be exposed.

[0092] An etching process can be performed on the first interlayer insulating layer 180. The portions of the first interlayer insulating layer 180 covered by the mask pattern may not be removed, and the portions of the first interlayer insulating layer 180 exposed by the mask pattern may be removed. Vias VHs may be formed in the first interlayer insulating layer 180. In some example embodiments, the vias VHs may be formed with a cross-sectional area that decreases with increasing depth.

[0093] The first doped region DR1 and the second doped region DR2 can be exposed through the via VH, respectively. The via VH can be filled with a metallic material for forming the upper contacts 231 and 232. For example, the upper contacts 231 and 232 may include at least one or a combination of W, Mo, Co, Cu, Al, Ti, Ta, and Ti / TiN. Depending on the shape of the via VH, the upper contacts 231 and 232 may be formed with a cross-sectional area decreasing from the upper end of the via VH toward the lower end. However, the shape of the via VH and the upper contacts 231 and 232 is not limited thereto, and the via VH and the upper contacts 231 and 232 may be formed with a uniform cross-sectional area.

[0094] Reference Figure 8 and Figure 9 Source / drain contacts 250 can be formed on the source / drain pattern 150. To form the source / drain contacts 250, the mask pattern on the first element side can be removed first.

[0095] A mask pattern may be formed on the first element. The mask pattern may expose a portion of the first interlayer insulating layer 180. For example, a portion of the first interlayer insulating layer 180 corresponding to the second source / drain pattern 152 may be exposed.

[0096] An etching process can be performed on the first interlayer insulating layer 180 exposed through the mask pattern. A portion of the first interlayer insulating layer 180 can be removed by the etching process. A portion of the second source / drain pattern 152 can also be removed during the etching process. Vias VHs can be formed in the first interlayer insulating layer 180 and the second source / drain pattern 152. In some example embodiments, the vias VHs can be formed with a cross-sectional area that decreases with increasing depth.

[0097] The second source / drain pattern 152 can be exposed through a via VH. The via VH can be filled with a metallic material for forming the upper source / drain contact 252. For example, the upper source / drain contact 252 may include at least one or a combination of W, Mo, Co, Cu, Al, Ti, Ta, and Ti / TiN.

[0098] Reference Figures 10 to 12 An upper etch stop layer 161 may be formed on the gate cap pattern 165, the first interlayer insulating layer 180, the upper contacts 231 and 232, and the upper source / drain contacts 252. The upper etch stop layer 161 may be formed conformally. Subsequently, a second interlayer insulating layer 181 may be formed on the upper etch stop layer 161.

[0099] A mask pattern may be formed on the second interlayer insulating layer 181. The mask pattern may expose portions of the second interlayer insulating layer 181 and the upper etch stop layer 161. For example, portions of the second interlayer insulating layer 181 and the upper etch stop layer 161 corresponding to the upper contacts 231 and 232 and the upper source / drain contacts 252, respectively, may be exposed.

[0100] An etching process can be performed on the exposed second interlayer insulating layer 181 and the exposed upper etch stop layer 161. The etching process removes portions of the second interlayer insulating layer 181 and the upper etch stop layer 161. Vias VH can be formed in the second interlayer insulating layer 181 and the upper etch stop layer 161.

[0101] The top surfaces of the upper contacts 231 and 232, as well as the top surface of the upper source / drain contact 252, can be exposed through the via VH. First upper vias 241 and 242 and a second upper via 262 can be formed within the via VH. For example, the first upper vias 241 and 242 and the second upper via 262 may comprise at least one or a combination of W, Mo, Co, Cu, Al, Ti, Ta, and Ti / TiN.

[0102] Reference Figures 13 to 15 An upper wiring insulating layer 182 may be formed on the second interlayer insulating layer 181. A mask pattern may be formed on the upper wiring insulating layer 182. The mask pattern may expose a portion of the upper wiring insulating layer 182. For example, portions of the upper wiring insulating layer 182 corresponding to the first upper vias 241 and 242 and the second upper via 262 may be exposed.

[0103] An etching process can be performed on the upper wiring insulating layer 182 exposed by the mask pattern. A portion of the upper wiring insulating layer 182 can be removed by the etching process. The upper wiring 210 can be formed in the portion of the upper wiring insulating layer 182 removed by the etching process.

[0104] Reference Figure 16 The semiconductor device can be flipped so that the substrate faces upwards, and then the substrate can be removed. After substrate removal, a planarization process can be performed. For example, the planarization process can be a chemical mechanical polishing (CMP) process.

[0105] A lower barrier layer 111 can be formed in the second region. A bottom pattern DBP can be doped (e.g., in...) Figure 15 A lower barrier layer 111 is formed on the (shown in the image) to remove the bottom pattern BP (in, for example) Figure 15 (as shown in the diagram), and the doped bottom pattern DBP can be left unremoved. A lower barrier layer 111 can be formed on a portion of the bottom surface of the doped bottom pattern DBP and the device isolation layer 105. The lower barrier layer 111 can be constructed of, for example, oxides, nitrides, etc.

[0106] The bottom pattern BP can be replaced with a lower insulating layer 110 in the first region. After removing the bottom pattern, the lower insulating layer 110 can be formed. The bottom surface of the lower insulating layer 110 can be coplanar with the bottom surface of the lower barrier layer 111. For example, a planarization process can be performed on the lower insulating layer 110 and the lower barrier layer 111.

[0107] Reference Figure 17 It can etch a portion of the lower insulating layer 110, the sacrificial contact pattern PLH, and the first source / drain pattern 151, and can form the lower source / drain contact 251.

[0108] The lower barrier layer 111, the device isolation layer 105, the first interlayer insulating layer 180, the upper etch stop layer 161, and the second interlayer insulating layer 181 can be etched, and conductive pillars 190 can be formed.

[0109] Reference Figure 18 A down etch stop layer 162 may be formed on the lower insulating layer 110 and the lower barrier layer 111. The down etch stop layer 162 may be configured to prevent the device isolation layer 105 from being removed when a planarization process is performed on the lower insulating layer 110. For example, because the lower insulating layer 110 and the device isolation layer 105 are formed of the same oxide, the down etch stop layer 162 can prevent the device isolation layer 105 from being removed during the planarization process of the lower insulating layer.

[0110] A lower wiring insulating layer 183 may be formed on the lower etch stop layer 162. The lower etch stop layer 162 may be configured to cover the bottom surface of the conductive pillar 190 and the bottom surface of the lower source / drain contact 251. The lower etch stop layer 162 may be formed conformally.

[0111] Reference Figure 19 A lower wiring 220 can be formed on the underside of the semiconductor device. A mask pattern can be formed on the lower wiring insulating layer 183. The mask pattern can expose portions of the lower wiring insulating layer 183 and the lower etch stop layer 162. For example, portions of the lower wiring insulating layer 183 and the lower etch stop layer 162 corresponding to the lower source / drain contacts 251 and the conductive pillars 190, respectively, can be exposed.

[0112] An etching process can be performed on the lower wiring insulating layer 183 and the lower etch stop layer 162 exposed by the mask pattern. The etching process removes portions of the lower wiring insulating layer 183 and the lower etch stop layer 162. Lower wiring 220 can be formed in the portions where the lower wiring insulating layer 183 and the lower etch stop layer 162 have been removed. A first power line 221 can contact the bottom surface of the lower source / drain contact 251, and a second power line 222 can contact the bottom surface of the conductive post 190.

[0113] In the following text, the same reference numerals refer to Figure 1The same elements as those in the semiconductor device will be used, and a detailed description of them will be omitted. For clarity, they will be referred to as... Figure 1 The semiconductor device is described with a focus on the different components.

[0114] Figure 20 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0115] Reference Figure 20 The semiconductor device according to some example embodiments may include the following contacts 233 and 234.

[0116] The doped bottom pattern (DBP) may include a first well region WR1 and a second well region WR2. The first well region WR1 and the second well region WR2 may be positioned at the same height. The first well region WR1 and the second well region WR2 may be arranged side-by-side in a second direction D2. The first well region WR1 and the second well region WR2 may be arranged to be stacked in the second direction D2.

[0117] In some example embodiments, a first doped region DR1 and a second doped region DR2 may be disposed on the underside of a doped bottom pattern DBP. The first doped region DR1 may be disposed on the underside of a first well region WR1, and the second doped region DR2 may be disposed on the underside of a second well region WR2. The bottom surfaces of the first doped region DR1, the second doped region DR2, the first well region WR1, and the second well region WR2 may be coplanar. The first doped region DR1 and the second doped region DR2 may be formed by an ion implantation process after substrate removal.

[0118] Lower contacts 233 and 234 may be disposed within the lower barrier layer 111. Lower contacts 233 and 234 may pass through the lower barrier layer 111. The top surfaces of lower contacts 233 and 234 may contact the bottom surfaces of the first doped region DR1 and the second doped region DR2, respectively, and the bottom surfaces of lower contacts 233 and 234 may contact the lower wiring 220. A silicide layer may be formed between the first lower contact 233 and the first doped region DR1. A silicide layer may be formed between the second lower contact 234 and the second doped region DR2.

[0119] A first lower contact 233 may be disposed on the bottom surface of a first doped region DR1, which is located below a first well region WR1. A second lower contact 234 may be disposed on the bottom surface of a second doped region DR2, which is located below a second well region WR2. The top surface of the first lower contact 233 may contact the bottom surface of the first doped region DR1, and the top surface of the second lower contact 234 may contact the bottom surface of the second doped region DR2.

[0120] The lower wiring 220 may include a third power line 223 disposed on the bottom surface of the first lower contact 233. The third power line 223 may extend in the third direction D3. The third power line 223 may pass through the lower wiring insulating layer 183 and the lower etch stop layer 162. The third power line 223 may supply power to the first doped region DR1 through the first lower contact 233. The first doped region DR1 may be electrically connected to the third power line 223 through the first lower contact 233. The second doped region DR2 may be electrically connected to the second power line 222 through the second lower contact 234.

[0121] Figure 21 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure. Figure 22 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0122] Reference Figure 21 and Figure 22 According to some example embodiments, the semiconductor device may include an upper contact 231 or 232 disposed in either a first doped region DR1 or a second doped region DR2. The upper contacts 231 and 232 may extend in a first direction D1.

[0123] The doped bottom pattern (DBP) may include a first well region WR1 and a second well region WR2. (See reference...) Figure 21 The first doped region DR1 may be disposed below the doped bottom pattern DBP, and the second doped region DR2 may be disposed above the doped bottom pattern DBP. The first doped region DR1 may be disposed below the first well region WR1, and the second doped region DR2 may be disposed above the second well region WR2. The first doped region DR1 and the second doped region DR2 may be disposed at different heights. The first doped region DR1 and the second doped region DR2 may be configured not to overlap in the second direction D2. However, the exemplary embodiment is not limited to this, and the first doped region DR1 and the second doped region DR2 may be configured to partially overlap in the second direction D2.

[0124] The upper contact 232 can be disposed on the second doped region DR2. (For...) Figure 1 The description of the upper contact 232 can also be applied to Figure 21 Upper contact element 232.

[0125] The lower contact 233 may be disposed within the lower barrier layer 111. The lower contact 233 may pass through the lower barrier layer 111. The top surface of the lower contact 233 may contact the bottom surface of the first doped region DR1, and the bottom surface of the lower contact 233 may contact the lower wiring 220.

[0126] The upper wiring 210 may include a third upper wiring 213 and a fourth upper wiring 214. The third upper wiring 213 is electrically connected to the lower wiring 220 via a conductive post 190, and the fourth upper wiring 214 is electrically connected to the upper contact 232. The third upper wiring 213 and the fourth upper wiring 214 may be spaced apart from each other in the second direction D2. However, the example embodiment is not limited thereto, and the third upper wiring 213 and the fourth upper wiring 214 may be connected to each other.

[0127] The lower wiring 220 may include a third power line 223 disposed on the bottom surface of the lower contact 233. The third power line 223 may extend on the third direction D3. The third power line 223 may pass through the lower wiring insulating layer 183 and the lower etch stop layer 162. The third power line 223 may supply power to the first doped region DR1 through the lower contact 233.

[0128] Reference Figure 22 The first doped region DR1 can be disposed above the doped bottom pattern DBP, and the second doped region DR2 can be disposed below the doped bottom pattern DBP. The first doped region DR1 can be disposed above the first well region WR1, and the second doped region DR2 can be disposed below the second well region WR2.

[0129] The upper contact 231 can be disposed in the first doped region DR1. (For...) Figure 1 The description of the upper contact 231 can also be applied to Figure 22 Upper contact element 231.

[0130] The lower contact 234 may be disposed within the lower barrier layer 111. The lower contact 234 may pass through the lower barrier layer 111. The top surface of the lower contact 234 may contact the bottom surface of the second doped region DR2, and the bottom surface of the lower contact 234 may contact the second power line 222.

[0131] Figure 23 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0132] Reference Figure 23 A semiconductor device according to some example embodiments may include a first upper source / drain contact 253 disposed on a first source / drain pattern 151 and a second upper source / drain contact 252 disposed on a second source / drain pattern 152. For Figure 1 The description of the source / drain contact 252 can also be applied to... Figure 23 The second source / drain contact 252.

[0133] The first upper source / drain contact 253 may be disposed on the upper side of the first source / drain pattern 151. The first upper source / drain contact 253 may pass through the first interlayer insulation layer 180 and a portion of the first source / drain pattern 151. The first upper source / drain contact 253 may electrically connect the upper wiring 210 and the first source / drain pattern 151.

[0134] An upper via 261 may be disposed on the first upper source / drain contact 253. The upper via 261 may pass through the upper etch stop layer 161 and the second interlayer insulating layer 181. The upper via 261 may electrically connect the first source / drain pattern 151 and the upper wiring 210.

[0135] The upper via 261 can be electrically connected to the fourth upper wiring 214. The fourth upper wiring 214 can extend on the third direction D3. The top surface of the upper via 261 can contact the bottom surface of the fourth upper wiring 214, and the bottom surface of the upper via 261 can contact the top surface of the first upper source / drain contact 253.

[0136] Reference Figure 23 According to some example embodiments, a semiconductor device may include a bottom pattern BP and a doped bottom pattern DBP on a substrate 100.

[0137] The bottom pattern BP may protrude from the substrate 100. The bottom pattern BP may extend in the third direction D3. The bottom pattern BP may be spaced apart from the adjacent doped bottom pattern DBP in the second direction D2. The bottom pattern BP may be separated from the adjacent doped bottom pattern DBP by the device isolation layer 105. Multiple channel patterns CP may be disposed on the bottom pattern BP. The individual channel patterns CP may be spaced apart from each other in the third direction D3.

[0138] The bottom pattern BP can be formed by etching a portion of the substrate 100, but the example embodiment is not limited thereto. For example, the bottom pattern BP may include an epitaxial layer grown from the substrate 100. The bottom pattern BP may include Si or Ge as an elemental semiconductor material. The bottom pattern BP may be a region doped with impurities, similar to the doped bottom pattern DBP.

[0139] Figure 24 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0140] Reference Figure 24The doped bottom pattern DBP can be disposed at the same height as the channel pattern CP and the lower gate electrode 120_B of the first element in the second direction D2. The doped bottom pattern DBP can be superimposed on the channel pattern CP and the lower gate electrode 120_B of the first element in the second direction D2. The bottom surface of the doped bottom pattern DBP can be positioned at the same height as the bottom surface of the bottom pattern BP and the bottom surface of the device isolation layer 105.

[0141] The top surface of the doped bottom pattern DBP can be positioned at the same height as the top surface of the device isolation layer 105. The top surface of the doped bottom pattern DBP can also be positioned at the same height as the top surface of the uppermost channel pattern CP or the top surface of the active pattern AP. However, the example embodiment is not limited to this, and the top surface of the doped bottom pattern DBP can be positioned at a lower height than the top surface of the device isolation layer 105.

[0142] In some example embodiments, the doped bottom patterned DBP can be formed by removing nanosheets and filling a silicon layer of a thickness corresponding to the thickness of the removed nanosheets. In other example embodiments, the doped bottom patterned DBP can be a region in which nanosheets are not formed. In other example embodiments, a stacked structure on the doped bottom patterned DBP may not be formed, and therefore a process for removing the stacked structure may not be performed.

[0143] The doped bottom pattern (DBP) may include a first well region WR1 and a second well region WR2. The first well region WR1 and the second well region WR2 may be positioned at the same height. The first well region WR1 and the second well region WR2 may be arranged side-by-side in a second direction D2. The first well region WR1 and the second well region WR2 may be arranged to be stacked in the second direction D2.

[0144] In some example embodiments, a first doped region DR1 and a second doped region DR2 may be disposed above the doped bottom pattern DBP. The first doped region DR1 may be disposed above the first well region WR1, and the second doped region DR2 may be disposed above the second well region WR2.

[0145] Although not shown, as in the example embodiment described above, at least one of the first doped region DR1 and the second doped region DR2 may be disposed on the underside of the doped bottom pattern DBP.

[0146] The above description of specific examples of this disclosure is for illustrative purposes only, and those skilled in the art with ordinary knowledge of this disclosure will be able to make various modifications, alterations and additions within the spirit and scope of this disclosure, and such modifications, alterations and additions should be interpreted as being included within the scope of the claims.

Claims

1. A semiconductor device, comprising: An active pattern is present in the first region and includes a plurality of channel patterns stacked and spaced apart from each other in a first direction; Gate electrodes, surrounding the plurality of channel patterns; The bottom pattern is doped in the second region and includes a first well region and a second well region. The first well region has a dopant concentration of a first conductivity type, and the second well region is at the same height as the first well region and has a dopant concentration of a second conductivity type. A device isolation layer is located between the active pattern and the doped bottom pattern in a second direction intersecting the first direction; A first doped region is formed within a first well region and has a dopant concentration of a first conductivity type that is greater than that of other portions of the first well region. as well as A second doped region is formed within the second well region and has a higher dopant concentration of the second conductivity type than that within the second well region. The bottom surface of the device isolation layer is positioned at a height corresponding to the bottom surface of the doped bottom pattern, and The first and second doped regions are located at a height equal to or higher than the bottom surface of the device isolation layer.

2. The semiconductor device according to claim 1, further comprising: The upper wiring is positioned at a height higher than the active pattern and the doped bottom pattern. At least one of the first doped region and the second doped region is electrically connected to the upper wiring.

3. The semiconductor device according to claim 2, further comprising: Source / drain patterns, on one side of the plurality of channel patterns, The source / drain pattern is electrically connected to the upper wiring.

4. The semiconductor device according to claim 3, further comprising: The lower insulating layer is located below the height of the plurality of channel patterns; The lower barrier layer is located below the height of the doped bottom pattern; as well as The lower wiring is positioned below the height of the lower insulation layer and the lower barrier layer.

5. The semiconductor device according to claim 4, wherein, At least one of the first doped region and the second doped region is electrically connected to the lower wiring.

6. The semiconductor device according to claim 4, further comprising: The lower source / drain contact is positioned on the source / drain pattern through the lower insulating layer and electrically connects the source / drain pattern and the lower wiring.

7. The semiconductor device according to claim 4, further comprising: The conductive post extends in the first direction and connects the upper wiring and the lower wiring.

8. The semiconductor device according to claim 3, wherein, The first doped region is located above the first well region, and the second doped region is located above the second well region. The semiconductor device further includes: The upper contact is located on at least one of the first doped region and the second doped region, and extends in a first direction; and The first via connects the upper contact and the upper wiring.

9. The semiconductor device according to claim 8, further comprising: The upper source / drain contact extends in a first direction on the source / drain pattern; as well as The second via connects to the source / drain pattern and the upper wiring. The length of the upper contact is greater than the length of the upper source / drain contact.

10. The semiconductor device according to claim 1, wherein, The first doped region is located below the first well region, and the second doped region is located below the second well region. The semiconductor device further includes: The first lower contact is located on the first doped region; and The second lower contact is located on the second doped region.

11. The semiconductor device of claim 10, further comprising: The lower insulating layer is located below the height of the plurality of channel patterns; The lower barrier layer is located below the height of the doped bottom pattern; as well as The lower wiring is positioned below the height of the lower insulation layer and the lower barrier layer. The first lower contact and the second lower contact pass through the lower barrier layer to make contact with the lower wiring.

12. The semiconductor device according to claim 1, wherein, The first doped region is located above the first well region, and the second doped region is located below the second well region. The semiconductor device further includes a lower contact on the second doped region.

13. The semiconductor device according to claim 1, further comprising: The bottom pattern is located at a height lower than the active pattern and at the same height as the doped bottom pattern. The bottom surface of the bottom pattern is positioned at the same height as the bottom surface of the device isolation layer.

14. The semiconductor device according to claim 1, wherein: The upper surface of the doped bottom pattern is positioned at a height corresponding to the upper surface of the active pattern.

15. A semiconductor device, comprising: A lower insulating layer and a lower barrier layer, wherein the lower insulating layer is in a first region and the lower barrier layer is in a second region; An active pattern is on a lower insulating layer and includes a plurality of channel patterns stacked and spaced apart from each other in a first direction; Gate electrodes, surrounding the plurality of channel patterns; Source / drain pattern, on one side of the plurality of channel patterns; The bottom pattern is doped on the lower barrier layer and includes a first well region and a second well region positioned side by side in a second direction intersecting the first direction; The first doped region is formed in the first well region; as well as The second doped region is formed in the second well region. The bottom surface of the lower barrier layer is coplanar with the bottom surface of the lower insulating layer.

16. The semiconductor device of claim 15, further comprising: The lower etch stop layer is located on the bottom surface of the lower insulating layer and the bottom surface of the lower barrier layer; as well as The lower wiring is positioned below the height of the lower insulating layer and the lower barrier layer, and is located on one side of the lower etch stop layer.

17. The semiconductor device of claim 16, further comprising: The lower contact penetrates the lower barrier layer and is electrically connected to at least one of the first doped region and the second doped region and the lower wiring.

18. The semiconductor device of claim 15, further comprising: The upper wiring is located at a height higher than the active pattern and the doped bottom pattern; as well as The upper contact extends in a first direction over at least one of the first doped region and the second doped region. The bottom surface of the upper contact is positioned at a height corresponding to the bottom surface of the gate electrode.

19. The semiconductor device of claim 18, further comprising: The upper source / drain contact extends in a first direction on the source / drain pattern, and the top surface of the upper source / drain contact is coplanar with the top surface of the upper contact. as well as An upper etch stop layer is applied to the top surface of the upper source / drain contact and the top surface of the upper contact.

20. A semiconductor device, comprising: A lower insulating layer and a lower barrier layer, wherein the lower insulating layer is in a first region and the lower barrier layer is in a second region; An active pattern is on a lower insulating layer and includes a plurality of channel patterns stacked and spaced apart from each other in a first direction; Gate electrodes, surrounding the plurality of channel patterns; Source / drain pattern, on one side of the plurality of channel patterns; The bottom pattern is doped on the lower barrier layer and includes a first well region and a second well region superimposed in a second direction intersecting the first direction; A device isolation layer is located in the second direction between the active pattern and the doped bottom pattern; The first doped region is formed on the upper side of the first well region; The second doped region is formed on the upper side of the second well region and is positioned at a height corresponding to the first doped region. The first upper contact extends in a first direction over a first doped region; The second upper contact extends in the first direction over the second doped region; The upper wiring and the lower wiring are located at a height higher than the active pattern and the doped bottom pattern, and the lower wiring is located at a height lower than the lower insulating layer and the lower barrier layer. The lower source / drain contact is positioned on the source / drain pattern through the lower insulating layer and electrically connects the source / drain pattern and the lower wiring. as well as The conductive post extends in the first direction and connects the upper wiring and the lower wiring.

Images