Cell region of semiconductor device and method for manufacturing the same

Abstract

Embodiments of the present application relate to a cell region of a semiconductor device and a method of manufacturing the same. The cell region (of the semiconductor device) includes: first and second active regions located on opposite sides of a first reference line and adjacent to the first reference line and doped with different dopants accordingly; and dummy gate segments, each of which overlaps with the active regions; corresponding AR portions of the active regions are defined between adjacent dummy gate segments; each of the first and second active regions includes adjacent first and second AR portions; the first and second AR portions define first and second AR segments; each of the first and second AR segments has first and second profiles located at proximal and distal ends of the first reference line accordingly; and the proximal profile of each of the first and second AR segments is planar; and the distal profile of the first or second AR segment is stepped, such that the first or second AR segment is a concave polygonal shape.

Description

Technical Field

[0001] Embodiments of this application relate to cell regions of semiconductor devices and methods for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of analog and digital devices to solve problems in many different fields. Advances in semiconductor process technology nodes have gradually reduced component size and spacing, leading to a gradual increase in transistor density. ICs have become smaller and smaller. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a cell region of a semiconductor device is provided, the cell region comprising: an active region extending along a first direction and including a first active region and a second active region; the first active region and the second active region being located on opposite sides of a first reference line extending parallel to the first direction, adjacent to a second direction perpendicular to the first direction, and correspondingly configured with different first type dopants and second type dopants; and dummy gate segments extending in the second direction, each dummy gate segment overlapping the active region; corresponding AR portions of the active regions being defined between adjacent dummy gate segments in the first direction; each of the first active region and the second active region including a first AR portion and a second AR portion in the adjacent AR portions in the first direction; the first AR portion and the second AR portion defining a first AR segment and a second AR segment; each of the first AR segment and the second AR segment having a first profile and a second profile relative to the second direction, the first profile and the second profile being close to and far from the first reference line, respectively; and the proximal profile of each of the first AR segment and the second AR segment being planar; and the distal profile of the first AR segment or the second AR segment being stepped, such that the first AR segment or the second AR segment is a concave polygonal shape.

[0004] According to one aspect of the embodiments of this application, a cell region of a semiconductor device is provided, the cell region comprising: an active region extending along a first direction and including a first active region and a second active region; the first active region and the second active region being located on opposite sides of a first reference line extending parallel to the first direction, adjacent to a second direction perpendicular to the first direction, and correspondingly configured with different first type dopants and second type dopants; and dummy gate segments extending in the second direction, each dummy gate segment overlapping the active region; corresponding AR portions of the active regions being defined between adjacent dummy gate segments in the first direction; each of the first active region and the second active region including a first AR portion in the adjacent AR portion in the first direction. The first AR segment and the second AR segment define a first AR segment and a second AR segment; each of the first AR segment and the second AR segment has a first profile and a second profile relative to a second direction, the first profile and the second profile correspondingly close to and far from a first reference line; and the distal profile of the first AR segment or the second AR segment is stepped, such that the first AR segment or the second AR segment is a concave polygonal shape; a gate segment extending along the second direction and including a first gate segment and a second gate segment; each of the first gate segment and the second gate segment overlaps with a first active region and a second active region; each of the first gate segment and the second gate segment hangs over the distal profile with a substantially uniform overhang distance.

[0005] According to another aspect of the embodiments of this application, a method for manufacturing a cell region of a semiconductor device is provided, the method comprising: forming an active region extending along a first direction and including a first active region and a second active region, the first active region and the second active region being located on opposite sides of a first reference line extending parallel to the first direction, adjacent to a second direction perpendicular to the first direction, and correspondingly configured with different first type dopants and second type dopants; and forming dummy gate segments extending along the second direction, each dummy gate segment overlapping the active region; and wherein: corresponding AR portions of the active region are defined between adjacent dummy gate segments in the first direction; the first active region... Each of the region and the second active region includes a first AR portion and a second AR portion in an AR portion adjacent in a first direction; the first AR portion and the second AR portion define a first AR segment and a second AR segment, and each of the first AR segment and the second AR segment has a first profile and a second profile relative to the second direction, the first profile and the second profile correspondingly being closer to and farther from the first reference line; and forming the active region includes adjusting the width of the AR portion as follows: the proximal profile of each of the first AR segment and the second AR segment is planar, and the distal profile of the first AR segment or the second AR segment is stepped, such that the first AR portion or the second AR portion is a concave polygonal shape. Attached Figure Description

[0006] In the accompanying drawings, one or more embodiments are shown by way of example and not limitation, wherein elements having the same reference numerals denote the same elements throughout. Unless otherwise disclosed, the drawings are not drawn to scale.

[0007] Figure 1 These are block diagrams based on some embodiments.

[0008] Figures 2A-2B These are layout diagrams based on some embodiments.

[0009] Figure 3 This is a layout diagram based on some embodiments.

[0010] Figures 4A-4D These are layout diagrams based on some embodiments.

[0011] Figures 5A-5B These are corresponding sections based on some embodiments.

[0012] Figure 6 and Figure 7 This is a flowchart of a corresponding method according to some embodiments.

[0013] Figure 8 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0014] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, operations, arrangements, etc., may be considered. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spacing relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing relation terms are intended to include different orientations of the device during use or operation. Devices may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relation descriptors used herein can be interpreted accordingly. In some embodiments, the term standard cell structure refers to standardized building blocks included in various standard cell structure libraries. In some embodiments, various standard cell structures are selected from their libraries and used as components in layout diagrams representing circuits.

[0017] In some embodiments, the cell region (of the semiconductor device) includes: first and second active regions located on opposite sides of a first reference line and adjacent to the first reference line, and respectively doped with different dopants; and dummy gate segments, each dummy gate segment overlapping an active region; corresponding AR (active region) portions of the active regions are defined between adjacent dummy gate segments; each of the first and second active regions includes adjacent first AR portions and second AR portions; the first AR portions and second AR portions define first AR segments and second AR segments; each of the first and second AR segments has a first profile and a second profile respectively proximate and distant from the first reference line; and the proximal profile of each of the first and second AR segments is planar; and the distal profile of the first or second AR segment is stepped, such that the first or second AR segment is a concave polygonal shape. In some embodiments, the cell region further includes: a first dielectric structure and a second dielectric structure respectively adjacent to a first end and a second end of the first gate segment; a third dielectric structure and a fourth dielectric structure respectively adjacent to a first end and a second end of the second gate segment. The length of at least one of the first to fourth dielectric structures differs from the other dielectric structures in the first to fourth dielectric structures. Consider a cell region based on another method, which is the counterpart of this cell region.

[0018] The corresponding cell region has a planar near-end profile of the corresponding AR segment, and the corresponding AR segment has a stepped far-end profile. Since the corresponding far-end profile is planar and the height of the corresponding dielectric structure is uniform, the corresponding gate segments have the same length.

[0019] In addition, the effective capacitance of the cell region depends on the gate segment length. At least in part, because the distal profile of the first AR segment is stepped or the distal profile of the second AR segment is stepped, one or more gate segments have different lengths, such that at least one gate segment is shorter than the corresponding gate segment of the corresponding cell region. Therefore, due to the different lengths of the gate segments, the effective capacitance of the cell region is lower than the equivalent capacitance of the corresponding cell region. In some embodiments, the equivalent capacitance of the cell region is about 2% to about 10% lower than the effective capacitance of the corresponding cell region.

[0020] The threshold voltage (Vt) of a transistor depends particularly on the distance between the AR section and the adjacent N / P boundary. Since the proximal profile of each of the first and second AR segments is planar, the distance between the reference line and each AR section of at least one pair of vertically adjacent AR sections is less than the corresponding distance in the corresponding cell region. Therefore, the threshold voltage of the transistor in at least one pair of vertically adjacent AR sections is greater than the corresponding threshold voltage of the corresponding transistor in the corresponding AR section of the corresponding cell region. Furthermore, the leakage of the transistor in the cell region (cell region leakage) is inversely proportional to the threshold voltage of the transistor in the cell region. Therefore, the leakage in this cell region is lower than the leakage in the corresponding cell region. In some embodiments, the leakage current in this cell region is about 5% to about 30% lower than the leakage in the corresponding cell region.

[0021] Figure 1 This is a block diagram of cell region 102 of device 100 according to some embodiments.

[0022] Device 100 is an example of an integrated circuit (IC). In some embodiments, device 100 is referred to as a semiconductor device. Device 100 includes a macro region 101. Macro region 101 includes a functional unit region 102. In some embodiments, functional unit region 102 includes one or more active devices, passive devices, etc. Examples of active devices or active elements include, but are not limited to, transistors, diodes, etc. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, etc.

[0023] In some embodiments, macroregion 101 comprises one or more instances of functional unit region 102 and / or one or more other functional unit regions. In such embodiments, macroregion 101 is configured to provide / perform a given computational function, which comprises less complex functions correspondingly provided by instances of functional unit region 102 and / or one or more other functional unit regions. In some embodiments, one or more instances of functional unit region 102 and / or one or more other functional unit regions represent mutually coupled building blocks including macroregion 101.

[0024] In some embodiments, macro region 101 is understood to be similar to an architectural hierarchy in modular programming, where subroutines / procedures are called by a main program (or other subroutines) to perform a given computational function. In this context, device 100 uses macro region 101 to perform one or more given functions. Therefore, in this case, in terms of architectural hierarchy, device 100 is analogous to a main program, and macro region 101 is analogous to a subroutine / procedure. In some embodiments, macro region 101 is a software macro. In some embodiments, macro region 101 is a hardware macro. In some embodiments, macro region 101 is a software macro described numerically in register-transfer-level (RTL) code. In some embodiments, macro region 101 has not yet been composed, placed, and routed so that the software macro can be composed, placed, and routed for various process technology nodes. In some embodiments, macro region 101 is a hardware macro described numerically in a binary file format (e.g., Graphical Database System II (GDSII) streaming format), where the binary file format represents the planar geometry, text labels, other information, etc., of one or more layouts of macro region 101 in a hierarchical form. In some embodiments, the binary file format is referred to as a non-text file format. In some embodiments, macro regions 101 have been synthesized, placed, and wired to make the hardware macro specific to a particular process technology node.

[0025] In some embodiments, examples of functions provided by a macro region (e.g., macro region 101) include memory, power grid, clock tree, adder, phase-locked loop (PLL), delay-locked loop (DLL), flip-flop, shift register, analog-to-digital converter (ADC), digital-to-analog converter (DAC), interface, high-level Boolean logic, etc. Examples of memory include static random-access memory (SRAM), dynamic RAM (DRAM), resistive RAM, magnetoresistive RAM (MRAM), read-only memory (ROM), etc. Examples of flip-flops are scan-insertion type D flip-flops (SDFQ), etc. In some embodiments, examples of functions provided by a functional unit area (e.g., functional unit area 102) include inverter, tri-state inverter, buffer, latch, multiplexer (MUX), driver, latch, delay, half adder, full adder, compressor, low-level Boolean logic, etc. Examples of low-level Boolean logic include AND, OR, NAND, NOR, XOR, INV, AOI (AND-OR-Invert), OAI (OR-AND-Invert), etc.

[0026] Functional unit region 102 includes corresponding segments in one or more metallization layers. The figures in this disclosure assume a Cartesian coordinate system (unless otherwise stated), where the first, second, and third directions are, for example, parallel to the X, Y, and Z axes respectively. In some embodiments, the first to third directions correspond to directions other than the X, Y, and Z axes. In some embodiments, in even-numbered metallization layers, the major and minor axes of the segments extend respectively in the first and second directions; in such embodiments, in odd-numbered metallization layers, the major and minor axes of the segments extend respectively in the second and first directions. In such embodiments, the boundaries of functional unit region 102 are described according to the first and second directions.

[0027] In some embodiments, the functional unit region 102 corresponds to a transistor element layer (e.g., see...). Figures 5A-5B This layer has circuit elements, such as transistors, formed during front-end process (FEOL) fabrication. In functional cell region 102, above and / or below the active region (AR) layer (e.g., see...), Figures 5A-5B Various metal layers and corresponding interconnect layers are stacked alternately on and / or under insulating layers during back-end fabrication (BEOL). BEOL fabrication provides power networks and / or wiring for the circuitry of device 100, including macro regions 101 and functional cell regions 102.

[0028] Figure 2A This is a layout diagram of functional unit area (CR) 202A according to some embodiments.

[0029] Unit 202A is Figure 1 Example of functional unit area 102. Figure 2A In the middle, section line 5A-5A' corresponds to Figure 5A Section 502A; Section line 5B-5B' corresponds to Figure 5B Section 502B. Element region 202A is arranged relative to the following: an alpha (α) orbit (or alpha line) extending parallel to the X-axis (not shown) and a beta (β) orbit (β line) extending parallel to the Y-axis (not shown).

[0030] exist Figure 2A In other layout diagrams disclosed herein, it is assumed that the first and second directions correspond to parallel directions to the X and Y axes. In some embodiments, it is assumed that the first and second directions have orientations other than those parallel to the X and Y axes. Figure 2A In other layout diagrams disclosed herein, rows extend parallel to the X-axis and overlap with the corresponding alpha orbits.

[0031] Transistor-based devices consist of cell regions that can be represented by a layout diagram. Figure 2AThe layout diagrams shown herein and other layout diagrams disclosed herein are examples of layout diagrams. Regarding transistors, examples constituting transistor-based devices include field-effect transistors (FETs). Examples of transistor-based device architectures are complementary metal-oxide-semiconductor (CMOS) architectures. FETs include negative-channel metal-oxide-semiconductor (NMOS) FETs (NFETs) and positive-channel metal-oxide-semiconductor (PMOS) FETs (PFETs). Regarding CMOS architectures, examples of FET architectures include planar field-effect transistor (FET) architectures, finFET architectures, gate-all-around (GAAFET) architectures, etc. Examples of GAAFET architectures include nanowire architectures, nanosheet architectures, fork-plate architectures, etc.

[0032] The structure in a transistor-based device is represented by a pattern (also called a shape) in a layout diagram. To simplify the discussion, Figure 2A The elements in the layout diagrams and other layout diagrams disclosed herein will be referred to as structures rather than patterns. For example, Figure 2A The shape of the gate segment instance is referred to as the gate segment itself, not the gate shape.

[0033] A layout diagram is a top view. The shapes in a layout diagram are two-dimensional relative to the X and Y axes, while the devices represented are three-dimensional. Therefore, shapes in such a layout diagram are described as having a width / length relative to the X-axis and a height relative to the Y-axis. Relative to the Z-axis, for example, the bottom / back side of a first component represented in the layout diagram is stacked on top / front of a second component device represented in the layout diagram, or the top / front side of the first component is stacked below the bottom / back side of the second component.

[0034] Typically, devices are organized as stacked layers relative to the Z-axis, with corresponding structures, i.e., the layers to which the respective structures belong. Each shape in the layout diagram more specifically represents a component in the corresponding layer of the corresponding device. Furthermore, the layout diagram typically represents the relative depth of a shape and its corresponding layer, i.e., its position along the Z-axis, by superimposing a second shape on top of a first shape, such that the second shape at least partially overlaps the first shape. For simplicity, some structures in the device that have a first stacking order along the Z-axis are represented in the layout diagram using a second stacking order along the Z-axis, i.e., a different / twisted stacking order.

[0035] Layout diagrams vary in the amount of detail they represent. In some cases, selected layers of a layout diagram are combined / abstracted into a single layer, for example, for simplicity. Or, and / or additionally, in some cases, not all layers of the corresponding device are represented; that is, for example, selected layers of the layout diagram are omitted for simplicity. Or, and / or additionally, in some cases, not all elements of a given depiction layer of the corresponding device are represented; that is, for example, selected elements of a given depiction layer of the layout diagram are omitted for simplicity. The layout diagrams disclosed herein are examples in which selected layers and / or selected elements of a given layer are omitted.

[0036] According to the numbering convention of the corresponding process technology nodes in the manufacturing of devices, on the front side of the device, the first metallization layer is either Metallization Layer Zero (MET0) or Metallization Layer One (MET1), and correspondingly, the first interconnect layer on the first metallization layer is Interconnect Layer Zero (VIA0) or Interconnect Layer One (VIA1). In such an embodiment, also depending on the numbering convention of the corresponding process technology nodes, on the back side of the device (not shown), the first buried metallization layer is either Buried Metallization Zero (BMET0) or Buried Metallization Layer One (BMET1), and correspondingly, the first buried interconnect layer under the first metallization layer is Interconnect Layer Zero (VIA0) or Interconnect Layer One (VIA1).

[0037] Generally, regarding the figures disclosed herein (unless otherwise stated), the following naming convention is used for the front side of the device: The first metallization layer is assumed to be MET0; the first interconnect layer is assumed to be VIA0; the second metallization layer is assumed to be MET1; the second interconnect layer is assumed to be VIA1; and the third metallization layer is assumed to be MET2. The metallized segment in the MET0 layer is called the M0 segment. The via structure in layer VIA0 is called the V0 structure. The metallized segment in the MET1 layer is called the M1 segment. The via structure in layer VIA1 is called the V1 structure. The metallized segment in the MET2 layer is called the M2 segment.

[0038] Generally, for the figures disclosed herein (unless otherwise stated), the following naming convention is used for the back side of the device: Assume the first buried metallization layer is BMET0; assume the first buried interconnect layer is BVIA0; assume the second buried metallization layer is BMET1; assume the second buried interconnect layer is BVIA1; assume the third buried metallization layer is BMET2. The metallized segment in layer BMET0 is called the buried M0 (BM0) segment. The via structure in layer BVIA0 is called the BV0 structure. The metallized segment in layer BMET1 is called the buried M1 (BM1) segment. The via structure in layer BVIA1 is called the BV1 structure. The metallized segment in layer BMET2 is called the buried M2 (BM2) segment.

[0039] exist Figure 2AIn the cell region 202A, the cell region includes: a negative (n-type) active region 208N(1) extending substantially parallel to the X-axis and used for the corresponding NFET; an n-type well (n-well) 205(1); a positive (p-type) active region 208P(1) extending substantially parallel to the X-axis, located in the N-well 205(1), and used for the corresponding PFET; gate segments 210(1)-210(2) extending substantially parallel to the Y-axis; pseudo-gate segments 212(1)-212(3) extending substantially parallel to the X-axis; metal-to-source / drain contact (MD) structures 214(1)-214(4) extending substantially parallel to the X-axis; and diced gate (CG) shapes (or patterns) 206(1)-206(4) (also referred to as 206(1)-206(4)). It should be understood that, based on a layout diagram including a given CG shape (e.g., Figure 2A During the fabrication of the corresponding semiconductor device, the portion of the corresponding gate segment (e.g., 210(1) or 210(2)) that overlaps with the given CG shape (e.g., 206(1)-206(4)) will be removed. Therefore, in some embodiments, each CG shape (e.g., 206(1)-206(4)) represents a dielectric structure (discussed below) that replaces the portion of the corresponding gate segment (e.g., 210(1)-210(2)) that overlaps with the CG shape (e.g., 204(1)-306(4”)). In some embodiments, dielectric structures 206(1)-206(4) are referred to as cut-off gate (CG) structures 206(1)-206(4). In some embodiments, dielectric structures 206(1)-206(4) are described as byproducts of trimming the precursor portions of the gate segments located below the corresponding CG shapes (e.g., 206(1), 206(4)), such as the precursors of gate segments 210(1) and 210(2).

[0040] In some embodiments, the dummy gate segments (e.g., 212(1)-212(3)) are gate segments not coupled to a voltage source. In some embodiments, the dummy gate segments are gate segments not coupled to a voltage source (e.g., VDD, VSS, etc.). In some embodiments, the dummy gate segments are isolated dummy gate (IDG) structures. In some embodiments, the isolated dummy gate (IDG) structure is a dielectric structure comprising one or more dielectric materials and used as an electrical isolation structure. Therefore, the IDG structure is not a conductive structure and therefore does not have a function, e.g., as an active gate of a transistor. The IDG structure comprises one or more dielectric materials and used as an electrical isolation structure. In some embodiments, the IDG structure is based on a gate segment as a precursor. In some embodiments, the IDG structure is based on a dummy gate structure. In some embodiments, the dummy gate structure includes decoupled gate segments to form non-functional gate segments, e.g., as a gate of a transistor, a gate insulating layer, (optionally) one or more spacers, etc. In some embodiments, the IDG structure is formed by the following steps: first, forming a gate segment, for example, included in a dummy gate structure; sacrificing / removing (e.g., etching) the gate segment to form a trench; (optionally) removing portions of the substrate previously located below, above, or around the gate segment to deepen the trench; and then filling the trench with one or more dielectric materials such that the physical dimensions of the resulting electrically isolated structure (i.e., the IDG) are similar to the dimensions of the sacrificed gate segment. In some embodiments, the IDG is a dielectric component comprising one or more dielectric materials (e.g., oxides, nitrides, oxynitrides, or other suitable materials) and used as an isolation component. In some embodiments, the IDG is continuous polysilicon on an oxide diffusion (OD) edge structure, referred to as a CPODE structure.

[0041] exist Figure 2A In the middle, the active regions 208N(1) and 208P(1) are located on opposite sides of the reference line 222(1) extending parallel to the X-axis, and are adjacent (perpendicularly adjacent) relative to the Y-axis. Figure 2A It is assumed that reference line 222(1) represents the boundary between the NMOS and PMOS regions of cell region 202A. In some embodiments, reference line 222(1) does not represent the boundary between the NMOS and PMOS regions of cell region 202A. Figure 2A It is also assumed that reference line 222(1) represents the boundary of N-well 205(1). In some embodiments, the boundary of N-well (e.g., reference line 222(1)) is referred to as the N / P boundary or the P / N boundary. In some embodiments, reference line 222(1) does not represent the boundary of N-well.

[0042] Each of the gate segments 210(1)-210(2), the pseudo-gate segments 212(1)-222(3), and the MD structures 214(1)-244 overlaps with each of the active regions 208N(1) and 208P(1). In the case where a portion of one of the MD structures 214(1)-214(4) overlaps with an active region (e.g., active regions 208N(1) and 208P(1)), the corresponding overlapping sub-region of the active region is relatively more heavily doped to serve as the source / drain (S / D) region of the corresponding transistor. In the case where a portion of one of the gate segments 210(1)-210(2) overlaps with an active region (e.g., active regions 208N(1) and 208P(1)), the corresponding overlapping sub-region of the active region is configured to serve as the channel region of the corresponding transistor. Therefore, compared to, for example, the S / D region, the overlapping sub-region of the gate segment of the active region is not relatively more heavily doped.

[0043] The corresponding AR portions of active regions 208N(1) and 208P(1) are defined between adjacent (horizontally adjacent) pseudo-gate segments 212(1)-212(3) relative to the X-axis. Active region 208N(1) includes AR portions 218N(1) and 218N(2). Active region 208P(1) includes AR portions 218P(1) and 218P(2). Each pair of horizontally adjacent AR portions defines a corresponding AR segment. Therefore, AR portions 218N(1) and 218N(2) define AR segment 204N(1) of active region 218N(1), and AR portions 218P(1) and 218P(2) define AR segment 204P(1) of active region 218P(1).

[0044] In some embodiments, relative to the Y-axis: cell region 202A is stacked on (e.g., adjacent to) another cell region, such as another instance of cell region 202A or a different cell region; and / or cell region 202A is stacked below (e.g., adjacent to) another cell region, such as another instance of cell region 202A or a different cell region. In some embodiments, relative to the X-axis: cell region 202A is adjacent to (e.g., to the left) another cell region, such as another instance of cell region 202A or a different cell region; and / or cell region 202A is right adjacent to (e.g., to the right) another cell region (e.g., another instance of cell region 202A or a different cell region).

[0045] Relative to the Y-axis: The AR portion 218N(1) has sides sde_21 and sde_22; the AR portion 218N(2) has sides sde_23 and sde_24; the AR portion 218P(1) has sides sde_25 and sde_26; the AR portion 218P(2) has sides sde_27 and sde_28. Each of the sides sde_21 - sde_28 is substantially planar. The sides sde_21 - sde_28 are substantially parallel. The sides sde_22 and sde_24 are substantially collinear. The sides sde_21 and sde_23 are substantially non - collinear. The sides sde_25 and sde_27 are substantially collinear. The sides sde_26 and sde_28 are substantially non - collinear.

[0046] In terms of the distance from the Y-axis to the reference line 222(1): The side sde_22 is proximal, while the side sde_21 is distal; the side sde_24 is proximal, while the side sde_23 is distal; the side sde_25 is proximal, while the side sde_26 is distal; the side sde_27 is proximal, while the side sde_28 is distal.

[0047] In terms of the distance from the Y-axis to the reference line 222(1): The AR segment 208N(1) has a proximal profile formed by the sides sde_22 and sde_24 and a distal profile formed by the sides sde_21 and sde_23; the AR segment 208P(1) has a proximal profile formed by the sides sde_25 and sde_27 and a distal profile formed by the sides sde_26 and sde_28. The proximal profile of the AR segment 208N(1) is substantially planar. The distal profile of the AR segment 208N(1) is stepped. The proximal profile of the AR segment 208P(1) is substantially planar. The distal profile of the AR segment 208P(1) is stepped.

[0048] Each of the AR segments 204N(1) and 204P(1) has a concave polygon shape. In some embodiments, a concave polygon is defined as a polygon having one or more interior angles greater than 180 degrees (180°). The interior angle of the AR segment 204N(1) is 220(1), where The AR segment 204P(1) has an interior angle 220(2), where

[0049] Relative to the Y-axis: Each of the AR portions 218N(1) and 218P(1) has a width Wnom; each of the AR portions 218N(1) and 218P(1) has a width Ws, where the width Ws is different from the width Wnom such that Ws < Wnom. The width Ws is equal to or greater than the width Wmin such that Wmin ≤ Ws < Wnom, where the width Wmin is the minimum width of the active region set by one or more design rules according to the corresponding semiconductor process technology node.

[0050] The difference HcΔ1 between the width Wnom and Ws represents the step size of each of the AR segments 204N(1) and 204P(1), such that HcΔ1 = Wnom - Ws, where 0 < Wmin ≤ HcΔ1. In some embodiments, the step size is referred to as the jog size.

[0051] With respect to the Y-axis, the cell region 202A has a height Hcr, and the AR portions 218N(1) and 218P(2), and 218N(2) and 218P(2) are separated by a gap (i.e., the AR portion-to-portion distance) having a size Sarp; the size Sarp is the sum of the distance DNarp and the distance DParp. The distance DNarp is the distance from the reference line 222(1) to each of the sides sd_22 of the AR portion 218N(1) and sde_24 of the AR portion 218N(2). The distance DParp is the distance from the reference line 222(1) to each of the sides sd_25 of the AR portion 218P(1) and sde_27 of the AR portion 218P(2). Figure 2A It is assumed that the distance DNarp is substantially equal to the distance DParp, such that DNarp ≈ DParp.

[0052] The size Sarp is equal to or greater than the size Smin, such that Smin ≤ Sarp, where the width Smin is the minimum distance set according to one or more design rules of the corresponding semiconductor process technology node.

[0053] In Figure 2A each of the gate segments 210(1) and 210(2) overhangs above the distal profile of the AR segments 204N(1), 204P(1) with a substantially uniform overhang distance Dovh with respect to the Y-axis. In Figure 2A it is assumed that the distance Dovh is substantially equal to the minimum overhang distance Dovhmin, where the distance Dovhmin is the minimum distance of the overhang of the gate segment set by one or more design rules of the corresponding semiconductor process technology node. In some embodiments, Dovhmin < Dovh.

[0054] In Figure 2AIn this context, the gate segment length is considered to be relative to the Y-axis. Gate segment 210(1) is longer than gate segment 210(2). Because the distal profile of AR segment 204N(1) is stepped, the distance between the end of gate segment 210(2) hanging above AR portion 218N(2) and reference line 222(1) is not as far as the end of gate segment 210(1) hanging above AR portion 218N(1). Because the distal profile of AR segment 204P(1) is stepped, the distance between the end of gate segment 210(2) hanging above AR portion 218P(2) and reference line 222(1) is not as far as the end of gate segment 210(1) hanging above AR portion 218P(1). Therefore, the length L_210(2) of gate segment 210(2) is less than the length L_210(1) of gate segment 210(1), such that L_210(1) <L_210(2)。

[0055] exist Figure 2A In this configuration, the ends of gate segment 210(1) are respectively adjacent to dielectric structures 206(1) and 206(2). The ends of gate segment 210(2) are respectively adjacent to dielectric structures 206(3) and 206(4). In some embodiments, dielectric structures 206(1)-206(4) are formed of a dielectric material (e.g., a dielectric material) different from the gap material (not shown) that fills the gap space around dielectric structures 206(1)-206(4), for example, the gap material is another dielectric material. In some embodiments, dielectric structure 206(1) is formed of a nitride material, while the gap material is an oxide, and vice versa. In some embodiments, dielectric structures 206(1)-206(4) are formed of the same material as the gap material, making the dielectric structures easier to identify (or recognize) in the corresponding layout diagram than in a device manufactured according to the layout diagram.

[0056] The height of each of the dielectric structures 206(1)-206(4) varies relative to the Y-axis to achieve a dangling distance Dovhmin for the corresponding end of the corresponding gate segment. Typically, the height of the dielectric structures 206(1)-206(4) is inversely proportional to the width of the corresponding AR portion. Since each of the AR portions 218N(1) and 218P(1) has a width Wnom, the height of each of the dielectric structures 206(1) and 206(2) is correspondingly 1 / 2 * Hcnom.

[0057] Figure 2AAssume Hcnom is Hcmin, where Hcmin is the minimum height of the dielectric structure (e.g., 206(1)-206(4)) set by one or more design rules of the corresponding semiconductor process technology node. In some embodiments, Hcmin < Hcnom. Since each of the AR portions 218N(2) and 218P(2) has a width Ws, the height of each of the dielectric structures 206(3) and 206(4) is relatively greater than the height of each of the AR portions 218P(1) and 218N(1). Therefore, the height of each of the dielectric structures 206(3) and 206(4) is correspondingly 1 / 2 * Hcnom + HcΔ2. With respect to the distance Dovhmin of each overhang end of each gate segment 210(1) and 210(2), Dovhmin = 1 / 2 * (Smin - Hcmin). The cell region height Hcr ≤ 2 * (Wnom + Smin).

[0058] Consider a cell region according to another method, which is the counterpart of cell region 202A. The corresponding cell region has corresponding portions corresponding to AR segments 204N(1) and 204P(1) and corresponding portions corresponding to gate segments 210(1)-210(2). The proximal profile of the corresponding AR segment is planar, while the distal profile of the corresponding AR segment is stepped. The corresponding cell region has portions corresponding to dielectric structures 206(1)-206(4), wherein the corresponding dielectric structures have a uniform height. Since the corresponding distal profile is planar and the height of the corresponding dielectric structure is uniform, the corresponding gate segments have the same length.

[0059] In addition, the effective capacitance of the cell region depends on the gate segment length. At least in part, due to the stepped distal profile of AR segment 204N(1) and AR segment 204P(1), the gate segments 210(1) and 210(2) have different lengths, such that the length of gate segment 210(2) is shorter than the corresponding gate segment of the corresponding cell region. Therefore, due to the different lengths of gate segments 210(1) and 210(2), the effective capacitance of cell region 202A is lower than that of the corresponding cell region. In some embodiments, the effective capacitance of cell region 202A is about 2% to about 10% lower than that of the corresponding cell region. Other cell regions disclosed herein advantageously exhibit a similar reduction in effective capacitance compared to their respective corresponding cell regions.

[0060] The threshold voltage (Vt) of a transistor depends in particular on the distance between the AR portion and the adjacent N / P boundary. Since the proximal profiles of each AR segment 204N(1) and 204P(1) are planar, the distance between AR portions 218N(2) and 218P(2) and reference line 222(1) is smaller than the corresponding distance of the corresponding cell region. Therefore, the threshold voltage of the transistors in AR portions 218N(2) and 218P(2) is greater than the corresponding threshold voltage of the corresponding transistor in the corresponding AR portion of the corresponding cell region. The leakage of the transistor in the cell region (cell region leakage) is inversely proportional to the threshold voltage of the transistor in the cell region. Therefore, the leakage of cell region 202A is lower than that of the corresponding cell region. In some embodiments, the leakage of cell region 202A is about 5% to about 30% lower than that of the corresponding cell region. Other cell regions disclosed herein advantageously exhibit similar reduced leakage compared to their corresponding corresponding cell regions.

[0061] Figure 2B This is a layout diagram of functional unit area (CR) 202B according to some embodiments.

[0062] Unit 202B is similar to Figure 2A Cell region 202A. For the sake of brevity, the discussion will focus on the differences between cell region 202B and cell region 202A, rather than their similarities. Generally speaking, compared to cell region 202A: cell region 202B has more AR parts and AR segments; the width of the AR parts has more variation.

[0063] Unit region 202B includes: active regions 208N(2), 208N(3), 208P(2) and 208P(3); N-well 205(2); reference lines 222(2) and 222(3); and AR segments

[0056] 204N(2), 204N(3), 204N(4), 204N(5), 204P(2), 204P(3), 204P(4) and 204P(5).

[0064] Each of the active regions 208N(2) and 208P(2) includes a high AR portion with a width Wt and an AR portion with a cell width Wsngl. In some embodiments, the width Wt is in the range of Wnom ≤ Wt ≤ (≈3*Wnom).

[0065] Each of the active regions 208N(3) and 208P(3) includes a high AR portion with a width Wt and an AR portion with a cell width Wsngl. In some embodiments, the width Wsngl is in the range of (≈0.8*Wnom)≤Wt≤(≈1.2*Wnom).

[0066] Figure 3This is a layout diagram of the functional unit area (CR) 302 according to some embodiments.

[0067] Unit 302 is similar to Figure 2B Cell region 202B. For the sake of brevity, the discussion will focus on the differences between cell region 302 and cell region 202B, rather than their similarities. Generally, the AR inter-part distance value of cell region 302 differs from that of cell region 202B, which has a uniform AR inter-part distance Sarp.

[0068] To simplify Figure 3 The diagram does not show all the structures. Cell region 302 includes: active regions 308N(1), 308N(2), 308P(1), and 308P(2); an N-type well; reference lines 322(1) and 322(2); and AR sections 318N(11), 318N(12), 318N(13), 318N(14), 318N(15), 318N(16), 318N(17), and 318N(18). 318P(11), 318P(12), 318P(13), 318P(14), 318P(15), 318P(16), 318P(17) and 318P(18); and AR segments 304N(1), 304N(2), 304N(3), 304N(4), 304P(1), 304P(2), 304P(3) and 304P(4). The dielectric structure includes dielectric structures 306(1)-306(4).

[0069] Relative to reference line 322(1): AR portion 318N(13) has a proximal sd_31; AR portion 318N(14) has a proximal sd_32; AR portion 318P(13) has a proximal sd_33; AR portion 318P(14) has a proximal sd_34.

[0070] Cell region 302 includes two values ​​of the distance between AR parts, namely S1 and S2. For example, sides sde_31 and sde_33 are separated by the distance between AR parts S1, and sides sde_33 and sde_34 are separated by the distance between AR parts S2, where Smin ≤ S2. <S1。

[0071] Figure 4A This is a layout diagram of functional unit area (CR) 402A according to some embodiments.

[0072] Unit 402A is similar to Figure 3 Cell region 302. For the sake of brevity, the discussion will focus on the differences between cell region 402A and cell region 302, rather than their similarities. Typically, compared to cell region 302, cell region 402A includes a pseudo-AR portion and an N-well with varying width.

[0073] To simplify Figure 4A The diagram does not show all the structures. Unit region 402A includes: active regions 408N(1), 408N(2), 408P(1) and 408P(2); N-well 405(1); reference lines 422(1), 422(2) and 422(3); AR sections 418N(11), 418N(12), 418N(13), 418N(14), 418N(15), 418N(16), 418P(11), 418P(12), 418P(13) and 418P(14); pseudo AR sections (DAR sections) 424N(1), 424N(2) and 424P(3); and AR segments 404N(1), 404N(2) and 404P(1). The N-well 405(1) includes NW portions 426(1) and 426(2). The dummy gates include dummy gates 412(1) and 412(2).

[0074] AR portions 418N(11) and 418P(11) represent the CR portion 428(1) of cell region 402A. The CR portion 428(1) has an NMOS-PMOS (NP) arrangement relative to the Y-axis. AR portions 418P(14) and 418N(14) represent the CR portion 428(2) of cell region 402A. The CR portion 428(2) has a PMOS-NMOS (PN) arrangement relative to the Y-axis. AR segments 404N(1), 404P(1), and 404N(2) together represent the CR portion 428(3) of cell region 402A. Alternatively, AR portions 418N(12)-418N(13), 418P(12)-418P(13), and 418N(15)-418N(16) represent the CR portion 428(3) of cell region 402A. The CR section 428(3) has an NMOS-PMOS-NMOS (NPN) arrangement relative to the Y-axis.

[0075] Relative to the Y-axis: NW portion 426(1) has an upper side sde_41 and a lower side sde_43; NW portion 426(1) has a width d1; NW portion 426(2) has an upper side sde_42 and a lower side sde_44; NW portion 426(2) has a width d2. NW portion 426(2) is narrower than NW portion 426(1) such that d2 < d1.

[0076] Relative to the X-axis, each DAR section extends between corresponding adjacent dummy gates. Figure 4AIn this structure, each of the DAR portions 424N(1), 424N(2), and 424P(1) extends between the dummy gates 412(1) and 412(2). In some embodiments, a DAR portion is defined as an AR portion in which there is no source / drain (S / D) region, i.e., no region in which there is relatively more doped compared to the S / D region. In some embodiments, a DAR portion is defined as an AR portion without an overlying gate segment. Each DAR portion serves as an isolation structure. DAR portion 424N(1) isolates AR portion 418N(11) from AR portion 418N(12). DAR portion 424P(2) isolates each of AR portions 418P(11) and 418P(14) from AR portion 414P(12). DAR portion 424N(2) isolates AR portion 418N(14) from AR portion 418N(15).

[0077] exist Figure 4A In the middle, relative to the Y-axis, each of the CR parts 428(1) and 428(2) has a height H41, and the cell region 402A has a height H42, where H42 = (≈2.0*H41); the width W41 is in the range of Wmin≤W41≤W42; the width W42 is W42 = W41 + n*W45, where n is a positive integer, W42≤(≈1.5*W42), W45 is the width of the protrusion between (A) AR parts 418N(12) and 418N(13) and (B) AR parts 418N(15) and 418N(16); the width W43 is in the range of (≈1.5*W41)≤W43≤(≈2.0*W41); the width W44 is in the range of (≈1.5*W41)≤W44≤(≈W43).

[0078] Figure 4B This is a layout diagram of functional unit area (CR) 402B according to some embodiments.

[0079] Unit 402B is similar to Figure 4A Cell region 402A. For the sake of brevity, the discussion will focus on the differences between cell region 402B and cell region 402A, rather than their similarities. Typically, the NMOS and PMOS regions are reversed compared to cell region 402A, thus there are two N-wells instead of one.

[0080] To simplify Figure 4BThe diagram does not show all the structures. Unit region 402B includes: active regions 408P(2), 408P(3) and 408N(3); N-wells 405(2) and 405(3); reference lines 422(4), 422(5) and 422(6); and AR sections 418P(21), 418P(22), 418P(23), 418P(24), 418P(25), 418P(26), 418N(21), 418N(22), 418N(23) and 418N(24); DAR sections 424P(2), 424P(3) and 424N(3); and AR segments 404P(2), 404P(3) and 404N(3). N-well 405(2) includes NW sections 426(3) and 426(4). The N-well 405(3) includes NW portions 426(5) and 426(6). The dummy gates include dummy gates 412(3) and 412(4).

[0081] AR portions 418P(21) and 418N(21) represent the CR portion 428(4) of cell region 402B. The CR portion 428(4) has a PMOS-NMOS(PN) arrangement relative to the Y-axis. AR portions 418N(24) and 418P(24) represent the CR portion 428(5) of cell region 402B. The CR portion 428(5) has an NMOS-PMOS(PN) arrangement relative to the Y-axis. AR segments 404P(2), 404N(3), and 404P(3) together represent the CR portion 428(6) of cell region 402B. Alternatively, AR portions 418P(22)-418P(23), 418N(22)-418N(23), and 418P(25)-418P(26) represent the CR portion 428(6) of cell region 402B. The CR section 428(6) has a PMOS-NMOS-PMOS (PNP) arrangement relative to the Y-axis.

[0082] Relative to the Y-axis: NW portion 426(3) has a lower side sde_45; NW portion 426(3) has a width d3; NW portion 426(4) has a lower side sde_46; NW portion 426(4) has a width d4; NW portion 426(5) has an upper side sde_47; NW portion 426(5) has a width d3; NW portion 426(6) has an upper side sde_48; NW portion 426(5) has a width d4. NW portion 426(3) is narrower than NW portion 426(4), and NW portion 426(5) is narrower than NW portion 426(6), such that d3 <d4。

[0083] Relative to the X-axis, each DAR section extends between corresponding adjacent dummy gates. Figure 4BIn this configuration, each of the DAR portions 424N(1), 424N(2), and 424P(1) extends between the dummy gates 412(1) and 412(2). The DAR portion 424P(2) isolates the AR portion 418P(21) from the AR portion 418P(22). The DAR portion 424N(3) isolates each of the AR portions 418N(21) and 418N(24) from the AR portion 418N(22). The DAR portion 424P(3) isolates the AR portion 418(24) from the AR portion 418P(25).

[0084] exist Figure 4B In the middle, the relationship between H41 and H42, and the widths W41-W45, are related to... Figure 4A The same as in.

[0085] Figure 4C This is a layout diagram of functional unit area (CR) 402C according to some embodiments.

[0086] The first part of cell 402C is similar to Figure 4A Unit area 402A and Figure 4B Part of cell region 4020B. The second part of cell region 402C is similar to... Figure 2B The section on cell region 202B. For the sake of brevity, the discussion will focus on the differences between cell region 402C and cell regions 402A and 202B, rather than their similarities.

[0087] To simplify Figure 4C The diagram does not show all the structures. Among the other components, cell region 402C includes: active regions 408P(4), 408P(5), 408N(4) and 408N(5); and CR portions 428(7), 428(8) and 428(9).

[0088] The first portion of cell region 402C is represented by CR portion 428(7). CR portion 428(7) is similar to each of CR portion 428(1) of cell region 404A and cell region 428(4) of cell region 404B, but has additional NMOS and PMOS regions arranged in different vertical directions. Relative to the Y-axis, CR portion 428(7) consists of three sub-CR portions stacked on top of each other, including: a first sub-CR portion with a PN arrangement; a second sub-CR portion with an NP arrangement; and a third sub-CR portion with a PN arrangement. Each of the first, second, and third sub-CR portions of CR portion 428(7) has a height H41. Thus, CR portion 428(7) has a PNNPPN arrangement.

[0089] The second part of the aforementioned cell region 402C is represented by CR portions 428(8) and 428(9). Although the combined CR portions 428(8) and 428(9) are similar to cell region 202B, the differences exhibited by the combination of CR portions 428(8) and 428(9) include the following: the NMOS and PMOS regions are reversed, thereby increasing the number of N-wells; and the number of NMOS and PMOS regions is greater than that in cell region 202B.

[0090] Relative to the Y-axis: Each of the CR portions 428(8) and 428(9) has a PN arrangement, and the combination of the CR portions 428(8) and 428(9) has a PNPN arrangement.

[0091] exist Figure 4C In the middle, relative to the Y-axis: cell area 402C has a height H43, where H43 = (≈3.0 * H41); each of CR parts 428(8) and 429(9) has a height H44, where H44 = (≈1.5 * H41); width W46 is in the range of (≈1.5 * W41) ≤ W46 ≤ (≈2.5 * W41); width W47 is in the range of (≈0.8 * W41) ≤ W47 ≤ (≈W46).

[0092] Figure 4D This is a layout diagram of functional unit area (CR) 402D according to some embodiments.

[0093] The first part of cell 402D is similar to Figure 4C Part of cell region 402C. The second part of cell region 402D is similar to... Figure 2A The section of cell region 202A. For the sake of brevity, the discussion will focus on the differences between cell region 402D and cell regions 402C and 202A, rather than their similarities.

[0094] To simplify Figure 4D The diagram does not show all the structures. Among the other components, cell region 402D includes: active regions 408N(6), 408N(7), 408P(6) and 408P(7); and CR portions 428(10) and 428(11).

[0095] The first portion of the aforementioned cell region 402D is represented by CR portion 428(10). CR portion 428(10) is similar to CR portion 428(7) of cell region 404C, but has different vertically arranged NMOS and PMOS regions. Relative to the Y-axis, CR portion 438(10) consists of three sub-CR portions stacked on top of each other, including: a first sub-CR portion with an NP arrangement; a second sub-CR portion with a PN arrangement; and a third sub-CR portion with an NP arrangement. Each of the first, second, and third sub-CR portions of CR portion 428(10) has a height H41. Therefore, CR portion 428(10) has an arrangement of NPPNNP.

[0096] The second part of the aforementioned cell region 402D is represented by CR portion 428(11). Although CR portion 428(11) is similar to cell region 202A, the differences of CR portion 428 include: the NMOS and PMOS regions are reversed, thereby increasing the number of N-wells; and the number of NMOS and PMOS regions is greater than that in cell region 202A. CR portion 428(11) has a PN arrangement relative to the Y-axis.

[0097] exist Figure 4D In the middle, relative to the Y-axis: cell region 402D has a height H45, where H45 = (≈(H41+H42)) = (≈(2.0*(1 / 2*H41)+H42); width W48 is in the range of (≈1.5*W41)≤W48≤(≈4.5*W41”); width W49 is in the range of (≈0.8*W41)≤W49≤(≈W48).

[0098] Figure 5A and Figure 5B These are corresponding cross-sectional views 502A and 502B of the functional unit area according to some embodiments.

[0099] In particular, Figures 5A-5B Based on Figure 2A A cross-sectional view of the element region of element 202A. Figures 5A-5B Corresponding to Figure 2A The cross-sectional lines are 5A-5A' and 5B-5B'.

[0100] Figures 5A-5B Each of the following includes: a P-type substrate 534; an N-well 505 formed in the substrate 534; a P-type fin 530 formed in the N-well 505 relative to the Z-axis portion; an N-type fin 532 formed in the substrate 534 relative to the Z-axis portion; a fin insulator 536 formed on the sides of the fins 530 and 532; and a gate insulating layer 538 formed on the fins 530 and 532 and on the upper surface of the N-well 505, on the fin insulator 536, and on the substrate 534.

[0101] Figure 5A It also includes the MD structure 514(3). Figure 5B It also includes gate segment 510(2). Figures 5A-5B In each of the N-wells 505, fin 530 represents the fin with Figure 2A The active region 208P(1) corresponds to a portion of the active region; fin 532 represents the active region corresponding to... Figure 2A The active region 208N(1) corresponds to the active region portion.

[0102] Figure 6 This is a flowchart (flowchart) of a method 600 for manufacturing a device according to some embodiments.

[0103] According to some embodiments, method 600 can, for example, use EDA system 800 ( Figure 8 (discussed below) and IC Manufacturing System 900 ( Figure 9 (As discussed below) to achieve this. Examples of cell regions and / or macro regions that can be manufactured according to method 600 include the cell regions or macro regions disclosed herein.

[0104] exist Figure 6 In this method 600, blocks 602-604 are included. In block 602, a layout diagram is generated, which includes one or more layout diagrams corresponding to one or more cell regions, one or more macro regions disclosed herein, etc. According to some embodiments, for example, an EDA system 800 can be used (…). Figure 8 (This will be discussed below) to implement block 602. The process proceeds from block 602 to block 604.

[0105] At block 604, based on the layout diagram, (A) one or more photolithographic exposures are performed, or (B) one or more photolithographic masks are fabricated, or (C) at least one of one or more components in the device (e.g., device) layer is fabricated. See below. Figure 9 Discussion of IC manufacturing system 900 in China.

[0106] Figure 7 This is a flowchart of a method 700 for manufacturing a device according to some embodiments.

[0107] Method 700 is an example of block 604 (see discussion above). Figure 6 According to some embodiments, method 700 may, for example, use IC manufacturing system 900 (see...). Figure 9 (Discussed below) to achieve this. Examples of devices that can be manufactured according to method 700 include devices including one or more cell regions or macroscopic regions disclosed herein. Method 700 includes blocks 710-730.

[0108] At block 710, a first (e.g., parallel to the X-axis) extending in a first direction is formed. Figure 2A 208N(1); or similar) and the second (e.g., Figure 2A The 208P(1); or similar) active region. The first active region has a first conductivity type (e.g., Figure 2A The second active region has a second conductivity type different from the first conductivity type (e.g., N-type, etc.). Figure 2A (e.g., P-type in the example). The first (e.g., 208N(1)) and the second (e.g., 208P(1)) active regions are located on opposite sides of a first reference line (e.g., 222(1)) extending parallel to a first direction (e.g., the X-axis), and are adjacent to a second direction perpendicular to the first direction (e.g., parallel to the Y-axis). Within block 710, the process proceeds to block 712.

[0109] At block 712, adjust the width of the AR portion of the active region in the first (e.g., 208N(1)) and second (e.g., 208P(1)) regions. Examples of AR portions include... Figure 2A The AR portions are 218N(1)-218N(2) and 218P(1)-218P(2), etc. Adjacent AR portions of the active region define the AR portion. Examples of AR portions include... Figure 2A AR segments 204N(1) and 204P(1), etc. The adjustment of the width of the AR portion results in the following: the proximal profile of each of the first (e.g., 204N(1)) and the second (e.g., 204P(1)) AR segments is planar; and the distal profile of the first AR segment (e.g., 204N(1)) and / or the second AR segment (e.g., 204P(1)) is stepped, such that the first AR segment (e.g., 204N(1)) and / or the second AR segment (e.g., 204P(1)) is a concave polygonal shape. From block 712, the flow leaves block 710 and proceeds to block 714.

[0110] At block 714, a sub-region of AR is doped to form an S / D region. An example of an S / D region is shown in... Figure 2A The discussion took place against this backdrop. The process proceeded from block 714 to block 716.

[0111] At block 716, a gate segment extending along a second direction (e.g., parallel to the Y-axis) is formed. Figure 2A 210(1)-210(2), etc.), pseudo-gate segment (e.g. Figure 2A 212(1)-220(3) etc.) and dielectric structures (e.g. Figure 2B (e.g., 206(1)-206(4)). The process proceeds from block 716 to block 718.

[0112] At block 718, the dummy gate segment (e.g., Figure 2AThe 212(1)-210(3), etc.) are converted into IDG structures. Discussion of IDG structures is included in... Figure 2A In the discussion, the process proceeds from block 718 to block 720. In some embodiments, the dummy gate segment is not converted into an IDG structure; in such embodiments, the process proceeds from block 716 to block 720.

[0113] At block 720, an MD structure is formed (e.g., Figure 2A (e.g., 214(1)-214(4)). The process proceeds from block 720 to block 722.

[0114] At block 722, VG ​​contacts (not shown) and VD contacts (not shown) are formed in the respective (A) gate segments (e.g., Figure 2A (e.g., 210(1)-210(2) etc.) and (B)MD structures (e.g.) Figure 2A Above 214(1)-214(4), etc. The process proceeds from block 722 to block 724.

[0115] At block 724, one or more S / D regions and / or one or more gate segments are coupled together to form the corresponding transistor. Within block 724, the process proceeds to block 726.

[0116] At block 726, the M0 section (not shown) is formed above (A) the corresponding VG contact and / or (B) the corresponding VD contact. The flow proceeds from block 726 to block 728.

[0117] At block 726, a first M0 segment is formed (e.g., 214(1)), which covers the third active region (e.g., Figure 2A 208P(2)); Figure 2B Above 208P(3), 208N(4); or similar substances.

[0118] At block 728, a V0 structure (not shown) is formed above the corresponding segment in the M0 section. The process proceeds from block 728 to block 730.

[0119] At block 730, an M1 segment (not shown) is formed above the corresponding structure in the V0 structure.

[0120] In some embodiments, with respect to block 716, the result of forming the gate segments includes: a first gate segment (e.g., 210(2)) overlapping a first AR portion (e.g., 218N(2)) of a first active region (e.g., 208N(1)) and a first AR portion (e.g., 218P(2)) of a second active region (e.g., 208P(1)); and a second gate segment (e.g., 210(1)) overlapping a second AR portion (e.g., 218N(1)) of a first active region (e.g., 208N(1)) and a second AR portion (e.g., 218P(1)) of a second active region (e.g., 208P(1)). In some embodiments, block 716 includes, relative to a second direction (e.g., the Y-axis), trimming the length of the first gate segment (e.g., 210(2)) so that it differs from the length of the second gate segment (e.g., 210(1)).

[0121] In some embodiments, method 700 further includes a dielectric structure formed extending in a second direction (e.g., the Y-axis), the dielectric structure including a first (e.g., 206(3)), a second (e.g., 206(4)), a third (e.g., 2016(1)), and a fourth (e.g., 206(2)) dielectric structure. The first (e.g., 206(3)) and the second (e.g., 206(4)) dielectric structures are respectively adjacent to a first end and a second end of a first gate segment (e.g., 210(2)). The third (e.g., 206(1)) and the fourth (e.g., 206(2)) dielectric structures are respectively adjacent to a first end and a second end of a second gate segment (e.g., 210(1)). Relative to the second direction (e.g., the Y-axis), forming a dielectric structure includes forming the length of each of the first (e.g., 206(3)) and second (e.g., 206(4)) dielectric structures, such that it differs from the length of each of the third (e.g., 206(1)) and fourth (e.g., 206(2)) dielectric structures.

[0122] In some embodiments, block 716 includes forming first (e.g., 412(2)) and second (e.g., 412(1)) pseudo-gate segments such that there are no non-pseudo-gate segments between them. This results in a first pseudo-AR portion (e.g., 424N(1), 424P(1)) of the first (e.g., 208N(1)) and second (e.g., 208P(1)) active regions being defined between the first (e.g., 412(2)) and second (e.g., 412(1)) pseudo-gate segments.

[0123] With respect to each of the first (e.g., 408N(1)) and the second (e.g., 408P(1)) active regions, the first pseudo AR portion (e.g., 424N(1), 424P(1)) is located between the following AR portions and is adjacent in a first direction (e.g., horizontally adjacent): the third AR portion (e.g., 418N(11), 418P(11)); and the first (e.g., 418N(13), 418P(13)) or the second (e.g., 418N(12), 418P(12)) AR portion.

[0124] In some embodiments, the result of forming the gate segment with respect to block 716 includes:

[0125] Each of the first gate segment (e.g., 210(2)) and the second gate segment (e.g., 210(1)) overlaps with the first active region (e.g., 208N(1)) and the second active region (e.g., 208P(1)). In some embodiments, block 716 includes trimming each gate segment (e.g., 210(2)) relative to a second direction (e.g., the Y-axis) so that it hangs over the distal profile with a substantially uniform overhang distance.

[0126] Figure 8 This is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0127] In some embodiments, the EDA system 800 includes an Automatic Placement and Routing (APR) system. In some embodiments, the EDA system 800 is a general-purpose computing device including a processor 802 (e.g., a hardware processor) and a non-transient computer-readable storage medium 804 (also referred to as memory). Among other things, the storage medium 804 also encodes computer program code 806, i.e., a set of executable instructions. Execution of the instructions 806 by the processor 802 represents (at least partially) an EDA tool that implements, according to one or more embodiments, some or all of, one or more methods for generating a layout diagram corresponding to the layout diagrams disclosed herein (hereinafter referred to as the processes and / or methods).

[0128] Storage medium 804 storage layout diagram 816, such as the layout diagram disclosed herein.

[0129] Processor 802 is electrically coupled to storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and storage medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in storage medium 804 to make EDA system 800 available for performing part or all of the processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0130] In one or more embodiments, storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, storage medium 804 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0131] In one or more embodiments, storage medium 804 stores instructions, i.e., computer program code 806, configured to enable EDA system 800 (where such execution represents (at least partially) EDA tools) to perform some or all of the said processes and / or methods. In one or more embodiments, storage medium 804 also stores information that facilitates the execution of some or all of the said processes and / or methods. In one or more embodiments, storage medium 804 stores a standard cell library 807, including standard cells corresponding to components of the layout diagrams disclosed herein. Storage medium 804 stores one or more layout diagrams 816, such as one or more layout diagrams corresponding to the layout diagrams disclosed herein, one or more compiler macros 817, etc., based on layout diagrams including one or more layout diagrams disclosed herein.

[0132] EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 802.

[0133] EDA system 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows EDA system 800 to communicate with a network 814 to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more EDA systems 800.

[0134] EDA system 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. This information is transmitted to processor 802 via bus 808. EDA system 800 is also configured to receive information related to the user interface (UI) via I / O interface 810. This information is stored as UI 842 on computer-readable medium 804.

[0135] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 800. In some embodiments, a software application such as those available from CADENCE DESIGN SYSTEMS Inc. is used. Use tools or another suitable layout generation tool to generate layouts that include standard cells.

[0136] In some embodiments, these processes are implemented as the functions of a program stored in a non-transient computer-readable recording medium. Examples of non-transient computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0137] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system 900 and its associated IC manufacturing process according to some embodiments.

[0138] In some embodiments, based on Figure 7 The layout diagram generated by frame 702 is implemented in IC manufacturing system 900. Figure 7 Block 704, wherein a manufacturing system 900 is used to manufacture (A) one or more semiconductor masks or (B) at least one component in an early semiconductor integrated circuit layer. In some embodiments, the IC manufacturing system 900 implements Figure 6 Flowcharts, etc.

[0139] exist Figure 9 In this IC manufacturing system 900, entities such as design studio 920, mask room 930, and IC manufacturing plant / manufacturer (“Fab”) 950 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 920, mask room 930, and IC manufacturing plant 950 are owned by a single, larger company. In some embodiments, two or more of the design studio 920, mask room 930, and IC manufacturing plant 950 coexist in a shared facility and use shared resources.

[0140] Design studio (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 960 to be manufactured. The layers combine to form various IC features. For example, a portion of IC design layout 922 includes various IC features such as active regions, gate terminals, source and drain terminals, metal lines or vias for interlayer interconnects, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Depending on the context, source / drain regions may be referred to individually or collectively as source or drain. Design company 920 implements appropriate design processes to form IC design layout 922. The design process includes one or more of logic design, physical design, or location and routing. IC design layout 922 is presented in one or more data files containing geometric pattern information. For example, IC design layout 922 is represented in GDSII file format or DFII file format.

[0141] Mask chamber 930 includes data preparation 932 and mask fabrication 934. Mask chamber 930 uses an IC design layout 922 to fabricate one or more masks 935 for fabricating various layers of an IC device 960 according to the IC design layout 922. Mask chamber 930 performs mask data preparation 932, where the IC design layout 922 is converted into a representative data file (“RDF”). Mask data preparation 932 provides the RDF to mask fabrication 934. Mask fabrication 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) or semiconductor wafer. The design layout is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 950. Figure 9 In this embodiment, mask data preparation 932, mask fabrication 934, and mask 935 are shown as separate elements. In some embodiments, mask data preparation 932 and mask fabrication 934 are collectively referred to as mask data preparation.

[0142] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution adjustment features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is further used, which treats OPC as an inverse imaging problem.

[0143] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout processed by OPC. This set of mask generation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 934, which may undo some modifications performed by OPC to satisfy the mask creation rules.

[0144] In some embodiments, mask data preparation 932 includes a lithography process inspection (LPC), which simulates a process performed by an IC manufacturing plant 950 to manufacture an IC device 960. The LPC simulates this process based on an IC design layout 922 to manufacture a simulated device, such as IC device 960. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after the LPC has manufactured the simulated device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further optimize the IC design layout 922.

[0145] For clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, mask data preparation 932 includes additional features, such as logical operations (LOPs) that modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0146] After mask data preparation 932 and during mask fabrication 934, a mask 935 or a set of masks 935 is fabricated based on a modified IC design layout. In some embodiments, a pattern is formed on the mask (photomask or mask stencil) using a mechanism of electron beam (e-beam) or multiple electron beams based on the modified IC design layout. The mask is formed using various techniques. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, a phase-shifting technique is used to form the mask. In a phase-shifting mask (PSM), various features in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and image quality. In various examples, the phase-shifting mask is an attenuated PSM or an alternating PSM. The masks produced by mask manufacturing 934 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0147] IC Manufacturing Plant 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Manufacturing Plant 950 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end process (BEOL) fabrication) for the interconnection and packaging of IC products, and a third manufacturing facility for providing other services for foundry operations.

[0148] IC manufacturing plant 950 uses a mask 935 manufactured by mask chamber 930 and manufacturing tool 952 to manufacture IC device 960. Therefore, IC manufacturing plant 950 uses IC design layout 922 at least indirectly to manufacture IC device 960. In some embodiments, semiconductor wafer 953 is manufactured by IC manufacturing plant 950 using mask 935 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate on which a material layer is formed. The semiconductor wafer also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0149] In some embodiments, the cell region (of the semiconductor device) includes: an active region extending along a first direction and including a first active region and a second active region; the first active region and the second active region are located on opposite sides of a first reference line extending parallel to the first direction, adjacent to a second direction perpendicular to the first direction, and are respectively configured with different first and second types of dopants; and dummy gate segments extending in the second direction, each dummy gate segment overlapping the active region; corresponding AR portions of the active region are defined between adjacent dummy gate segments in the first direction; each of the first active region and the second active region includes a first AR portion and a second AR portion in the AR portions adjacent in the first direction; the first AR portion and the second AR portion define a first AR segment and a second AR segment; each of the first AR segment and the second AR segment has a first profile and a second profile relative to the second direction, the first profile and the second profile being close to and far from the first reference line, respectively; and the proximal profile of each of the first AR segment and the second AR segment is planar; and the distal profile of the first AR segment or the second AR segment is stepped, such that the first AR segment or the second AR segment is a concave polygonal shape.

[0150] In some embodiments, the width of the first AR portion of the first active region is different from the width of the second AR portion of the first active region relative to the second direction.

[0151] In some embodiments, the width of the first AR portion of the second active region is different from the width of the second AR portion of the second active region relative to the second direction.

[0152] In some embodiments, the cell region further includes: a gate segment extending along a second direction and including a first gate segment and a second gate segment; the first gate segment overlaps with a first AR portion of a first active region and a first AR portion of a second active region; the second gate segment overlaps with a second AR portion of a first active region and a second AR portion of a second active region; and the length of the first gate segment is different from the length of the second gate segment relative to the second direction.

[0153] In some embodiments, the cell region further includes: a dielectric structure extending along a second direction, including a first dielectric structure, a second dielectric structure, a third dielectric structure, and a fourth dielectric structure; the first dielectric structure and the second dielectric structure respectively adjacent to a first end and a second end of the first gate segment; the third dielectric structure and the fourth dielectric structure respectively adjacent to a first end and a second end of the second gate segment; and the length of each of the first dielectric structure and the second dielectric structure is different from the length of each of the third dielectric structure and the fourth dielectric structure relative to the second direction.

[0154] In some embodiments, each of the first active region and the second active region further includes a third AR portion; the first AR portion and the second AR portion define a first AR segment and a second AR segment; the cell region further includes a well configured with a second type of dopant; the first AR portion and the second AR portion are located in a first region of the well; the third AR portion is located in a second region of the well; and the width of the first region of the well is different from the width of the second region of the well relative to a second direction.

[0155] In some embodiments, there is no non-pseudo-gate segment between the first pseudo-gate segment and the second pseudo-gate segment; a first pseudo AR portion of the first active region and the second active region is defined between the first pseudo-gate segment and the second pseudo-gate segment; for each of the first active region and the second active region, the first pseudo AR portion is located between the third AR portion and the first AR portion or the second AR portion in the AR portion, and is adjacent to the third AR portion and the first AR portion or the second AR portion in a first direction.

[0156] In some embodiments, the distal contours of the first AR segment and the second AR segment are stepped, such that each of the first AR segment and the second AR segment is a concave polygon shape.

[0157] In some embodiments, the cell region further includes: a gate segment extending along a second direction and including a first gate segment and a second gate segment; each of the first gate segment and the second gate segment overlaps with a first active region and a second active region; and each gate segment hangs over the distal profile with a substantially uniform overhang distance.

[0158] In some embodiments, a cell region of a semiconductor device includes: an active region extending along a first direction and including a first active region and a second active region; the first active region and the second active region are located on opposite sides of a first reference line extending parallel to the first direction, adjacent to a second direction perpendicular to the first direction, and are respectively configured with different first type dopants and second type dopants; and dummy gate segments extending in the second direction, each dummy gate segment overlapping an active region; corresponding AR portions of the active regions are defined between adjacent dummy gate segments in the first direction; each of the first active region and the second active region includes a first AR portion and a second AR portion in adjacent AR portions in the first direction. The first AR portion and the second AR portion define a first AR segment and a second AR segment; each of the first AR segment and the second AR segment has a first profile and a second profile relative to a second direction, the first profile and the second profile correspondingly close to and far from a first reference line; and the distal profile of the first AR segment or the second AR segment is stepped, such that the first AR segment or the second AR segment is a concave polygonal shape; a gate segment, extending along the second direction, and including the first gate segment and the second gate segment; each of the first gate segment and the second gate segment overlaps with the first active region and the second active region; each of the first gate segment and the second gate segment hangs over the distal profile with a substantially uniform overhang distance.

[0159] In some embodiments, the distal contours of the first AR portion and the second AR portion are stepped, such that the first AR portion or the second AR portion is a concave polygon shape.

[0160] In some embodiments, the length of the first gate segment is different from the length of the second gate segment relative to the second direction.

[0161] In some embodiments, the cell region further includes: a dielectric structure extending along a second direction and including a first dielectric structure, a second dielectric structure, a third dielectric structure, and a fourth dielectric structure; the first dielectric structure and the second dielectric structure respectively adjacent to a first end and a second end of the first gate segment; the third dielectric structure and the fourth dielectric structure respectively adjacent to a first end and a second end of the second gate segment; and the length of at least one of the first to fourth dielectric structures is different from that of the other dielectric structures among the first to fourth dielectric structures relative to the second direction.

[0162] In some embodiments, a method of manufacturing a cell region of a semiconductor device includes: forming an active region extending along a first direction and including a first active region and a second active region, the first active region and the second active region being located on opposite sides of a first reference line extending parallel to the first direction, adjacent to a second direction perpendicular to the first direction, and correspondingly configured with different first type dopants and second type dopants; and forming dummy gate segments extending along a second direction, each dummy gate segment overlapping the active region; and wherein: corresponding AR portions of the active region are defined between adjacent dummy gate segments in the first direction; the first active region and the second active region... Each of the components includes a first AR portion and a second AR portion in an adjacent AR portion in a first direction; the first AR portion and the second AR portion define a first AR segment and a second AR segment, and each of the first AR segment and the second AR segment has a first profile and a second profile relative to a second direction, the first profile and the second profile correspondingly proximal to and away from a first reference line; and forming an active region includes adjusting the width of the AR portion as follows: the proximal profile of each of the first AR segment and the second AR segment is planar, and the distal profile of the first AR segment or the second AR segment is stepped, such that the first AR portion or the second AR portion is a concave polygonal shape.

[0163] In some embodiments, forming an active region further includes: the width of the first AR portion forming the first active region being different from the width of the second AR portion of the first active region relative to the second direction.

[0164] In some embodiments, the method further includes: forming a gate segment extending along a second direction and including a first gate segment and a second gate segment, wherein the first gate segment overlaps with a first AR portion of a first active region and a first AR portion of a second active region, and the second gate segment overlaps with a second AR portion of a first active region and a second AR portion of a second active region; and forming the gate segment relative to the second direction includes: trimming the length of the first gate segment to a length different from that of the second gate segment.

[0165] In some embodiments, the method further includes: forming a dielectric structure extending along a second direction and including a first dielectric structure, a second dielectric structure, a third dielectric structure, and a fourth dielectric structure, wherein the first and second dielectric structures are respectively adjacent to a first end and a second end of a first gate segment, and the third and fourth dielectric structures are respectively adjacent to a first end and a second end of a second gate segment; and forming the dielectric structure relative to the second direction includes: forming a length of each of the first and second dielectric structures that is different from the length of each of the third and fourth dielectric structures.

[0166] In some embodiments, forming a dummy gate segment includes the steps of: forming a first dummy gate segment and a second dummy gate segment such that there is no non-dummy gate segment between them; a first dummy AR portion of a first active region and a second active region is defined between the first dummy gate segment and the second dummy gate segment; for each of the first active region and the second active region, the first dummy AR portion is located between a third AR portion and the first AR portion or the second AR portion, and is adjacent to the third AR portion and the first AR portion or the second AR portion in a first direction.

[0167] In some embodiments, adjusting the width further results in the following: the distal contours of the first AR segment and the second AR segment are stepped, such that each of the first AR segment and the second AR segment is a concave polygon shape.

[0168] In some embodiments, the method further includes: forming a gate segment extending along a second direction and including a first gate segment and a second gate segment; each of the first gate segment and the second gate segment overlapping a first active region and a second active region; and forming the gate segment relative to the second direction includes: trimming each gate segment such that the gate segment hangs over the distal profile with a substantially uniform overhang distance.

[0169] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. Having read the foregoing specification, those skilled in the art will be able to influence various variations, equivalent substitutions, and various other embodiments widely disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

Claims

1. A cell region of a semiconductor device, the cell region comprising: The active region extends along the first direction and includes the first active region and the second active region; The first active region and the second active region are located on opposite sides of a first reference line extending parallel to the first direction, adjacent to a second direction perpendicular to the first direction, and are respectively configured with different first type dopants and second type dopants; as well as The pseudo-gate segment extends in the second direction, and each of the pseudo-gate segments overlaps with the active region; The corresponding active region portion of the active region is defined between the adjacent pseudo-gate segments in the first direction; Each of the first active region and the second active region includes a first active region portion and a second active region portion of the active region portions that are adjacent in a first direction; The first active region portion and the second active region portion define the first active segment and the second active segment; Relative to the second direction, each of the first active segment and the second active segment has a first profile and a second profile, the first profile being closer to and the second profile being farther away from the first reference line, respectively; and The proximal profile of each of the first active segment and the second active segment is planar; and The distal contour of the first active segment or the second active segment is stepped, making the first active segment or the second active segment a concave polygon shape.

2. The unit region according to claim 1, wherein, Relative to the second direction, The width of the first active region portion of the first active region is different from the width of the second active region portion of the first active region.

3. The unit region according to claim 2, wherein, Relative to the second direction, The width of the first active region portion of the second active region is different from the width of the second active region portion of the second active region.

4. The unit region according to claim 2, further comprising: A gate segment extends along the second direction and includes a first gate segment and a second gate segment; The first gate segment overlaps with the first active region portion of the first active region and the first active region portion of the second active region; The second gate segment overlaps with the second active region portion of the first active region and the second active region portion of the second active region; as well as Relative to the second direction, The length of the first gate segment is different from the length of the second gate segment.

5. The unit region according to claim 4, further comprising: The dielectric structure, extending along the second direction, includes a first dielectric structure, a second dielectric structure, a third dielectric structure, and a fourth dielectric structure; The first dielectric structure and the second dielectric structure are respectively adjacent to the first end and the second end of the first gate segment; The third dielectric structure and the fourth dielectric structure are respectively adjacent to the first end and the second end of the second gate segment; and Relative to the second direction, The length of each of the first dielectric structure and the second dielectric structure is different from the length of each of the third dielectric structure and the fourth dielectric structure.

6. The unit region according to claim 1, wherein, Each of the first active region and the second active region further includes a third active region portion; The first active region portion and the second active region portion define the first active segment and the second active segment; The cell region further includes a well configured with the second type of dopant; The first active region portion and the second active region portion are located in the first region of the trap; The third active region is located in the second region of the trap; as well as Relative to the second direction, The width of the first region of the trap is different from the width of the second region of the trap.

7. The unit region according to claim 1, wherein, There is no non-pseudo-gate segment between the first pseudo-gate segment and the second pseudo-gate segment; The first pseudo-active region portion of the first active region and the second active region is defined between the first pseudo-gate segment and the second pseudo-gate segment; For each of the first active region and the second active region, The first pseudo-active region portion is located between the third active region portion and the first active region portion or the second active region portion of the active region portion, and is adjacent to the third active region portion and the first active region portion or the second active region portion in the first direction.

8. A cell region of a semiconductor device, the cell region comprising: The active region extends along the first direction and includes the first active region and the second active region; The first active region and the second active region are located on opposite sides of a first reference line extending parallel to the first direction, adjacent to a second direction perpendicular to the first direction, and are respectively configured with different first type dopants and second type dopants; as well as The pseudo-gate segment extends in the second direction, and each of the pseudo-gate segments overlaps with the active region; The corresponding active region portion of the active region is defined between the pseudo-gate segments adjacent in the first direction; Each of the first active region and the second active region includes a first active region portion and a second active region portion in adjacent active region portions in the first direction; The first active region portion and the second active region portion define the first active segment and the second active segment; Relative to the second direction, each of the first active segment and the second active segment has a first profile and a second profile, the first profile and the second profile correspondingly approaching and moving away from the first reference line; and The distal contour of the first active segment or the second active segment is stepped, making the first active segment or the second active segment a concave polygon shape. A gate segment extends along the second direction and includes a first gate segment and a second gate segment; Each of the first gate segment and the second gate segment overlaps with the first active region and the second active region; Each of the first gate segment and the second gate segment hangs over the distal profile with a substantially uniform overhang distance.

9. A method for manufacturing a cell region of a semiconductor device, the method comprising: An active region is formed that extends along the first direction and includes a first active region and a second active region. The first active region and the second active region are located on opposite sides of a first reference line extending parallel to the first direction, adjacent to a second direction perpendicular to the first direction, and are respectively configured with different first type dopants and second type dopants; as well as A pseudo-gate segment is formed extending along the second direction, and each pseudo-gate segment overlaps with the active region; and in: The corresponding active region portion of the active region is defined between the pseudo-gate segments adjacent in the first direction; Each of the first active region and the second active region includes a first active region portion and a second active region portion of the active region portions that are adjacent in a first direction; The first active region portion and the second active region portion define the first active segment and the second active segment. Relative to the second direction, each of the first active segment and the second active segment has a first profile and a second profile, the first profile being closer to and the second profile being farther from the first reference line, respectively; and Forming the active region includes adjusting the width of a portion of the active region, as follows: The proximal profile of each of the first active segment and the second active segment is planar, and The distal contour of the first active segment or the second active segment is stepped, making the first active segment or the second active segment a concave polygon shape.

10. The method according to claim 9, wherein, Forming the pseudo-gate segment includes: The first pseudo-gate segment and the second pseudo-gate segment are formed such that there are no non-pseudo-gate segments between the first pseudo-gate segment and the second pseudo-gate segment. The first pseudo-active region portion of the first active region and the second active region is defined between the first pseudo-gate segment and the second pseudo-gate segment; For each of the first active region and the second active region, The first pseudo-active region portion is located between the third active region portion and the first active region portion or the second active region portion, and is adjacent to the third active region portion and the first active region portion or the second active region portion in the first direction.

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