Photoelectric device, preparation method thereof and photoelectric detection device

Abstract

The invention provides a photoelectric device, a preparation method thereof and a photoelectric detection device. The dark count rate of the device can be reduced. The photoelectric device includes: a substrate; a working region in the substrate, the working region including a first well region, a second well region and a first highly doped region of the first conductivity type, and a third well region, a fourth well region and a second highly doped region of the second conductivity type, where the third well region forms an avalanche region with at least one of the second well region and the first highly doped region, and the fourth well region forms an avalanche region with at least one of the second well region and the first highly doped region. The first well region is exposed out of the first surface, and the first well region is configured to have the effect of a passivation layer so as to reduce the surface electric field of the first surface.

Description

Technical Field

[0001] This application relates to the field of photoelectric detection technology, and in particular to a photoelectric device and its preparation method, and a photoelectric detection device. Background Technology

[0002] A single-photon avalanche diode (SPAD) is a solid-state photodetector avalanche diode with single-photon detection capability, which has attracted much attention in recent years. The working principle of a SPAD for single-photon detection is as follows: A bias voltage greater than the breakdown voltage is applied to the SPAD. When a photon is incident, valence band electrons absorb the photon and jump to the conduction band, generating photogenerated electron-hole pairs. These photogenerated electron-hole pairs are accelerated under the influence of an applied electric field and gain sufficient energy to collide with the crystal lattice, producing new electron-hole pairs; this process is called collisional ionization. These new electron-hole pairs are accelerated under the influence of the applied electric field and collide with the crystal lattice, generating new electron-hole pairs. This process repeats, causing the number of charge carriers in the SPAD to increase rapidly, the current to increase dramatically, and a large avalanche current to form; this phenomenon is called the avalanche multiplication effect.

[0003] However, the carriers released by the surface defects of a single-photon avalanche diode will drift to the avalanche region under the influence of the electric field, causing dark counting. A large dark counting rate will seriously affect the detection accuracy of the single-photon avalanche diode. Summary of the Invention

[0004] The purpose of this application is to provide an optoelectronic device and an optoelectronic detection apparatus that can reduce the dark count rate of the device and improve the accuracy of device detection.

[0005] To achieve the above objectives, some embodiments of this application provide the following technical solutions:

[0006] In a first aspect, this application provides an optoelectronic device, comprising:

[0007] A substrate having a first surface and a second surface opposite to the first surface;

[0008] The working area, located in the substrate, includes:

[0009] A first well region extending downward from a first surface of a substrate, the first well region being of a first conductivity type, the first well region being configured to have the effect of a passivation layer to reduce the surface electric field of the first surface;

[0010] The second well region is located below the first well region and is of the first conductivity type;

[0011] A third well region is located below the second well region, and the third well region is of the second conductivity type; and,

[0012] The first highly doped region is of a first conductivity type and its doping concentration is at least greater than that of the first well region and / or the second well region. The first highly doped region extends from the first surface to the third well region and is surrounded by the first well region and the second well region.

[0013] The optoelectronic device also includes a fourth well region distributed outside the working area. The fourth well region is of the second conductivity type. A second highly doped region is provided near the first surface of the fourth well region. The second highly doped region is of the second conductivity type and is exposed on the first surface. The doping concentration of the second highly doped region is greater than that of the fourth well region.

[0014] The third well region forms an avalanche region with at least one of the second well region and the first highly doped region.

[0015] In some embodiments, the width of the first highly doped region is smaller than that of the first well region and / or the second well region;

[0016] The width of the third well region is greater than that of the first well region and / or the second well region.

[0017] In some embodiments, the working region further includes a carrier drift region of a second conductivity type, wherein the doping concentration of the carrier drift region has a gradient change along the depth direction from the first surface to the second surface, and the built-in electric field generated by the gradient change satisfies the condition that the carriers formed in the carrier drift region are driven to the avalanche region, wherein the first surface and the second surface are two opposing surfaces of the substrate.

[0018] In some embodiments, the doping concentration of the fourth well region is greater than that of the carrier drift region and / or the third well region, thereby generating a built-in electric field with the electric field direction pointing towards the fourth well region and driving the carriers in the carrier drift region to move towards the avalanche region.

[0019] In some embodiments, an isolation region is further included, disposed around the periphery of the fourth well region, wherein the isolation region is one of deep trench isolation or shallow trench isolation.

[0020] In some embodiments, the substrate is further provided with a light trapping structure near the second surface, and a microlens array is further provided on the outer side of the second surface, wherein the first surface and the second surface are two opposing surfaces of the substrate.

[0021] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type;

[0022] Alternatively, the first conductivity type is P-type, and the second conductivity type is N-type.

[0023] Secondly, this application also provides a photoelectric detection device, comprising:

[0024] substrate,

[0025] An array of optoelectronic devices disposed on a substrate, the array of optoelectronic devices including multiple optoelectronic devices as described above.

[0026] In some embodiments, the photoelectric detection device is a positive-incident type, and its light-incident surface is a first surface;

[0027] Alternatively, the photoelectric detection device is a back-in type, with its light-incident surface being the second surface, wherein the first surface and the second surface are two opposing surfaces of the substrate.

[0028] Thirdly, this application also provides a method for fabricating the optoelectronic device as described above, the method comprising the following steps:

[0029] A substrate is provided, the substrate being of a second conductivity type, the substrate having opposing first and second surfaces;

[0030] A working region is set at a selected location on the substrate, and ions of a second conductivity type are implanted around the working region to form a fourth well region;

[0031] Ion implantation of a second conductivity type is performed at a third depth from the first surface in the working area to form a third well region;

[0032] Ion implantation of a first conductivity type is performed at a second depth from the first surface in the working area to form a second well region. The second depth is less than the third depth. The side of the second well region away from the first surface is in contact with the side of the third well region close to the first surface.

[0033] Ion implantation of a first conductivity type is performed at a first depth from the first surface in the working area to form a first well region, the first depth being less than the second depth;

[0034] A first conductivity type is heavily doped at a selected location on the substrate to form a first highly doped region that extends from a first surface to a third well region and is surrounded by a first well region and a second well region.

[0035] A second highly doped region of a second conductivity type is formed near the first surface in the fourth well region to form a second highly doped region exposed on the first surface.

[0036] The first well region is exposed on the first surface and is configured to have the effect of a passivation layer to reduce the surface electric field of the first surface.

[0037] In some embodiments, the substrate is subjected to a reverse doping process, such that the concentration of impurities of a second conductivity type in the substrate decreases from the second surface to the first surface.

[0038] Based on the above description, this application provides an optoelectronic device, which is a diode, including a first highly doped region, a third well region, a fourth well region, and a second highly doped region. When a reverse electric field is applied between the first and second highly doped regions, the optoelectronic device operates in Geiger mode and can be used as an avalanche diode. Furthermore, the optoelectronic device provided in this application also includes a first well region, a second well region, and a carrier drift region. The structural design of this optoelectronic device has at least the following advantages:

[0039] Firstly, the first well region and the second well region are arranged around the first highly doped region, which can act as a virtual guard ring to reduce the dark count rate of the device;

[0040] Secondly, the first well region is exposed on the first surface. The first well region is configured to have a passivation effect, reducing the electric field strength of the first surface, thereby weakening the activation ability of the external electric field on defects, suppressing the surface defect-assisted tunneling effect that triggers avalanche breakdown, and thus suppressing the generation of dark counts related to surface defects, further reducing the dark count rate of the device.

[0041] Thirdly, in the optoelectronic device provided in this application, the doping concentration of the carrier drift region has a gradient change along the depth direction from the first surface to the second surface. The built-in electric field in the vertical direction generated by this gradient change drives the carriers formed in the carrier drift region to the third well region. Furthermore, the doping concentration of the fourth well region is designed to be greater than that of the carrier drift region and / or the third well region, thereby generating a transverse built-in electric field with the electric field direction pointing towards the fourth well region. This transverse built-in electric field drives the carriers in the carrier drift region to move towards the central region of the carrier drift region. Through the combination of the above-mentioned vertical and transverse built-in electric fields, the carriers in the carrier drift region can be driven towards the avalanche region, thereby improving the photodetection efficiency of the optoelectronic device. Attached Figure Description

[0042] Figure 1 A schematic cross-sectional view of the optoelectronic device provided in the first embodiment of this application;

[0043] Figure 2 Potential diagram of the optoelectronic device provided in this application;

[0044] Figure 3A This is a schematic diagram of the electric field of an optoelectronic device provided in one embodiment of this application;

[0045] Figure 3B A schematic diagram of the electric field of an optoelectronic device provided in another embodiment of this application;

[0046] Figure 4A A schematic plan view of the first depth of the optoelectronic device provided in this application;

[0047] Figure 4BA schematic plan view of the second depth of the optoelectronic device provided in this application;

[0048] Figure 5 A schematic cross-sectional view of the optoelectronic device provided in the second embodiment of this application;

[0049] Figure 6 A schematic cross-sectional view of the optoelectronic device provided in the third embodiment of this application;

[0050] Figure 7 This is a schematic diagram of the optoelectronic device provided in this application;

[0051] Figure 8 A schematic diagram of the optoelectronic device provided in this application (rear-mounted type);

[0052] Figure 9 A schematic cross-sectional view of the optoelectronic device provided in the fourth embodiment of this application;

[0053] Figure 10 A schematic cross-sectional view of the optoelectronic device provided in the fifth embodiment of this application;

[0054] Figure 11A This is a schematic diagram of the planar shape of the optoelectronic device provided in the first embodiment of this application;

[0055] Figure 11B This is a schematic diagram of the planar shape of the optoelectronic device provided in the second embodiment of this application;

[0056] Figure 11C This is a schematic diagram of the planar shape of the optoelectronic device provided in the third embodiment of this application;

[0057] Figure 12 This is a schematic diagram of the photoelectric detection device provided in an embodiment of this application.

[0058] Explanation of reference numerals in the attached figures: Optoelectronic device 100; First well region 11; Second well region 12; Third well region 13; First highly doped region 14; Carrier drift region 15; Fourth well region 16; Second highly doped region 17; Isolation region 18; Optical trap structure 19; Microlens array 21; First surface 101; Second surface 102; Avalanche region 103; Optoelectronic detection device 200. Detailed Implementation

[0059] The present application will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application. Any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present application.

[0060] Dark count rate is an important parameter of the device involved in this application, namely the SPAD (Single-Photon Avalanche Diode) device. It is defined as the frequency of voltage pulse counts generated by the collisional ionization process of dark carriers in a SPAD device under high electric field strength in the absence of light illumination. Dark count has a significant impact on the sensitivity of SPAD devices. The causes of dark count are mainly of three types: thermal excitation, trap-assisted generation, and interband tunneling. Traps-assisted generation refers to the introduction of many defects during SPAD manufacturing processes (such as doping and annealing). Generally, the trap density is highest on the surface of the SPAD device and near the shallow trench isolation (STI) area. These defects can trap and release carriers, thus causing dark count.

[0061] Based on this, this application provides an optoelectronic device that can reduce the impact of surface defects on dark count, thereby reducing the dark count rate of the SPAD device. The optoelectronic device includes: a substrate having a first surface and a second surface opposite to the first surface; a working region located in the substrate; the working region includes: a first well region extending downward from the first surface of the substrate, the first well region being of a first conductivity type; a second well region located below the first well region, the second well region being of the first conductivity type; a third well region located below the second well region, the third well region being of a second conductivity type; and a first highly doped region, the first highly doped region being of the first conductivity type, and its doping concentration being at least greater than that of the first well region and / or the second well region, the first highly doped region penetrating through the first well region and the second well region and contacting the third well region; wherein the first well region is exposed on the first surface and forms a passivation effect.

[0062] Based on the above description, the optoelectronic device 100 provided in this application is a single-photon avalanche diode, which can be used for single-photon detection. Figure 1 This is a schematic cross-sectional view of the optoelectronic device 100 according to this exemplary embodiment. The optoelectronic device 100 provided in this embodiment is disposed in a substrate, which is silicon-based, a wafer, or other substrate material. The substrate has a first surface 101 and a second surface 102 opposite to the first surface 101. For ease of explanation, in this embodiment, the depth direction is defined as the direction from the first surface 101 toward the second surface 102, and the direction from the first surface to the second surface is defined as the downward direction. It should be noted that in this embodiment, of the pair of charges generated in the optoelectronic device 100, the charge conductivity type used as the signal charge is called the first conductivity type, and the opposite conductivity type of the first conductivity type is called the second conductivity type.

[0063] In this embodiment, the first well region 11 has a first conductivity type and extends downward from the first surface 101 of the substrate, disposed in a first depth. Here, "the first well region 11 is disposed in a first depth" means, for example, that the region with the highest implanted impurity concentration (peak) is disposed in the first depth; however, this peak does not necessarily need to be disposed in the first depth, and design or manufacturing errors are permissible. Subsequent explanations regarding the well region depth will follow this description and will not be repeated.

[0064] The second well region 12 has a first conductivity type and is located below the first well region 11. Specifically, the second well region 12 is arranged in a second depth, which is greater than the first depth, and the projection of the second well region 12 on a projection plane parallel to the first surface 101 along the depth direction at least partially overlaps with the projection of the first well region 11.

[0065] The third well region 13 is located below the second well region 12 and has a second conductivity type. Specifically, the third well region 13 is arranged at a third depth, which is greater than the second depth, and the projection of the third well region 13 on a projection plane parallel to the first surface 101 along the depth direction at least partially overlaps with the projection of the second well region 12. In one embodiment, the third well region 13 may be in contact with the second well region 12. Alternatively, in another embodiment, the third well region 13 is spaced apart from the second well region 12 and does not contact the second well region 12.

[0066] The first highly doped region 14 has a first conductivity type, and the doping concentration of the first highly doped region 14 is at least greater than that of the first well region 11 and / or the second well region 12, the first highly doped region 14 being surrounded by the first well region 11 and the second well region 12. Furthermore, the first highly doped region 14 extends from the first surface 101 to the third well region 13 and is in contact with the third well region 13.

[0067] As is easily understood, the first highly doped region 14 and the third well region 13 have opposite conductivity types, thus allowing a PN junction (avalanche region 103) to be formed at the interface between the first highly doped region 14 and the third well region 13. In Geiger mode, a self-sustaining avalanche multiplication process can occur, thereby enabling single-photon detection.

[0068] Furthermore, in the optoelectronic device 100 provided in this application embodiment, a first well region 11 and a second well region 12 are arranged around the first highly doped region 14. The first well region 11 and the second well region 12 have the same conductivity type as the first highly doped region 14 (i.e., the first conductivity type), and the doping concentration of the first well region 11 and the second well region 12 is lower than that of the first highly doped region 14. The first well region 11 and the second well region 12 can serve as a guard ring. Under the action of the second well region 12, the edge electric field strength of the avalanche region 103 is reduced, thereby suppressing the influence of surface defects on dark counting and reducing the dark counting rate of the optoelectronic device 100. In addition, in the optoelectronic device 100 provided in this application, the first well region 11 is implanted at a first depth close to the first surface 101 to passivate the device surface, thereby reducing the surface electric field strength and making it difficult for carriers released from surface defects to enter the avalanche region 103, thereby suppressing the influence of surface defects on dark counting and reducing the dark counting rate of the optoelectronic device 100.

[0069] Specifically, such as Figure 2 As shown, it illustrates the potential diagram of the optoelectronic device 100. According to... Figure 2 As can be seen, without the first well region 11, the potential of the photoelectric device 100 increases sharply as the depth approaches the first surface 101. With the first well region 11, although the potential of the photoelectric device 100 fluctuates as the depth approaches the first surface 101, the potential of the photoelectric device 100 is significantly lower near the first surface 101 than when the first well region 11 is not present. Therefore, the first well region 11 can effectively reduce the surface electric field intensity, thereby reducing the probability of surface defects entering the avalanche region 103 and lowering the dark count rate of the device.

[0070] As an optional implementation, in this embodiment of the application, the third well region 13 is arranged in contact with the second well region 12, so that the third well region 13 and at least one of the second well region 12 and the first highly doped region 14 form an avalanche region 103.

[0071] Specifically, the extent of the avalanche region 103 is related to the doping concentration and doping depth of the second well region 12. For example, as Figure 3A As shown, when the doping concentration of the first highly doped region 14 is much greater than that of the second well region 12, the electric field strength is highest at the boundary between the first highly doped region 14 and the third well region 13, which is the avalanche region 103. With increasing doping concentration and / or doping depth of the second well region 12, as... Figure 3BAs shown, the electric field strength at the boundary between the second well region 12 and the third well region 13 is enhanced, and the avalanche region 103 extends to the boundary between the second well region 12 and the third well region 13. Based on the above description, the effective photosensitive area of ​​the optoelectronic device 100 can be adjusted by controlling the doping status of the second well region 12, thereby improving the photodetection efficiency of the optoelectronic device 100.

[0072] As an optional implementation, the width of the first highly doped region 14 is smaller than that of the first well region 11 and / or the second well region 12. Here, the width of the first highly doped region 14 refers to, for example, the width of the first highly doped region 14 projected onto the first surface 101 along the depth direction.

[0073] Indicative Figure 4A A schematic plan view of the first depth of the optoelectronic device 100 is shown. Figure 4B A schematic plan view of the second depth of the optoelectronic device 100 is shown. Figure 4A As shown, the first well region 11 is the region surrounding the first highly doped region 14, and the width of the first well region 11 refers to, for example, the diameter of the first well region 11 projected onto the first surface 101 along the depth direction. Figure 4B As shown, the second well region 12 is a region surrounding the first highly doped region 14. The width of the second well region 12 refers to, for example, the diameter of the second well region 12 projected onto the first surface 101 along the depth direction. For example, in the embodiments of this application, the width of the first highly doped region 14 is smaller than the width of the first well region 11, and the width of the first highly doped region 14 is smaller than the width of the second well region 12.

[0074] As an optional implementation, the width of the third well region 13 is greater than that of the first well region 11 and / or the second well region 12. Here, the width of the third well region 13 refers to, for example, the diameter of the third well region 13 projected along the depth direction onto a projection plane parallel to the first surface 101.

[0075] As an optional implementation, the width of the first well region 11 and the width of the second well region 12 are substantially equal.

[0076] like Figure 5As shown, as an optional implementation, the working region also includes a carrier drift region 15 of a second conductivity type. The doping concentration of the carrier drift region 15 has a gradient change along the depth direction from the first surface 101 to the second surface 102. The built-in electric field generated by the gradient change satisfies the condition that the carriers formed in the carrier drift region 15 are driven towards the avalanche region 103. Specifically, the carrier drift region 15 is reverse-doped, with the highest doping concentration near the second surface 102 and the lowest doping concentration near the first surface 101. The gradient concentration forms a built-in electric field in the carrier drift region 15, which can promote the drift of photogenerated carriers towards the avalanche region 103 to trigger avalanche multiplication. In this way, the photodetection efficiency of the optoelectronic device 100 can be improved.

[0077] As an optional implementation, the optoelectronic device 100 provided in this application embodiment further includes a fourth well region 16 extending along the depth direction. The fourth well region 16 is of a second conductivity type, and is distributed outside the working region and in contact with the carrier drift region 15 and / or the third well region 13. The doping concentration of the fourth well region 16 is greater than that of the carrier drift region 15 and / or the third well region 13, thereby generating a built-in electric field pointing towards the fourth well region 16 and driving the carriers in the carrier drift region 15 to move towards the avalanche region 103.

[0078] It is easy to understand that there is a doping concentration difference between the fourth well region 16 and the carrier drift region 15, which allows a transverse built-in electric field to be formed between them. This promotes the drift of photogenerated carriers towards the central region of the optoelectronic device 100. Furthermore, under the influence of the built-in electric field in the carrier drift region 15, these photogenerated carriers will eventually drift towards the avalanche region 103 located in the central region of the optoelectronic device 100, thereby triggering avalanche multiplication. In this way, photogenerated carriers at different locations in the optoelectronic device 100 can be driven to the avalanche region 103, thereby improving the photodetection efficiency of the optoelectronic device 100.

[0079] For example, as an optional implementation, taking N-type doping as the first conductivity type and P-type doping as the second conductivity type, the third well region 13 in the optoelectronic device 100 provided in this application embodiment is a P-well. The carrier drift region 15 is P-type doped, and the doping concentration gradient of the carrier drift region 15 increases along the depth direction from the first surface 101 to the second surface 102; that is, the doping concentration of the carrier drift region 15 is high near the second surface 102, while the doping concentration is low near the first surface 101. For example, the doping concentration of the carrier drift region 15 near the second surface 102 can be 10. 18 cm -3 ~1021 cm -3 Near the first surface 101, the doping concentration of the carrier drift region 15 can be 10. 12 cm -3 ~10 14 cm -3 Based on the inverse gradient concentration of the P-type doping, a built-in electric field can be formed pointing from the first surface 101 to the second surface 102. Under the action of this built-in electric field, photogenerated minority carriers (i.e., photogenerated electrons) in the carrier drift region 15 drift, thereby promoting the spontaneous drift of photogenerated electrons to the avalanche region 103.

[0080] Furthermore, the fourth well region 16 is p-type doped to form a deep p-well, and the p-type doping concentration of the fourth well region 16 is greater than the p-type doping concentration of the carrier drift region 15 and / or the doping concentration of the third well region 13 (for example, the doping concentration of the third well region 13 is 10). 16 cm -3 ~10 18 cm -3 In this case, the doping concentration of the fourth well region 16 can be 10. 17 cm -3 ~10 19 cm -3 This allows the formation of a built-in electric field pointing from the carrier drift region 15 to the fourth well region 16. Under the influence of this built-in electric field, photogenerated electrons are promoted to drift towards the central region. Furthermore, under the influence of the built-in electric field in the carrier drift region 15, these photogenerated electrons will eventually drift towards the avalanche region 103 located in the central region of the optoelectronic device 100, thereby triggering avalanche multiplication. In this way, the photodetection efficiency of the optoelectronic device 100 can be improved.

[0081] For example, as another optional implementation, taking P-type doping as the first conductivity type and N-type doping as the second conductivity type, the third well region 13 in the optoelectronic device 100 provided in this application embodiment is an N-well. The carrier drift region 15 is N-type doped, and the doping concentration gradient of the carrier drift region 15 increases along the depth direction from the first surface 101 to the second surface 102; that is, the doping concentration is high near the second surface 102 and low near the first surface 101. Based on this inverse gradient concentration of N-type doping, a built-in electric field can be formed pointing from the second surface 102 to the first surface 101. Under the action of this built-in electric field, photogenerated minority carriers (i.e., photogenerated holes) in the carrier drift region 15 drift, promoting the spontaneous drift of photogenerated holes towards the avalanche region 103.

[0082] Furthermore, the fourth well region 16 is N-type doped to form a deep N-well, and the N-type doping concentration of the fourth well region 16 is greater than that of the carrier drift region 15. This allows the formation of a built-in electric field pointing from the fourth well region 16 to the carrier drift region 15. Under the action of this built-in electric field, photogenerated minority carriers are promoted to drift towards the central region. Moreover, under the action of the built-in electric field of the carrier drift region 15, these photogenerated minority carriers will eventually drift towards the avalanche region 103 located in the central region of the optoelectronic device 100, thereby triggering avalanche multiplication. In this way, the photodetection efficiency of the optoelectronic device 100 can be improved.

[0083] As an optional implementation, a second highly doped region 17 is provided near the first surface 101 in the fourth well region 16. The second highly doped region 17 is of a second conductivity type and is exposed on the first surface 101. The doping concentration of the second highly doped region 17 is set to be greater than the doping concentration of the fourth well region 16. Contact plugs can be connected through the second highly doped region 17. Compared with the contact resistance of directly connecting to the contact plug through the fourth well region 16, connecting the contact plug through the second highly doped region 17 can reduce the contact resistance.

[0084] By connecting the contact plugs through the first highly doped region 14 and the second highly doped region 17 respectively, a reverse bias voltage greater than the breakdown voltage can be applied to the optoelectronic device 100 using the contact plugs, so that the optoelectronic device 100 operates in Geiger mode and realizes single-photon detection.

[0085] like Figure 6 As shown, in some embodiments, the optoelectronic device 100 further includes an isolation region 18 disposed around the fourth well region 16. The isolation structure is configured to separate the operating region from the peripheral region of the optoelectronic device 100, preventing photogenerated carriers from diffusing from the operating region to the peripheral region, while the peripheral region does not affect the normal operation of the optoelectronic device 100. Exemplarily, the isolation region 18 includes an insulating material. The isolation region 18 can be either deep trench isolation or shallow trench isolation.

[0086] Based on the above description, the optoelectronic device 100 provided in this application can be used for single-photon detection. It should be noted that the optoelectronic device 100 provided in this application can adapt to both normal incidence and back incidence photon detection methods.

[0087] In one embodiment, the single-photon avalanche diode is a front-incident type, and its light-incident surface is the first surface 101. For example... Figure 7 As shown, this diagram illustrates the optoelectronic device 100 provided in this application under normal incidence. Under normal incidence, incident light shines on the optoelectronic device 100 along the direction from the first surface 101 to the second surface 102, exciting the carrier drift region 15 to generate photogenerated electron-hole pairs. Under the action of an applied electric field, the photogenerated electron-hole pairs accelerate and collide with the crystal lattice, ultimately forming an avalanche current.

[0088] In another embodiment, the single-photon avalanche diode is a back-input type, with its light-input surface being the second surface 102. For example... Figure 8 As shown, this is a schematic diagram of the optoelectronic device 100 provided in this application under back-incidence conditions. Under back-incidence conditions, incident light shines on the optoelectronic device 100 along the direction from the second surface 102 to the first surface 101, exciting the carrier drift region 15 to generate photogenerated electron-hole pairs. Under the action of an applied electric field, the photogenerated electron-hole pairs accelerate and collide with the crystal lattice, eventually forming an avalanche current.

[0089] like Figure 9 As shown, as an optional implementation, a light trapping structure 18 is also provided on the substrate near the second surface 102. By using the light trapping structure 18, as many incident photons as possible can be absorbed, thereby improving the photodetection efficiency of the optoelectronic device 100.

[0090] like Figure 10 As shown, as an optional implementation, a microlens array 21 is also provided on the outer side of the second surface 102. The microlens array 21 can be solid or liquid. Using the microlens array 21, incident light can be focused onto the working area of ​​the optoelectronic device 100, thereby improving the photon detection efficiency of the optoelectronic device 100.

[0091] As an optional implementation, the boundary profile of the third well region 13 can be either a circle or a regular polygon. Specifically, for example... Figure 11A , Figure 11B and Figure 11C As shown, this application provides schematic diagrams of three planar shapes of optoelectronic devices 100.

[0092] like Figure 11A As shown, from the inside out, the projections of the first highly doped region 14, the first well region 11, the second well region 12, and the third well region 13 onto a plane (such as the first surface 101) are as follows: the first highly doped region 14, the first well region 11, the second well region 12, and the third well region 13 are all circular.

[0093] like Figure 11B and Figure 11C As shown, the projections of the first highly doped region 14, the first well region 11, the second well region 12, and the third well region 13 onto the first surface 101 can also be octagonal or square.

[0094] It should be noted that the well region of the optoelectronic device 100 can also be designed in other shapes. Optoelectronic devices 100 composed of well regions of other shapes or composed of combinations of well regions of different shapes are also within the scope of protection of this application.

[0095] This application also provides a photoelectric detection device 200, which includes: a substrate, and a photoelectric device array disposed on the substrate, the photoelectric device array including a plurality of photoelectric devices 100 provided in the embodiments of this application.

[0096] As an optional implementation, an isolation region 18 with electrical isolation function is disposed between adjacent optoelectronic devices 100. For example, Figure 12 As shown, several single-photon avalanche diodes are arranged in an array to form a pixel array. Due to the isolation region 18 set for each single-photon avalanche diode, crosstalk between adjacent avalanche diodes can be avoided.

[0097] This application also provides a method for fabricating an optoelectronic device, used to prepare the optoelectronic device provided in the embodiments of this application. The method includes the following steps:

[0098] A substrate is provided, the substrate being of a second conductivity type, the substrate having opposing first and second surfaces;

[0099] A working region is set at a selected location on the substrate, and ions of a second conductivity type are implanted around the working region to form a fourth well region;

[0100] Ion implantation of a second conductivity type is performed at a third depth from the first surface in the working area to form a third well region;

[0101] Ion implantation of a first conductivity type is performed at a second depth from the first surface in the working area to form a second well region. The second depth is less than the third depth. The side of the second well region away from the first surface is in contact with the side of the third well region close to the first surface.

[0102] Ion implantation of a first conductivity type is performed at a first depth from the first surface in the working area to form a first well region, the first depth being less than the second depth;

[0103] A first conductivity type is heavily doped at a selected location on the substrate to form a first highly doped region that extends from a first surface to a third well region and is surrounded by a first well region and a second well region.

[0104] A second highly doped region of a second conductivity type is formed near the first surface in the fourth well region to form a second highly doped region exposed on the first surface.

[0105] The first well region is exposed on the first surface and is configured to have the effect of a passivation layer to reduce the surface electric field of the first surface.

[0106] Specifically, let's take an example where the first conductivity type is N-type and the second conductivity type is P-type:

[0107] In the case of N-type conductivity, the dopant may include boron, boron difluoride, or indium; in the case of P-type conductivity, the dopant may include arsenic, phosphorus, or nitrogen.

[0108] A P-type substrate can be grown on a substrate, and a working region can be set at a selected location on the substrate. A deep P-well fabrication process is performed around the working region to form a fourth well region. Within the working region, P-type doping is performed at a third depth from the first surface to form a third well region; N-type doping is performed at a second depth from the first surface to form a second well region; and N-type doping is performed at a first depth from the first surface to form a first well region, wherein the third depth is greater than the second depth, and the second depth is greater than the first depth. N-type heavy doping is performed at a selected location on the substrate to form a first highly doped region extending from the first surface to the third well region and surrounded by the first and second well regions. P-type heavy doping is performed near the first surface of the fourth well region to form a second highly doped region, which is exposed on the first surface.

[0109] It should be noted that the first well region is exposed on the first surface, and the first well region is configured to have the effect of a passivation layer to reduce the surface electric field of the first surface.

[0110] In some embodiments, the fabrication method further includes performing a DTI (Deep Trench Insulator) fabrication process or an STI (Shallow Trench Insulator) fabrication process on the periphery of the fourth well region.

[0111] In some embodiments, the fabrication method further includes fabricating a light trapping structure near the second surface of the substrate.

[0112] In some embodiments, the substrate is subjected to a reverse doping process, such that the concentration of impurities of a second conductivity type in the substrate decreases from the second surface to the first surface.

[0113] It should be noted that the preparation methods provided in the embodiments of this application are not intended to describe a specific order. In some cases, the order of the preparation methods can be interchanged. For example, the order in which the first highly doped region and the second highly doped region are prepared can be interchanged.

[0114] In the description of this application, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0115] The above-disclosed embodiments are merely preferred embodiments of this application, but are not intended to limit the scope of this application. Those skilled in the art will understand that any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and scope of this application and the appended claims are equivalent substitutions and still fall within the scope of the invention.

[0116] The application fields of the present invention include, but are not limited to, the field of electronic power conversion technology. As long as the essence of the technical solution does not deviate from the scope of the technical solutions of the various embodiments of the present invention, it shall fall within the protection scope of the present invention.

[0117] Although preferred embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will recognize that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present application as disclosed in the appended claims.

Claims

1. An optoelectronic device, characterized in that, include: A substrate having a first surface and a second surface opposite to the first surface; A working area, located in the substrate, comprising: A first well region extending downward from a first surface of the substrate, the first well region being of a first conductivity type, the first well region being configured to have the effect of a passivation layer to reduce the surface electric field of the first surface; A second well region located below the first well region, the second well region being of the first conductivity type; A third well region located below the second well region, the third well region being of a second conductivity type; and, A first highly doped region, which is of a first conductivity type and has a doping concentration at least greater than that of the first well region and / or the second well region, extends from the first surface to the third well region and is surrounded by the first well region and the second well region; The optoelectronic device further includes a fourth well region distributed outside the working area. The fourth well region is of the second conductivity type. A second highly doped region is provided near the first surface of the fourth well region. The second highly doped region is of the second conductivity type and is exposed on the first surface. The doping concentration of the second highly doped region is greater than that of the fourth well region. The third well region forms an avalanche region with at least one of the second well region and the first highly doped region.

2. The optoelectronic device as described in claim 1, characterized in that: The width of the first highly doped region is smaller than that of the first well region and / or the second well region; The width of the third well region is greater than that of the first well region and / or the second well region.

3. The optoelectronic device as described in claim 1, characterized in that: The working area also includes a carrier drift region of a second conductivity type, wherein the doping concentration of the carrier drift region has a gradient change along the depth direction from the first surface to the second surface, and the built-in electric field generated by the gradient change satisfies the condition that the carriers formed in the carrier drift region are driven toward the avalanche region, wherein the first surface and the second surface are two opposing surfaces of the substrate.

4. The optoelectronic device as described in claim 3, characterized in that: The doping concentration of the fourth well region is greater than that of the carrier drift region and / or the third well region, thereby generating a built-in electric field pointing towards the fourth well region and driving the carriers in the carrier drift region to move towards the avalanche region.

5. The optoelectronic device as described in claim 1, characterized in that: It also includes an isolation zone, which is located around the fourth well region. The isolation zone is either a deep trench isolation zone or a shallow trench isolation zone.

6. The optoelectronic device according to any one of claims 1 to 5, characterized in that: The substrate is further provided with a light trapping structure near the second surface, and a microlens array is further provided on the outer side of the second surface, wherein the first surface and the second surface are two opposing surfaces of the substrate.

7. The optoelectronic device as described in claim 1, characterized in that, The optoelectronic device is a single-photon avalanche diode sensor. The first conductivity type is N-type, and the second conductivity type is P-type; Alternatively, the first conductivity type is P-type, and the second conductivity type is N-type.

8. A photoelectric detection device, characterized in that, include: substrate, An array of optoelectronic devices disposed on the substrate, the array of optoelectronic devices comprising a plurality of optoelectronic devices as described in any one of claims 1-7.

9. The photoelectric detection device as described in claim 8, characterized in that: The photoelectric detection device is of the positive-incident type, and its light-incident surface is the first surface; Alternatively, the photoelectric detection device is a back-input type, with its light-input surface being the second surface, wherein the first surface and the second surface are two opposing surfaces of the substrate.

10. A method for fabricating an optoelectronic device as described in any one of claims 1 to 7, characterized in that, The preparation method includes the following steps: A substrate is provided, the substrate being of a second conductivity type, the substrate having opposing first and second surfaces; A working region is set at a selected location on the substrate, and ions of a second conductivity type are implanted around the working region to form a fourth well region; Ion implantation of a second conductivity type is performed at a third depth from the first surface in the working area to form a third well region; Ion implantation of a first conductivity type is performed at a second depth in the working area from the first surface to form a second well region. The second depth is less than the third depth. The side of the second well region facing away from the first surface is in contact with the side of the third well region close to the first surface. Ion implantation of a first conductivity type is performed at a first depth in the working area from the first surface to form a first well region, the first depth being less than the second depth; A first conductivity type is heavily doped at a selected location on the substrate to form a first highly doped region that extends from the first surface to the third well region and is surrounded by the first well region and the second well region. A second conductivity type is heavily doped in the fourth well region near the first surface to form a second highly doped region, which is exposed on the first surface. The first well region is exposed on the first surface and is configured to have the effect of a passivation layer to reduce the surface electric field of the first surface.

11. The method for fabricating the optoelectronic device as described in 10, characterized in that, The substrate is subjected to a reverse doping process, such that the concentration of impurities of the second conductivity type in the substrate decreases from the second surface to the first surface.

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