SDD high-counting-rate pulse signal processing method, system, equipment and medium

Abstract

The invention discloses an SDD high-counting-rate pulse signal processing method, system and device and a medium, and belongs to the field of digital signal processing.The method comprises the steps that pulse charges output by an SDD are read in real time through a transistor reset type pre-amplifier, and original step voltage signals are output according to the pulse charges; acquiring, converting and outputting an original step voltage signal into a first digital signal in real time through a first channel; collecting, converting and outputting the effective voltage signal into a second digital signal in real time through a second channel; wherein the effective voltage signal is obtained by subtracting the bias voltage signal from the original step voltage signal; when the second digital signal is greater than or equal to a first preset threshold value, processing the first digital signal through a bias following algorithm to update a bias voltage signal output by the digital-to-analog converter; and processing the second digital signal output by the second channel in real time through a preset digital signal processing algorithm. According to the invention, the problem of low resolution of an SDD system under a high counting rate can be solved.

Description

Technical Field

[0001] This application relates to the field of digital signal processing, and in particular to a method, system, device and medium for processing high count rate pulse signals using SDD. Background Technology

[0002] Silicon drift detectors (SDDs) can achieve extremely high count rates and excellent energy resolution for detecting low-energy X-rays, representing the highest performance level in the field of X-ray energy spectroscopy measurement. They are core components of X-ray fluorescence analysis and electron microscopy spectrometers, and are widely used in materials science, advanced manufacturing, life sciences, and space exploration.

[0003] However, the optimal performance of SDD heavily relies on a high-performance readout electronics system. Current mainstream SDD energy spectrum measurement systems are based on TRP, CR differentiators, and digital trapezoidal filtering algorithms; however, they generally suffer from reduced energy resolution when processing high count rate signals. This phenomenon is mainly caused by two factors: first, the baseline calculation frequency of the filter decreases as the count rate increases, leading to a larger baseline sampling interval and introducing errors; second, in the exponential pulse processing path obtained through analog differentiator conversion, the non-ideal characteristics of the capacitors (such as dielectric absorption (DA) and equivalent series resistance) cause distortion of the pulse signal after CR differentiation, especially long tailing. At high count rates, this distortion significantly exacerbates baseline drift and fluctuations, severely deteriorating the system's energy resolution and limiting the overall performance of the detection system in high-throughput scenarios.

[0004] Therefore, improving the resolution of SDD systems at high count rates is a technical problem that needs to be solved. Summary of the Invention

[0005] This application provides a method, system, device, and medium for processing high count rate pulse signals in SDD, which can solve the problem of significant resolution degradation in SDD systems under high count rates in the prior art.

[0006] This application provides a high-count-rate SDD pulse signal processing method in some embodiments, applied to a digital pulse signal processing device. The digital pulse signal processing device includes: a transistor-reset preamplifier, a dual-channel analog-to-digital converter (ADC), and a digital-to-analog converter (DAC); the dual-channel ADC includes: a first channel and a second channel; the SDD high-count-rate pulse signal processing method includes: The transistor-reset preamplifier reads the pulse charge output by SDD in real time and outputs the original step voltage signal based on the pulse charge. The original step voltage signal is acquired in real time through the first channel, and the original step voltage signal is converted and output as a first digital signal. The effective voltage signal is acquired in real time through the second channel and converted into a second digital signal; wherein, the effective voltage signal is calculated by subtracting the bias voltage signal output by the current digital-to-analog converter from the original step voltage signal; When the second digital signal is greater than or equal to the first preset threshold, the first digital signal is processed by the bias follower algorithm, and the bias voltage signal output by the digital-to-analog converter is updated according to the processing result. The second digital signal output from the second channel is processed in real time using a preset digital signal processing algorithm.

[0007] Compared to existing technologies, the above embodiments have the following advantages: First, the first channel retains the original step voltage signal, and the second channel obtains the effective voltage signal by subtracting the bias voltage signal from the original step voltage signal. Since the bias voltage signal is output by the digital-to-analog converter and can be updated in real time, the amplitude of the effective voltage signal after the bias update can be kept in the near-zero range, facilitating the next stage of amplification. The traditional differential capacitor is eliminated from the front-end structure, thus eliminating signal distortion caused by the non-ideal characteristics of the capacitor at its source. Second, when the effective voltage signal exceeds a threshold, a bias following algorithm is triggered, using the first channel signal to estimate the baseline offset in real time and synchronously updating the DAC output, synchronizing the baseline compensation behavior with the event occurrence. Since the compensation action is based on real-time sampled data rather than fixed-period calculation, its compensation frequency automatically increases with the count rate, achieving faster baseline updates with higher count rates, thereby ensuring that all effective X-ray events remain within the dynamic range of the second channel. Finally, when the second channel signal after bias compensation enters the digital signal processing algorithm, the subsequent trapezoidal filtering is no longer affected by nonlinear distortion, thus significantly improving the energy spectrum stability and resolution.

[0008] Further, the step of processing the second digital signal output from the second channel in real time using a preset digital signal processing algorithm includes: Based on the peak arrival time of the second digital signal, the second digital signal is shaped into a triangular channel signal and a trapezoidal channel signal, respectively; wherein the peak arrival time of the triangular channel signal is shorter than the peak arrival time of the trapezoidal channel signal. The event stack triggered in the trapezoidal channel signal is determined based on the triangular channel signal; The baseline mean is obtained by processing the first signal segment in the trapezoidal channel signal that has not triggered the events by a moving average filter. The absolute height of the trapezoid in the trapezoidal channel signal is calculated based on the baseline mean to form energy spectrum data.

[0009] Compared to existing technologies, the above embodiments offer the following advantages: by shaping the second digital signal into triangular channel signals and trapezoidal channel signals respectively, trigger detection and energy extraction are structurally separated. The triangular channel signal has a shorter peak time, enabling faster response to pulse changes and identification of the trigger moment; the trapezoidal channel signal has a longer integration window, allowing for stable energy calculation. After pile-up identification, only the trapezoidal signal segments that have not been triggered for pile-up are averaged, thus avoiding pile-up pulse interference with baseline estimation and ensuring that the energy calculation benchmark remains undisturbed. This design allows triggering and energy shaping to be handled by different structures, reducing the transmission of pile-up effects at the functional level from the source, thereby maintaining the stability of energy spectral resolution in high count rate environments.

[0010] Further, determining the stack of triggered events in the trapezoidal channel signal based on the triangular channel signal includes: The trigger signal in the triangular channel signal is determined by finding the zero-crossing point of the bipolar triangle after differentiation of the triangular channel signal. The stage markers in the trapezoidal channel signal are determined based on the trigger signals in the triangular channel signal. The stack of triggered events is determined based on the occurrence times of all the aforementioned trigger signals and all the aforementioned stage markers.

[0011] Compared to existing technologies, the above embodiments have the following advantages: By differentiating the triangular channel signal and utilizing the zero-crossing point of its bipolar structure to determine the trigger signal, the trigger recognition process is independent of amplitude magnitude but relies on signal variation characteristics. Therefore, stable trigger times can still be obtained under different pulse amplitude conditions. Subsequently, all trigger times are mapped to different stage markers of the trapezoidal channel, so that the stacking judgment no longer depends on the shape of a single pulse but on the relative positional relationship of different pulses in time. This recognition method is based on relative time structure rather than amplitude difference, which can prevent weak pulses from being ignored or noise from being incorrectly identified as stacking events, thereby improving the accuracy of stacking detection and providing a stable event classification basis for subsequent baseline recovery algorithms.

[0012] Further, the stage markers include: a trapezoidal rise time marker, a trapezoidal flat-top time marker, and a trapezoidal fall time marker; determining the stack of triggered events based on the occurrence times of all the trigger signals and all the stage markers includes: When the trapezoidal channel signal is at the trapezoidal rising moment mark, and the triangular channel signal has two trigger signals, it is determined that the trapezoidal channel signal is currently in a rising accumulation state. When the trapezoidal channel signal has experienced the trapezoidal rising moment mark and is at the trapezoidal flat top moment mark, and the triangular channel signal has two trigger signals, it is determined that the trapezoidal channel signal is currently in a flat top stacking state. When the trapezoidal channel signal has successively experienced the trapezoidal rising time mark and the trapezoidal flat top time mark, and is at the trapezoidal falling time mark, and the triangular channel signal has two trigger signals, then it is determined that the trapezoidal channel signal is currently in a falling accumulation state.

[0013] Compared to existing technologies, the above embodiments have the following advantages: By combining the rising, flat-top, and falling phase markers of the trapezoidal channel signal and determining the accumulation phase based on the number of trigger signals in the triangular channel, the accumulation event can be classified and identified. When accumulation occurs in the rising phase, it directly affects the peak formation process, so all rising accumulation pulses are rejected; when it occurs in the flat-top phase, it changes the flat-top region, so when flat-top accumulation occurs, pulses that have completed amplitude extraction are retained, while pulses that have not completed amplitude extraction are rejected; when it occurs in the falling phase, it does not affect the flat-top region of the next pulse, and all pulse signals are retained. Since accumulation identification no longer depends on changes in pulse amplitude or slope, but is based on a combination of phase markers and the number of triggers, it can maintain identification stability in high count rate scenarios, which helps to reduce the impact of accumulation on energy output results.

[0014] Further, the step of processing the first digital signal through a bias follower algorithm and updating the bias voltage signal output by the digital-to-analog converter according to the processing result when the second digital signal is greater than or equal to the first preset threshold includes: Determine whether the second digital signal is greater than or equal to a second preset threshold; wherein the second preset threshold is greater than the first preset threshold; the second preset threshold is the minimum second digital signal output by the second channel when multiple consecutive events accumulate; If the second digital signal is less than the second preset threshold, a timer is started, and when the count of the timer equals a preset time, a first bias voltage signal is output through the digital-to-analog converter; wherein, the first bias voltage signal is a voltage signal that is lower than the third preset threshold of the current original step voltage signal; If the second digital signal is greater than or equal to the second preset threshold, and the transition of the first digital signal ends, then the first bias voltage signal is output through the digital-to-analog converter.

[0015] Compared to existing technologies, the above embodiments have the following advantages: By setting two different thresholds and combining a timer mechanism with a transition termination condition, the bias adjustment no longer depends on a fixed period but is triggered by the signal state. When the second digital signal exceeds the first threshold but is below the second threshold, the system does not immediately adjust the bias but starts a timer, outputting the first bias voltage only after the timer reaches a preset value. The preset value is the rise time plus the flat-top time of the trapezoid, which can maximize the preservation of effective X-ray events. When the second digital signal exceeds the second threshold and the first channel signal has completed the transition phase, the bias update is immediately performed, thereby ensuring that the compensation action only occurs when the actual accumulation forms an offset. This method keeps the bias adjustment synchronized with the signal evolution process, reduces the baseline offset of the second digital signal after the bias update, and maximizes the utilization of the second channel's range.

[0016] Furthermore, before processing the first signal segment in the trapezoidal channel signal that did not trigger the accumulation of the event by the moving average filtering, the method further includes: filtering out noise signals in the trapezoidal channel signal by a fourth preset threshold; wherein the fourth preset threshold is the amplitude of the smallest unidentifiable signal in the triangular channel signal.

[0017] Compared to existing technologies, the above embodiments have the following advantages: a fourth threshold is introduced before the moving average, and based on this threshold, minute amplitude signals that cannot be recognized by the triangular channel are filtered out, ensuring that the segments entering the averaging operation consist only of true baseline segments. Since this threshold is set based on the minimum signal amplitude that the triangular channel can recognize, noise components can be eliminated without losing effective pulse information, thereby maintaining a low baseline estimation error even when the count rate increases, providing a stable reference basis for energy extraction.

[0018] Furthermore, the SDD high count rate pulse signal processing method further includes: real-time detection of the reset state of the transistor reset type preamplifier; when the transistor reset type preamplifier is reset, outputting a second bias voltage signal through the digital-to-analog converter; wherein the second bias voltage signal is a voltage signal lower than a fifth preset threshold of the historical minimum original step voltage signal.

[0019] Compared with the prior art, the above embodiments have the following beneficial effects: by detecting the preamplifier reset state in real time and forcibly outputting the second bias voltage when the reset occurs, the effective voltage signal is suppressed to a range lower than the threshold corresponding to the historical minimum step voltage, thereby ensuring that the second digital signal remains within the range of the second channel after the preamplifier is reset.

[0020] Another embodiment of this application provides an SDD high count rate pulse signal processing system, applied to a digital pulse signal processing device, the digital pulse signal processing device including: a transistor reset type preamplifier, a dual-channel analog-to-digital converter, and a digital-to-analog converter; the dual-channel analog-to-digital converter includes: a first channel and a second channel; the SDD high count rate pulse signal processing system includes: a transistor reset type preamplifier module, a first channel module, a second channel module, a bias module, and a digital pulse processing module; The transistor-reset preamplifier module is used to read the pulse charge output by SDD in real time through the transistor-reset preamplifier, and output the original step voltage signal according to the pulse charge; The first channel module is used to acquire the original step voltage signal in real time through the first channel and convert the original step voltage signal into a first digital signal. The second channel module is used to acquire an effective voltage signal in real time through the second channel and convert the effective voltage signal into a second digital signal; wherein, the effective voltage signal is calculated by subtracting the bias voltage signal output by the current digital-to-analog converter from the original step voltage signal; The bias module is used to process the first digital signal through a bias following algorithm when the second digital signal is greater than or equal to a first preset threshold, and update the bias voltage signal output by the digital-to-analog converter according to the processing result. The digital pulse processing module is used to process the second digital signal output from the second channel in real time using a preset digital signal processing algorithm.

[0021] Another embodiment of this application also provides a terminal device, including: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the steps of the SDD high count rate pulse signal processing method of this application.

[0022] Another embodiment of this application also provides a computer-readable storage medium item, including: a stored computer program, which, when the computer program is running, controls the device where the computer-readable storage medium is located to perform the steps of the SDD high count rate pulse signal processing method of this application. Attached Figure Description

[0023] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a flowchart illustrating a high count rate pulse signal processing method for SDD provided in some embodiments of this application; Figure 2 This is a schematic diagram of the structure of a digital pulse signal processing device provided in some embodiments of this application; Figure 3 This is a step signal diagram after applying the DCA bias follower algorithm and amplifying the output signal of a second channel provided in some embodiments of this application; Figure 4 This is a schematic diagram of a bias following algorithm provided in some embodiments of this application; Figure 5 This is a flowchart illustrating a digital pulse processing link provided in some embodiments of this application; Figure 6 This is a schematic diagram of a slow threshold discrimination method provided in some embodiments of this application; Figure 7 This is a state transition diagram of a stacking rejector provided in some embodiments of this application; Figure 8 This is a baseline histogram comparison of a DAC bias follower scheme and a CR differentiator scheme provided in some embodiments of this application; Figure 9 This is a comparison chart of the resolution stability of a DAC bias follower scheme and a CR differentiator scheme provided in some embodiments of this application; Figure 10 This is a schematic diagram of the structure of an SDD high count rate pulse signal processing system provided in some embodiments of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0027] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0029] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0030] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0031] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0032] Current mainstream SDD energy dispersive spectroscopy (SDD) systems are based on TRP (Transient Regression Precision), CR (Regression-Based Differentiation), and digital trapezoidal filtering algorithms. However, they generally suffer from reduced energy resolution when processing high count rate signals. This phenomenon is mainly caused by two factors: First, the baseline calculation frequency of the filter decreases as the count rate increases, leading to a larger baseline sampling interval and introducing errors. Second, in the exponential pulse processing path obtained through analog differentiator conversion, the non-ideal characteristics of the capacitor (such as dielectric absorption (DA) and equivalent series resistance) cause distortion of the pulse signal after CR differentiation, especially long tailing. At high count rates, this distortion significantly exacerbates baseline drift and fluctuations, severely deteriorating the system's energy resolution and limiting the performance of the entire detection system in high-throughput scenarios.

[0033] Please refer to Figure 1 To address the problem of improving the resolution of SDD systems at high count rates in existing technologies, this application provides a high count rate pulse signal processing method for SDD, which is applied to a digital pulse signal processing device. The digital pulse signal processing device includes: a transistor reset type preamplifier, a dual-channel analog-to-digital converter, and a digital-to-analog converter; the dual-channel analog-to-digital converter includes: a first channel and a second channel.

[0034] Preferably, refer to Figure 2 This is a schematic diagram of the structure of a digital pulse signal processing device provided in some embodiments of this application. The digital pulse signal processing device includes: a detector (SDD), a transistor reset-type preamplifier (TRP), a digital-to-analog converter (DAC), a subtractor, an operational amplifier, a dual-channel analog-to-digital converter (ADC), and an FPGA chip embedded with digital signal processing algorithms. The dual-channel ADC includes an A channel (i.e., the first channel) and a B channel (the second channel). The digital signal processing algorithms include: a fast triangle filter, a slow trapezoidal filter, a baseline restorer, a stacking rejector, and a bias follower algorithm.

[0035] from Figure 2As shown in the schematic diagram, the digital pulse signal processing device provided in this embodiment divides the original step voltage signal output by the transistor-reset preamplifier into two paths: one path is directly connected to the A channel of the ADC to provide an instantaneous level value for the real-time calculation of the bias follower algorithm, and is output to the bias follower DAC, whose generated bias voltage signal is input to the inverting input of the subtractor; the other path of the original step voltage signal is connected to the non-inverting input of the subtractor, and after subtracting the bias voltage signal generated by the DAC, it is input to the next stage operational amplifier for amplification, and finally acquired by the B channel of the ADC. This design can enable the bias follower DAC to output the original step voltage signal acquired by the A channel when the FPGA detects that the amplified step signal (i.e., the second digital signal) acquired by the B channel is out of range, and pull the signal back to near 0 V through the subtractor, so as to keep the signal within the input range of the ADC while the operational amplifier continues to amplify the subsequent effective signals.

[0036] Figure 1 The SDD high count rate pulse signal processing method shown includes S101 to S105, specifically as follows: S101: The pulse charge output by SDD is read in real time through the transistor reset type preamplifier, and the original step voltage signal is output according to the pulse charge.

[0037] S102: The original step voltage signal is acquired in real time through the first channel, and the original step voltage signal is converted and output as a first digital signal.

[0038] S103: The effective voltage signal is acquired in real time through the second channel, and the effective voltage signal is converted and output as a second digital signal; wherein, the effective voltage signal is calculated by subtracting the bias voltage signal output by the current digital-to-analog converter from the original step voltage signal.

[0039] refer to Figure 3 This is a step signal diagram of the output signal of the second channel provided in this application embodiment, after applying the DCA bias follower algorithm and amplifying it, i.e., the effective voltage signal. Figure 3 The corresponding dual-mode ADC used is the AD9251, which features 14-bit resolution, an 80MHz sampling rate, an input range of ±1V, and supports dual-channel synchronous sampling. Its original output is a 14-bit offset binary code, which is converted to 16-bit two's complement binary code within the FPGA for subsequent calculations. Therefore, a signal that originally corresponds to an analog input range of ±1V is represented in the digital domain as a value ranging from 0 to 2V. Figure 3The solid blue line represents the amplified and conditioned step signal (i.e., the effective voltage signal) acquired by the second channel of the AD9251. To amplify the ±1V step signal output by the TRP while ensuring that the amplified signal remains within the input range of the AD9251, the system incorporates a bias follower DAC and a fixed bias DAC to jointly perform level adjustment. The digital pulse processor uses the AD9767 as the bias follower DAC. This device has 14-bit resolution, and its clock interface is connected to the AD9251's 80MHz accompanying clock via the FPGA's internal global clock buffer. Actual measurements show that the AD9767's output voltage settling time is less than 200 ns, indicating its fast bias update capability and minimal introduction of dead time.

[0040] S104: When the second digital signal is greater than or equal to the first preset threshold, the first digital signal is processed by the bias follower algorithm, and the bias voltage signal output by the digital-to-analog converter is updated according to the processing result.

[0041] Furthermore, in some embodiments of this application, the step of processing the first digital signal through a bias follower algorithm and updating the bias voltage signal output by the digital-to-analog converter according to the processing result when the second digital signal is greater than or equal to a first preset threshold includes: Determine whether the second digital signal is greater than or equal to a second preset threshold; wherein the second preset threshold is greater than the first preset threshold; the second preset threshold is the minimum second digital signal output by the second channel when multiple consecutive events accumulate; If the second digital signal is less than the second preset threshold, a timer is started, and when the count of the timer equals a preset time, a first bias voltage signal is output through the digital-to-analog converter; wherein, the first bias voltage signal is a voltage signal that is lower than the third preset threshold of the current original step voltage signal; If the second digital signal is greater than or equal to the second preset threshold, and the transition of the first digital signal ends, then the first bias voltage signal is output through the digital-to-analog converter.

[0042] This application sets two different thresholds and combines a timer mechanism with a transition termination condition to make bias adjustment no longer dependent on a fixed period, but triggered by the signal state. When the second digital signal exceeds the first threshold but is below the second threshold, the system does not immediately adjust the bias, but starts a timer. The first bias voltage is output only after the timer reaches a preset value, which is the rise time plus the flattening time of a trapezoid, maximizing the preservation of valid X-ray events. Only when the second digital signal exceeds the second threshold and the first channel signal has completed its transition phase is the bias update performed immediately, ensuring that compensation only occurs when actual accumulation forms an offset. This method synchronizes bias adjustment with the signal evolution process, reduces baseline offset of the second digital signal after the bias update, and maximizes the utilization of the second channel's range.

[0043] Furthermore, in some embodiments of this application, the SDD high count rate pulse signal processing method further includes: real-time detection of the reset state of the transistor reset type preamplifier; when the transistor reset type preamplifier is reset, outputting a second bias voltage signal through the digital-to-analog converter; wherein the second bias voltage signal is a voltage signal lower than a fifth preset threshold of the historical minimum original step voltage signal.

[0044] This application detects the preamplifier reset status in real time and forces the output of a second bias voltage when a reset occurs, so that the effective voltage signal is suppressed to a range lower than the threshold corresponding to the historical minimum step voltage, thereby ensuring that the second digital signal remains within the range of the second channel after the preamplifier is reset.

[0045] Specifically, refer to Figure 4The schematic diagram of the bias algorithm shows that when the second channel signal exceeds the first preset threshold and the rising edge of the step pulse has ended, counter C is started. When the count of C reaches the sum of the preset trapezoidal rise time and the flat-top time, the counter is cleared, and the DAC updates its output value to be slightly lower than the amplitude of the current original step voltage signal acquired by the first channel. This counting mechanism ensures that the bias voltage remains stable before the trapezoidal formation of the current pulse event is completed and the amplitude has not been extracted, thus ensuring that the amplitude extraction is completed before the bias update. The margin of the first preset threshold is slightly higher than the amplitude of a single event pulse, which ensures that the second channel can fully acquire the signal when it is about to exceed the threshold and a single event arrives. If the second digital signal exceeds the second preset threshold, it means that two or more consecutive events have accumulated in the system, causing the original step voltage signal to exceed the input range of the second channel before the DAC bias update. At this time, the state of the first channel is detected, and when the accumulated X-ray event transition ends (i.e., after the first channel signal transition ends), the DAC updates its output value to be slightly lower than the current original step voltage signal acquired by the first channel. This design enables accurate bias adjustment, maximizing the utilization of the second channel's range without introducing excessive dead time. During DAC bias updates, the second channel cannot acquire the complete stacked signal. Such signals, after trapezoidal shaping, typically exhibit rising-edge stacking or flat-top stacking characteristics, and their pulse amplitude will be judged and discarded in the stack rejection logic. The stacking event loss caused by this mechanism is acceptable to the system. Furthermore, when TRP resets and the output voltage drops sharply from its maximum to its minimum value, the bias follower DAC responds immediately, updating its output to slightly below the minimum TRP output voltage. This strategy ensures that the step signal is always positively amplified and that the effective data is within the ADC's range. It is important to note that, similar to the TRP reset process, the downward-jumping data caused by the DAC bias update is masked to avoid generating a reverse trapezoidal shape with abnormal amplitude. Finally, the fixed-bias DAC is responsible for shifting the amplified TRP step signal, which is in the 0~2V range, to the ±1V range, matching it with the ADC's input dynamic range, thereby optimizing the ADC's range utilization and signal digitization accuracy.

[0046] S105: The second digital signal output from the second channel is processed in real time using a preset digital signal processing algorithm.

[0047] Furthermore, in some embodiments of this application, the step of processing the second digital signal output from the second channel in real time using a preset digital signal processing algorithm includes: Based on the peak arrival time of the second digital signal, the second digital signal is shaped into a triangular channel signal and a trapezoidal channel signal, respectively; wherein the peak arrival time of the triangular channel signal is shorter than the peak arrival time of the trapezoidal channel signal. The event stack triggered in the trapezoidal channel signal is determined based on the triangular channel signal; The baseline mean is obtained by processing the first signal segment in the trapezoidal channel signal that has not triggered the events by a moving average filter. The absolute height of the trapezoid in the trapezoidal channel signal is calculated based on the baseline mean to form energy spectrum data.

[0048] Preferably, in some embodiments of this application, the step of shaping the second digital signal into a triangular channel signal and a trapezoidal channel signal according to the peak time of the second digital signal includes: the amplified step signal (i.e. the second digital signal) collected by channel B is divided into two paths, one path is shaped into a triangle with a shorter peak time, and during the period when the triangle pulse exceeds the trigger threshold, the zero-crossing point of its differential bipolar triangle is found to generate a trigger signal; the other path is shaped into a trapezoid with a longer peak time.

[0049] refer to Figure 5 The flowchart of the digital pulse processing link shown can be interpreted in some embodiments of this application as follows: when the second digital signal output from the second channel is processed in real time using a preset digital signal processing algorithm, it can be achieved through... Figure 5 The digital pulse processing link shown processes the second digital signal. The complete digital pulse processing link includes a fast triangle filter, a slow trapezoidal filter, a baseline restorer, a stacking rejector, and a peak detector. Timing information, trigger event count, count rate statistics, waveform, baseline histogram, and energy spectrum are transmitted to the host computer via UDP and TCP protocols, respectively. After further differentiation of the fast triangle, a bipolar triangle is obtained. During periods when the amplitude of the fast triangle exceeds the fast threshold, the zero-crossing point of the bipolar triangle is detected to generate a trigger, avoiding timing deviations caused by different fast threshold settings. This trigger signal is synchronized with the slow trapezoidal filter and generates rise, flat, fall, and base flag signals through a counter to identify the current forming stage of the slow trapezoidal filter, thereby controlling the state transitions of the baseline restorer and the stacking rejector.

[0050] Because the step signal output by the SDD is superimposed with deviations caused by detector leakage current, electronic noise, etc., trapezoidal shaping of the noisy step signal cannot eliminate baseline offset. To determine the actual height of the trapezoid, accurate baseline estimation is required. Baseline calculation is achieved using a moving average filter and a gating scheme.

[0051] This application structurally separates trigger detection and energy extraction by shaping the second digital signal into triangular and trapezoidal channel signals. The triangular channel signal has a shorter peak time, enabling faster response to pulse changes and identification of the trigger moment; the trapezoidal channel signal has a longer integration window, allowing for stable energy calculation. After pile-up identification, only the trapezoidal signal segments that have not been triggered by pile-up are averaged, thus avoiding interference from pile-up pulses in baseline estimation and ensuring that the energy calculation benchmark remains undisturbed. This design separates triggering and energy shaping into different structures, reducing the transmission of pile-up effects at the functional level from the source, thereby maintaining the stability of energy spectral resolution in high count rate environments.

[0052] Furthermore, in some embodiments of this application, determining the stacking of triggered events in the trapezoidal channel signal based on the triangular channel signal includes: The trigger signal in the triangular channel signal is determined by finding the zero-crossing point of the bipolar triangle after differentiation of the triangular channel signal. The stage markers in the trapezoidal channel signal are determined based on the trigger signals in the triangular channel signal. The stack of triggered events is determined based on the occurrence times of all the aforementioned trigger signals and all the aforementioned stage markers.

[0053] Preferably, in some embodiments of this application, determining the stage flags in the trapezoidal channel signal based on the trigger signal in the triangular channel signal includes: synchronizing the trigger signal of the triangular channel signal with the trapezoidal channel signal in time, and generating the rise time flag of the trapezoid, the flat top time flag of the trapezoid, the fall time flag of the trapezoid, and the base return time flag of the trapezoid in the trapezoidal channel signal through a counter. These flags are used for subsequent baseline calculation and stacking rejection logic.

[0054] This application determines the trigger signal by differentiating the triangular channel signal and utilizing the zero-crossing point of its bipolar structure. This makes the trigger recognition process independent of amplitude magnitude, relying instead on signal variation characteristics, thus achieving stable trigger times under different pulse amplitude conditions. Subsequently, all trigger times are mapped to different stage markers of the trapezoidal channel, making stacking judgment dependent on the relative temporal position of different pulses rather than the shape of a single pulse. This recognition method, based on relative temporal structure rather than amplitude differences, prevents weak pulses from being ignored or noise from being incorrectly identified as stacking events, thereby improving the accuracy of stacking detection and providing a stable event classification basis for subsequent baseline recovery algorithms.

[0055] Further, in some embodiments of this application, the stage markers include: a trapezoidal rise time marker, a trapezoidal flat-top time marker, and a trapezoidal fall time marker; determining the triggered event stack based on the occurrence times of all the trigger signals and all the stage markers includes: When the trapezoidal channel signal is at the trapezoidal rising moment mark, and the triangular channel signal has two trigger signals, it is determined that the trapezoidal channel signal is currently in a rising accumulation state. When the trapezoidal channel signal has experienced the trapezoidal rising moment mark and is at the trapezoidal flat top moment mark, and the triangular channel signal has two trigger signals, it is determined that the trapezoidal channel signal is currently in a flat top stacking state. When the trapezoidal channel signal has successively experienced the trapezoidal rising time mark and the trapezoidal flat top time mark, and is at the trapezoidal falling time mark, and the triangular channel signal has two trigger signals, then it is determined that the trapezoidal channel signal is currently in a falling accumulation state.

[0056] Based on the trigger signals generated by the fast triangle channel signal and the trapezoidal forming stage markers in the slow trapezoidal channel signal, the processor can identify whether the trapezoid is in a certain state and what kind of accumulation state it is in. Two trigger signals arriving within the trapezoid's rising interval indicate that the trapezoid will enter a rising accumulation state; two trigger signals arriving after the rising interval and within the flat-top interval indicate that the trapezoid will enter a flat-top accumulation state; two trigger signals arriving within the falling interval after the rising interval plus the flat-top time indicate that the trapezoid will enter a falling accumulation state; if only one trigger signal arrives within the trapezoidal forming interval, the trapezoid will traverse the rising, flat-top, and falling states without producing any accumulation. Amplitude extraction of the X-ray event is performed only within the flat-top interval of the trapezoid. The average value of a segment of the trapezoid's flat-top is calculated, and after subtracting the baseline average value before the rising interval, the absolute height of the trapezoid is obtained. These effective amplitudes are recorded to form the energy spectrum.

[0057] Preferably, in some embodiments of this application, Figure 5 The stacking rejector in the digital pulse processing link shown identifies stacking based on a stage flag and the current stage state of the trapezoidal channel signal. For example... Figure 7The stacking rejector state transition diagram shown initially indicates that the state machine mapping the trapezoidal channel signal is in an idle state. When the rise flag arrives, it transitions to the rising state. If the rise flag arrives in the rising state, it transitions to the rising stacking state; otherwise, it transitions to the flat-top state when the flat flag arrives. Since stacking on all rising edges causes trapezoidal flat-top distortion, it waits for the fall flag in the rising stacking state before transitioning to the flat-top state. If the rise flag arrives in the flat-top state, it transitions to the flat-top stacking state; otherwise, it transitions to the falling state when the fall flag arrives. Flat-top stacking may cause partial trapezoidal flat-top distortion. Peak values ​​calculated before flat-top stacking are valid, while peak values ​​calculated after flat-top stacking are invalid. Therefore, it waits for the fall flag in the flat-top stacking state before transitioning to the falling state. If the rise flag arrives in the falling state, it transitions to the falling stacking state; otherwise, it transitions to the idle state when the base flag arrives. Falling-edge stacking does not affect the distinction between the two trapezoidal flat tops. Therefore, if a rise indicator arrives during the falling-edge stacking state, the system switches to the rising-edge stacking state; if a flat indicator arrives, it switches to the flat-top state. The peak detector only operates in the flat-top state. When the flat indicator arrives, the signal rise time counter is activated. After eliminating the effects of ballistic deficit, the mean of the flat top is calculated. This mean is subtracted from the baseline mean to obtain the absolute amplitude of the X-ray event, which is then written into the energy spectrum.

[0058] This application classifies and identifies accumulation events by combining the rising, flat-top, and falling phase markers of the trapezoidal channel signal and determining the accumulation stage based on the number of trigger signals in the triangular channel. When accumulation occurs in the rising phase, it directly affects the peak formation process, so all rising accumulation pulses are rejected. When accumulation occurs in the flat-top phase, it changes the flat-top region; therefore, when flat-top accumulation occurs, pulses with completed amplitude extraction are retained, while pulses with incomplete amplitude extraction are rejected. When accumulation occurs in the falling phase, it does not affect the flat-top region of the next pulse, and all pulse signals are retained. Since accumulation recognition no longer relies on changes in pulse amplitude or slope but is based on a combination of phase markers and the number of trigger signals, it can maintain recognition stability in high count rate scenarios, which helps to reduce the impact of accumulation on energy output results.

[0059] Furthermore, in some embodiments of this application, before processing the first signal segment in the trapezoidal channel signal that has not triggered the accumulation of the event by the moving average filtering, the method further includes: filtering out noise signals in the trapezoidal channel signal by a fourth preset threshold; wherein the fourth preset threshold is the amplitude of the smallest unidentifiable signal in the triangular channel signal.

[0060] Because fast triangle filtering has a short rise time, it can generate timing triggers relatively quickly, but its suppression effect on high-frequency noise is weak. The fast threshold cannot be set lower than the noise level, otherwise false triggers will occur. When the detector's leakage current or electronics generate small abrupt signals, they will also be filtered into a small triangle and a small trapezoid. If the amplitude of the small triangle is lower than the fast threshold, no trigger will occur, and the small trapezoid will be identified as the baseline of the trapezoid, resulting in a larger baseline amplitude. This probability is greater at high count rates. Therefore, a slow threshold discrimination method is needed to filter out noise signals in the trapezoidal channel signal.

[0061] Preferably, in some embodiments of this application, the step of filtering out noise signals in the trapezoidal channel signal using a fourth preset threshold includes: applying a slow threshold discrimination method to lower the threshold lower limit of the fast triangle channel, identifying some abrupt small signals (small amplitude signals that the fast triangle channel cannot identify) generated by detector leakage current and electronic noise. These data will also not be sent to the moving average filter for baseline calculation. Therefore, it can be ensured that... Figure 5 The data used by the moving average filter during operation are the true baselines of the trapezoidal channel signals. For trapezoidal signals that have not accumulated, a baseline average is updated before amplitude extraction, and these averages are recorded to form a baseline histogram. like Figure 6 The diagram illustrates the slow threshold discrimination method. The blue solid line represents the amplified step signal. An unexpected small abrupt change occurs at approximately 19.5µs, which cannot be identified by the fast threshold (shown by the red dashed line). The small trapezoid (shown by the purple solid line) is then considered the baseline, distorting the baseline mean of subsequent normal trapezoids. A slow threshold (shown by the purple dashed line) is set. When the trapezoid exceeds this threshold but falls below the fast threshold, the search for the maximum value of the small trapezoid's flat top is initiated, serving as another trigger for baseline identification. In the signal processing chain, the trapezoid is digitally delayed, making it easy to locate the rise time of the delayed small trapezoid based on the flat time of the undelayed small trapezoid.

[0062] This application introduces a fourth threshold before the moving average and filters out minute amplitude signals that cannot be recognized by the triangular channel, ensuring that the segments entering the averaging operation consist only of true baseline segments. Since this threshold is set based on the minimum signal amplitude that the triangular channel can recognize, it can eliminate noise components without losing effective pulse information, thereby maintaining a low baseline estimation error even when the count rate increases, providing a stable reference basis for energy extraction.

[0063] To further illustrate the effectiveness of the SDD high count rate pulse signal processing method provided in the embodiments of this application, the following is based on... Figure 3The corresponding dual-mode ADC used is AD9251 and the bias follower DAC is D9767 as verification cases, and the performance of the method provided in the embodiments of this application is compared with that of the traditional CR differentiator-based scheme.

[0064] The digital pulse signal processing device proposed in this application significantly alleviates the baseline drift problem at high count rates by using a combined analog signal conditioning and digital filtering approach, achieving high-resolution stability at high count rates. In the verification and comparison, this application utilizes... 55 Using an Fe source, the energy resolution and baseline characteristics of two processor schemes for the Mn-Kα peak (5.89 keV) were compared at different input count rates. Figure 8 As shown, the red solid line is the baseline histogram of the CR differentiator scheme, which is larger and wider on the right, indicating baseline drift. Furthermore, the CR differentiator scheme also has a DC bias, therefore its baseline histogram is not symmetrical about 0. The blue solid line is the baseline histogram of the scheme in this application, which is a quasi-Gaussian shape symmetrical about 0 and has less widening, reflecting better baseline stability. Figure 9 As shown, at a low count rate of 10 kcps, both the CR differentiator scheme and the scheme of this application exhibit good resolution, at 124.71 eV and 126.64 eV, respectively. However, when the input count rate increases to 500 kcps, the resolution of the CR differentiator scheme deteriorates significantly to 133.29 eV, while the scheme of this application remains stable, with the resolution changing only slightly to 127.01 eV, demonstrating excellent count rate adaptability.

[0065] In summary, the SDD high count rate pulse signal processing method provided in this application has the following advantages compared to the prior art: First, the first channel retains the original step voltage signal, and the second channel obtains the effective voltage signal by subtracting the bias voltage signal from the original step voltage signal. Since the bias voltage signal is output by the digital-to-analog converter and can be updated in real time, the amplitude of the effective voltage signal after the bias update can be kept in the near-zero range, which is convenient for the next stage of amplification. The traditional differential capacitor is eliminated from the front-end structure, thus eliminating the signal distortion caused by the non-ideal characteristics of the capacitor at the source. Second, when the effective voltage signal exceeds the threshold, the bias following algorithm is triggered, which uses the first channel signal to estimate the baseline offset in real time and updates the DAC output synchronously, so that the baseline compensation behavior is synchronized with the event occurrence. Since the compensation action is based on real-time sampled data rather than fixed-period calculation, its compensation frequency automatically increases with the count rate, realizing that the higher the count rate, the faster the corresponding baseline update, thereby ensuring that all effective X-ray events are kept within the dynamic range of the second channel. When the second channel signal, after bias compensation, enters the digital signal processing algorithm, the subsequent trapezoidal filtering is no longer affected by nonlinear distortion, thus significantly improving the energy spectrum stability and resolution.

[0066] like Figure 10 As shown, based on the above-described method embodiments, this application provides an SDD high count rate pulse signal processing system, applied to a digital pulse signal processing device. The digital pulse signal processing device includes: a transistor reset type preamplifier, a dual-channel analog-to-digital converter, and a digital-to-analog converter; the dual-channel analog-to-digital converter includes: a first channel and a second channel; the SDD high count rate pulse signal processing system includes: a transistor reset type preamplifier module 201, a first channel module 202, a second channel module 203, a bias module 204, and a digital pulse processing module 205.

[0067] Further, in some embodiments of this application, the transistor-reset preamplifier module 201 is used to read the pulse charge output by the SDD in real time through the transistor-reset preamplifier, and output the original step voltage signal according to the pulse charge; the first channel module 202 is used to acquire the original step voltage signal in real time through the first channel, and convert the original step voltage signal into a first digital signal; the second channel module 203 is used to acquire the effective voltage signal in real time through the second channel, and convert the effective voltage signal into a second digital signal; wherein, the effective voltage signal is calculated by subtracting the bias voltage signal output by the current digital-to-analog converter from the original step voltage signal; the bias module 204 is used to process the first digital signal through a bias following algorithm when the second digital signal is greater than or equal to a first preset threshold, and update the bias voltage signal output by the digital-to-analog converter according to the processing result; the digital pulse processing module 205 is used to process the second digital signal output by the second channel in real time through a preset digital signal processing algorithm.

[0068] Further, in some embodiments of this application, the digital pulse processing module 205 includes: a signal shaping unit, a stacking identification unit, a baseline mean calculation unit, and an energy spectrum forming unit; the digital pulse processing module 205 is used to process the second digital signal output from the second channel in real time using a preset digital signal processing algorithm, including: the signal shaping unit is used to shape the second digital signal into a triangular channel signal and a trapezoidal channel signal respectively according to the peak time of the second digital signal; wherein the peak time of the triangular channel signal is less than the peak time of the trapezoidal channel signal; the stacking identification unit is used to determine the event stacking triggered in the trapezoidal channel signal according to the triangular channel signal; the baseline mean calculation unit is used to process the first signal segment in the trapezoidal channel signal that has not triggered the event stacking by a moving average filter to obtain the baseline mean; the energy spectrum forming unit is used to calculate the absolute height of the trapezoid in the trapezoidal channel signal according to the baseline mean to form energy spectrum data.

[0069] Furthermore, in some embodiments of this application, the stacking identification unit is used to determine the triggered event stacking in the trapezoidal channel signal based on the triangular channel signal, including: determining the trigger signal in the triangular channel signal by finding the zero-crossing point of the bipolar triangle after the triangular channel signal is differentiated; determining each stage flag in the trapezoidal channel signal based on the trigger signal in the triangular channel signal; and determining the triggered event stacking based on the occurrence time points of all the trigger signals and all the stage flags.

[0070] Further, in some embodiments of this application, the stage markers include: a trapezoidal rising time marker, a trapezoidal flat-top time marker, and a trapezoidal falling time marker; determining the stacking of triggered events based on the occurrence times of all the trigger signals and all the stage markers includes: when the trapezoidal channel signal is at the trapezoidal rising time marker, and the triangular channel signal has two trigger signals, then the trapezoidal channel signal is determined to be in a rising stacking state; when the trapezoidal channel signal has passed through the trapezoidal rising time marker and is at the trapezoidal flat-top time marker, and the triangular channel signal has two trigger signals, then the trapezoidal channel signal is determined to be in a flat-top stacking state; when the trapezoidal channel signal has successively passed through the trapezoidal rising time marker and the trapezoidal flat-top time marker, and is at the trapezoidal falling time marker, and the triangular channel signal has two trigger signals, then the trapezoidal channel signal is determined to be in a falling stacking state.

[0071] Further, in some embodiments of this application, the bias module 204 includes: a judgment unit, a first execution unit, and a second execution unit; the bias module 204 is used to process the first digital signal through a bias following algorithm when the second digital signal is greater than or equal to a first preset threshold, and update the bias voltage signal output by the digital-to-analog converter according to the processing result, including: the judgment unit is used to determine whether the second digital signal is greater than or equal to a second preset threshold; wherein, the second preset threshold is greater than the first preset threshold; the second preset threshold is the minimum second digital signal output by the second channel when multiple consecutive events accumulate; the first execution unit is used to start a timer if the second digital signal is less than the second preset threshold, and output a first bias voltage signal through the digital-to-analog converter when the count of the timer is equal to a preset time; wherein, the first bias voltage signal is a voltage signal lower than a third preset threshold of the current original step voltage signal; the second execution unit is used to output the first bias voltage signal through the digital-to-analog converter if the second digital signal is greater than or equal to the second preset threshold and the transition of the first digital signal ends.

[0072] Furthermore, in some embodiments of this application, before processing the first signal segment in the trapezoidal channel signal that has not triggered the accumulation of the event by the moving average filtering, the method further includes: filtering out noise signals in the trapezoidal channel signal by a fourth preset threshold; wherein the fourth preset threshold is the amplitude of the smallest unidentifiable signal in the triangular channel signal.

[0073] Furthermore, in some embodiments of this application, the bias module 204 is also used to detect the reset state of the transistor reset type preamplifier in real time. When the transistor reset type preamplifier is reset, it outputs a second bias voltage signal through the digital-to-analog converter. The second bias voltage signal is a voltage signal that is lower than the fifth preset threshold of the historical minimum original step voltage signal.

[0074] It is understood that the above system embodiments correspond to the method embodiments of this application, and can implement the SDD high count rate pulse signal processing method provided by any of the above method embodiments of this application.

[0075] In summary, the SDD high count rate pulse signal processing system provided in this application has the following advantages compared to the prior art: First, the first channel retains the original step voltage signal, and the second channel obtains the effective voltage signal by subtracting the bias voltage signal from the original step voltage signal. Since the bias voltage signal is output by the digital-to-analog converter and can be updated in real time, the amplitude of the effective voltage signal after the bias update can be kept in the near-zero range, which is convenient for the next stage of amplification. The traditional differential capacitor is eliminated from the front-end structure, thus eliminating the signal distortion caused by the non-ideal characteristics of the capacitor. Second, when the effective voltage signal exceeds the threshold, the bias following algorithm is triggered, which uses the first channel signal to estimate the baseline offset in real time and updates the DAC output synchronously, so that the baseline compensation behavior is synchronized with the event. Since the compensation action is based on real-time sampled data rather than fixed-period calculation, its compensation frequency automatically increases with the count rate, realizing that the higher the count rate, the faster the corresponding baseline update, thereby ensuring that all effective X-ray events are kept within the dynamic range of the second channel. When the second channel signal, after bias compensation, enters the digital signal processing algorithm, the subsequent trapezoidal filtering is no longer affected by nonlinear distortion, thus significantly improving the energy spectrum stability and resolution.

[0076] It should be noted that the system embodiments described above are merely illustrative, and some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the system embodiments provided in this application, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0077] Based on the above embodiments of the SDD high count rate pulse signal processing method, another embodiment of this application provides a terminal device, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the SDD high count rate pulse signal processing method of any embodiment of this application.

[0078] For example, in this embodiment, the computer program can be divided into one or more modules, which are stored in the memory and executed by the processor to complete this application. The one or more module units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the terminal device.

[0079] The terminal device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0080] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device via various interfaces and lines.

[0081] Based on the above-described method embodiments, another embodiment of this application provides a computer-readable storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to execute the SDD high count rate pulse signal processing method described in any of the above-described method embodiments of this application.

[0082] The modules / units integrated in the device / terminal equipment, if implemented as software functional units and sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

Claims

1. A method for processing high count rate pulse signals in SDD (Single Count Discharge), characterized in that, An application is made in a digital pulse signal processing device, the digital pulse signal processing device comprising: a transistor-reset preamplifier, a dual-channel analog-to-digital converter, and a digital-to-analog converter; the dual-channel analog-to-digital converter comprising: a first channel and a second channel; the SDD high count rate pulse signal processing method comprising: The transistor-reset preamplifier reads the pulse charge output by SDD in real time and outputs the original step voltage signal based on the pulse charge. The original step voltage signal is acquired in real time through the first channel, and the original step voltage signal is converted and output as a first digital signal. The effective voltage signal is acquired in real time through the second channel and converted into a second digital signal; wherein, the effective voltage signal is calculated by subtracting the bias voltage signal output by the current digital-to-analog converter from the original step voltage signal; When the second digital signal is greater than or equal to the first preset threshold, the first digital signal is processed by the bias follower algorithm, and the bias voltage signal output by the digital-to-analog converter is updated according to the processing result. The second digital signal output from the second channel is processed in real time using a preset digital signal processing algorithm.

2. The SDD high count rate pulse signal processing method as described in claim 1, characterized in that, The real-time processing of the second digital signal output from the second channel using a preset digital signal processing algorithm includes: Based on the peak arrival time of the second digital signal, the second digital signal is shaped into a triangular channel signal and a trapezoidal channel signal, respectively; wherein the peak arrival time of the triangular channel signal is shorter than the peak arrival time of the trapezoidal channel signal. The event stack triggered in the trapezoidal channel signal is determined based on the triangular channel signal; The baseline mean is obtained by processing the first signal segment in the trapezoidal channel signal that has not triggered the events by a moving average filter. The absolute height of the trapezoid in the trapezoidal channel signal is calculated based on the baseline mean to form energy spectrum data.

3. The SDD high count rate pulse signal processing method as described in claim 2, characterized in that, The step of determining the stack of triggered events in the trapezoidal channel signal based on the triangular channel signal includes: The trigger signal in the triangular channel signal is determined by finding the zero-crossing point of the bipolar triangle after differentiation of the triangular channel signal. The stage markers in the trapezoidal channel signal are determined based on the trigger signals in the triangular channel signal. The stack of triggered events is determined based on the occurrence times of all the aforementioned trigger signals and all the aforementioned stage markers.

4. The SDD high count rate pulse signal processing method as described in claim 3, characterized in that, The stage markers include: a trapezoidal rise time marker, a trapezoidal flat top time marker, and a trapezoidal fall time marker; determining the stack of triggered events based on the occurrence times of all the trigger signals and all the stage markers includes: When the trapezoidal channel signal is at the trapezoidal rising moment mark, and the triangular channel signal has two trigger signals, it is determined that the trapezoidal channel signal is currently in a rising accumulation state. When the trapezoidal channel signal has experienced the trapezoidal rising moment mark and is at the trapezoidal flat top moment mark, and the triangular channel signal has two trigger signals, it is determined that the trapezoidal channel signal is currently in a flat top stacking state. When the trapezoidal channel signal has successively experienced the trapezoidal rising time mark and the trapezoidal flat top time mark, and is at the trapezoidal falling time mark, and the triangular channel signal has two trigger signals, then it is determined that the trapezoidal channel signal is currently in a falling accumulation state.

5. The SDD high count rate pulse signal processing method as described in claim 2, characterized in that, When the second digital signal is greater than or equal to a first preset threshold, the first digital signal is processed by a bias follower algorithm, and the bias voltage signal output by the digital-to-analog converter is updated according to the processing result, including: Determine whether the second digital signal is greater than or equal to a second preset threshold; wherein the second preset threshold is greater than the first preset threshold; the second preset threshold is the minimum second digital signal output by the second channel when multiple consecutive events accumulate; If the second digital signal is less than the second preset threshold, a timer is started, and when the count of the timer equals a preset time, a first bias voltage signal is output through the digital-to-analog converter; wherein, the first bias voltage signal is a voltage signal that is lower than the third preset threshold of the current original step voltage signal; If the second digital signal is greater than or equal to the second preset threshold, and the transition of the first digital signal ends, then the first bias voltage signal is output through the digital-to-analog converter.

6. The SDD high count rate pulse signal processing method as described in claim 2, characterized in that, Before processing the first signal segment in the trapezoidal channel signal that did not trigger the accumulation of the event by the moving average filtering, the method further includes: filtering out noise signals in the trapezoidal channel signal by a fourth preset threshold; wherein the fourth preset threshold is the amplitude of the smallest signal that cannot be identified in the triangular channel signal.

7. The SDD high count rate pulse signal processing method as described in claim 1, characterized in that, Also includes: The reset state of the transistor-reset preamplifier is detected in real time. When the transistor-reset preamplifier is reset, a second bias voltage signal is output through the digital-to-analog converter. The second bias voltage signal is a voltage signal that is lower than the fifth preset threshold of the historical minimum original step voltage signal.

8. A high-count-rate pulse signal processing system for SDD, characterized in that, The system is applied to a digital pulse signal processing device, which includes: a transistor-reset preamplifier, a dual-channel analog-to-digital converter, and a digital-to-analog converter; the dual-channel analog-to-digital converter includes: a first channel and a second channel; the SDD high-count-rate pulse signal processing system includes: a transistor-reset preamplifier module, a first channel module, a second channel module, a bias module, and a digital pulse processing module; The transistor-reset preamplifier module is used to read the pulse charge output by SDD in real time through the transistor-reset preamplifier, and output the original step voltage signal according to the pulse charge; The first channel module is used to acquire the original step voltage signal in real time through the first channel and convert the original step voltage signal into a first digital signal. The second channel module is used to acquire an effective voltage signal in real time through the second channel and convert the effective voltage signal into a second digital signal; wherein, the effective voltage signal is calculated by subtracting the bias voltage signal output by the current digital-to-analog converter from the original step voltage signal; The bias module is used to process the first digital signal through a bias following algorithm when the second digital signal is greater than or equal to a first preset threshold, and update the bias voltage signal output by the digital-to-analog converter according to the processing result. The digital pulse processing module is used to process the second digital signal output from the second channel in real time using a preset digital signal processing algorithm.

9. A terminal device, characterized in that, The method includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement an SDD high count rate pulse signal processing method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein, when the computer program is executed, it controls the device on which the computer-readable storage medium is located to perform an SDD high count rate pulse signal processing method as described in any one of claims 1 to 7.

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