BC battery and manufacturing method thereof

Abstract

The invention provides a BC battery and a manufacturing method thereof, the BC battery comprises a substrate, a PN layer, a plurality of P main grids, a plurality of N main grids and a fine grid, the substrate comprises a front surface and a back surface, the PN layer is arranged on the back surface and comprises a plurality of P regions and a plurality of N regions, the P regions and the N regions are alternately arranged along a first direction, the P main grids and the P regions are arranged in a one-to-one correspondence manner, and the fine grid is arranged on the back surface of the substrate. The N main grids and the N areas are arranged in a one-to-one correspondence manner, the fine grids are arranged in the P areas or the N areas and are connected with the P main grids or the N main grids, and the sectional area of each fine grid is in negative correlation with the current-carrying distance of the fine grid. According to the BC battery provided by the embodiment of the invention, the sectional area of each fine grid is in negative correlation with the current-carrying distance of the fine grid, the fine grids are optimized according to the positions of the fine grids, and due to the conductive design distributed according to needs, the conduction efficiency of the BC battery is improved. And the collection speed and efficiency of current carriers are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of battery manufacturing technology, and more particularly to a BC battery and its manufacturing method. Background Technology

[0002] In related technologies, while method C batteries integrate the PN junction and electrodes entirely on the back side, avoiding front-side metal obstruction and improving light absorption, the problem of unreasonable back electrode structure design has long existed. In particular, the cross-sectional area of ​​the fine grid is usually designed uniformly, without considering the differences in current transmission distance at different locations, resulting in low overall current collection efficiency of the battery, affecting output power and conversion efficiency. Summary of the Invention

[0003] This invention provides a BC battery to solve the defect of low current collection efficiency caused by unreasonable fine grid design in the existing C battery manufacturing method, and to improve the current collection efficiency of the C battery manufacturing method.

[0004] This invention provides a BC battery, comprising: The substrate includes the front and back sides; A PN layer is disposed on the back side and includes multiple P regions and multiple N regions, which are arranged alternately along a first direction. Multiple P-main gates are configured one-to-one with the multiple P-regions; Multiple N main gates are configured in a one-to-one correspondence with the multiple N regions; A fine gate is disposed in the P region or the N region and connected to the P main gate or the N main gate; The cross-sectional area of ​​the fine grid is negatively correlated with its current-carrying distance.

[0005] In some embodiments, each P region includes a plurality of P units extending along a second direction perpendicular to the first direction, and each N region includes a plurality of N units extending along the second direction. The P units and the N units are rhomboid and staggered in the first direction.

[0006] In some embodiments, the BC battery includes: A first passivation layer is disposed on the back side and located outside the PN layer, and the region on the first passivation layer corresponding to the N region is a tunneling region; A deposition layer covers the outside of the first passivation layer; The second passivation layer is located outside the deposition layer.

[0007] In some embodiments, the rhombus includes a second diagonal extending along the second direction, the P main gate and the N main gate are both arranged on the second diagonal, and the fine gate extends along the first direction.

[0008] In some embodiments, in the P unit or the N unit, a plurality of fine gates are arranged sequentially along the second direction.

[0009] In some embodiments, the rhombus includes a first diagonal extending along the first direction, and the fine grid includes: The first fine grid is arranged on the first diagonal line; Multiple second fine grids are arranged on both sides of the first fine grid; In the direction away from the first fine grid, the cross-sectional area of ​​the second fine grid gradually increases.

[0010] An embodiment of the present invention discloses a manufacturing method, comprising: Pretreatment of the matrix; A P-region and an N-region are defined on the back side of the substrate, and a PN junction is prepared. The back surface is passivated to form a first passivation layer; The N region is subjected to tunneling treatment; Polycrystalline silicon is deposited on the surface of the first passivation layer; The back surface is passivated to form a second passivation layer; Fabricating electrodes.

[0011] In some embodiments, staggered first and second oblique grooves are engraved on the back side to form a plurality of rhomboid regions, and the plurality of rhomboid regions whose diagonals are on the same straight line are prepared to have the same polarity.

[0012] In some embodiments, the electrode fabrication includes: etching a main trench to fabricate a main gate, etching a fine trench to fabricate a fine gate, wherein the cross-sectional area of ​​the fine trench is negatively correlated with its current-carrying distance.

[0013] In some embodiments, the pretreatment of the matrix includes: The substrate is cleaned and texturized; A positive passivation layer is deposited on the front side of the substrate; The back side of the substrate is made flat.

[0014] In the BC battery of this invention, the cross-sectional area of ​​the fine grid is negatively correlated with its current carrying distance. The fine grid is optimized according to its position. This on-demand conductivity design greatly improves the collection speed and efficiency of charge carriers. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is one of the structural schematic diagrams of the BC battery provided by the present invention.

[0017] Figure 2 This is the second schematic diagram of the BC battery provided by the present invention.

[0018] Figure 3 This is the third schematic diagram of the BC battery provided by the present invention.

[0019] Figure 4 This is a schematic diagram of the manufacturing method of the BC battery provided by the present invention.

[0020] Figure label: 100, BC battery; 1. Matrix; 11. Front; 12. Back; 2. PN layer; 21. P region; 22. N region; 23. P main gate; 24. N main gate; 25. Fine gate; 251. First fine gate; 252. Second fine gate; 211. P cell; 221. N cell; 3. First passivation layer; 31. Tunneling zone; 4. Sedimentary layer; 5. Second passivation layer; 61. First inclined groove; 62. Second inclined groove. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0022] like Figures 1 to 3 As shown, the BC battery 100 of this embodiment includes a substrate 1, a PN layer 2, a plurality of P main gates 23, a plurality of N main gates 24 and fine gates 25.

[0023] The substrate 1 includes a front side 11 and a back side 12.

[0024] The PN layer 2 is located on the back side 12 and includes multiple P regions 21 and multiple N regions 22, which are arranged alternately along a first direction.

[0025] Multiple P main gates 23 are configured in a one-to-one correspondence with multiple P areas 21.

[0026] Multiple N main gates 24 are configured in a one-to-one correspondence with multiple N regions 22.

[0027] The fine grid 25 is located in region P 21 or region N 22 and is connected to the P main grid 23 or N main grid 24.

[0028] Among them, the cross-sectional area of ​​the fine grid 25 is negatively correlated with its current-carrying distance.

[0029] For ease of description, the technical solution of this application will be described below with the left and right directions as the first direction, wherein the left and right directions are as follows: Figure 2 As shown.

[0030] The substrate 1 serves as the basic material for the BC cell 100. The front side 11 is used to absorb sunlight, and the back side 12 integrates the PN junction and electrode system.

[0031] The entire PN layer 2 is located on the back side 12, forming a back contact structure (manufacturing method C), which avoids the metal electrode on the front side 11 blocking light and improves light absorption efficiency.

[0032] P region 21 and N region 22 are arranged alternately along the left and right directions on the back side 12 to achieve a spatial layout of charge separation regions.

[0033] Each P-region 21 and N-region 22 is equipped with a corresponding P-main grid 23 and N-main grid 24, which are used to collect current and extract electrical energy.

[0034] The fine grid 25, as a secondary conductive network, extends from each P region 21 or N region 22 and connects to the corresponding main grid, undertaking the task of local current carrying.

[0035] The cross-sectional area of ​​the fine gate 25 is not uniform, but optimized according to its "current-carrying distance" from the main gate. For example, the cross-sectional area of ​​the fine gate 25 is larger where the current-carrying distance is short, and smaller where the current-carrying distance is long, thus ensuring that more current can be collected at the location with the shorter current-carrying distance.

[0036] In related technologies, although the C-type battery integrates the PN junction and electrodes entirely on the back side 12, avoiding metal obstruction on the front side 11 and improving light absorption, the problem of unreasonable electrode structure design on the back side 12 has long existed. In particular, the cross-sectional area of ​​the fine grid 25 is usually designed uniformly, without considering the difference in current transmission distance at different locations, resulting in low overall current collection efficiency of the battery, affecting output power and conversion efficiency.

[0037] In the BC battery 100 of this invention, the cross-sectional area of ​​the fine grid 25 is negatively correlated with its current carrying distance. The fine grid 25 is optimized according to its position. This on-demand conductive design greatly improves the collection speed and efficiency of charge carriers.

[0038] In some embodiments, each P region 21 includes a plurality of P units 211 extending along a second direction perpendicular to the first direction, and each N region 22 includes a plurality of N units 221 extending along the second direction. The P units 211 and N units 221 are both rhomboid and are staggered in the first direction.

[0039] For ease of description, the technical solution of this application will be described below with the vertical direction as the second direction, where the vertical direction is as follows: Figure 1 As shown.

[0040] Regions P21 and N22 are divided into multiple independent P units 211 and N units 221. These units are rhomboid in shape and are arranged sequentially in the vertical direction. Moreover, the P units 211 and N units 221 are staggered in the horizontal direction, that is, they are not directly aligned, forming an alternating pattern.

[0041] Insulation is applied between P unit 211 and N unit 221.

[0042] In some embodiments, the BC battery 100 includes a first passivation layer 3, a deposition layer 4, and a second passivation layer 5.

[0043] The first passivation layer 3 is located on the back side 12 and outside the PN layer 2. The area on the first passivation layer 3 corresponding to the N region 22 is the tunneling region 31.

[0044] The deposition layer 4 covers the outside of the first passivation layer 3.

[0045] The second passivation layer 5 is located outside the deposition layer 4.

[0046] After the PN layer 2 is formed, a first passivation layer 3 is deposited on the entire back side 12, and then the first passivation layer 3 is polished to expose the P region 21 and the N region 22.

[0047] A tunneling process is performed at the location corresponding to N area 22 to form "tunneling area 31".

[0048] Subsequently, a layer of polycrystalline silicon or other conductive material is deposited on the outer side to form a deposition layer 4, so that the deposition layer 4 is electrically connected to the N region 22 below through the tunneling region 31.

[0049] Finally, a second passivation layer 5 is applied to protect the deposited layer 4 and provide insulation.

[0050] The BC battery 100 of this embodiment of the invention, by providing a tunneling region 31 and a deposition layer 4, can improve the electron transport capability, thereby enhancing the conductivity of the N region 22.

[0051] In some embodiments, the rhombus includes a second diagonal extending along a second direction, with both the P main gate 23 and the N main gate 24 arranged along the second diagonal, and the fine gate 25 extending along a first direction.

[0052] Each rhombus cell has two diagonals, with the one extending vertically referred to as the second diagonal. In this embodiment, the P main gate 23 and N main gate 24 are respectively located on the second diagonal of their respective rhombus cells.

[0053] The gate lines of multiple P cells 211 in the same P region 21 are connected to form a P main gate 23, and the gate lines of multiple N cells 221 in the same N region 22 are connected to form an N main gate 24.

[0054] The fine grid 25 extends in the left-right direction, perpendicular to the P main grid 23 or N main grid 24, and the fine grid 25 is symmetrically arranged on both sides of the P main grid 23 or N main grid 24.

[0055] In the BC battery 100 of this invention, the main grid and the fine grid 25 are arranged vertically, so that the current converges from the edge of the cell to the central main grid in the shortest and symmetrical way, which greatly reduces the distance and time of lateral migration of charge carriers in the semiconductor and reduces resistance loss and recombination loss.

[0056] In some embodiments, in P unit 211 or N unit 221, a plurality of fine gates 25 are arranged sequentially along a second direction.

[0057] Within each P-cell 211 or N-cell 221, multiple fine gates 25 are arranged sequentially along the vertical direction. Within a rhombus, multiple parallel fine gates 25 extend from the interior, collectively undertaking the task of carrier collection in that region.

[0058] These fine grids 25 have one end close to the main grid and the other end extending away from the main grid to the edge of the rhombus, thus forming a complete conductive grid.

[0059] The BC battery 100 of this invention improves the carrier collection efficiency by increasing the number of fine grids 25 per unit area.

[0060] In some embodiments, the rhombus includes a first diagonal extending along a first direction, and the fine gate 25 includes a first fine gate 251 and a plurality of second fine gates 252.

[0061] The first fine grid 251 is arranged on the first diagonal.

[0062] Multiple second fine grids 252 are arranged on both sides of the first fine grid 251.

[0063] In particular, the cross-sectional area of ​​the second fine grid 252 gradually increases in the direction away from the first fine grid 251.

[0064] The rhombus has a first diagonal extending in the left-right direction. The "first fine grid 251" is located on the first diagonal, and multiple "second fine grids 252" are arranged symmetrically or asymmetrically on its upper and lower sides.

[0065] For example, within the rhomboid region, the cross-sectional area of ​​the second fine grid 252 above the first diagonal gradually increases from bottom to top. The cross-sectional area of ​​the second fine grid 252 below the first diagonal gradually increases from top to bottom.

[0066] like Figure 4 As shown, the manufacturing method of this invention includes: Pretreatment is performed on substrate 1.

[0067] P-region 21 and N-region 22 are divided on the back side 12 of substrate 1 and a PN junction is prepared.

[0068] The back side 12 is passivated to form a first passivation layer 3.

[0069] Tunneling treatment was carried out on area N22.

[0070] Polycrystalline silicon is deposited on the surface of the first passivation layer 3.

[0071] The back side 12 is passivated to form a second passivation layer 5.

[0072] Fabricating electrodes.

[0073] First, the substrate 1 is pretreated. Then, P-region 21 and N-region 22 are fabricated on the back side 12 by means of masking, etching or ion implantation, and a PN junction is formed.

[0074] Next, a first passivation process is performed to generate a first passivation layer 3 to isolate the P region 21 and the N region 22. Then, the first passivation layer 3 is polished to expose the P region 21 and the N region 22.

[0075] Subsequently, a special tunneling treatment was performed on N region 22—that is, a hole was opened in the corresponding area of ​​N region 22, and then polysilicon was deposited in the first passivation layer 3 to construct a tunneling contact structure.

[0076] Afterwards, a second passivation layer 5 is formed by passivation again, completing the double-layer protection; finally, the P main gate 23, N main gate 24 and fine fine gate 25 network are fabricated by photolithography and metallization processes.

[0077] In some embodiments, first oblique grooves 61 and second oblique grooves 62 are engraved on the back side 12 in an alternating manner to form a plurality of rhomboid regions, and the plurality of rhomboid regions whose diagonals are located on the same straight line are prepared to have the same polarity.

[0078] By etching two sets of oppositely oriented grooves on the back side 12—the first groove 61 sloping from the upper right to the lower left, and the second groove 62 sloping from the upper left to the lower right—the two grooves intersect and naturally form enclosed rhomboid regions. These rhomboid regions constitute the basic units of the subsequent P-units 211 and N-units 221. Those rhomboid regions whose diagonals are on the same straight line are made to have the same conductivity type (i.e., both are P-regions 21 or both are N-regions 22).

[0079] The BC battery 100 of this embodiment of the invention has a first inclined groove 61 and a second inclined groove 62 arranged to form a P region 21 or an N region 22. The process is simple and the pattern is regular.

[0080] In some embodiments, fabricating the electrode includes: etching a main trench to fabricate a main gate, and etching a fine trench to fabricate a fine gate 25, wherein the cross-sectional area of ​​the fine trench is negatively correlated with its current-carrying distance.

[0081] Main trenches and fine trenches are formed on the passivation layer using an etching process, and then filled with metal to form the main gate and fine gate 25. The main trenches are used to define the positions of the P main gate 23 and N main gate 24, while the fine trenches are used to construct the fine gate 25 network.

[0082] The cross-sectional area of ​​the fine trench is not fixed, but dynamically adjusted according to its "current carrying distance" from the main grid. The greater the current carrying distance, the larger the trench cross-sectional area; the closer the current carrying distance, the narrower the trench.

[0083] In some embodiments, pretreatment of substrate 1 includes: The substrate 1 is cleaned and texturized.

[0084] A positive passivation layer is deposited on the front side 11 of the substrate 1.

[0085] Make the back side 12 of the substrate 1 flat.

[0086] Pre-treatment is a prerequisite for high-quality battery manufacturing. First, the silicon wafer is thoroughly cleaned to remove organic matter, metal ions, and particulate contaminants. Then, a texturing process is performed to form a pyramid-shaped microstructure on the front side 11, enhancing light-harvesting capabilities and reducing reflection loss. Next, a passivation layer is deposited on the front side 11, which serves both as surface passivation and as an anti-reflection film and protective layer. Finally, the back side 12 is ground or polished to achieve a smooth and flat surface, providing a good foundation for the subsequent precise processing of the PN junction and electrode patterning on the back side 12.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A BC battery, characterized in that, include: The substrate (1) includes a front side (11) and a back side (12); A PN layer (2) is provided on the back side (12) and includes a plurality of P regions (21) and a plurality of N regions (22), which are arranged alternately along a first direction; Multiple P main gates (23) are configured one-to-one with multiple P regions (21); Multiple N main gates (24) are configured one-to-one with multiple N regions (22); A fine grid (25) is disposed in the P region (21) or the N region (22) and connected to the P main grid (23) or the N main grid (24); The cross-sectional area of ​​the fine grid (25) is negatively correlated with its current-carrying distance.

2. The BC battery according to claim 1, characterized in that, Each of the P regions (21) includes a plurality of P units (211) extending along a second direction perpendicular to the first direction, and each of the N regions (22) includes a plurality of N units (221) extending along the second direction. The P units (211) and the N units (221) are rhomboid and staggered in the first direction.

3. The BC battery according to claim 1, characterized in that, The BC battery includes: The first passivation layer (3) is disposed on the back side (12) and located outside the PN layer (2), and the area on the first passivation layer (3) corresponding to the N region (22) is the tunneling region (31). A deposition layer (4) covers the outside of the first passivation layer (3); The second passivation layer (5) is located outside the deposition layer (4).

4. The BC battery according to claim 2, characterized in that, The rhombus includes a second diagonal extending along the second direction, the P main gate (23) and the N main gate (24) are both arranged on the second diagonal, and the fine gate (25) extends along the first direction.

5. The BC battery according to claim 4, characterized in that, In the P unit (211) or the N unit (221), a plurality of fine grids (25) are arranged sequentially along the second direction.

6. The BC battery according to claim 5, characterized in that, The rhombus includes a first diagonal extending along the first direction, and the fine grid (25) includes: The first fine grid (251) is arranged on the first diagonal line; Multiple second fine grids (252) are arranged on both sides of the first fine grid (251); In the direction away from the first fine gate (251), the cross-sectional area of ​​the second fine gate (252) gradually increases.

7. A method for manufacturing a BC battery according to any one of claims 1-6, characterized in that, include: The matrix (1) is pretreated; A P-region (21) and an N-region (22) are divided on the back side (12) of the substrate (1) and a PN junction is prepared. The back surface (12) is passivated to form a first passivation layer (3); The N region (22) is subjected to tunneling treatment; Polycrystalline silicon is deposited on the surface of the first passivation layer (3); The back surface (12) is passivated to form a second passivation layer (5); Fabricating electrodes.

8. The manufacturing method according to claim 7, characterized in that, The back side (12) is engraved with staggered first oblique grooves (61) and second oblique grooves (62) to form multiple rhomboid regions, and the multiple rhomboid regions located on the same straight line on the diagonal are prepared to have the same polarity.

9. The manufacturing method according to claim 7, characterized in that, The electrode fabrication includes: etching a main trench to fabricate a main gate, and etching a fine trench to fabricate a fine gate (25), wherein the cross-sectional area of ​​the fine trench is negatively correlated with its current-carrying distance.

10. The manufacturing method according to claim 7, characterized in that, The pretreatment of the substrate (1) includes: The substrate (1) is cleaned and texturized; A positive passivation layer is deposited on the front side (11) of the substrate (1); The back side (12) of the substrate (1) is made flat.

Images