Method for etching semiconductor structure and for conditioning process reactor

Abstract

The invention relates to a method for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is processed. An engineered polysilicon surface layer is deposited on a susceptor supporting the semiconductor structure. The polysilicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polysilicon surface layer, or by controlling the thickness of the polysilicon surface layer.

Description

[0001] This application is a divisional application of the application filed on May 9, 2022, with application number 202280041717.3 and entitled "Method for Etching Semiconductor Structures and Method for Adjusting Processing Reactors".

[0002] Cross-reference of related applications

[0003] This application claims priority to U.S. Nonprovisional Patent Application No. 17 / 319,885, filed May 13, 2021, and U.S. Nonprovisional Patent Application No. 17 / 319,888, filed May 13, 2021. The full text of both applications is incorporated herein by reference. Technical Field

[0004] This disclosure relates to methods for etching semiconductor structures and methods for regulating reactors used to process individual semiconductor structures. Background Technology

[0005] In a single-wafer thermal processing chamber, the semiconductor structure is supported by a substrate. In some cases, it is desirable to etch the top surface of the structure. For example, silicon-on-insulator structures can be smoothed by etching to achieve target top silicon layer thickness and surface roughness. Such structures can experience edge boundary effects where chemical processes near the edges of the semiconductor structure are interrupted. These effects can be caused by interruptions in heat transfer, momentum transfer, mass transfer, or a combination thereof. Edge boundary effects can cause edge roll-off near the edges of the semiconductor structure. Especially in the fabrication of advanced (e.g., 10 nm technology and above) CMOS devices, there is an increasing demand for semiconductor structures with uniform thickness and flatness across the wafer.

[0006] Conventional methods for reducing localized edge boundary effects are limited. For example, varying the pressure in the processing chamber is limited by throughput and reactor configuration. The gap between the wafer edge and the substrate is limited by manufacturing tolerances and thermal expansion. Increasing the height of the recesses within the substrate where the semiconductor structure resides causes the affected area to extend towards the inner region of the semiconductor structure. Furthermore, varying the gap and recess depth cannot improve the orientational thickness uniformity determined by centering the semiconductor structure within the substrate.

[0007] A method is needed to mitigate edge loading effects during semiconductor structure etching in order to improve the thickness uniformity of etched semiconductor structures.

[0008] This section aims to introduce the reader to various aspects of the technology that may relate to the various aspects of this disclosure described and / or claimed below. This discussion is intended to help provide the reader with background information to facilitate a better understanding of the various aspects of this disclosure. Therefore, it should be understood that these statements should be read in this context and not as an endorsement of prior art. Summary of the Invention

[0009] One aspect of this disclosure relates to a method for etching a semiconductor structure in a processing reactor. The processing reactor includes a substrate supporting the semiconductor structure. A polysilicon surface layer is deposited on the substrate. The polysilicon surface layer is contacted with a first etchant to create a surface-modified polysilicon surface layer. A semiconductor structure is mounted onto the substrate on which the surface-modified polysilicon surface layer is disposed. The semiconductor structure is contacted with a second etchant to etch the semiconductor structure.

[0010] Another aspect of this disclosure relates to a method for etching a semiconductor structure in a processing reactor. The processing reactor includes a substrate supporting the semiconductor structure. A polysilicon surface layer is deposited on the substrate at a temperature below 1150°C. The semiconductor structure is loaded onto the substrate on which the polysilicon surface layer is disposed. The semiconductor structure is brought into contact with an etchant to etch the semiconductor structure.

[0011] Another aspect of this disclosure relates to a method for regulating a processing reactor for processing a single semiconductor structure. The reactor includes a substrate for supporting the semiconductor structure. When the semiconductor structure is not mounted on the substrate, a stripping etchant is introduced into the processing reactor to strip a polysilicon surface layer from the substrate. When the semiconductor structure is not mounted on the substrate, the polysilicon surface layer is deposited onto the substrate. When the semiconductor structure is not mounted on the substrate, a trenching etchant is introduced into the processing reactor. The trenching etchant contacts the polysilicon surface layer to create a surface-modified polysilicon surface layer.

[0012] Another aspect of this disclosure relates to a method for regulating a processing reactor for processing a single semiconductor structure. The reactor includes a substrate for supporting the semiconductor structure. When the semiconductor structure is not mounted on the substrate, a stripping etchant is introduced into the processing reactor to strip a polysilicon surface layer from the substrate. When the semiconductor structure is not mounted on the substrate, the polysilicon surface layer is deposited on the substrate at a temperature below 1150°C.

[0013] Various improvements are possible to the features mentioned in the foregoing aspects of this disclosure. Further features may also be incorporated into the foregoing aspects of this disclosure. These improvements and additional features may exist individually or in any combination. For example, the various features discussed below with respect to any illustrative embodiments of this disclosure may be incorporated individually or in any combination into any of the foregoing aspects of this disclosure. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view of the processing reactor used for etching semiconductor structures before the semiconductor structures are loaded into the reactor;

[0015] Figure 2 This is a perspective view of the processing reactor containing the semiconductor structure.

[0016] Figure 3 This is a cross-sectional view of the processing reactor containing the semiconductor structure.

[0017] Figure 4 This is a detailed cross-sectional view of the processing reactor showing the preheating ring and base, in which a polycrystalline silicon surface layer is deposited on the preheating ring and base;

[0018] Figure 5 It is a detailed cross-sectional view of the processing reactor showing the preheating ring and the base, in which a polycrystalline silicon surface layer is deposited on the preheating ring and the base and a semiconductor structure is placed on the base;

[0019] Figure 6 This is a cross-sectional view of the silicon structure in an insulator;

[0020] Figure 7 It is a graph showing the effect of particle size and grooving factor on the surface area of ​​polycrystalline silicon surface layers; and

[0021] Figure 8 This is a bar chart showing the edge thickness in the SOI structure processed according to Example 2.

[0022] In all drawings, the corresponding reference character indicates the corresponding part. Detailed Implementation

[0023] This disclosure relates to methods for regulating a reactor used to process a single semiconductor structure (e.g., etch or smooth a structure) and methods for etching a semiconductor structure in a processing reactor. The processing reactor includes a base on which an engineered polysilicon surface layer is applied.

[0024] Figures 1 to 2 The illustration shows an example processing reactor 100 for use according to embodiments of the present disclosure. The illustrated reactor 100 is a single-substrate (i.e., semiconductor structure) reactor in which a single substrate is loaded onto the reactor 100 during processing.

[0025] Reactor 100 includes a processing chamber 102 in which a single semiconductor is etched. Reactor 100 may be adapted for other semiconductor structure processing, such as CVD growth (i.e., epitaxial growth) of structural thin films. Reactor 100 includes a gas injection port 106 located at one end of the processing chamber 102 and a gas exhaust port 108 located at the opposite end of the processing chamber 102. A gas manifold 140 located between the gas injection port 106 and the processing chamber 102 is used to guide the intake gas 110 through the gas injection port 106 into the processing chamber 102 enclosed by the upper window 112 and the lower window 114.

[0026] During operation, the incoming processing gas 110 flows through the gas manifold 140 and enters the processing chamber 102 through the inlet 103. The gas 110 flows through the processing chamber 102 and is discharged through the gas outlet 108.

[0027] Reactor 100 is contained within processing chamber 102 for supporting semiconductor structure 104. Figure 3 The reactor 100 comprises a base 120. The base 120 is connected to a shaft 122, which is connected to a motor (not shown) for a rotating mechanism (not shown) for rotating the shaft 122, the base 120, and the semiconductor structure 104 about the vertical axis X of the reactor system 100. A preheating ring 126 surrounds the base 120 to heat the process gas before it contacts the semiconductor structure 104. The outer edge 124 of the base 120 and the inner edge of the preheating ring 126 are separated by an annular gap 125 to allow rotation of the base 120. The semiconductor structure 104 is rotated to uniformly process the structure in the reactor 100. The reactor 100 also includes a preheating ring support 127 that supports the preheating ring 126 and facilitates movement of portions of the preheating ring 126.

[0028] The intake air 110 can be heated before contacting the semiconductor structure 104. Both the preheating ring 126 and the base 120 are generally opaque to absorb radiant heating light generated by high-intensity radiant heating lamps 128, which can be located above and below the processing chamber 102. Devices other than the high-intensity lamps 128 can be used to supply heat to the processing chamber 102, such as resistance heaters and induction heaters. Maintaining the preheating ring 126 and the base 120 at a temperature above ambient allows the preheating ring 126 and the base 120 to transfer heat to the intake air 110 as the gas 110 passes over them. Semiconductor structure 104 ( Figure 3 The diameter of the preheating ring 126 may be smaller than the diameter of the base 120 to allow the base 120 to heat the intake 110 before it contacts the semiconductor structure 104. The preheating ring 126 and the base 120 may be constructed of, for example, silicon carbide or opaque graphite coated with silicon carbide.

[0029] The upper and lower windows 112 and 114 each include a generally annular body made of a transparent material (e.g., quartz) to allow radiant heating light to be transmitted into the processing chamber 102 and to the preheating ring 126, the base 120, and the semiconductor structure 104. Windows 112 and 114 may be planar or, as... Figure 1 As shown, windows 112 and 114 may have a generally dome-shaped configuration. In other embodiments, one or both of windows 112 and 114 may have an inwardly recessed configuration. The upper and lower windows 112 and 114 are coupled to the upper and lower chamber walls 130 and 132 of the processing chamber 102, respectively.

[0030] The upper and lower chamber walls 130 and 132 define the outer perimeter of the treatment chamber 102 and are adjacent to the gas injection port 106 and the gas discharge port 108.

[0031] Reactor 100 may include upper and lower liners 134, 136 disposed within the processing chamber to prevent reaction between gas 110 and chamber walls 130, 132 (which are typically made of a metallic material such as stainless steel). Liners 134, 136 may be made of a suitable non-reactive material (e.g., quartz).

[0032] Reactor 100 is exemplary and, unless otherwise stated, any reactor that allows the semiconductor structure 104 to be processed (e.g., etched) according to the methods of this disclosure may generally be used.

[0033] According to the method of this disclosure, the processing reactor 100 processes the engineered polysilicon surface layer 135 ( ) before processing the semiconductor structure 104. Figure 4 A "film" or "film" is deposited on the preheating ring 126 and the substrate 120 to regulate the process. In the first step S1, any existing surface layer or coating is stripped from the preheating ring 126 and the substrate 120 (i.e., a "removal etching" is performed). A stripping etchant, such as hydrogen chloride (HCl), may be introduced into the reactor 100 to strip any previously deposited polysilicon surface layer from the substrate 120 and the preheating ring 126 when the semiconductor structure is not mounted on the substrate 120. In some embodiments, the stripping step S1 may be eliminated (e.g., if the substrate 120 and / or the preheating ring 126 are not coated with a previously deposited polysilicon surface layer).

[0034] In the second step S2, the polycrystalline silicon surface layer 135 ( Figure 4 (This may also be referred to herein as a "polycrystalline silicon" layer or "coating") is deposited on the substrate 120 and the preheating ring 126. The polycrystalline silicon surface layer 135 is deposited on the front surface of the substrate 120 and the preheating ring 126 by contacting the front surface with a silicon-containing gas that decomposes and forms the polycrystalline silicon layer (i.e., the semiconductor structure is not mounted on the substrate 120). Examples of silicon-containing gases include methylsilane, silicon tetrahydrode (silane), trisilane, disilane, pentalosilane, neopentylsilane, tetrasilane, dichlorosilane (SiH₂Cl₂), trichlorosilane (SiHCl₃), silicon tetrachloride (SiCl₄), etc. The silicon-containing gas may be mixed with a carrier gas such as hydrogen (e.g., trichlorosilane in hydrogen). The gas concentration can be determined based on the desired deposition effect (e.g., deposition rate).

[0035] Processing chamber 102 can be at any suitable pressure (e.g., atmospheric pressure) during polysilicon deposition. Deposition time may vary depending on deposition temperature, concentration, and desired thickness. In some embodiments, the polysilicon layer is at least 0.25 µm thick or at least about 0.5 µm, at least 1 µm, at least 2.5 µm, or at least 4 µm thick (e.g., 0.25 µm to 10 µm, from 0.25 µm to about 5 µm, or from about 1 µm to about 5 µm).

[0036] The deposited polysilicon layer can be engineered to enhance or promote certain properties of the polysilicon layer. For example, the deposited polysilicon layer can be engineered to increase the surface area of ​​the polysilicon layer. In some embodiments, the polysilicon layer is deposited at a relatively low temperature to reduce the grain size of the deposited coating. For example, in embodiments where trichlorosilane is used as the silicon-containing gas, the polysilicon can be deposited at a temperature below 1150°C. In some embodiments, the polysilicon surface layer 135 is deposited on the substrate 120 at temperatures below 1125°C, below 1100°C, below 1075°C, below 1050°C, below 1000°C, or below 900°C, or from 800°C to 1150°C, from 800°C to 1100°C, or from 900°C to 1050°C. The deposition temperature of gases other than trichlorosilane can be selected based on known suitable temperatures (e.g., according to the disclosed method).

[0037] Alternatively, or in addition to controlling the temperature at which the polysilicon layer is deposited, the polysilicon surface layer 135 on the substrate 120 and / or preheating ring 126 may also be “grooved” to increase the surface area of ​​the polysilicon layer 135 and create an engineered surface layer. The substrate 120 and / or preheating ring 126 can be grooved by introducing a grooving etchant into the processing chamber 102 of the processing reactor 100. Generally, the grooving etchant (which may also be referred to herein as the “first etchant”) is introduced into the chamber 102 before the semiconductor structure is mounted on the substrate 120. The grooving etchant is used to groove the polysilicon surface layer and create a “surface-modified” polysilicon surface layer 135.

[0038] Any suitable grooving etchant can be used, such as hydrogen, hydrogen chloride, or a mixture of hydrogen and hydrogen chloride.

[0039] In some embodiments, the polysilicon coating 135 deposited on the substrate is relatively thick, for example at least 1.25 µm, at least 1.5 µm, at least 1.75 µm, or at least 2 µm (e.g., from 1.25 µm to 5.0 µm, from 1.5 µm to 5 µm, or from 1.75 µm to 5 µm). Such a relatively thick polysilicon coating can increase the surface area of ​​the coating relative to a thinner coating.

[0040] Once the engineered polysilicon surface layer 135 (i.e., deposited and / or contacted with an etchant at a relatively low temperature to prepare a surface-modified polysilicon surface layer and / or a relatively thick polysilicon surface layer, as described above) is formed on the substrate 120 and / or the preheating ring 126, then in the third step S3, the semiconductor structure 104 ( Figure 3 and 5 It is loaded onto base 120.

[0041] Once the semiconductor structure 104 is mounted on the substrate 120, in the fourth step S4, the semiconductor structure is brought into contact with a smoothing etchant (also referred to herein as the “second etchant”) to etch and / or smooth the semiconductor structure 104. The smoothing etchant may be selected from hydrogen, hydrogen chloride, or a mixture of hydrogen and hydrogen chloride.

[0042] Generally, the semiconductor structure 104 can be any structure in which the desired etched structure is desired. See now for reference. Figure 6 In some embodiments, the semiconductor structure is a silicon-on-insulator (SOI) structure 104. The SOI structure 104 includes a disposal structure 110, a silicon top layer 125, and a dielectric layer 115 disposed between the disposal structure 110 and the silicon layer 125. The SOI structure 104 can be produced by any method known to those skilled in the art. In some embodiments, the semiconductor structure 104 has a certain amount of oxide at its edges.

[0043] Once the semiconductor structure 104 (which may be referred to herein as the “first” semiconductor structure) is in contact with a smoothing etchant, additional structures can be processed according to embodiments of the present disclosure. The first semiconductor structure 104 is removed from the substrate 120 after it has been etched (e.g., smoothed). The substrate 120 is brought into contact with a stripping etchant (i.e., step S1 above) to strip the surface-modified polysilicon surface layer 135 from the substrate 120. A second polysilicon surface layer is deposited on the substrate 120 and the preheating ring 126 (step S2). In some embodiments, the second polysilicon surface layer is deposited at a relatively low temperature to reduce the grain size of the deposited surface layer (e.g., below 1150°C, below 1125°C, below 1100°C, below 1075°C, below 1050°C, below 1000°C, or below 900°C).

[0044] Alternatively, or in addition to depositing the second polysilicon surface layer 135 at a relatively low temperature to reduce the grain size of the second polysilicon surface layer, in some embodiments, the second polysilicon surface layer is contacted with a first etchant (i.e., a separate gas having the same or similar concentration as the first etchant) to produce a second surface-modified polysilicon surface layer. A second semiconductor structure (e.g., the same type as structure 104 described above) is mounted on a substrate 120 (e.g., having the polysilicon surface layer deposited at the relatively low temperature and / or surface-modified as described above). The second semiconductor structure is contacted with a second etchant (i.e., a separate gas having the same or similar concentration as the second etchant) to etch the second semiconductor structure.

[0045] The methods disclosed herein offer several advantages compared to conventional methods for etching semiconductor structures. In embodiments where the polycrystalline silicon surface layer is deposited on a substrate at relatively low temperatures (e.g., below 1150°C, below 1125°C, below 1100°C, below 1075°C, below 1050°C, below 1000°C, or below 900°C), the grain size of the polycrystalline silicon can be reduced, thereby increasing the surface area of ​​the surface layer. In embodiments where the polycrystalline surface layer is surface-modified, for example by contacting it with a trenching etchant, the surface area of ​​the polycrystalline silicon surface layer is increased, reducing edge effects and improving the uniformity of the etched semiconductor structure. In embodiments where a relatively thick polycrystalline silicon surface layer is deposited on a substrate (e.g., at least 1.25 µm, at least 1.5 µm, at least 1.75 µm, or at least 2 µm), the polycrystalline silicon surface layer can be characterized by an increased surface area.

[0046] Without being constrained by any particular theory, it can be assumed that increased surface area improves the etching rate of the polycrystalline silicon surface layer relative to the semiconductor structure. This is similar to depleting the etching gas at the gap between the substrate and the semiconductor structure, much like depleting the gas on the semiconductor structure surface, which reduces edge roll-off at the semiconductor edges and improves thickness uniformity. The dependence of the etchant concentration at the semiconductor structure edges on the gap size between the substrate and the semiconductor structure weakens, and the influence of wafer centering on the substrate is reduced.

[0047] Example

[0048] The process disclosed herein is further illustrated by the following examples. These examples should not be considered as intended to be limiting.

[0049] Example 1: Surface area increases with particle size and slotting factor.

[0050] Figure 7 The surface area increases with the grain size and grooving factor of the 2 µm polycrystalline silicon layer. For example, from... Figure 7 It is evident that reducing the particle size and increasing the grooving factor can increase the surface area by up to two orders of magnitude.

[0051] Example 2: Edge rolling of polycrystalline silicon substrate coating engineered by temperature-reduced deposition and / or grooving Reduction effect

[0052] Several polycrystalline silicon engineering coatings were formed on the substrate, and the edge thickness effect was evaluated. Deposition temperature was used to control the grain size, as shown in Table 1. A mixture of H2 and H2+HCl was used for trenching to further increase the total exposed surface area.

[0053] The semiconductor structure is a 300 mm SOI wafer. The edge thickness roll-off from a radial position of 147 mm to the wafer edge is evaluated. The azimuth thickness range at the 147 mm radial position is also evaluated (i.e., the thickness variation across the wafer rotation angle at 147 mm).

[0054] like Figure 8 The differences between the reference coating process (with a temperature gradient from 1150°C to 1000°C and a thickness of 1 µm) and other experiments, as shown, indicate that increasing the polysilicon coating thickness from 1 µm to 2 µm reduces the edge thickness range by more than 50%. Without being constrained by any particular theory, the improved uniformity can be attributed to the increased surface area due to increased roughness. As the layer thickness increases, both surface roughness and total surface area increase. Grooving the polysilicon coating by contacting it with an etchant (Experiments B and C) further reduces edge roll-off and improves uniformity, resulting in an additional 10 Å increase in thickness range. In Experiment D, decreasing the coating temperature from 1150°C to 1000°C reduces the grain size by approximately 2 to 3 times and further increases the thickness range by an additional 5 Å.

[0055] Coating temperature Thickness (µm) Slotting time (s) Reference test 1150-->1000 dynamic 1 0 Coating Test A 1150℃ 2 0 Coating Test B 1150℃ 2 <![CDATA[30 (with H2)]]> Coating Test C 1150℃ 2 <![CDATA[30 (with H2 + HCL)]]> Coating Test D 1000℃ 2 0

[0056] Table 1: Polycrystalline Silicon Coating Conditions

[0057] As used herein, the terms “about,” “generally,” “substantially,” and “approximately” when used in conjunction with ranges of size, concentration, temperature, or other physical or chemical properties or characteristics mean to cover variations that may exist within the upper and / or lower limits of the range of properties or characteristics, including, for example, variations caused by rounding, measurement methods, or other statistical variations.

[0058] When elements of this disclosure and its embodiments are introduced, the articles “a / an” and “the / said” are intended to mean that one or more elements are present. The terms “comprising,” “including,” “containing,” and “having” are intended to be inclusive and mean that additional elements may be present in addition to the listed elements. The use of terms indicating a particular orientation (e.g., “top,” “bottom,” “side,” etc.) is for convenience of description and does not require any particular orientation of the described item.

[0059] Since various changes can be made to the above construction and methods without departing from the scope of this disclosure, all matters contained in the above description and shown in the accompanying drawings are intended to be illustrative rather than limiting.

Claims

1. A method for etching a semiconductor structure in a processing reactor, the processing reactor including a base supporting the semiconductor structure, the method comprising: A polycrystalline silicon surface layer is deposited on the substrate; The polycrystalline silicon surface layer is brought into contact with a first etchant to produce a surface-modified polycrystalline silicon surface layer; A semiconductor structure is mounted on a substrate on which a polycrystalline silicon surface layer with the surface modification is disposed; and The semiconductor structure is brought into contact with a second etchant to etch the semiconductor structure.

2. The method according to claim 1, wherein the first etchant is hydrogen, hydrogen chloride, or a mixture of hydrogen and hydrogen chloride.

3. The method of claim 1, wherein the polycrystalline silicon surface layer is deposited on the substrate at a temperature below 1150°C.

4. The method of claim 1, wherein the polycrystalline silicon surface layer is deposited on the substrate at a temperature below 1100°C.

5. The method of claim 3, wherein the polycrystalline silicon surface layer is deposited by introducing trichlorosilane into the processing reactor.

6. The method of claim 1, wherein the processing reactor comprises a preheating ring having an opening in which the base is disposed, the method further comprising: A polycrystalline silicon surface layer is deposited on the preheating ring; and The polycrystalline silicon surface layer disposed on the preheating ring is brought into contact with the first etchant to produce a surface-modified polycrystalline silicon surface layer.

7. The method of claim 1, wherein the substrate is made of silicon carbide or graphite coated with silicon carbide.

8. The method of claim 1, wherein before depositing the polysilicon surface layer onto the substrate, the substrate is contacted with a stripping etchant to strip the previously deposited polysilicon surface layer from the substrate.

9. The method of claim 1, wherein the semiconductor structure is a silicon-on-insulator structure having a disposal structure, a silicon top layer, and a dielectric layer disposed between the disposal structure and the silicon top layer.

10. The method of claim 1, wherein the second etchant is hydrogen, hydrogen chloride, or a mixture of hydrogen and hydrogen chloride.

11. The method of claim 1, wherein the polycrystalline silicon surface layer has a thickness of at least 1.25 µm.

12. The method of claim 1, wherein the semiconductor structure is a first semiconductor structure, the method further comprising: The first semiconductor structure is removed from the substrate after etching the first semiconductor structure; The substrate is brought into contact with a stripping etchant to strip the surface-modified polycrystalline silicon surface layer from the substrate. A second polycrystalline silicon surface layer is deposited on the substrate; The second polysilicon surface layer is brought into contact with the first etchant to produce a second surface-modified polysilicon surface layer; The second semiconductor structure is mounted onto the substrate on which the second surface-modified polycrystalline silicon surface layer is disposed; and The second semiconductor structure is brought into contact with the second etchant to etch the second semiconductor structure.

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