Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the semiconductor device comprising: a step region disposed on a substrate, the step region comprising a plurality of conductive layers stacked in a direction perpendicular to the substrate, an insulating film layer disposed between adjacent conductive layers, at least one insulating film layer comprises a first insulating layer, an isolating layer and a supporting layer which are distributed in the direction parallel to the substrate, and overlapping areas of orthographic projection of the isolating layer on the substrate and orthographic projection of two conductive layers adjacent to the isolating layer on the substrate are overlapped. The orthographic projection of the supporting layer on the substrate and the orthographic projection of the two conductive layers adjacent to the supporting layer on the substrate are overlapped; the dielectric constant of the isolation layer is smaller than that of the first insulation layer. According to the scheme provided by the embodiment, the film layer with the small dielectric constant is arranged between the adjacent conducting layers, stray capacitance is reduced, power consumption is reduced, and the working speed of the device is increased.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] Electrodes in the memory can be connected to a stepped region, where stepped electrodes are placed, and then connected to external electrodes via vias. Parasitic capacitance exists between these stepped electrodes, which affects device performance. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which reduces parasitic capacitance and improves device performance.

[0006] This application provides a semiconductor device, including: a stepped region disposed on a substrate, the stepped region including a plurality of conductive layers stacked along a direction perpendicular to the substrate, wherein for any conductive layer, the orthographic projection of the conductive layer on the substrate is at least partially located outside the orthographic projection of the plurality of conductive layers disposed on the side of the conductive layer away from the substrate on the substrate; and at least two adjacent conductive layers have overlapping orthographic projections on the substrate.

[0007] An insulating film layer is disposed between adjacent conductive layers. At least one of the insulating film layers includes a first insulating layer, an isolation layer, and a support layer distributed along a direction parallel to the substrate. The isolation layer is located between the first insulating layer and the support layer. For an insulating film layer located between two adjacent conductive layers that overlap in their orthographic projection onto the substrate, the isolation layer overlaps in the orthographic projection onto the substrate and in the overlapping region of the orthographic projection of the two adjacent conductive layers onto the substrate. The support layer overlaps in the orthographic projection onto the substrate and in the overlapping region of the orthographic projection of the two adjacent conductive layers onto the substrate. The dielectric constant of the isolation layer is less than that of the first insulating layer.

[0008] In some embodiments, the dielectric constant of the support layer is less than the dielectric constant of the first insulating layer.

[0009] In some embodiments, for an insulating film layer located between two adjacent conductive layers whose orthographic projections onto the substrate overlap, the orthographic projection of the first insulating layer onto the substrate is located outside the overlapping region of the orthographic projections of the two conductive layers adjacent to the first insulating layer onto the substrate.

[0010] In some embodiments, for any conductive layer, the conductive layer includes a first sub-part, the orthographic projection of the first sub-part onto the substrate being located outside the orthographic projection of a plurality of conductive layers disposed on the substrate-facing side of the conductive layer onto the substrate; the support layer is also distributed in a portion of the first sub-part on the substrate-facing side and is connected to the conductive layer.

[0011] In some embodiments, the bottommost conductive layer is provided with an isolation layer and a support layer connected to the bottommost conductive layer on the side facing the substrate.

[0012] In some embodiments, except for the topmost conductive layer, the remaining conductive layers include two conductive sublayers, and the multiple conductive sublayers of the multiple conductive layers are divided into two groups, with the two conductive sublayers of the same conductive layer located in different groups, and the topmost conductive layer belonging to one group; the multiple conductive sublayers of the same group are stacked in a stepped manner along a direction perpendicular to the substrate; in one group, from the topmost conductive sublayer to the next bottommost conductive sublayer, the orthographic projections of every two conductive sublayers on the substrate overlap, and the orthographic projection of the bottommost conductive sublayer on the substrate is outside the orthographic projections of the other conductive sublayers in the group on the substrate; in the other group, except for the bottommost and next bottommost conductive sublayers, the orthographic projections of every two conductive sublayers on the substrate overlap, and the orthographic projections of the topmost conductive layer on the substrate overlap with the orthographic projections of the adjacent conductive sublayers;

[0013] In the two sets of conductive sublayers, the arrangement directions of the topmost conductive sublayer to the bottommost conductive sublayer in the substrate are opposite, and the distance between the bottommost conductive sublayers in the two sets along the first direction is less than the distance between the topmost conductive sublayers along the first direction.

[0014] In some embodiments, in addition to the bottommost conductive layer, the support layer connected to the two conductive sublayers of the same conductive layer includes two spaced-apart support sublayers, each support sublayer being connected to one conductive sublayer; and each conductive sublayer has a support sublayer connected to the conductive sublayer on the substrate side.

[0015] In some embodiments, the stepped region includes a first stepped region and a second stepped region distributed along a second direction. The conductive layer, the isolation layer, and the support layer are projected onto the substrate in the orthographic projection of the first stepped region onto the substrate and are located outside the orthographic projection of the second stepped region onto the substrate. The first stepped region includes a first stepped structure, and the second stepped region includes a second stepped structure. The steps of the first stepped structure and the second stepped structure correspond one-to-one. The second stepped structure blocks part of the film layer of the first stepped structure, and each step of the second stepped structure exposes the following film layer on the sidewall facing the second stepped structure: the two adjacent conductive layers at the top of the step of the first stepped structure corresponding to that step, the support layer and the isolation layer between the two adjacent conductive layers, and the first insulating layer and the support layer facing the substrate from the side of the two adjacent conductive layers. This disclosure provides a method for manufacturing a semiconductor device, including:

[0016] A stacked structure comprising multiple alternating first insulating layers and sacrificial layers is formed on a substrate; the stacked structure includes a first stepped region and a second stepped region distributed along a second direction.

[0017] Etching removes the two first insulating layers and two sacrificial layers that are furthest from the substrate in the second step region;

[0018] The first insulating layer and the sacrificial layer are etched simultaneously in the first and second stepped regions to form a first stepped structure in the first stepped region and a second stepped structure in the second stepped region. The orthogonal projections of the multiple steps of the first stepped structure and the multiple steps of the second stepped structure onto the substrate are distributed along a first direction, which is perpendicular to the second direction. The sidewall of the first stepped structure facing the second stepped structure and not blocked by the second stepped structure is shielded.

[0019] In the first stepped region, the sacrificial layer exposed by the first stepped structure is etched in a direction parallel to the substrate to form a plurality of first lateral grooves; a plurality of conductive layers are formed to fill the plurality of first lateral grooves, and the conductive layers of different layers are disconnected.

[0020] The first insulating layer exposed by the first stepped structure is etched along a direction parallel to the substrate to form a plurality of second lateral grooves; a plurality of support layers are formed to fill the plurality of second lateral grooves.

[0021] The sidewall of the first stepped structure facing the second stepped structure and not obscured by the second stepped structure is exposed. The first insulating layer located between the overlapping regions of adjacent conductive layers that overlap in their orthogonal projection onto the substrate is replaced with an isolation layer, the dielectric constant of which is less than that of the first insulating layer.

[0022] In some embodiments, simultaneously etching the first insulating layer and the sacrificial layer in the first stepped region and the second stepped region to form a first stepped structure in the first stepped region and a second stepped structure in the second stepped region includes:

[0023] The substrate includes a first region and a second region distributed along a first direction;

[0024] The topmost first insulating layer and sacrificial layer of the first region are removed by etching.

[0025] Etch the topmost first insulating layer and sacrificial layer of the first sub-region adjacent to the second region in the first region, and etch the topmost first insulating layer and sacrificial layer of the second sub-region adjacent to the first region in the second region;

[0026] Etch the top two layers of first insulating layer and two layers of sacrificial layer of the third sub-region adjacent to the first sub-region in the first region, and etch the top two layers of first insulating layer and two layers of sacrificial layer of the fourth sub-region adjacent to the second sub-region in the second region;

[0027] One or more sub-regions are formed on the side of the third sub-region away from the second region, and one or more sub-regions are formed on the side of the fourth sub-region away from the first region. The two first insulating layers and two sacrificial layers at the top layer of the current sub-region are etched in sequence to form the first stepped structure and the second stepped structure.

[0028] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of the semiconductor device described above.

[0029] This application includes a semiconductor device and a method for manufacturing the same, and an electronic device. The semiconductor device includes: a stepped region disposed on a substrate, the stepped region including a plurality of conductive layers stacked along a direction perpendicular to the substrate, wherein for any conductive layer, the orthographic projection of the conductive layer onto the substrate is at least partially located outside the orthographic projections of a plurality of conductive layers disposed on the side of the conductive layer facing away from the substrate; at least two adjacent conductive layers having overlapping orthographic projections onto the substrate; an insulating film layer disposed between adjacent conductive layers, at least one of the insulating film layers including a first insulating layer, an isolation layer, and a support layer distributed along a direction parallel to the substrate, the isolation layer being located between the first insulating layer and the support layer; for the insulating film layer located between two adjacent conductive layers having overlapping orthographic projections onto the substrate, the isolation layer overlaps in the region where the orthographic projection onto the substrate is overlapped with the overlapping region where the orthographic projection of the isolation layer is overlapped with the overlapping region where the orthographic projection of the support layer is overlapped with the overlapping region where the orthographic projection of the support layer is overlapped with the overlapping region where the orthographic projection of the support layer is overlapped with the overlapping region where the orthographic projection of the support layer is overlapped with the overlapping region where the orthographic projection of the support layer is overlapped with the overlapping region where the orthographic projection of the support layer is overlapped with the overlapping region where the orthographic projection of the support layer is overlapped with the overlapping region where the orthographic projection of the support layer is overlapped with the overlapping region where the dielectric constant of the isolation layer is less than that of the first insulating layer. The solution provided in this embodiment involves setting a film layer with a small dielectric constant between adjacent conductive layers, thereby reducing parasitic capacitance, lowering power consumption, and improving device operating speed.

[0030] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0031] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0032] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0033] Figure 1A Three-dimensional schematic diagrams of semiconductor devices provided for some embodiments, Figure 1B For along Figure 1A A schematic diagram of the AA' direction. Figure 1C For along Figure 1A A schematic diagram of the BB' direction;

[0034] Figure 2A Top view of the stacked structure provided in some embodiments; Figure 2B For along Figure 2A A schematic diagram of a cross-section perpendicular to the AA' direction of the substrate; Figure 2C For along Figure 2A A schematic diagram of a cross-section perpendicular to the BB' direction of the substrate;

[0035] Figure 3A A schematic cross-sectional view along the AA' direction after etching the first insulating layer and the sacrificial layer, provided for some embodiments; Figure 3B A schematic cross-sectional view along the BB' direction after etching the first insulating layer and the sacrificial layer, provided for some embodiments;

[0036] Figure 4A A schematic cross-sectional view along the AA' direction after re-etching the first insulating layer and the sacrificial layer, as provided in some embodiments; Figure 4B A schematic cross-sectional view along the BB' direction after re-etching the first insulating layer and sacrificial layer, as provided in some embodiments;

[0037] Figure 5A A schematic cross-sectional view along the AA' direction after exposing the first and second sub-regions, provided for some embodiments; Figure 5B A schematic cross-sectional view along the BB' direction after exposing the first and second sub-regions, provided for some embodiments;

[0038] Figure 6A A schematic cross-sectional view along the AA' direction after etching the first insulating layer and sacrificial layer of the first and second sub-regions, as provided in some embodiments; Figure 6B A schematic cross-sectional view along the BB' direction after etching the first insulating layer and sacrificial layer of the first and second sub-regions, as provided in some embodiments;

[0039] Figure 7A A schematic cross-sectional view along the AA' direction after etching the first insulating layer and sacrificial layer of multiple sub-regions, as provided in some embodiments; Figure 7B A schematic cross-sectional view along the BB' direction after etching the first insulating layer and sacrificial layer of multiple sub-regions, as provided in some embodiments;

[0040] Figure 8A A schematic cross-sectional view along the AA' direction after re-etching the first insulating layer and the sacrificial layer, as provided in some embodiments; Figure 8B A schematic cross-sectional view along the BB' direction after re-etching the first insulating layer and sacrificial layer, as provided in some embodiments;

[0041] Figure 9A A schematic cross-sectional view along the AA' direction after forming a stepped structure, provided for some embodiments; Figure 9B A schematic cross-sectional view along the BB' direction after forming a stepped structure, provided for some embodiments;

[0042] Figure 10A A schematic cross-sectional view along the AA' direction after the formation of a dummy layer is provided for some embodiments; Figure 10B A schematic cross-sectional view along the BB' direction after forming a dummy layer, provided for some embodiments;

[0043] Figure 11A A schematic cross-sectional view along the AA' direction after etching the dummy layer, provided for some embodiments; Figure 11B A schematic cross-sectional view along the BB' direction after etching the dummy layer, provided for some embodiments;

[0044] Figure 12 A schematic cross-sectional view along the BB' direction after the formation of the first transverse groove, provided for some embodiments;

[0045] Figure 13 A schematic cross-sectional view along the BB' direction after the formation of the conductive layer is provided for some embodiments;

[0046] Figure 14 A schematic cross-sectional view along the BB' direction after disconnecting the conductive layer in different first transverse grooves, as provided in some embodiments;

[0047] Figure 15 A schematic cross-sectional view along the BB' direction after the support layer is formed, provided for some embodiments;

[0048] Figure 16A A schematic cross-sectional view along the AA' direction after the first insulating layer between the conductive layers is exposed, as provided in some embodiments; Figure 16B A schematic cross-sectional view along the BB' direction after the first insulating layer between the conductive layers is exposed, as provided in some embodiments;

[0049] Figure 17A A schematic cross-sectional view along the AA' direction after etching to expose the first insulating layer, provided for some embodiments; Figure 17B A schematic cross-sectional view along the BB' direction after etching to expose the first insulating layer, as provided in some embodiments. Detailed Implementation

[0050] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0052] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0053] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0054] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0055] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0056] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0057] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0058] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0059] Figure 1A Three-dimensional schematic diagrams of semiconductor devices provided for some embodiments, Figure 1B For along Figure 1A A schematic diagram of the AA' direction perpendicular to the substrate. Figure 1C For along Figure 1A A schematic diagram of the BB' direction perpendicular to the substrate. (See diagram below.) Figure 1A , Figure 1B , Figure 1C As shown, the semiconductor device provided in this disclosure embodiment may include: disposed on a substrate ( Figure 1A , Figure 1B , Figure 1C The substrate is not shown in the figure. The substrate is disposed in the form of a substrate. Figure 1A , Figure 1B and Figure 1C The semiconductor device includes a stepped region on the substrate (located in the lower center area). This stepped region comprises multiple conductive layers 7 stacked perpendicular to the substrate direction. For any conductive layer 7, its orthographic projection onto the substrate is at least partially outside the orthographic projections of the multiple conductive layers disposed on the side of the conductive layer 7 facing away from the substrate. That is, a portion of the conductive layer 7 is not obscured by other conductive layers above it, allowing vias to be formed in the unobscured areas to connect the conductive layer 7 to external electrodes. The semiconductor device may also include a memory array region (not shown in the figure) disposed on the substrate. The memory array region includes multiple layers of memory cells stacked perpendicular to the substrate direction and multiple electrodes (such as bit lines or word lines) connected to the memory cells. The conductive layer 7 can be connected to the electrodes of the memory array region, thereby enabling the connection between the electrodes of the memory array region and external electrodes. Among the multiple conductive layers 7, at least two adjacent conductive layers 7 have overlapping orthographic projections onto the substrate. (Reference) Figure 1C As can be seen, multiple sets of adjacent conductive layers 7 overlap in their orthographic projection onto the substrate. Specifically, adjacent conductive layers 7 are those adjacent along a direction perpendicular to the substrate.

[0060] An insulating film layer is disposed between adjacent conductive layers 7, and at least one of the insulating film layers includes a first insulating layer 11, an isolation layer 5, and a support layer 6 distributed parallel to the substrate direction. The isolation layer 5 is located between the first insulating layer 11 and the support layer 6. Some adjacent conductive layers 7 may include a support layer 6 and an isolation layer 5, for example, as shown below. Figure 1C As shown, the top two conductive layers 7 include a support layer 6 and an insulating layer 5. The remaining adjacent conductive layers 7 may include a first insulating layer 11, an insulating layer 5, and a support layer 6.

[0061] For the insulating film layer located between two adjacent conductive layers 7 whose orthographic projections onto the substrate overlap, the isolation layer 5 overlaps in the region where its orthographic projection onto the substrate overlaps with the region where the two adjacent conductive layers of the isolation layer 5 overlap with their orthographic projections onto the substrate; the support layer 6 overlaps in the region where its orthographic projection onto the substrate overlaps with the region where the two adjacent conductive layers of the support layer 6 overlap with their orthographic projections onto the substrate; the dielectric constant of the isolation layer 5 is less than the dielectric constant of the first insulating layer 11. For example, Figure 1CAs shown, the orthographic projections of adjacent conductive layers 7 onto the substrate overlap. The region where the orthographic projections of adjacent conductive layers 7 overlap is called the overlap region. The isolation layer 5 is distributed in the overlap region of adjacent conductive layers 7, and the support layer 6 is also distributed in the overlap region of adjacent conductive layers 7. The solution provided in this embodiment, by placing a film layer with a small dielectric constant between adjacent conductive layers 7 that have overlapping orthographic projections, helps to reduce parasitic capacitance between adjacent conductive layers, reduce power consumption, and improve the operating speed of the device.

[0062] In some embodiments, the conductive layer 7 extends along a second direction Y parallel to the substrate, the insulating layer 5 extends along the second direction Y, and the support layer 6 extends along the second direction Y. The first insulating layer 11 extends along a direction parallel to the substrate.

[0063] In some embodiments, for an insulating film layer located between two adjacent conductive layers 7 whose orthographic projections onto the substrate overlap, the orthographic projection of the first insulating layer 11 onto the substrate is located outside the overlapping region of the orthographic projections of the two conductive layers 7 adjacent to the first insulating layer 11 onto the substrate. The solution provided in this embodiment completely excludes the first insulating layer 11, which has a larger dielectric constant, from the overlapping portion of the adjacent conductive layers 7, thereby minimizing parasitic capacitance. However, the embodiments of this disclosure are not limited to this; the first insulating layer 11 may be partially disposed between the overlapping portions, and an isolation layer 5 may be partially disposed between them.

[0064] In some embodiments, the dielectric constant of the support layer 6 may be less than that of the first insulating layer 11. The solution provided in this embodiment, by using a material with a lower dielectric constant as the support layer, can further reduce the parasitic capacitance between adjacent conductive layers. However, this embodiment is not limited to this; the dielectric constant of the support layer 6 may be the same as or approximately the same as that of the first insulating layer 11.

[0065] In some embodiments, for any conductive layer 7, the conductive layer 7 includes a first sub-part, the orthographic projection of the first sub-part onto the substrate being outside the orthographic projection of the plurality of conductive layers 7 disposed on the substrate-facing side of the conductive layer 7 onto the substrate; the support layer 6 is also distributed in a portion of the first sub-part on the substrate-facing side and is connected to the conductive layer 7. For example, such as Figure 1C As shown, the conductive layer 7 of the sub-bottom layer has a support layer 6 distributed on the side facing the substrate.

[0066] In some embodiments, the bottom conductive layer 7 is provided with an isolation layer 5 and a support layer 6 connected to the bottom conductive layer 7 on the side facing the substrate.

[0067] In some embodiments, the isolation layer 5 is further distributed on the substrate-facing side of the sub-bottom conductive layer 7 and connected to the conductive layer 7, and the orthographic projection of the isolation layer 5 on the substrate is located within the orthographic projection of the conductive layer 7 connected to the isolation layer 5 on the substrate.

[0068] In some embodiments, except for the topmost conductive layer 7, the remaining conductive layers 7 may include two conductive sublayers 71 (the two conductive sublayers 71 are equidistant from the substrate), and the multiple conductive sublayers 71 of the multiple conductive layers 7 are divided into two groups, with the two conductive sublayers 71 of the same conductive layer located in different groups, and the topmost conductive layer 7 belonging to one group; the multiple conductive sublayers 71 of the same group are stacked in a stepped manner along a direction perpendicular to the substrate; in one group, from the topmost conductive sublayer 71 to the second-bottom conductive sublayer 71, the orthographic projections of every two conductive sublayers 71 on the substrate overlap, and the orthographic projection of the bottommost conductive sublayer 71 on the substrate is outside the orthographic projections of the other conductive sublayers 71 in the group on the substrate; in the other group, except for the bottommost conductive sublayer 71 and the second-bottom conductive sublayer 71, the orthographic projections of every two conductive sublayers 71 on the substrate overlap, and the topmost conductive layer 7 overlaps with the orthographic projections of the adjacent conductive sublayer 71 on the substrate;

[0069] In the two sets of conductive sublayers 71, the arrangement directions of the topmost conductive sublayer 71 to the bottommost conductive sublayer 71 in the orthogonal projection onto the substrate are opposite. That is, they are arranged in opposite directions from the bottommost conductive sublayer 71 to form a stepped structure, and the distance between the bottommost conductive sublayer 71 in both sets along the first direction X is less than the distance between the topmost conductive sublayer 71 in the first direction X. In this embodiment, the conductive layer forms two stepped structures. This embodiment is not limited to this; the conductive layer may form only one stepped structure. The first direction X and the second direction Y are perpendicular. Figure 1A , Figure 1C The number of conductive layers 7 shown is merely an example, and the embodiments disclosed herein are not limited thereto and may include more or fewer conductive layers 7.

[0070] In some implementations, the support layer 6 connected to the two conductive sublayers 71 of the same conductive layer 7 includes two spaced-apart support sublayers 61, each support sublayer 61 being connected to one conductive sublayer 71; and each conductive sublayer 71 has the support sublayer 61 connected to the conductive sublayer 71 on the substrate side.

[0071] In some embodiments, the stepped region includes a first stepped region 100 and a second stepped region 200 distributed along a second direction Y. The orthographic projection of the conductive layer 7, the isolation layer 5, and the support layer 6 onto the substrate is located within the orthographic projection of the first stepped region 100 onto the substrate and outside the orthographic projection of the second stepped region 200 onto the substrate. The second stepped structure exposes the sidewalls of the first stepped structure facing the second stepped structure. The first stepped structure includes multiple steps, and the second stepped structure includes multiple steps, with the number of steps being identical and corresponding one-to-one. The second stepped structure obscures a portion of the film layer of the first stepped structure, and each step of the second stepped structure exposes the two adjacent conductive layers 7 at the top of the corresponding step of the first stepped structure, the support layer 6 and the isolation layer 5 between the two adjacent conductive layers 7, and the first insulating layer 11 and the support layer 6 facing the substrate of the two adjacent conductive layers 7 facing the sidewalls of the second stepped structure. That is, the second step structure has four fewer steps than the corresponding steps of the first step structure. Therefore, each step of the first step structure exposes four sequentially stacked film layers facing the sidewall of the second step structure: two adjacent conductive layers 7, an isolation layer 5 and a support layer 6 between the conductive layers 7, and a first insulating layer 11 and a support layer 6 facing the substrate side of the two adjacent conductive layers 7. The solution provided in this embodiment allows the first step structure to be shielded during manufacturing by setting the second step structure, so that the first insulating layer 11 between adjacent conductive layers can be replaced with the support layer 6 and the isolation layer 5.

[0072] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" described in this embodiment may include deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" described in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0073] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0074] 1) Forming a stacked structure;

[0075] A first insulating film and a sacrificial layer film are sequentially and alternately deposited on a substrate to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and sacrificial layers 10; the stacked structure includes a first stepped region 100 and a second stepped region 200 distributed along the second direction Y, the first stepped region 100 can form a contact electrode to connect the memory cell to an external circuit.

[0076] Photoresist is coated in the first stepped region 100 to form a photoresist layer 9, such as... Figure 2A , Figure 2B and Figure 2C As shown. The second-step region 200 is not covered by the photoresist layer 9. Among them, Figure 2A Top view of the stacked structure provided in some embodiments; Figure 2B For along Figure 2A A schematic diagram of a cross-section perpendicular to the AA' direction of the substrate; Figure 2C For along Figure 2A A schematic diagram of a cross-section perpendicular to the BB' direction of the substrate. Figure 2A , Figure 2B and Figure 2C The substrate is not shown.

[0077] As used herein, the term "substrate" means and includes a base material or structure on which a material such as a vertical field-effect transistor is formed. A substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate can be a conventional silicon substrate or other bulk substrate that includes layers of semiconductor material.

[0078] In some embodiments, the first insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2). The materials of the subsequent second insulating film are similar to those of the first insulating film and will not be described further.

[0079] In some embodiments, the sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as SiN.

[0080] 2) Etch the first insulating layer 11 and the sacrificial layer 10;

[0081] The top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 of the second stepped region 200 are removed by etching using a patterning process; the first stepped region 100 remains unchanged; as Figure 3A and Figure 3BAs shown, where, Figure 3A A schematic cross-sectional view along the AA' direction after etching the first insulating layer 11 and the sacrificial layer 10, as provided in some embodiments; Figure 3B A schematic cross-sectional view along the BB' direction after etching the first insulating layer 11 and the sacrificial layer 10, as provided in some embodiments.

[0082] 3) Etch the first insulating layer 11 and the sacrificial layer 10 again;

[0083] The stacked structure includes two regions distributed along a first direction X: a first region 301 and a second region 302.

[0084] In the region where the second step region 200 and the first region 301 overlap, the topmost first insulating layer 11 and sacrificial layer 10 of that region are etched away; in the region where the first step region 100 and the first region 301 overlap, the topmost first insulating layer 11 and sacrificial layer 10 of that region are etched away; Figure 4A and Figure 4B As shown, Figure 4A A schematic cross-sectional view along the AA' direction after re-etching the first insulating layer 11 and the sacrificial layer 10, as provided in some embodiments; Figure 4B A schematic cross-sectional view along the BB' direction after re-etching the first insulating layer 11 and the sacrificial layer 10, as provided in some embodiments.

[0085] 4) Expose the first sub-region 301_1 and the second sub-region 302_1;

[0086] Photoresist is applied, and the area is exposed to reveal a first sub-region 301_1 of the first region 301, adjacent to the second region 302, extending along a first predetermined length in the first direction X; and a second sub-region 302_1 of the second region 302, adjacent to the first region 301, extending along a second predetermined length in the first direction X. The first sub-region 301_1 and the second sub-region 302_1 extend along a second direction Y and penetrate the stacked structure in the second direction Y. Figure 5A and Figure 5B As shown, Figure 5A A cross-sectional schematic diagram along the AA' direction after exposing the first sub-region 301_1 and the second sub-region 302_1, as provided in some embodiments;

[0087] Figure 5B A schematic cross-sectional view along the BB' direction after exposing the first sub-region 301_1 and the second sub-region 302_1, as provided in some embodiments.

[0088] 5) Etch the first insulating layer 11 and the sacrificial layer 10 of the first sub-region 301_1 and the second sub-region 302_1;

[0089] In the first sub-region 301_1, the topmost first insulating layer 11 and sacrificial layer 10 are etched away; in the second sub-region 302_1, the topmost first insulating layer 11 and sacrificial layer 10 are etched away; as follows Figure 6A and Figure 6B As shown, Figure 6A A schematic cross-sectional view along the AA' direction after etching the first insulating layer 11 and sacrificial layer 10 of the first sub-region 301_1 and the second sub-region 302_1, as provided in some embodiments; Figure 6B A schematic cross-sectional view along the BB' direction after etching the first insulating layer 11 and sacrificial layer 10 of the first sub-region 301_1 and the second sub-region 302_1, as provided in some embodiments.

[0090] 6) Etch the first insulating layer 11 and sacrificial layer 10 in the first sub-region 301_1, the second sub-region 302_1, the third sub-region 301_2, and the fourth sub-region 302_2;

[0091] Photoresist is exposed to expose a third sub-region 301_2 in the first region 301 that is adjacent to the first sub-region 301_1 and extends along the first direction X for a third preset length, and a fourth sub-region 302_2 in the second region 302 that is adjacent to the second sub-region 302_1 and extends along the first direction X for a fourth preset length. The third sub-region 301_2 and the fourth sub-region 302_2 extend along the second direction Y and penetrate the stacked structure in the second direction Y.

[0092] In the first sub-region 301_1, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away; in the second sub-region 302_1, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away; in the third sub-region 301_2, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away; in the fourth sub-region 302_2, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away; as follows Figure 7A and Figure 7B As shown, Figure 7A A schematic cross-sectional view along the AA' direction after etching the first insulating layer 11 and sacrificial layer 10 of the first sub-region 301_1, the second sub-region 302_1, the third sub-region 301_2, and the fourth sub-region 302_2, as provided in some embodiments; Figure 7B A schematic cross-sectional view along the BB' direction after etching the first insulating layer 11 and sacrificial layer 10 of the first sub-region 301_1, the second sub-region 302_1, the third sub-region 301_2, and the fourth sub-region 302_2, as provided in some embodiments.

[0093] 7) Etch the first insulating layer 11 and sacrificial layer 10 of the first sub-region 301_1, the second sub-region 302_1, the third sub-region 301_2, the fourth sub-region 302_2, the fifth sub-region 301_3, and the sixth sub-region 302_3;

[0094] Photoresist is exposed to expose a fifth sub-region 301_3 in the first region 301 that is adjacent to the third sub-region 301_2 and extends along the first direction X for a fifth preset length, and a sixth sub-region 302_3 in the second region 302 that is adjacent to the fourth sub-region 302_2 and extends along the first direction X for a sixth preset length. The fifth sub-region 301_3 and the sixth sub-region 302_3 extend along the second direction Y and penetrate the stacked structure in the second direction Y.

[0095] In the first sub-region 301_1, the third sub-region 301_2, and the fifth sub-region 301_3, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away in each region; in the second sub-region 302_1, the fourth sub-region 302_2, and the sixth sub-region 302_3, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away in each region; as follows Figure 8A and Figure 8B As shown, Figure 8A A schematic cross-sectional view along the AA' direction after re-etching the first insulating layer 11 and the sacrificial layer 10, as provided in some embodiments; Figure 8B A schematic cross-sectional view along the BB' direction after re-etching the first insulating layer 11 and the sacrificial layer 10, as provided in some embodiments.

[0096] 8) Forms a stepped structure;

[0097] Photoresist is exposed to expose a seventh sub-region 301_4 in the first region 301 that is adjacent to the fifth sub-region 301_3 and extends along the first direction X for a seventh preset length, and an eighth sub-region 302_4 in the second region 302 that is adjacent to the sixth sub-region 302_3 and extends along the first direction X for an eighth preset length. The seventh sub-region 301_4 and the eighth sub-region 302_4 extend along the second direction Y and penetrate the stacked structure in the second direction Y.

[0098] In the first sub-region 301_1, the third sub-region 301_2, the fifth sub-region 301_3, and the seventh sub-region 301_4, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away; in the second sub-region 302_1, the fourth sub-region 302_2, the sixth sub-region 302_3, and the eighth sub-region 302_4, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away.

[0099] Photoresist is exposed to reveal a ninth sub-region 301_5 in the first region 301 that is adjacent to the seventh sub-region 301_4 and has a ninth preset length along the first direction X, and a tenth sub-region 302_5 in the second region 302 that is adjacent to the eighth sub-region 302_4 and has a tenth preset length along the first direction X. The ninth sub-region 301_5 and the tenth sub-region 3025 extend along the second direction Y and penetrate the stacked structure in the second direction Y.

[0100] In the first sub-region 301_1, the third sub-region 301_2, the fifth sub-region 301_3, the seventh sub-region 301_4, and the ninth sub-region 301_5, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away; in the second sub-region 302_1, the fourth sub-region 302_2, the sixth sub-region 302_3, the eighth sub-region 302_4, and the tenth sub-region 302_5, the top two layers of the first insulating layer 11 and the two layers of the sacrificial layer 10 are etched away; forming a staircase, as shown below. Figure 9A and Figure 9B As shown, Figure 9A A schematic cross-sectional view along the AA' direction after forming a stepped structure, provided for some embodiments; Figure 9B This is a cross-sectional schematic diagram along the BB' direction after forming a stepped structure according to some embodiments. At this time, stepped structures are formed in the film layers of both the first region 301 and the second region 302. A first stepped structure is formed in the first stepped region 100, and a second stepped structure is formed in the second stepped region 200. The first stepped structure includes two sub-stepped structures arranged opposite each other along the first direction X, and the second stepped structure also includes two sub-stepped structures arranged opposite each other along the first direction X. A groove is formed between the two sub-stepped structures of the first stepped structure. A groove is also formed between the two sub-stepped structures of the second stepped structure. The second stepped structure partially obscures the film layer of the first stepped structure and exposes a portion of the film layer. (Refer to...) Figure 16B In the area shown in the dashed box, because the second step region 200 has etched away 4 more film layers (two first insulating layers 11 and two sacrificial layers 10) than the first step region 100, the final stepped structure has 4 more film layers in each step of the first step structure than the corresponding step in the second step structure. These four film layers are not blocked by the second step structure.

[0101] In some embodiments, the lengths of the plurality of sub-regions along the first direction X may be the same. However, the embodiments disclosed herein are not limited thereto.

[0102] 9) Create a virtual layer 8;

[0103] A dummy layer film is deposited to form a dummy layer 8 covering the first region 301 and the second region 302; as shown. Figure 10A and Figure 10B As shown, Figure 10A A schematic cross-sectional view along the AA' direction after forming the dummy layer 8, provided for some embodiments; Figure 10B This is a schematic cross-sectional view along the BB' direction after the formation of the dummy layer 8, provided for some embodiments. In this embodiment, the dummy layer 8 can protect the film layer of the second step region 200 during subsequent operations in the first step region 100, and also protect the film layer in the first step region 100 that is blocked by the second step structure.

[0104] In some embodiments, the dummy layer film may be, for example, a film layer with an etching selectivity ratio between carbon and a first insulating layer film and a sacrificial layer film.

[0105] 10) Etch the dummy layer 8;

[0106] Photoresist is coated on the second stepped region 200 to form a photoresist layer 300, exposing the first stepped region 100. The dummy layer 8 of the first stepped region 100 is etched away, while the dummy layer 8 of the second stepped region 200 is retained, thereby protecting the film layer of the second stepped region 200. Figure 11A and Figure 11B As shown, Figure 11A A schematic cross-sectional view along the AA' direction after etching the dummy layer 8, as provided in some embodiments; Figure 11B A schematic cross-sectional view along the BB' direction after etching the dummy layer 8, as provided in some embodiments.

[0107] 11) Form the first transverse groove A1;

[0108] Based on the trenches of the first stepped region 100, the sacrificial layer 10 exposed in the trenches is etched laterally (etched along a direction parallel to the substrate) for an eleventh predetermined length, forming a plurality of first lateral grooves A1 located between adjacent first insulating layers 11; as shown Figure 12 As shown, Figure 12 A schematic cross-sectional view along the BB' direction after the formation of the first transverse groove A1 is provided for some embodiments. The cross-sectional view along the AA' direction is the same. Figure 11A (Details omitted here). The eleventh preset length can be set so that the subsequently formed conductive layer 7 is not blocked by the second stepped structure, thereby completely removing the first insulating layer 11 between the overlapping portions of adjacent conductive layers 7 and minimizing the parasitic capacitance between adjacent conductive layers. However, the embodiments of this disclosure are not limited to this; the conductive layer 7 can be partially blocked, in which case the first insulating layer 11 can exist between the overlapping portions of subsequent adjacent conductive layers 7.

[0109] 12) Forming a conductive layer 7;

[0110] A conductive thin film is deposited to form a conductive layer 7; the conductive thin film fills the first transverse groove A1 and covers the sidewall of the first insulating layer 11; as shown Figure 13 As shown, Figure 13 A schematic cross-sectional view along the BB' direction after the formation of conductive layer 7 is provided for some embodiments. The cross-sectional view along the AA' direction is the same. Figure 11A (The rest is omitted.)

[0111] In some embodiments, the stacked structure may further include a memory array region, and the conductive layer 7 may be fabricated simultaneously with the electrodes of the memory array region, i.e., a conductive thin film may be deposited simultaneously in the memory array region and the stepped region. Alternatively, the conductive layer 7 in the stepped region and the electrodes in the memory array region may be formed separately and then connected together, thereby leading out multiple memory cells in the memory array region and realizing the connection between the electrodes of the memory array region and external electrodes.

[0112] In some embodiments, the conductive thin film may be one or more of the following different types of materials:

[0113] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0114] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0115] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0116] 13) Disconnect the conductive layer 7 in the different first transverse grooves A1;

[0117] The conductive film outside the first transverse groove A1 (the conductive film covering the topmost first insulating layer 11 and the conductive film covering the sidewalls of the first insulating layer 11) is etched away, so that the conductive layers 7 in different first transverse grooves A1 are disconnected. Each conductive layer 7 can be a film layer, or it can include two independent conductive sub-layers 71, such as... Figure 14 As shown, Figure 14 A schematic cross-sectional view along the BB' direction after disconnecting the conductive layer 7 in different first transverse grooves A1, as provided in some embodiments.

[0118] 14) Form a support layer 6;

[0119] Based on the trench of the first stepped region 100, the first insulating layer 11 exposed in the trench is laterally etched to form a second lateral groove A2 located between adjacent conductive sublayers 71 or between adjacent conductive sublayers 71 and sacrificial layer 10; the size of the second lateral groove A2 along the first direction X is smaller than the size of the first lateral groove A1 along the first direction X.

[0120] A support layer thin film is deposited to form a support layer 6, which fills the second lateral groove A2 and covers the side of the conductive layer 7 opposite to the substrate 1, as shown below. Figure 15 As shown, Figure 15 This is a schematic cross-sectional view along the BB' direction after the support layer 6 has been formed, as provided in some embodiments. The support layer 6 can support the conductive layers 7 when the first insulating layer 11 between adjacent conductive layers 7 is subsequently removed.

[0121] In some embodiments, the support layer film may be a material with an etching selectivity ratio to the first insulating film and the sacrificial layer film, such as polycrystalline silicon or silicon oxycarbide (SiOC). The dielectric constant of the support layer film may be less than that of the first insulating film, but the embodiments disclosed herein are not limited thereto. The dielectric constant of the support layer film may be the same as or close to that of the first insulating film.

[0122] 15) Expose the first insulating layer 11 between adjacent conductive layers 7;

[0123] The support layer 6 on the sidewall of the conductive layer 7 is etched away, and the support layer 6 exposed on the side of the conductive layer 7 away from the substrate 1 (i.e. the support layer 6 not covered by another conductive layer 7) is etched away. At this time, the support layers 6 of different layers are disconnected.

[0124] The photoresist layer 300 is exposed, revealing the second stepped region 200. The dummy layer 8 of the second stepped region 200 is etched away. At this time, the sidewall of the first insulating layer 11 in the first stepped region 100, which is in contact with the conductive layer 7, is exposed towards the second stepped region 200. Figure 16A and Figure 16B As shown, Figure 16A A schematic cross-sectional view along the AA' direction after the first insulating layer 11 between the conductive layers 7 is exposed, as provided in some embodiments; Figure 16B A schematic cross-sectional view along the BB' direction after the first insulating layer 11 between the conductive layers 7 is exposed, as provided in some embodiments.

[0125] 16) The first insulating layer 11 is etched out;

[0126] Wet etching of the first insulating layer 11 removes the first insulating layer 11 exposed in the first stepped region 100 in step 15, including the first insulating layer 11 in contact with the conductive layer 7 (regions of the first insulating layer 11 not in contact with the conductive layer 7 are not removed), and also a portion of the penultimate first insulating layer 11; wherein, the first insulating layer 11 in contact with the conductive layer 7 includes the first insulating layer 11 located between adjacent conductive layers 7 along the direction perpendicular to the substrate, and also includes the first insulating layer 11 located between the conductive layer 7 and the sacrificial layer 10, such as... Figure 17A and Figure 17B As shown, Figure 17A A schematic cross-sectional view along the AA' direction after etching to expose the first insulating layer 11, as provided in some embodiments; Figure 17B This is a schematic cross-sectional view along the BB' direction after etching to expose the first insulating layer 11, as provided in some embodiments. At this time, a portion of the first insulating layer 11 between adjacent sacrificial layers 10 in the second step region 200 is etched away, forming a transverse groove between adjacent sacrificial layers 10.

[0127] 17) Form an isolation layer 5;

[0128] An isolation layer film is deposited. The area vacated after etching the first insulating layer 11 in step 16) is etched away. The isolation layer film in the second step region 200 is removed, leaving only the isolation layer film in the first step region 100, forming an isolation layer 5. The isolation layer 5 fills the region between adjacent conductive layers 7 along the direction perpendicular to the substrate 1, and the region between adjacent conductive layers 7 and the first insulating layer 11 along the direction perpendicular to the substrate 1. Figure 1A , Figure 1B and Figure 1C As shown.

[0129] The insulating layer film is made of a material with a dielectric constant lower than that of the first insulating layer 11, such as silicon oxycarbide (SiOC). The dielectric constant K of the insulating layer film can be between 2.5 and 3.0. The solution provided in this embodiment reduces the parasitic capacitance generated between the conductive sublayers 71 by replacing the film layer between the conductive sublayers 71 with a material with a lower dielectric constant, thereby improving the device's operating speed and reducing power consumption.

[0130] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0131] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A stepped region disposed on a substrate, the stepped region comprising a plurality of conductive layers stacked along a direction perpendicular to the substrate, wherein for any conductive layer, the orthographic projection of the conductive layer onto the substrate is at least partially located outside the orthographic projection of the plurality of conductive layers disposed on the side of the conductive layer away from the substrate onto the substrate; there are at least two adjacent conductive layers whose orthographic projections onto the substrate overlap. An insulating film layer is disposed between adjacent conductive layers. At least one of the insulating film layers includes a first insulating layer, an isolation layer, and a support layer distributed along a direction parallel to the substrate. The isolation layer is located between the first insulating layer and the support layer. For an insulating film layer located between two adjacent conductive layers that overlap in their orthographic projection onto the substrate, the isolation layer overlaps in the orthographic projection onto the substrate and in the overlapping region of the orthographic projection of the two adjacent conductive layers onto the substrate. The support layer overlaps in the orthographic projection onto the substrate and in the overlapping region of the orthographic projection of the two adjacent conductive layers onto the substrate. The dielectric constant of the isolation layer is less than that of the first insulating layer.

2. The semiconductor device according to claim 1, characterized in that, The dielectric constant of the support layer is less than that of the first insulating layer.

3. The semiconductor device according to claim 1, characterized in that, For an insulating film layer located between two adjacent conductive layers whose orthographic projections onto the substrate overlap, the orthographic projection of the first insulating layer onto the substrate is located outside the overlapping region of the orthographic projections of the two conductive layers adjacent to the first insulating layer onto the substrate.

4. The semiconductor device according to claim 1, characterized in that, For any conductive layer, the conductive layer includes a first sub-section, the orthographic projection of the first sub-section onto the substrate being located outside the orthographic projection of a plurality of conductive layers disposed on the substrate side of the conductive layer; the support layer is also distributed in a portion of the first sub-section on the substrate side and is connected to the conductive layer.

5. The semiconductor device according to claim 1, characterized in that, The bottom conductive layer has an isolation layer and a support layer connected to it on the side facing the substrate.

6. The semiconductor device according to claim 1, characterized in that, Except for the topmost conductive layer, the remaining conductive layers include two conductive sublayers, and the multiple conductive sublayers of the multiple conductive layers are divided into two groups. The two conductive sublayers of the same conductive layer are located in different groups, and the topmost conductive layer belongs to one of the groups. The multiple conductive sublayers in the same group are stacked in a stepped manner along the direction perpendicular to the substrate. In one group, from the topmost conductive sublayer to the next bottommost conductive sublayer, the orthographic projections of every two conductive sublayers on the substrate overlap, and the orthographic projection of the bottommost conductive sublayer on the substrate is outside the orthographic projections of the other conductive sublayers in the group on the substrate. In the other group, except for the bottommost and the next bottommost conductive layers, the orthographic projections of every two conductive layers onto the substrate overlap, and the topmost conductive layer overlaps with the orthographic projections of its adjacent conductive layer onto the substrate. In the two sets of conductive sublayers, the arrangement directions of the topmost conductive sublayer to the bottommost conductive sublayer in the substrate are opposite, and the distance between the bottommost conductive sublayers in the two sets along the first direction is less than the distance between the topmost conductive sublayers along the first direction.

7. The semiconductor device according to claim 6, characterized in that, The support layer connected to two conductive sublayers of the same conductive layer includes two spaced-apart support sublayers, each support sublayer being connected to one conductive sublayer; and each conductive sublayer has a support sublayer connected to the conductive sublayer on the substrate side.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The stepped region includes a first stepped region and a second stepped region distributed along a second direction. The conductive layer, the isolation layer, and the support layer are projected onto the substrate within the projection of the first stepped region onto the substrate and outside the projection of the second stepped region onto the substrate. The first stepped region includes a first stepped structure, and the second stepped region includes a second stepped structure. The steps of the first stepped structure and the second stepped structure correspond one-to-one. The second stepped structure blocks part of the film layer of the first stepped structure, and each step of the second stepped structure exposes the following film layer on the sidewall facing the second stepped structure: the two adjacent conductive layers at the top of the step of the first stepped structure corresponding to that step, the support layer and the isolation layer between the two adjacent conductive layers, and the first insulating layer and the support layer facing the substrate of the two adjacent conductive layers.

9. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure comprising multiple alternating first insulating layers and sacrificial layers is formed on a substrate; the stacked structure includes a first stepped region and a second stepped region distributed along a second direction. Etching removes the two first insulating layers and two sacrificial layers that are furthest from the substrate in the second step region; The first insulating layer and the sacrificial layer are etched simultaneously in the first and second stepped regions to form a first stepped structure in the first stepped region and a second stepped structure in the second stepped region. The orthogonal projections of the multiple steps of the first stepped structure and the multiple steps of the second stepped structure onto the substrate are distributed along a first direction, which is perpendicular to the second direction. The sidewall of the first stepped structure facing the second stepped structure and not blocked by the second stepped structure is shielded. In the first stepped region, the sacrificial layer exposed by the first stepped structure is etched in a direction parallel to the substrate to form a plurality of first lateral grooves; a plurality of conductive layers are formed to fill the plurality of first lateral grooves, and the conductive layers of different layers are disconnected. The first insulating layer exposed by the first stepped structure is etched along a direction parallel to the substrate to form a plurality of second lateral grooves; a plurality of support layers are formed to fill the plurality of second lateral grooves. The sidewall of the first stepped structure facing the second stepped structure and not obscured by the second stepped structure is exposed. The first insulating layer located between the overlapping regions of adjacent conductive layers that overlap in their orthogonal projection onto the substrate is replaced with an isolation layer, the dielectric constant of which is less than that of the first insulating layer.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The step of simultaneously etching the first insulating layer and the sacrificial layer in the first and second stepped regions to form a first stepped structure in the first stepped region and a second stepped structure in the second stepped region includes: The substrate includes a first region and a second region distributed along a first direction; The topmost first insulating layer and sacrificial layer of the first region are removed by etching. Etch the topmost first insulating layer and sacrificial layer of the first sub-region adjacent to the second region in the first region, and etch the topmost first insulating layer and sacrificial layer of the second sub-region adjacent to the first region in the second region; Etch the top two layers of first insulating layer and two layers of sacrificial layer of the third sub-region adjacent to the first sub-region in the first region, and etch the top two layers of first insulating layer and two layers of sacrificial layer of the fourth sub-region adjacent to the second sub-region in the second region; One or more sub-regions are formed on the side of the third sub-region away from the second region, and one or more sub-regions are formed on the side of the fourth sub-region away from the first region. The two first insulating layers and two sacrificial layers at the top layer of the current sub-region are etched in sequence to form the first stepped structure and the second stepped structure.

11. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 8, or the semiconductor device formed by the manufacturing method of the semiconductor device according to claim 9 or 10.

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