Semiconductor package and semiconductor package assembly

Abstract

The invention discloses a semiconductor package and a semiconductor package assembly. The semiconductor package comprises a first interconnection structure; the first chip is arranged on the first interconnection structure and is coupled with the first interconnection structure; a first redistribution layer disposed on the first chip and coupled to the first chip; a molding compound disposed on the first interconnect structure and encapsulating the first chip and the first redistribution layer; and a through-mold via passing through the molding compound and connecting between the first redistribution layer and the first interconnect structure; the first chip comprises a first back connection structure and a second back connection structure, a first transistor layer; a first front connection structure; and a first carrier on the first interconnect structure and coupled to the first interconnect structure. Therefore, the thick power supply / ground wire and the thin signal wire are separately arranged, and mutual interference possibly existing between power supply / ground transmission and signal transmission can be avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor packaging and semiconductor packaging assembly. Background Technology

[0002] To ensure the continued miniaturization and versatility of electronic products and communication equipment, semiconductor packages are expected to be small in size, support multi-pin connections, operate at high speeds, and offer high performance. This will put pressure on semiconductor package manufacturers, forcing them to develop high-density interconnects for signal routing and power delivery.

[0003] While existing semiconductor packages generally meet their intended uses, they are not satisfactory in all aspects. Therefore, a new type of semiconductor package is needed to improve signal integrity (SI), power integrity (PI), thermal conductivity, and voltage (IR) drop in high-density interconnects. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor package and semiconductor package assembly to improve signal integrity (SI), power integrity (PI), thermal conductivity and voltage drop (IR) in high-density interconnects, thereby enabling the semiconductor package and semiconductor package assembly to have better performance.

[0005] An embodiment of the present invention provides a semiconductor package, comprising: a first interconnect structure; a first chip disposed on and coupled to the first interconnect structure; a first redistribution layer disposed on and coupled to the first chip; a molding compound disposed on the first interconnect structure and encapsulating the first chip and the first redistribution layer; and a through-hole penetrating the molding compound and connecting the first redistribution layer and the first interconnect structure; wherein the first chip comprises: a first back-side connection structure coupled to the first interconnect structure; a first transistor layer located on the first back-side connection structure; a first front-side connection structure located on the first transistor layer; and a first carrier located on and coupled to the first interconnect structure.

[0006] Furthermore, the semiconductor package also includes a second redistribution layer disposed between the first carrier and the first redistribution layer. The second redistribution layer can further increase the flexibility and design adaptability of wiring and connections to suit different application scenarios.

[0007] Furthermore, the semiconductor package also includes a second interconnect structure located between the first interconnect structure and the first chip. The second interconnect structure can further increase the flexibility and design adaptability of wiring and connections to suit different application scenarios.

[0008] Furthermore, the through-hole is disposed around the first chip, thereby enabling signal transmission via an electrical connection path different from that of the first back-side connection structure.

[0009] Furthermore, the first rear connection structure is used for connecting to a power source or connecting to a power source and ground, or the first rear connection structure is used for connecting to a power source or connecting to a power source and ground, and is also used for signal transmission.

[0010] Furthermore, this first front-facing connection structure is used for signal transmission. This separates the thick power / ground wires from the thin signal wires, thus avoiding potential interference between power / ground transmission and signal transmission, and isolating the heat-generating power / ground transmission from the less heat-generating signal transmission to avoid negative impacts.

[0011] Furthermore, it also includes:

[0012] A second chip is disposed on and spaced apart from the first chip, wherein the second chip is encapsulated by molding compound. This allows for wireless transmission of signals using both the first and second chips.

[0013] Furthermore, the second chip is a transceiver chip. This allows for wireless transmission of signals using both the first and second chips.

[0014] Furthermore, it also includes a thermal interface material disposed between the first chip and the second chip. This can further improve heat dissipation efficiency and ensure the normal operation of the first chip and the second chip.

[0015] Furthermore, the second chip and the first chip are coupled via near-field coupling, which includes electrical coupling, magnetic coupling, and / or electromagnetic coupling. This allows for wireless signal transmission using both the first and second chips.

[0016] Furthermore, the semiconductor package also includes a third chip disposed on the second chip, and the third chip is coupled to the first redistribution layer. This allows for wireless transmission between the second chip and the third chip, and within both the second chip, to enable signal transmission for desired multi-chip applications.

[0017] Furthermore, the third chip includes:

[0018] The third back-side connection structure is connected to the first redistribution layer;

[0019] The third transistor layer is located on the third back-side connection structure;

[0020] A third front-side interconnect structure is located on the third transistor layer; and

[0021] The third carrier is located on the front connection structure. This allows for signal transmission and power / ground connection, and can also separate signal transmission and power / ground connection, improving performance.

[0022] Furthermore, the third chip is separated from the first chip by the molding compound, or the third chip is separated from the first chip by the molding compound and the thermal interface material, to improve heat dissipation.

[0023] Furthermore, the third chip and the second chip are coupled via near-field coupling, which includes electrical coupling, magnetic coupling, and / or electromagnetic coupling. This allows for wireless signal transmission using both the third and second chips.

[0024] Furthermore, the second chip is connected to the first redistribution layer through a first through-hole embedded in the molding compound, thereby providing power / ground and signal transmission paths for the second chip.

[0025] Furthermore, the first carrier is located close to the first interconnect structure, and the first back-side connection structure is located close to and connected to the first redistribution layer. Thus, the first back-side connection structure and the first front-side connection structure are respectively positioned on opposite sides of the first chip, arranged separately.

[0026] Furthermore, the first carrier includes a via that passes through the first carrier and connects the first front-side connection structure and the first interconnect structure. The via may be a through-silicon via (TSV) for electrical connection.

[0027] Furthermore, it also includes:

[0028] A second chip is disposed between the first interconnect structure and the first chip, the second chip being spaced apart from the first chip by the molding compound, and the first carrier being located above the second chip.

[0029] An embodiment of the present invention provides a semiconductor packaging assembly, comprising: a base; and a semiconductor package mounted on the base, wherein the semiconductor package includes: a first interconnect structure; a first chip disposed on and coupled to the first interconnect structure; a first redistribution layer disposed on and coupled to the first chip; a molding compound disposed on the first interconnect structure and encapsulating the first chip and the first redistribution layer; and a through-hole penetrating the molding compound and connecting between the first redistribution layer and the first interconnect structure, wherein the first chip includes: a first back-side connection structure connected to the first interconnect structure; a first transistor layer located on the first back-side connection structure; a first front-side connection structure located on the first transistor layer; and a first carrier located on the first front-side connection structure and coupled to the first interconnect structure; wherein the first back-side connection structure is close to the first interconnect structure, and the first carrier is close to and coupled to the first redistribution layer, or the first carrier is close to the first interconnect structure, and the first back-side connection structure is close to and coupled to the first redistribution layer.

[0030] Furthermore, the semiconductor package assembly also includes a thermal via that passes through the molding compound of the semiconductor package and connects to the first interconnect structure and the heat sink of the semiconductor package. This thermal via further improves heat dissipation efficiency.

[0031] The semiconductor package of the present invention includes: a first interconnect structure; a first chip disposed on and coupled to the first interconnect structure; a first redistribution layer disposed on and coupled to the first chip; a molding compound disposed on the first interconnect structure and encapsulating the first chip and the first redistribution layer; and a through-hole penetrating the molding compound and connecting the first redistribution layer and the first interconnect structure; wherein the first chip includes: a first back-side connection structure coupled to the first interconnect structure; a first transistor layer located on the first back-side connection structure; a first front-side connection structure located on the first transistor layer; and a first carrier located on and coupled to the first interconnect structure. Using the above scheme, the first chip can transmit power and ground through the first back-side connection structure, and the first chip can also transmit signals through the first front-side connection structure, thereby separating the thick power / ground lines from the thin signal lines. This avoids potential mutual interference between power / ground transmission and signal transmission, and separates the power / ground transmission, which generates more heat, from the signal transmission, which generates less heat, thus avoiding negative impacts. This improves signal integrity (SI), power integrity (PI), thermal conductivity, and voltage drop (IR) in semiconductor packaging and related structures, resulting in better performance of semiconductor packaging and semiconductor packaging assembly. Attached Figure Description

[0032] Figure 1 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0033] Figure 2 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0034] Figure 3 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0035] Figure 4 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0036] Figure 5 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0037] Figure 6 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0038] Figure 7 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0039] Figure 8 It includes some embodiments of the present invention. Figure 1 A schematic cross-sectional view of a semiconductor package assembly;

[0040] Figure 9 It includes some embodiments of the present invention. Figure 2 A schematic cross-sectional view of a semiconductor package assembly;

[0041] Figure 10 It includes some embodiments of the present invention. Figure 3 A schematic cross-sectional view of a semiconductor package assembly;

[0042] Figure 11 It includes some embodiments of the present invention. Figure 4 A schematic cross-sectional view of a semiconductor package assembly;

[0043] Figure 12 It includes some embodiments of the present invention. Figure 5 A schematic cross-sectional view of a semiconductor package assembly;

[0044] Figure 13 It includes some embodiments of the present invention. Figure 6 A schematic cross-sectional view of a semiconductor package assembly;

[0045] Figure 14 It includes some embodiments of the present invention. Figure 7 A schematic cross-sectional view of a semiconductor package assembly;

[0046] Figure 15 It includes some embodiments of the present invention. Figure 1 A schematic cross-sectional view of a semiconductor package assembly;

[0047] Figure 16 It includes some embodiments of the present invention. Figure 2 A schematic cross-sectional view of a semiconductor package assembly;

[0048] Figure 17 It includes some embodiments of the present invention. Figure 3 A schematic cross-sectional view of a semiconductor package assembly;

[0049] Figure 18 It includes some embodiments of the present invention. Figure 4 A schematic cross-sectional view of a semiconductor package assembly;

[0050] Figure 19 It includes some embodiments of the present invention. Figure 5 A schematic cross-sectional view of a semiconductor package assembly;

[0051] Figure 20 It includes some embodiments of the present invention. Figure 6 A schematic cross-sectional view of a semiconductor package assembly; and

[0052] Figure 21 It includes some embodiments of the present invention. Figure 7 A schematic cross-sectional view of a semiconductor package assembly. Detailed Implementation

[0053] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by reference to the appended claims. In embodiments of the invention, when an element or layer is referred to as being “located,” “connected to,” or “coupled to” another element or layer, it may be directly located, connected to, or coupled to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly located,” “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers. The same numbers always refer to the same element. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. “Directly above” or “directly below” may indicate that the projections of two or more of them at least partially overlap, while “not directly above” or “directly below” may indicate that the projections of two or more of them do not overlap at all.

[0054] Advanced integrated circuit (IC) devices are becoming increasingly feature-rich and their sizes are shrinking. While size reduction processes generally improve manufacturing efficiency and reduce associated costs, they also increase the complexity of IC device fabrication. For example, back-side power delivery network (BSPDN) technology is used to reduce the coupling between signal I / O (input / output) and power / ground in front-side routing, thereby reducing back-end line (BEOL) capacitance and voltage drop, and thus improving IC performance. While existing IC devices are generally adequate, they are not perfect in every aspect. For example, signal traces competing with the BSPDN for space on the back side of the chip (represented as traces in the illustrations of this invention), a situation also present in current front-side power delivery networks (FSPDNs). Furthermore, competition and contention between signal integrity (SI), power integrity (PI), and thermal conductivity in the back-side BSPDN can lead to degraded SI and PI performance in the chip, package, and printed circuit board (PCB). Furthermore, signal traces are located on the front side of the chip, and the BSPDN is preferentially facing downwards towards the PCB, which can easily lead to signal instability (SI). Therefore, further improvements to semiconductor packaging are needed to provide improved BSPDN signal design.

[0055] Figure 1This is a schematic cross-sectional view of a semiconductor package 500A according to some embodiments of the present invention. In some embodiments, the semiconductor package can be used to form a fan-out package, a two-dimensional (2D) package, a 2.5D package, a three-dimensional (3D) semiconductor package, or other suitable packages. In this embodiment, the semiconductor package 500A is a single fan-out chip package. The semiconductor package 500A can be mounted and coupled to a base 100. In some embodiments, the semiconductor package 500A includes a fan-out package, such as a system-on-chip (SOC) package. In some embodiments, the semiconductor package 500A may not include a base 100; that is, the base 100 is located outside the semiconductor package 500A. Figure 1 In the following figures, directions D10 and D12 are defined as horizontal directions (also considered as the extension direction of the conductive layer and / or conductive traces of the semiconductor package 500A), and direction D12 is defined as vertical direction (also considered as the extension direction of the vias and / or multiple vias of the semiconductor package 500A).

[0056] like Figure 1 As shown, the base 100, such as a printed circuit board (PCB), can be formed of polypropylene (PP), prepreg, FR-4, and / or other epoxy lamination materials. It should also be noted that the base 100 can be a single-layer or multi-layer structure. A plurality of pads 102 and / or conductive traces (not shown) are provided on the base 100. In one embodiment, the conductive traces may include signal trace segments or ground trace segments for input / output (I / O) connections of the semiconductor package 500A. Furthermore, the semiconductor package 500A is directly mounted on the conductive traces. In some other embodiments, the pads 102 are connected to different terminals of the conductive traces. The pads 102 are used for direct mounting of the semiconductor package 500A onto the pads 102.

[0057] like Figure 1 As shown, the semiconductor package 500A is mounted on the substrate 100 via bonding and / or reflow soldering processes. The semiconductor package 500A is mounted on the substrate 100 via a conductive structure 252. In some embodiments, the semiconductor package 500A is a fan-out semiconductor package, including a first interconnect structure 200, a first chip 300A, a first redistribution layer 230, a molding compound 412, a through mold via (TMV) TMV1 (or through-mold via), and the conductive structure 252.

[0058] A conductive structure 252 is disposed on the first interconnect structure 200, opposite to the first chip 300A. The conductive structure 252 contacts and is electrically connected (or coupled) to the first interconnect structure 200. Furthermore, the conductive structure 252 is electrically connected (or coupled) to the pad 102 of the base 100. In some embodiments, the conductive structure 252 includes a conductive ball structure (e.g., solder ball) or a conductive structure (e.g., copper bump or solder bump). For example, the conductive structure 252 may be a controlled collapse chip connection (C4) structure. In some embodiments, each conductive structure 252 may include an under bump metallurgy (UBM) layer and a conductive ball structure located on the UBM layer.

[0059] In some embodiments, the first interconnect structure 200 includes a substrate, a redistribution layer (RDL), or an interposer. In some embodiments, the interposer includes a glass interposer, a semiconductor (e.g., silicon) interposer, or an organic interposer. In some embodiments, the first interconnect structure 200 includes one or more conductive traces 202, one or more vias 204 disposed in one or more dielectric layers 206, and contact pads 208.

[0060] In some embodiments, the first interconnect structure 200 further includes a through-via (TV) TV1 passing through the first interconnect structure 200. For example... Figure 1 As shown, vias TV1 can be located near the edge 200E of the first interconnect structure 200, or they (vias TV1) can be located away from the edge 200E of the first interconnect structure 200. In such a way... Figure 1 In the cross-sectional view shown, conductive trace 202, via 204 and contact pad 208 are located between via TV1 near the opposite edge 200E of the first interconnect structure 200.

[0061] In some embodiments, the conductive trace 202, via 204, contact pad 208, and through-hole TV1 are all made of conductive material, such as copper, gold, silver, or other suitable metals. The dielectric layer 206 may include an extra-low K (ELK) dielectric and / or an ultra-low K (ULK) dielectric. It should be noted that... Figure 1 The number of conductive traces 202, vias 204, contact pads 208, through-holes TV1, and dielectric layers 206 shown are merely examples and are not intended to limit the scope of this invention.

[0062] In some embodiments, the semiconductor package 500A further includes a second interconnect structure 220 located between the first interconnect structure 200 and the first chip 300A. The second interconnect structure 220 is mounted and coupled to the first interconnect structure 200 using a conductive structure 262 via a bonding process. The conductive structures 252 and 262 may have the same or similar structures (e.g., conductive ball structures or conductive bumps). For example, the conductive structure 262 may include solder balls or microbumps. Furthermore, the dimensions (e.g., diameter) of the conductive structure 262 may be smaller than those of the conductive structure using the conductive structure 252.

[0063] The second interconnect structure 220 may partially cover the first interconnect structure 200 in the direction D12. Furthermore, the edge 220E of the second interconnect structure 220 is not flush with the corresponding edge 200E of the first interconnect structure 200.

[0064] The first interconnect structure 210 and the second interconnect structure 220 may have the same or similar structures. In some embodiments, the second interconnect structure 220 includes a substrate, a redistribution layer (RDL), or an interposer. In some embodiments, the second interconnect structure 220 includes one or more conductive traces 222, one or more vias 224 disposed in one or more dielectric layers 226, contact pads 228, and vias TV2. In some embodiments, the first interconnect structure 200 may be a substrate, while the second interconnect structure 220 may be an interposer. This configuration enhances the wiring flexibility and connectivity robustness of the semiconductor package.

[0065] In some embodiments, the materials of the conductive traces 222, vias 224, contact pads 228, and vias TV2 of the second interconnect structure 220 may be the same as or similar to the materials of the conductive traces 202, vias 204, contact pads 208, and vias TV1 of the first interconnect structure 200. In some embodiments, the material of the dielectric layer 226 of the second interconnect structure 220 may be the same as or similar to the material of the dielectric layer 206 of the first interconnect structure 200. In some embodiments, the dimensions (e.g., the linewidth of the conductive trace, the diameter of the via, or the size of the contact pad) of the conductive traces 222, vias 224, contact pads 228, and vias TV2 of the second interconnect structure 220 may be smaller than the dimensions of the first interconnect structure 200. The traces 202, vias 204, contact pads 208, and vias TV1 of the first interconnect structure 200.

[0066] It is important to note that Figure 1 The number of conductive traces 222, vias 224, contact pads 228, through-holes TV2, and dielectric layers 226 shown are merely examples and are not intended to limit the scope of this invention.

[0067] A first chip 300A is disposed above a first interconnect structure 200 and a second interconnect structure 220. The first chip 300A is mounted on and coupled to the second interconnect structure 220 using a conductive structure 272 via a bonding (or joining) process. Conductive structures 262 and 272 may have the same or similar structures (e.g., conductive bumps). For example, conductive structure 272 may include microbumps. Furthermore, the dimensions (e.g., diameter) of conductive structure 272 may be smaller than that of conductive structure 262. The first chip 300A is coupled to the first interconnect structure 200 via the second interconnect structure 220 and conductive structures 262 and 272.

[0068] In some embodiments, the first chip 300A includes a system-on-a-chip (SoC) chip, logic devices, memory devices, radio frequency (RF) devices, or any combination thereof. For example, the first chip 300A may include a micro control unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a radio frequency front end (RFFE) chip, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input-output (I / O) chip, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM) chip, a high bandwidth memory (HBM) chip, an application processor (AP) chip, an application-specific integrated circuit (ASIC) chip, or any combination thereof.

[0069] In some embodiments, the first chip 300A employs back-side power technology and can be fabricated using semiconductor nodes such as gate-all-around (GAA) technology. In some embodiments, the first chip 300A includes, from bottom to top, a first back-side interconnect structure 320, a first transistor layer 310, a first front-side interconnect structure 330, and a first carrier C1A.

[0070] The first transistor layer 310 includes a semiconductor substrate (or semiconductor base plate) (not shown) and at least one transistor (not shown) formed on the semiconductor substrate (or base plate). In some other embodiments, the first transistor layer 310 may include other active or passive elements formed on the semiconductor substrate.

[0071] A first back-side connection structure 320 is formed on the back side 310B of the first transistor layer 310. In other words, the first transistor layer 310 is located on the first back-side connection structure 320. The first back-side connection structure 320 is connected and coupled to the first interconnect structure 200 through the second interconnect structure 220 and conductive structures 262, 272. The first back-side connection structure 320 is connected and coupled to the first transistor layer 310 through a TV (via) (not shown) through the semiconductor substrate.

[0072] In some embodiments, the first back-side connection structure 320 may include multiple dielectric layers and conductive wiring (including power wiring and ground wiring) formed in the multiple dielectric layers. The conductive wiring, including conductive lines and vias (not shown), may be formed of copper or a copper alloy and may be formed using one or more damascene processes. The dielectric layers may include inter-layer dielectrics (ILDs) and inter-metal dielectrics (IMDs).

[0073] In some embodiments, the first back-side connection structure 320 is used to connect a power supply (not shown) and / or a ground (not shown). Alternatively, the first back-side connection structure 320 is used to connect a power supply (not shown) and / or a ground (not shown), and also for signal transmission. For example, the first back-side connection structure 320 may include power wiring (e.g., power wiring 320P) and ground wiring (not shown). Alternatively, the first back-side connection structure 320 may include power wiring (e.g., power wiring 320P), ground wiring (not shown), and signal wiring (not shown).

[0074] The first front-side connection structure 330 is located on the front side 310T of the first transistor layer 310 and is opposite to the first back-side connection structure 320. The first front-side connection structure 330 and the first back-side connection structure 320 are separated by the first transistor layer 310.

[0075] In some embodiments, the first front connection structure 330 may be similar to the first back connection structure 320 and includes multiple dielectric layers and conductive wiring formed in the multiple dielectric layers. The number of dielectric layers in the first front connection structure 330 and the first back connection structure 320 may be the same or different.

[0076] In some embodiments, the first front-side connection structure 330 may include only signal wiring 330S. The signal wiring 330S is used to transmit data signals, control signals, and other user signals.

[0077] like Figure 1 As shown, the first carrier C1A is located on and coupled to the first front-side connection structure 330. Furthermore, the first carrier C1A and the first transistor layer 310 are in contact with opposite sides of the first front-side connection structure 330. In some embodiments, the first carrier C1A is a silicon wafer carrier. In some embodiments, the first carrier C1A includes a through-hole (TV) TV3 that passes through the first carrier C1A and connects between the first front-side connection structure 330 and the first RDL 230.

[0078] like Figure 1 As shown, the first RDL 230 is arranged on / and coupled to the first chip 300A. In some embodiments, the first interconnect structure 200, the second interconnect structure 220 and the first RDL 230 may have the same or similar structures.

[0079] The first RDL 230 may partially or completely cover the first interconnect structure 200, the second interconnect structure 220, and the first chip 300A in direction D12. In some embodiments where the first RDL 230 partially covers the first interconnect structure 200, the edge R1E of the first RDL 230 is not flush with the corresponding edge 200E of the first interconnect structure 200. In some embodiments where the first RDL 230 completely covers the first interconnect structure 200, the edge R1E of the first RDL 230 is flush with the corresponding edge 200E of the first interconnect structure 200.

[0080] In some embodiments, the first RDL 230 includes one or more conductive traces 232 and one or more vias 234 disposed in one or more dielectric layers 236.

[0081] In some embodiments, the materials of the conductive traces 232 and vias 234 of the first RDL 230 may be the same as those of the conductive traces 202, vias 204, contact pads 208, and vias TV1 of the first interconnect structure 200, and the conductive traces 222, vias 224, contact pads 228, and vias TV2 of the second interconnect structure 220. In some embodiments, the material of the dielectric layer 236 of the first RDL 230 may be the same as or similar to the material of the dielectric layer 206 of the first interconnect structure 200 and the dielectric layer 226 of the second interconnect structure 220. It should be noted that... Figure 1 The number of conductive traces 232, vias 234, and dielectric layers 236 shown are merely examples and do not limit the scope of the invention.

[0082] like Figure 1 As shown, the first back-side connection structure 320 of the first chip 300A of the semiconductor package 500A is close to the first interconnect structure 200, and the first carrier C1A of the first chip 300A of the semiconductor package 500A is close to and coupled to the first RDL 230.

[0083] Optionally, the semiconductor package 500A may further include a second RDL 240 disposed between the first carrier C1A and the first RDL 230 along direction D12. Optionally, the second RDL 240 may be mounted on the first carrier C1A using a conductive structure 282 via a bonding (bonding) process. In some embodiments, conductive structures 272 and 282 may have the same or similar structures (e.g., conductive bumps) and dimensions (e.g., diameter). For example, conductive structure 272 may include microbumps. Alternatively, conductive structure 282 may include conductive pads (solder pads).

[0084] In some embodiments, the second RDL 240 includes one or more conductive traces 242 and one or more vias 244 disposed in one or more dielectric layers 246.

[0085] In some embodiments, the materials of the conductive traces 242 and vias 244 of the second RDL 240 may be the same as or similar to the materials of the conductive traces 202, vias 204, contact pads 208 and vias TV1 of the first interconnect structure 200, the conductive traces 222, vias 224, contact pads 228 and vias TV2 of the second interconnect structure 220, and the conductive traces 232 and vias 234 of the first RDL 230. In some embodiments, the material of the dielectric layer 246 of the second RDL 240 may be the same as or similar to the material of the first RDL 230. The dielectric layer 206 of the first interconnect structure 200, the dielectric layer 226 of the second interconnect structure 220, and the dielectric layer 236 of the first RDL 230. It should be noted that... Figure 1The number of conductive traces 242, vias 244, and dielectric layers 246 shown are merely examples and do not limit the scope of the invention.

[0086] In some embodiments, the edge R2E of the second RDL 240 is not flush with the corresponding edge R2E of the first RDL 230. In some embodiments, the edge R2E of the second RDL 240 may be flush with the corresponding edge 300AE of the first chip 300A or the corresponding edge 220E of the second interconnect structure 220.

[0087] Molding plastic 412 is disposed on the first interconnect structure 200 and encapsulates the first chip 300A and the first RDL 230. For example... Figure 1 As shown, molding compound 412 is disposed on the first interconnect structure 200. Furthermore, molding compound 412 surrounds and contacts the first chip 300A, the second interconnect structure 220, and an optional second RDL 240. Edges 200E of the first interconnect structure 200 can be exposed from the molding compound 412. In some embodiments, the upper surface 412T of the molding compound 412 can form the upper surface of the semiconductor package 500A. Edges 412E of the molding compound 412 can form the edges of the semiconductor package 500A.

[0088] In some embodiments, molding compound 412 may be formed of a non-conductive material, such as epoxy resin, resin, moldable polymer, etc. Molding compound 412 may be applied in a substantially liquid state and then cured by a chemical reaction (e.g., in an epoxy resin or resin). In some other embodiments, molding compound 412 may be an ultraviolet (UV) or thermosetting polymer, applied in the form of a gel or plastic solid, capable of being disposed around the first chip 300A, the second interconnect structure 220, the first RDL 230, and optionally the second RDL 240, and then cured using an UV or thermosetting process. Molding compound 412 may be cured using a mold (not shown).

[0089] like Figure 1 As shown, a through-hole (TMV) TMV1 passes through the molding compound 412 between the first RDL 230 and the first interconnect structure 200. Furthermore, the through-hole TMV1 connects and couples between the first RDL 230 and the first interconnect structure 200. For example, the two ends of the through-hole TMV1 are coupled to the through-hole TV1 of the first interconnect structure 200 and the conductive trace 232 of the first interconnect structure 200, respectively.

[0090] In some embodiments, the through-hole TMV1 is disposed near the edge (e.g., edge 412E) of the semiconductor package 500A. For example, the through-hole TMV1 may surround the first chip 300A, the second interconnect structure 220, and the optional second RDL 240.

[0091] In this embodiment, the through-hole TMV1 can be used as a signal through-hole for transmitting data signals, control signals and other user signals of the first chip 300A.

[0092] In this invention, the first chip 300A can be connected for power transmission and grounding via the first back-side connection structure 320, and the first chip 300A can also be connected for signal transmission via the first front-side connection structure 330. This separates the thick power / ground lines from the thin signal lines, avoiding potential interference between power / ground transmission and signal transmission, and isolating the heat-generating power / ground transmission from the less heat-generating signal transmission to avoid negative impacts. This improves signal integrity (SI), power integrity (PI), thermal conductivity, and voltage drop (IR) in the semiconductor package and related structures, resulting in better performance of the semiconductor package and semiconductor package assembly. In some embodiments, if there are special requirements, some signal lines can also be connected and transmitted via the first back-side connection structure 320 to adapt to actual needs.

[0093] Figure 2 This is a schematic cross-sectional view of a semiconductor package 500B according to some embodiments of the present invention. For the sake of brevity, it is similar to the previous reference. Figure 1 Elements described in the same or similar embodiments will not be repeated here. Figure 1 and Figure 2 As shown, the difference between semiconductor package 500A and semiconductor package 500B is at least that: the first chip 300A of semiconductor package 500B is disposed above / on the first interconnect structure 200, while there is no second interconnect structure 220 between the first chip 300A and the first interconnect structure 200. Figure 1 ).

[0094] like Figure 2 As shown, the conductive structure 272 of the semiconductor package 500B is directly connected (or coupled) between the first chip 300A and the first interconnect structure 200 and is in contact with the first chip 300A and the first interconnect structure 200. The package structure of the semiconductor package 500B can be a chip-substrate-PCB (for example, the first chip 300A is disposed on the first interconnect structure 200, and the first interconnect structure 200 is disposed on the base 100).

[0095] Semiconductor packages 500A and 500B offer the following advantages. In semiconductor packages 500A and 500B, the first chip 300A, having a rear-side power delivery network (BSPDN) (e.g., rear-side connection structure 320), can arrange signals in a front-side (FS) back-end ofline (BEOL) (e.g., front-side connection structure 330) separate from the BSPDN (e.g., rear-side connection structure 320), while power and ground wiring are located on the back-side (BS) of the BSPDN (e.g., rear-side connection structure 320). Signal wiring can be coupled to the first RDL 230 via wired communication (including vias (e.g., vias TV1, TV2), redistribution layers (e.g., the first RDL 230 and the second RDL 240), and through-mold vias (e.g., through-mold via TMV1) in epoxy molding compound (EMC) (e.g., molding compound 412) and fan-out wafer / panel level packages (FOW / PLP) (e.g., semiconductor packages 500A and 500B)).

[0096] In some embodiments, the packaging structure of semiconductor package 500A can be a chip-intermediate-substrate-PCB structure (e.g., a first chip 300A is disposed on a second interconnect structure 220, the second interconnect structure 220 is disposed on a first interconnect structure 200, and the first interconnect structure 200 is disposed on a base 100). The packaging structure of semiconductor package 500B can be a chip-substrate-PCB structure (e.g., a first chip 300A disposed on a first interconnect structure 200 on a base 100).

[0097] Compared to the signal input / output (I / O) in a conventional front-side power delivery network (FSPDN), the signal integrity (SI) in the FS-BEOL of the first chip 300A of the semiconductor packages 500A and 500B can be relaxed because the signal is completely separated from the power / ground and directly input / outputs upwards to the FOW / PLP level and multilayer RDLs (e.g., first RDL 230 and second RDL 240) and TMVs (e.g., through-hole TMV1). The width, thickness, and gaps of the multilayer RDLs (e.g., first RDL 230 and second RDL 240) and TMVs (e.g., through-hole TMV1) are increased, and the signal is not close to the power rail.

[0098] In semiconductor packages 500A and 500B, the first chip 300A of the BS (e.g., back-side connection structure 320) can be relaxed because all areas and layers are dedicated to reducing power and ground rails in the BSPDN (e.g., back-side connection structure 320), reducing signal isolation design and congestion, optimizing inductance and PI, and increasing the flexibility of power delivery design.

[0099] In semiconductor packages 500A and 500B, the FS-BEOL (e.g., front-side connection structure 330) of the first chip 300A facing upwards allows for 3D stacking with another BSPDN chip facing downwards. Alternatively, semiconductor packages 500A and 500B may allow multiple BSPDN chips to be stacked on top of each other in an FS-to-FS, FS-to-BS, or BS-to-BS configuration.

[0100] In semiconductor packages 500A and 500B, the back side (BS) of the first chip 300A (e.g., back side connection structure 320) can be used solely for power transmission and grounding, while the front side (FS) (e.g., front side connection structure 330) can be used solely for signal transmission, thereby decoupling the thick power / ground lines (e.g., power wiring 320P) from the thin signal lines (e.g., signal wiring 330S) (i.e., arranged separately, not on the same side or in the same manufacturing cell). Alternatively, the back side (BS) of the first chip 300A can also be used for power transmission, grounding, and signal transmission, while the front side (FS) of the first chip 300A is used solely for signal transmission.

[0101] In some embodiments, semiconductor packages 500A and 500B have through-holes (e.g., through-hole TV3) in a carrier (e.g., first carrier C1A), exposing the I / O (e.g., conductive structure 282) of a first chip 300A dedicated to signal transmission on the top of the carrier. A back-side connection structure (e.g., back-side connection structure 320) is used for connecting power and / or ground, and may also be used for signal transmission. A front-side connection structure (e.g., front-side connection structure 330) is used only for signal transmission.

[0102] In semiconductor packages 500A and 500B, the I / O (e.g., conductive structure 282) supporting upward signal transmission in the first chip 300A can take the form of pads or bumps, depending on whether a chip-first or chip-later process is used, and the number of FOW (fan out wafer) or PLP (panel level package) units.

[0103] Compared to a pure silicon carrier, vias (e.g., via TV3) in the carrier (e.g., the first carrier C1A) of semiconductor packages 500A and 500B can improve the effective thermal conductivity of the chip (e.g., the first chip 300A), thereby improving the thermal performance of semiconductor packages 500A and 500B.

[0104] In semiconductor packages 500A and 500B, since both the upper and lower surfaces of the chip (rather than one side of the chip) are used for signal I / O and power / ground (P / G), the bump pitch of the chip (e.g., the pitch of conductive structures 272 and 282) can be relaxed.

[0105] Figure 3 This is a schematic cross-sectional view of a semiconductor package 500C according to some embodiments of the present invention. For the sake of brevity, it is similar to the previous reference. Figure 1 Elements identical or similar to those described in the embodiments will not be repeated here. Figure 1 and Figure 2 As shown, the difference between semiconductor package 500B and semiconductor package 500C is at least that semiconductor package 500C also includes a second chip 340A.

[0106] like Figure 3 As shown, a second chip 340A of semiconductor package 500C is disposed above the first chip 300B. The second chip 340A and the first chip 300B are separated by molding compound 412. A first redistribution layer (RDL) 230 is disposed above and coupled to the second chip 340A. Molding compound 412 is disposed on the first interconnect structure 200 and encapsulates the first chip 300B, the second chip 340A, and the first RDL 230.

[0107] Optionally, the semiconductor package 500B may further include a second RDL 240 disposed between the second chip 340A and the first RDL 230 along direction D12. Optionally, the second RDL 240 may be directly disposed on the second chip 340A without the use of conductive structures, such as solder balls.

[0108] In some embodiments, the first chip 300B applied to the back-side power technology includes, from bottom to top, a first back-side connection structure 320, a first transistor layer 310, a first front-side connection structure 330, and a first carrier C1B.

[0109] In some embodiments, the second chip 340A includes a transceiver chip. Alternatively, the second chip 340A includes a logic chip, a memory chip, a radio frequency (RF) chip, and / or an analog chip with transceiver functionality.

[0110] In some embodiments, the second chip 340A and the first chip 300B are coupled to each other via near-field coupling. Near-field coupling may include electrical coupling, magnetic coupling, and / or electromagnetic coupling. Since the first chip 300B is coupled to the second chip 340A via near-field coupling, the first carrier C1B of the first chip 300B can be formed without a through-hole (TV).

[0111] like Figure 3As shown, a through-hole TMV1 is coupled between the first RDL 230 and the first interconnect structure 200. Furthermore, the through-hole (through-hole) TMV1 may surround the first chip 300A, the second chip 340A, and optionally the second chip 340A. In this embodiment, the through-hole TMV1 can be used as a signal via for transmitting data signals, control signals, and other user signals from the first chip 300B, and coupled to the second chip 340A. In some embodiments, the back face (BS) of the first chip 300B (e.g., back face connection structure 320) may be used purely (only) for power transmission and grounding, while the front face (FS) (e.g., front face connection structure 330) may be used purely (only) for signal transmission, thereby decoupling the thick power / ground lines (e.g., power wiring 320P) from the thin signal lines (e.g., signal wiring 330S) (i.e., arranged separately, not on the same side or in the same manufacturing unit). Signals can be transmitted to the second chip 340A via the front-side connection structure 330, and then via near-field coupling, subsequently to other components through the second RDL 240, the first RDL 230, vias (TMV1), and other paths. Power and ground connections of the second chip 340A can also be routed via the second RDL 240, the first RDL 230, and through-hole vias (TMV1), etc. In some embodiments, the BS of the first chip 300B can also be used for power transmission, grounding, and signal transmission, while the FS of the first chip 300B is used only for signal transmission. Signals can be transmitted to the second chip 340A via the front-side connection structure 330, and then via near-field coupling, subsequently to other components through the second RDL 240, the first RDL 230, through-hole vias (TMV1), and other paths. Power and ground connections of the second chip 340A can also be routed via the second RDL 240, the first RDL 230, and through-hole vias (TMV1), etc. The embodiments of this invention are applicable to scenarios requiring wireless transmission. The power / ground connection of the first chip 300B can be achieved through the first rear connection structure 320, while signal transmission can be achieved through the first front connection structure 330 (and wireless transmission to the second chip 340A). This separates the thick power / ground lines from the thin signal lines, avoiding potential interference between power / ground transmission and signal transmission, and isolating the heat-generating power / ground transmission from the less heat-generating signal transmission to prevent negative impacts. This improves signal integrity (SI), power integrity (PI), thermal conductivity, and voltage drop (IR) in the semiconductor package and related structures, resulting in better performance of the semiconductor package and assembly. In some embodiments, if there are special requirements, some signal lines can also be connected and transmitted through the first rear connection structure 320 to adapt to actual needs.The second chip 340A can communicate and transmit signals with the first chip 300B wirelessly. Therefore, a signal transmission path can be formed through the second chip 340A, the second RDL 240, the through-hole via (TMV1), and the first interconnect structure 200. Similarly, the power / ground transmission path for the second chip 340A can also be formed through the second RDL 240, the through-hole via (TMV1), and the first interconnect structure 200 to provide power / ground connections for the second chip 340A.

[0112] Figure 4 This is a schematic cross-sectional view of a semiconductor package 500D according to some embodiments of the present invention. For simplicity, it is consistent with previous references. Figures 1 to 3 Components that are identical or similar to those described will not be repeated here. Figure 3 and Figure 4 As shown, the difference between semiconductor package 500C and semiconductor package 500D is at least that semiconductor package 500D also includes thermal interface material (TIM) 250A.

[0113] like Figure 4 As shown, the second chip 340A is separated from the first chip 300B by molding compound 412 and thermally conductive interface material (TIM) 250A. TIM 250A is disposed between the first chip 300B and the second chip 340A along direction D12 to improve heat dissipation efficiency. Furthermore, TIM 250A is surrounded (or enclosed) by molding compound 412.

[0114] In some embodiments, the TIM 250A may comprise a metal or metal alloy, such as aluminum, copper, nickel, or cobalt. In some embodiments, the design of the TIM 250A (including its material selection, thickness, and positioning) must be co-optimized (co-designed) with the transceiver chip (e.g., the second chip 340A) to ensure proper operation of the transceiver chip and guarantee stable data transmission. Furthermore, the TIM 250A may comprise diamond, aluminum nitride, boron nitride, or other materials with high thermal conductivity. In some embodiments, the TIM 250A may be made of a non-metallic material, such as a polymer. This non-metallic TIM has a higher thermal conductivity than molding compound 412, thereby enabling faster heat dissipation.

[0115] Figure 5 This is a schematic cross-sectional view of a semiconductor package 500E according to some embodiments of the present invention. For the sake of brevity, it is similar to the previous reference. Figures 1 to 4 Elements described in the same or similar embodiments will not be repeated here. Figure 5As shown, the semiconductor package 500D includes a first interconnect structure 200, a first chip 300B, a second chip 340A, a third chip 350A, a first redistribution layer 230, a molding compound 412, a through-hole (TMV) TMV1, conductive structures 252, 272, and 292, and a through-hole V1. The first interconnect structure 200, the first chip 300B, the second chip 340A, the first redistribution layer 230, the molding compound 412, the through-hole (TMV) TMV1, and the conductive structures 252 and 272 are similar to those in the previous reference. Figures 1 to 4 For the sake of brevity, the same or similar semiconductor packages 500A to 500D will not be described again in this article.

[0116] like Figure 5 As shown, a third chip 350A is flipped and positioned above the second chip 340A. The third chip 350A is spaced apart from the first chip 300B by molding compound 412 and thermal interface materials (TIMs) 250B1 and 250B2. More specifically, the first chip 300B is spaced apart from the second chip 340A by molding compound 412, and the third chip 350A is spaced apart from the second chip 340A by molding compound 412 and thermal interface material (TIM) 250B1, and the third chip 350A is spaced apart from the second chip 340A by molding compound 412 and thermal interface material (TIM) 250B2. Furthermore, the third chip 350A is mounted on and coupled to the first RDL 230 using a conductive structure 292 via a bonding process. Conductive structures 272 and 292 may have the same or similar structure and dimensions (e.g., diameter).

[0117] In some embodiments, the third chip 350A and the second chip 340A are coupled to each other via near-field coupling. Near-field coupling may include electrical coupling, magnetic coupling, and / or electromagnetic coupling.

[0118] In some embodiments, the third chip 350A includes a system-on-a-chip (SoC) die, logic devices, memory devices, radio frequency (RF) devices, or any combination thereof. For example, the first semiconductor chip 128 and the second semiconductor chip 138 may each include a microcontroller unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a radio frequency front-end (RFFE) chip, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input / output (I / O) chip, a dynamic random access memory (DRAM) controller, a static random access memory (SRAM), a high-bandwidth memory (HBM), an application processor (AP) chip, an application-specific integrated circuit (ASIC) chip, or any combination thereof.

[0119] The first chip 300B and the third chip 350A may include the same or different devices. For example, the first chip 300A and the third chip 350A may include a SoC chip. Alternatively, the first chip 300A may include an SoC die, while the third chip 350A may include an HBM die. It should be noted that the three semiconductor dies are for illustrative purposes only, and more than three semiconductor dies and / or one or more passive components (e.g., resistors, capacitors, or inductors) may be disposed above / on the first redistribution layer 230 and / or the first RDL 230.

[0120] Similar to the first chip 300B, the third chip 350A also employs back-side power technology and is manufactured using a gate-around-all-aspects (GAA) process. From top to bottom, the third chip 350A includes a third back-side interconnect structure 370, a third transistor layer 360, a third front-side interconnect structure 380, and a third carrier C3A.

[0121] A third back-side connection structure 370 is connected to the first RDL 230. A third transistor layer 360 is located on the back-side connection structure 370. Furthermore, a third front-side connection structure 380 is located on the third transistor layer 360. Additionally, a third carrier C3A is located on the third front-side connection structure 380.

[0122] In some embodiments, the first chip 300B and the third chip 350A have the same or similar structures and materials. For example, the first back-side connection structure 320 and the third back-side connection structure 370 may have the same or similar structures and materials. The first transistor layer 310 and the third transistor layer 360 may have the same or similar structures and materials. The first front-side connection structure 330 and the third front-side connection structure 380 may have the same or similar structures and materials.

[0123] In some embodiments, the third chip 350A may completely or partially cover the first chip 300B. In some embodiments where the third chip 350A completely covers the first chip 300B, the edge 300BE of the first chip 300B is flush with the corresponding edge 350AE of the third chip 350A. In some embodiments where the third chip 350A partially covers the first chip 300B, the edge 300BE of the first chip 300B is not flush with the corresponding edge 350AE of the third chip 350A.

[0124] In some embodiments, a third chip 350A may partially cover a second chip 340A in direction D12. The edge 340AE of the second chip 340A is not flush with the corresponding edge 330AE of the third chip 350A. Based on the size difference between the second chip 340A and the third chip 350A, the second chip 340A is connected and coupled to a first RDL 230 via a through-hole V1 embedded in the molding compound 412. In some embodiments, the through-hole V1 may pass along direction D12 through a portion of the molding compound 412 located between the first RDL 230 and the second chip 340A, as well as the first RDL 230 itself. Furthermore, the through-hole V1 may surround the first chip 300B and the thermal interface material (TIM) 250B2.

[0125] In some embodiments, via V1 can be used as a signal via for transmitting data signals, control signals, and other user signals from the first chip 300B and the third chip 350A, and coupled to the second chip 340A. In some embodiments, some via V1 can be used for transmitting signals between the second chip 340A and other components, and some via V1 can be used for power / ground connections of the second chip 340A.

[0126] like Figure 5 As shown, a through-hole TMV1 is coupled between the first RDL 230 and the first interconnect structure 200. Furthermore, the through-hole TMV1 may surround the first chip 300A, the second chip 340A, the third chip 350A, TIMs 250B1 and 250B2, and the through-hole V1. In this embodiment, a portion of the through-hole TMV1 can be used as a signal through-hole for transmitting data signals, control signals, and other user signals from the first chip 300B and the third chip 350A, and coupled to the second chip 340A. A portion of the through-hole TMV1 can also be used to transmit power to the third chip 350A. The through-hole TMV1 can also be used for power / ground connections and / or signal transmission for the second chip 340A.

[0127] Semiconductor packages 500C, 500D, and 500E offer the following advantages. In semiconductor packages 500C, 500D, and 500E, a first chip 300B (or a third chip 350A) having a rear-side power delivery network (BSPDN) (e.g., rear-side connection structure 320 or 370) can have signal routing arranged in the front-side (FS) back-end process (BEOL) (e.g., front-side connection structure 330 or 380), separating the front-side connection structure 330 or 380 from the back-side (BS) power and ground routing in the BSPDN (e.g., rear-side connection structure 320 or 370). The signal routing can be wirelessly coupled to a first RDL 230.

[0128] In some embodiments, the packaging structure of semiconductor packages 500C, 500D and 500E can be a chip-substrate-PCB structure (for example, the first chip 300B is disposed on the first interconnect structure 200 disposed on the substrate 100).

[0129] Compared to signal input / output (I / O) in traditional front-end power supply networks (FSPDNs), the signal integrity (SI) requirements in the FS-BEOL of the first chip 300B (or third chip 350A) of semiconductor packages 500C, 500D, and 500E can be relaxed because the signals are completely decoupled from power / ground and wirelessly input / output to the FOW / PLP level and multi-layer RDL (e.g., first RDL 230) and TMV (e.g., through-hole TMV1), with increased width, thickness, and gaps, and the signals are not close to the power rails.

[0130] In semiconductor packages 500C, 500D, and 500E, since all areas and layers are dedicated to the power and ground rails in the BSPDN (e.g., back connection structure 320 or 370), the power integrity (PI) requirements in the BS (e.g., back connection structure 320 or 370) of the first chip 300B (or the third chip 350A) of the semiconductor packages 500C, 500D, and 500E can be relaxed. This reduces isolation design and signal congestion, optimizes inductance and PI, and increases the flexibility of power delivery design.

[0131] In semiconductor packages 500C, 500D, and 500E, near-field coupled I / O in the FS-BEOL (e.g., front-side connection structure 330 or 380) of the first chip 300B (or the third chip 350A) does not require through-holes (TVs) in the carrier (e.g., carrier C1B or C3A) to display signal I / O.

[0132] In semiconductor packages 500C, 500D, and 500E, the near-field coupling between the second chip 340A and the first chip 300B in each semiconductor package 500C, 500D, and 500E, and the near-field coupling between the second chip 340A and the third chip 350A in semiconductor package 500E, includes electrical coupling (e.g., capacitive coupling), magnetic coupling (e.g., inductive coupling), or electromagnetic coupling (e.g., radiation coupling).

[0133] In semiconductor packages 500C and 500D, a transceiver (TRX) Si chip (e.g., second chip 340A) is packaged on top of a first chip 300B (or a third chip 350A) (e.g., carrier C1B or C3A), and the gap between the TRX Si chip and the carrier is filled with EMC (e.g., molding compound 412) or thermal interface material (TIM) (e.g., TIM 250A).

[0134] In semiconductor packages 500C, 500D, and 500E, the TRX Si chip (e.g., the second chip 340A) may include a dedicated TRX silicon (or other semiconductor material) bridge chip. Alternatively, the TRX Si chip may include a logic chip, a memory chip, a radio frequency (RF) chip, and / or an analog chip with transceiver functionality.

[0135] When a TRX Si chip (e.g., the second chip 340A) includes logic chips, memory chips, radio frequency (RF) chips, and / or analog chips with transceiver functionality, the TRX Si chip can transmit and receive more coupled signals than a single chip (whether or not it has BSPDN).

[0136] When a TRX Si chip (e.g., second chip 340A) contains logic chips, memory chips, radio frequency (RF) chips, and / or analog chips with transceiver functionality, the TRX Si chip can help dissipate heat laterally within the EMC (e.g., molding compound 412).

[0137] In semiconductor package 500E, 3D stacked BSPDN chips (e.g., first chip 300B and third chip 350A) are disposed in an EMC (e.g., molding compound 412) having FS-BEOL (e.g., front-side interconnect structure 330) and coupled to a TRX Si (silicon) chip (e.g., second chip 340A). The TRX Si (silicon) chip can act as a centralized signal collector and output terminal.

[0138] In semiconductor packages 500C, 500D, and 500E, the backside (BS) of the first chip 300B (or the third chip 350A) (e.g., backside connection structure 320 or 370) can be used for power and / or grounding, and also for signal transmission, while the FS-BEOL (e.g., frontside connection structure 320 or 370) can be used for signal transmission. External components of the first chip 300B (or the third chip 350A) (e.g., 330 or 380) are used only for signal transmission. This embodiment of the invention can be applied to scenarios requiring wireless transmission. The power / ground connection of the first chip 300B can be achieved through the first backside connection structure 320 for power transmission and grounding, and signal transmission can be achieved through the first frontside connection structure 330 (and wireless transmission to the second chip 340A). This separates the thick power / ground lines from the thin signal lines, avoiding potential mutual interference between power / ground transmission and signal transmission, and isolating the heat-generating power / ground transmission from the less heat-generating signal transmission to avoid negative impacts. This improves signal integrity (SI), power integrity (PI), thermal conductivity, and voltage drop (IR) in semiconductor packages and related structures, resulting in better performance of semiconductor packages and semiconductor package assemblies. In some embodiments, if there are special requirements, some signal lines can also be connected and transmitted through the first back-side connection structure 320 to suit actual needs. The power / ground connection of the third chip 350A can be connected via the back-side connection structure 370 for power transmission and grounding, and signal transmission can be performed via the front-side connection structure 380 (and wireless transmission to the second chip 340A), thereby separating the thick power / ground lines from the thin signal lines. This avoids potential mutual interference between power / ground transmission and signal transmission, and separates the power / ground transmission with higher heat generation from the signal transmission with lower heat generation, avoiding negative impacts. This improves signal integrity (SI), power integrity (PI), thermal conductivity, and voltage drop (IR) in semiconductor packages and related structures, resulting in better performance of semiconductor packages and semiconductor package assemblies. In some embodiments, if there are special requirements, some signal lines can also be connected and transmitted through the back-side connection structure 370 to suit actual needs. The second chip 340A can be used to connect and transmit signals with the first chip 300B via wireless signal transmission, and also to connect and transmit signals with the third chip 350A via wireless signal transmission. Therefore, in this embodiment, signal transmission can be carried out through the second chip 340A, and then transmitted through the through-hole V1 to RDL 230, through-hole TMV1, the first interconnect structure 200, the base 100, etc.This allows for further separation of the power / ground and signal transmission of the first chip 300B and the third chip 350A (separated to opposite sides of each chip), thereby improving signal integrity (SI), power integrity (PI), thermal conductivity, and voltage drop (IR) in the semiconductor package and related structures, resulting in better performance of the semiconductor package and semiconductor package assembly.

[0139] Figure 6 This is a schematic cross-sectional view of a semiconductor package 500F according to some embodiments of the present invention. For the sake of brevity, it is similar to the previous reference. Figures 1 to 5 Elements identical or similar to those described in the embodiments will not be repeated here. Figure 2 and Figure 6 As shown, the difference between semiconductor package 500B and semiconductor package 500F is at least that the composite structure including first chip 300A and optional second RDL 240 mounted on first chip 300A is flipped and disposed between first interconnect structure 200 and first RDL 230.

[0140] In semiconductor package 500F, the first chip 300A is connected and coupled to the first RDL 230 via conductive structure 372. Conductive structure 272 ( Figure 2 ) and 372 can have the same or similar structures. In addition, the dimensions (e.g., diameter) of conductive structure 372 can be smaller than or equal to those of conductive structure 262.

[0141] like Figure 6 As shown, the first chip 300A, from bottom to top, includes a first carrier C1A, a first front-side interconnect structure 330, a first transistor layer 310, and a first back-side interconnect structure 320. In this embodiment, the first carrier C1A of the first chip 300A is close to the first interconnect structure 200. The first back-side interconnect structure 320 of the first chip 300A is close to and coupled to the first RDL 230, such that the conductive structure 372 is connected and coupled between the first back-side interconnect structure 320 and the first RDL 230 of the first chip 300A. In some embodiments, the first carrier C1A includes a through-hole (TV) TV3 that penetrates the first carrier C1A and connects between the first front-side interconnect structure 330 and the first interconnect structure 200 for signal transmission of the first chip 300A.

[0142] like Figure 6As shown, the semiconductor package 500A may optionally include a second RDL 240, which is disposed along direction D12 between the first carrier C1A of the first chip 300A and the first interconnect structure 200. The second RDL 240 is mounted and coupled to the first interconnect structure 200 using a bonding process of conductive structure 362. Conductive structures 282 and 362 may have the same or similar structures. Furthermore, the dimensions (e.g., diameter) of conductive structure 362 may be less than or equal to those of conductive structure 372.

[0143] like Figure 6 As shown, the first chip 300A can optionally be mounted on the second RDL 240 using a bonding process with conductive structure 382. In some embodiments, conductive structures 362 and 382 may have the same or similar structure and dimensions (e.g., diameter). For example, conductive structure 382 may include conductive bumps or conductive pads.

[0144] like Figure 6 As shown, via TMV1 is coupled between the first RDL 230 and the first interconnect structure 200. Furthermore, via TMV1 may surround the first chip 300A and an optional second RDL 240. In this embodiment, via TMV1 can be used as a through-hole (TMV) for power delivery, for transmitting power to the first chip 300A.

[0145] The embodiments of this invention can be applied to different manufacturing needs, thereby improving the design flexibility and adaptability of the manufacturing process. The power / ground connection of the first chip 300A can be achieved through the first rear connection structure 320 for power transmission and grounding, and signal transmission can be achieved through the first front connection structure 330. This separates the thick power / ground lines from the thin signal lines, avoiding potential mutual interference between power / ground transmission and signal transmission, and isolating the heat-generating power / ground transmission from the less heat-generating signal transmission to avoid negative impacts. This improves signal integrity (SI), power integrity (PI), thermal conductivity, and voltage drop (IR) in the semiconductor package and related structures, resulting in better performance of the semiconductor package and semiconductor package assembly. In some embodiments, if there are special requirements, some signal lines can also be connected and transmitted through the first rear connection structure 320 to adapt to actual needs.

[0146] Figure 7 This is a schematic cross-sectional view of a 500G semiconductor package according to some embodiments of the present invention. For the sake of brevity, it is similar to the previous reference. Figures 1 to 5 Elements described in the same or similar embodiments will not be repeated here. Figure 4 and Figure 7As shown, the difference between semiconductor package 500D and semiconductor package 500G is at least that the composite structure comprising a first chip 300B, a second chip 340A, a thermal interface material (TIM) 250A and an optional second RDL 240 is flipped and disposed between the first interconnect structure 200 and the first RDL 230.

[0147] In the semiconductor package 500G, the first chip 300B is connected and coupled to the first RDL 230 via a conductive structure 372. Conductive structure 272 ( Figure 4 ) and 372 can have the same or similar structures. In addition, the dimensions (e.g., diameter) of conductive structure 372 can be smaller than or equal to those of conductive structure 262.

[0148] like Figure 7 As shown, the first chip 300B, from bottom to top, includes a first carrier C1B, a first front interconnect structure 330, a first transistor layer 310, and a first back interconnect structure 320. In this embodiment, the first carrier C1B of the first chip 300B is close to the first interconnect structure 200. The first back interconnect structure 320 of the first chip 300B is close to and coupled to the first RDL 230, such that the conductive structure 372 is connected and coupled between the first back interconnect structure 320 and the first RDL 230. The first chip 300B and the first RDL 230.

[0149] like Figure 7 As shown, a second chip 340A in a 500G semiconductor package is disposed between the first interconnect structure 200 and the first chip 300B. Furthermore, a first carrier C1B of the first chip 300B is located above the second chip 340A. Signals from the first chip 300B can be coupled to the second chip 340A and transmitted to the first interconnect structure 200.

[0150] Molding compound 412 is disposed on the first interconnect structure 200 and encapsulates the first chip 300B, the second chip 340A, the thermal interface material (TIM) 250A, and the first RDL 230. Therefore, the second chip 340A is spaced apart from the first chip 300B, the molding compound 412, and the thermal interface material (TIM) 250A.

[0151] like Figure 7 As shown, the semiconductor package 500G may optionally include a second RDL 240 disposed along direction D12 between the second chip 340A and the first interconnect structure 200. The second RDL 240 is mounted and coupled to the first interconnect structure 200 using a bonding process of conductive structure 362. Conductive structures 282 and 362 may have the same or similar structures. Furthermore, the dimensions (e.g., diameter) of conductive structure 362 may be less than or equal to those of conductive structure 372.

[0152] like Figure 7 As shown, the second chip 340A can be optionally mounted and coupled to the second RDL 240 via a bonding process using conductive structure 392. In some embodiments, conductive structures 362 and 392 may have the same or similar structure and dimensions (e.g., diameter). For example, conductive structure 392 may include conductive bumps or conductive pads.

[0153] like Figure 7 As shown, via TMV1 is coupled between the first RDL 230 and the first interconnect structure 200. Furthermore, via TMV1 may surround the first chip 300B, the second chip 340A, TIM 250A, and optionally the second RDL 240. In this embodiment, via TMV1 can also be used as a power via to transmit power to the first chip 300B.

[0154] Semiconductor packages 500F and 500G offer the following advantages. In semiconductor packages 500F and 500G, a first chip 300A with a rear-side power delivery network (BSPDN) (e.g., rear-side connection structure 320) can separate signal routing in the front (FS) back-end line (BEOL) (e.g., front-side connection structure 330) from rear-side (BS) power and ground routing in the BSPDN (e.g., rear-side connection structure 320). The signal routing can be coupled to the first RDL 230 via wired communication (including vias (e.g., vias TV1, TV3) and redistribution layers in epoxy molding compound (EMC) (e.g., molding compound 412) (e.g., second RDL 240) and fan-out wafer / panel level package (FOW / PLP) (e.g., semiconductor packages 500F and 500G)).

[0155] In some embodiments, the packaging structure of semiconductor packages 500F and 500G can be a chip-substrate-PCB structure (e.g., the first chip 300B is disposed on the first interconnect structure 200 on the base 100).

[0156] Compared to signal input / output (I / O) in a conventional front-side power supply network (FSPDN), signal integrity (SI) in FS-BEOL is significantly improved because signals are completely decoupled from power / ground and input / output directly or wirelessly to the interposer (e.g., first interconnect structure 200) and multilayer RDL (e.g., second RDL 240) and vias (whose width, thickness, and gap are proportionally increased, and signals are not close to the power rails). Therefore, the requirements for FS-BEOL (e.g., front-side interconnect structure 330) of the first chip 300A (or first chip 300B) of semiconductor packages 500F and 500G can be relaxed.

[0157] In semiconductor package 500G, the FS-BEOL (e.g., front-side interconnect structure 330) to interposer (e.g., first interconnect structure 200) architecture of the first chip 300B allows communication between the BSPDN chip (e.g., the first chip 300B) and other chips (e.g., the second chip 340A), without BSPDN technology on the interposer.

[0158] In semiconductor packages 500F and 500G, the FS-BEOL (e.g., front-side connection structure 330) of the first chip 300A (or the first chip 300B) faces down, allowing 3D stacking on another BSPDN chip with the FS facing up.

[0159] In semiconductor packages 500F and 500G, since all areas and layers are dedicated to the power and ground rails in the BSPDN (e.g., back connection structure 320), the power integrity (PI) requirements in the BS (e.g., back connection structure 320) of the first chip 300A (or the first chip 300B) can be relaxed. This reduces isolation design and signal congestion, optimizes inductance and PI, and increases power delivery design flexibility. The dimensions of the FOW / PLP RDL (e.g., first RDL 230 and second RDL 240) and vias can be equal to or larger than the arrangement of the third chip 350A on the inserter (e.g., first interconnect structure 200). This arrangement is the same as or similar to the first chip 300A in semiconductor packages 500F and 500G. Therefore, semiconductor package 500E can also combine the advantages of semiconductor packages 500F and 500G.

[0160] The embodiments of this invention are applicable to scenarios requiring wireless transmission. The power / ground connection of the first chip 300B can be achieved through the first back-side connection structure 320 (along with RDL 230, through-hole via (TMV1), first interconnect structure 200, etc.) for power transmission and grounding. Signal transmission can be achieved through the first front-side connection structure 330 (and wireless transmission to the second chip 340A), thus separating the thick power / ground lines from the thin signal lines. This avoids potential mutual interference between power / ground transmission and signal transmission, and separates the heat-generating power / ground transmission from the less heat-generating signal transmission, preventing negative impacts. This improves signal integrity (SI), power integrity (PI), thermal conductivity, and voltage drop (IR) in the semiconductor package and related structures, resulting in better performance of the semiconductor package and assembly. In some embodiments, if there are special requirements, some signal lines can also be connected and transmitted through the first back-side connection structure 320 to adapt to actual needs. The second chip 340A can communicate and transmit signals with the first chip 300B via a wireless connection. Therefore, a signal transmission path can be formed through the second chip 340A, the second RDL 240, and the first interconnect structure 200. Similarly, the power / ground transmission path for the second chip 340A can also be formed through the second RDL 240 and the first interconnect structure 200 to provide power / ground connections for the second chip 340A.

[0161] Figure 8 This includes some embodiments of the present invention. Figure 1 A schematic cross-sectional view of the semiconductor package assembly 600A of the semiconductor package 500A. For simplicity, referencing previous references... Figure 1 Elements described in the same or similar embodiments will not be repeated here. In some embodiments, the semiconductor package assembly 600A is a semiconductor package assembly including one or more fan-out packages, two-dimensional (2D) packages, 2, 5D packages, three-dimensional (3D) semiconductor packages, or other suitable packages.

[0162] In some embodiments, the semiconductor package assembly 600A includes at least a base 100 and a semiconductor package 500A mounted on the base 100 using a conductive structure 252.

[0163] In some embodiments, the semiconductor package 500A includes a first interconnect structure 200, a second interconnect structure 220, a first chip 300A, a first redistribution layer (RDL) 230, a second RDL 240, a molding compound 412, a through-hole via (TMV) TMV1, and conductive structures 262, 272, and 282. The first chip 300A is disposed above and coupled to the first interconnect structure 200. The first redistribution layer (RDL) 230 is disposed above and coupled to the chip. The molding compound 412 is disposed on the first interconnect structure 200 and covers the first chip 300A, the first RDL 230, and the second interconnect structure 220. The through-hole TMV1 passes through the molding compound 412 and connects between the first RDL 230 and the first interconnect structure 200. The first chip 300A includes a first back-side connection structure 320, a first transistor layer 310, a first front-side connection structure 330, and a first carrier C1A. The first back-side connection structure 320 is connected to the first interconnect structure 200 via conductive structure 272, second interconnect structure 220, and conductive structure 262. A first transistor layer 310 is located on the first back-side connection structure 320. A first front-side connection structure 330 is located on the first transistor layer 310. A first carrier C1A is located on the first front-side connection structure 330 and is coupled to the first redistribution layer 230 via a second RDL 240 and conductive structure 282.

[0164] In the semiconductor package 500A of the semiconductor package assembly 600A, the first back-side connection structure 320 is close to the first interconnect structure 200. Furthermore, the first carrier C1A is close to and coupled to the first RDL 230.

[0165] In some embodiments, the semiconductor package assembly 600A may further include a heat sink 420 mounted on the semiconductor package 500A. For example... Figure 8 As shown, a heat sink 420 is disposed on the upper surface 412T of the molding compound 412. The heat sink 420 can completely cover the upper surface 412T of the molding compound 412 to enhance the heat dissipation capability of the semiconductor package assembly 600A. In some embodiments, the heat sink 420 can be mounted on the upper surface 412T of the molding compound 412 using a thermal interface material (TIM) 450 to further improve heat dissipation efficiency and accelerate heat dissipation. In some embodiments, TIMs 250A, 250B1, 250B2, and 450 can contain the same or similar materials.

[0166] In some embodiments, the heat sink 420 may include at least one protrusion 420-P. The protrusion 420-P extends upward from the upper surface 420T of the heat sink 420. In some embodiments, the fin-shaped protrusion 420-P may increase the surface area of ​​the heat sink 420, thereby further improving the heat dissipation capability of the semiconductor package assembly 600A.

[0167] In some embodiments, the semiconductor package assembly 600A may also include a thermal through mold via (TMV) 2. The thermal through mold via (or thermal via) 2 helps dissipate heat generated by the semiconductor package 500A to the external environment of the semiconductor package assembly 600A. Figure 8 As shown, a thermal through-hole TMV2 can pass through the molding compound 412 of the semiconductor package 500A along direction D12. In some embodiments, the thermal through-hole TMV2 can be connected to a through-hole TV4 of the first interconnect structure 200 of the semiconductor package 500A and the heat sink 420. In the first interconnect structure 200, the through-hole TV4 connected to the thermal through-hole TMV2 can be isolated from the through-hole TV1 connected to the through-hole TMV1. Furthermore, the thermal through-hole TMV2 can be connected to the heat sink 420 through a thermal interface material (TIM) 450. In some embodiments, the thermal through-hole TMV2 is arranged around the through-hole TMV1 (e.g., signal and / or power through-hole) of the first chip 300A and the semiconductor package 500A.

[0168] In some embodiments, the heat-permeable die through-hole TMV2 and TIM 450 may comprise a high thermal conductivity material, such as copper, diamond, aluminum nitride, boron nitride, or other suitable high thermal conductivity materials. In some embodiments, the through-hole TMV1 and the heat-permeable die through-hole TMV2 comprise different materials.

[0169] In some embodiments, the semiconductor package assembly 600A can provide a heat dissipation path for the semiconductor package 500A. Heat generated by the semiconductor package 500A can be dissipated through the first interconnect structure 200, the second interconnect structure 220, conductive structures 252, 262, 272, thermal via TMV2, TIM 450, and heat sink 420. The thermal via TMV2, TIM 450, and heat sink 420 can improve the efficiency of heat dissipation from the semiconductor package 500A to the external environment of the semiconductor package assembly 600A.

[0170] In some embodiments, the semiconductor package assembly 600A may further include a voltage regulator 430A disposed in the molding compound 412 of the semiconductor package. The voltage regulator 430A may be disposed on the first interconnect structure 200 and coupled to a via TV5 of the first interconnect structure 200 of the semiconductor package 500A. In the first interconnect structure 200, the via TV5 connected to the voltage regulator 430A may be isolated from the via TV1 connected to the through-mold via TMV1. In some embodiments, the via TV1 connected to the through-mold via TMV1 and the via TV5 connected to the voltage regulator 430A are different vias located within the first interconnect structure 200. Furthermore, vias TV1 and TV5 may be electrically connected or disconnected as needed. Additionally, the voltage regulator 430A may be connected to the first chip 300A via the first interconnect structure 200 and the second interconnect structure 220. Furthermore, the voltage regulator 430A may be connected to the base 100. In some embodiments, the voltage regulator 430A may be used to provide a stable voltage to circuitry in the semiconductor package assembly 600A.

[0171] In some embodiments, the semiconductor package assembly 600A may further include at least one power transmission related component 440. In some embodiments, the power transmission related component 440 is disposed on the base 100. Furthermore, the power transmission related component 440 may be arranged adjacent to the semiconductor package 500A in the direction D10 (i.e., laterally).

[0172] In some embodiments, the power delivery related components 440 may include passive devices (e.g., capacitors and / or inductors), active devices (e.g., power management integrated circuits (PMICs), voltage regulators, etc.), flexible printed circuits, or other suitable power delivery related components.

[0173] In some embodiments, the semiconductor package assembly 600A may further include an electromagnetic (EM) shielding layer 460. In some embodiments, the EM shielding layer 460 may cover at least a portion of the surface of the semiconductor package 500A. For example, the EM shielding layer 460 may completely cover the upper surface 412T and edge 412E of the molding compound 412. The edge 200E of the first interconnect structure 200 may be exposed from the EM shielding layer 460. In some embodiments, the EM shielding layer 460 may be integrated with the semiconductor package assembly 600A.

[0174] In some embodiments, the electromagnetic (EM) shielding layer 460 can protect the chip of the semiconductor package 500A (e.g., the first chip 300A) from interference or noise from digital circuits (e.g., power transmission related components 440).

[0175] In some embodiments, an electromagnetic (EM) shielding layer 460 formed of metal may be connected between TIM 450 and thermal via TMV2 to further improve heat dissipation efficiency and accelerate heat dissipation.

[0176] Figure 9 , 10 11, 12, 13, and 14 are schematic cross-sectional views of semiconductor package assemblies including semiconductor packages 500B, 500C, 600D, 600E, 600F, and 600G. According to some embodiments of the present invention, Figure 2 , 3 Examples 500D, 500E, 500F, and 500G are shown in 4, 5, 6, and 7. The embodiments are consistent with previous references. Figures 1 to 8 Elements that are identical or similar in description will not be repeated. (ein, for the sake of brevity.)

[0177] In some embodiments, semiconductor package assembly 600B includes at least a base 100 and a semiconductor package 500B mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 600C includes at least a base 100 and a semiconductor package 500C mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 600D includes at least a base 100 and a semiconductor package 500D mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 600E includes at least a base 100 and a semiconductor package 500E mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 600F includes at least a base 100 and a semiconductor package 500F mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 600G includes at least a base 100 and a semiconductor package 500G mounted on the base 100 using a conductive structure 252.

[0178] In some embodiments, the components of semiconductor packages 500B, 500C, 500D, 500E, 500F, and 500G are as previously referenced. Figure 2 , 3 The components in the semiconductor packages 500B, 500C, 500D, 500E, 500F and 500G described in 4, 5 and 6 are the same or similar, and will not be repeated here for the sake of brevity.

[0179] In some embodiments, each semiconductor package assembly 600B, 600C, 600D, 600E, 600F, and 600G may further include a heat sink 420, a thermal interface material (TIM) 450, a thermal via (TMV2), a voltage regulator 430A, at least one power transfer-related component 440, and an electromagnetic (EM) shielding layer 460. The arrangement of the heat sink 420, TIM 450, thermal via (TMV2), voltage regulator 430A, power transfer-related component 440, and electromagnetic (EM) shielding layer 460 is consistent with the previous reference. Figure 8 The arrangement in the semiconductor package assembly 600A described herein is the same or similar, and will not be repeated here for the sake of brevity.

[0180] Figure 15 This is a schematic cross-sectional view of a semiconductor package assembly 700A including a semiconductor package 500A according to some embodiments of the present invention. For the sake of brevity, it is compared with previous references. Figure 8 Elements described in the same or similar embodiments will not be repeated here. Figure 8 and Figure 15 As shown, the difference between semiconductor package 600A and semiconductor package 700A is at least that the voltage regulator 430B of semiconductor package 700A is disposed in the first interconnect structure 200 of semiconductor package 500A.

[0181] like Figure 15 As shown, voltage regulator 430B is embedded in the first interconnect structure 200 and coupled to conductive trace 202. Furthermore, voltage regulator 430B can be coupled to the first chip 300A via the first interconnect structure 200 and the second interconnect structure 220. Additionally, voltage regulator 430B can be coupled to the base 100. In some embodiments, voltage regulator 430B can be used to provide a stable voltage to circuitry in a semiconductor package assembly 700A. In some embodiments, voltage regulator 430B can be integrated into the first interconnect structure 200.

[0182] Figure 16 , 17 18, 19, 20, and 21 are schematic cross-sectional views of semiconductor package assemblies 700B, 700C, 700D, 700E, 700F, and 700G according to some embodiments of the present invention, these assemblies comprising... Figure 2 , 3 Semiconductor packages 500B, 500C, 500D, 500E, 500F, and 500G are listed in sections 4, 5, 6, and 7. For brevity, refer to the previous references. Figures 1 to 15 Elements described in the same or similar embodiments will not be repeated here.

[0183] In some embodiments, semiconductor package assembly 700B includes at least a base 100 and a semiconductor package 500B mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 700C includes at least a base 100 and a semiconductor package 500C mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 700D includes at least a base 100 and a semiconductor package 500D mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 700E includes at least a base 100 and a semiconductor package 500E mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 700F includes at least a base 100 and a semiconductor package 500F mounted on the base 100 using a conductive structure 252. Semiconductor package assembly 700G includes at least a base 100 and a semiconductor package 500G mounted on the base 100 using a conductive structure 252.

[0184] In some embodiments, the components of semiconductor packages 500B, 500C, 500D, 500E, 500F, and 500G are the same as or similar to those previously referenced. Figure 2 , 3 The semiconductor packages described in 4, 5, and 6 are similar to those in 500B, 500C, 500D, 500E, 500F, and 500G, and will not be repeated here for the sake of brevity.

[0185] In some embodiments, each of the semiconductor package assemblies 700B, 700C, 700D, 700E, 700F, and 700G may further include a voltage regulator 430B disposed in the first interconnect structure 200. The arrangement of the voltage regulator 430B is consistent with previous references. Figure 15 The arrangement in the semiconductor package assembly 700A described herein is the same or similar, and will not be repeated here for the sake of brevity.

[0186] In some embodiments, each semiconductor package assembly 700B, 700C, 700D, 700E, 700F, and 700G may further include a heat sink 420, a thermal interface material (TIM) 450, a thermal via (TMV2), at least one power transfer-related component 440, and an electromagnetic (EM) shielding layer 460. The arrangement of the heat sink 420, TIM 450, thermal via (TMV2), power transfer-related component 440, and electromagnetic (EM) shielding layer 460 is consistent with the previous reference. Figure 15 The arrangement in the semiconductor package assembly 700A described herein is the same or similar, and will not be repeated here for the sake of brevity.

[0187] It should be understood that although some features are shown in some embodiments but not in others, these features may be present (or may not be present) in other embodiments whenever possible. For example, although Figure 15-21Each example embodiment shown illustrates a specific arrangement of voltage regulator 430B, but any other combination of arrangements of voltage regulators may be used where applicable. Furthermore, semiconductor package assemblies may include multiple voltage regulators having arrangements of voltage regulators 430A and 430B for semiconductor package assemblies 600A-600G and 700A-700G (where applicable).

[0188] In addition to the advantages of semiconductor packages 500A, 500B, 500C, 500D, 500E, 500F, and 500G, semiconductor package assemblies 600A-600G and 700A-700G also offer the following advantages. In semiconductor package assemblies 600A-600G and 700A-700G, thermal interface material (TIM) can be applied inside thermal conductivity vias (TMVs) (e.g., TIM 250A, 250B1, and 250B2 can be applied inside thermal conductivity via TMV2), or applied to the top of a fan-out wafer / panel-level package (FOW / PLP) (e.g., TIM 450 can be applied to the upper surface 412T of semiconductor package 500A-500G), after which a heat sink (e.g., heat sink 420) is connected. Furthermore, the thermal conductivity vias and TIM can be made of any high thermal conductivity material, such as metals or metal alloys, including aluminum, copper, nickel, cobalt, diamond, aluminum nitride, boron nitride, etc., or other high thermal conductivity materials. Additionally, the voltage regulator (e.g., voltage regulator 430) can be integrated within the glass / silicon / organic interposer or within the substrate (e.g., Figure 15-21 The embedded voltage regulator 430B in the first interconnect structure 200 of the semiconductor package 700A-700G, or as a stand-alone component (e.g., Figure 8-14 A body voltage regulator 430A is disposed on the first interconnect structure 200 in the semiconductor package assembly 600A-600G.

[0189] This invention provides a semiconductor package. The semiconductor package includes a first interconnect structure, a first chip, a first redistribution layer (RDL), a molding compound, and a through-hole via (TMV). The first chip is disposed above and coupled to the first interconnect structure. The first redistribution layer (RDL) is disposed above and coupled to the first chip. The molding compound is disposed on the first interconnect structure and encapsulates the first chip and the first RDL. The through-hole via (TMV) passes through the molding compound and connects between the first RDL and the first interconnect structure. The first chip includes a first back-side connection structure, a first transistor layer, a first front-side connection structure, and a first carrier. The first back-side connection structure is connected to the first interconnect structure. The first transistor layer is located on the first back-side connection structure. The first front-side connection structure is located on the first transistor layer. The first carrier is located on and coupled to the first interconnect structure. In this invention, the first chip can be connected for power transmission and grounding via a first rear connection structure, and can also transmit signals via a first front connection structure. This separates the thick power / ground lines from the thin signal lines, avoiding potential mutual interference between power / ground transmission and signal transmission, and isolating the heat-generating power / ground transmission from the less heat-generating signal transmission to avoid negative impacts. This improves signal integrity (SI), power integrity (PI), thermal conductivity, and voltage drop (IR) in the semiconductor package and related structures, resulting in better performance of the semiconductor package and assembly. In some embodiments, if there are special requirements, some signal lines can also be connected and transmitted via the first rear connection structure to adapt to actual needs.

[0190] In some embodiments, the first back-side connection structure is close to the first interconnect structure, and the first carrier is close to and coupled to the first RDL. This allows the first back-side connection structure and the first front-side connection structure to be respectively disposed on the upper and lower sides of the first chip, thus separating the first back-side connection structure and the first front-side connection structure to improve the performance of the semiconductor package and related structures.

[0191] In some embodiments, the first interconnect structure includes an interposer, a substrate, or an RDL to provide electrical interconnection and mechanical support.

[0192] In some embodiments, the first carrier is a silicon wafer carrier. Therefore, the first chip can be an integrated circuit structure such as a silicon die, and the second chip, third chip, etc., can also be an integrated circuit structure such as a silicon die.

[0193] In some embodiments, the first carrier includes a through-hole that passes through the first carrier and connects between the first front-side connection structure and the first RDL. This allows for connection (e.g., signal connection) via a through-hole (through silicon via).

[0194] In some embodiments, the semiconductor package further includes a second RDL disposed between the first carrier and the first RDL, thereby allowing for more flexible wiring connections.

[0195] In some embodiments, the second RDL is mounted on the first carrier via a conductive structure. This allows for electrical and mechanical connection using the conductive structure.

[0196] In some embodiments, the semiconductor package further includes a second interconnect structure located between the first interconnect structure and the first chip, thereby allowing for more flexible wiring connections.

[0197] In some embodiments, the second interconnect structure includes an interposer layer or RDL to provide electrical interconnection and mechanical support.

[0198] In some embodiments, a through-hole via (TMV) is disposed around the first chip. The TMV is used to transmit at least a signal, such as to a first connection structure.

[0199] In some embodiments, the first transistor layer includes at least one transistor. Therefore, the first chip can be an integrated circuit structure such as a silicon die.

[0200] In some embodiments, the first rear connection structure is used to connect to power and / or ground, or the first rear connection structure is used to connect to power and / or ground and also for signal transmission.

[0201] In some embodiments, the first front-side connection structure is used for signal transmission. This separates the thick power / ground wires from the thin signal wires, thus avoiding potential mutual interference between power / ground transmission and signal transmission, and isolating the power / ground transmission, which generates more heat, from the signal transmission, which generates less heat, to avoid negative impacts.

[0202] In some embodiments, the semiconductor package further includes a conductive structure disposed on the first interconnect structure and opposite to the first chip. This conductive structure is used for electrical and mechanical connections.

[0203] In some embodiments, the semiconductor package further includes a second chip disposed above and spaced apart from the first chip, wherein the second chip is encapsulated by molding compound.

[0204] In some embodiments, the second chip is a transceiver chip. This allows for wireless transmission of signals using both the first and second chips.

[0205] In some embodiments, the semiconductor package further includes a thermal interface material (TIM) disposed between the first chip and the second chip to improve heat dissipation.

[0206] In some embodiments, the second chip and the first chip are coupled via near-field coupling. Near-field coupling may include electrical coupling, magnetic coupling, and / or electromagnetic coupling. This allows for wireless transmission of signals using both the first and second chips.

[0207] In some embodiments, the second chip includes a logic chip, a memory chip, a radio frequency (RF) chip, and / or an analog chip with transceiver functionality.

[0208] In some embodiments, the semiconductor package further includes a third chip disposed above / on the second chip, and the third chip is coupled to the first RDL. This allows for wireless transmission between the second chip and the third chip, as well as within the second chip, to enable signal transmission for desired multi-die applications.

[0209] In some embodiments, the third chip includes a third back-side connection structure, a third transistor layer, a third front-side connection structure, and a third carrier. The third back-side connection structure is connected to the first RDL. The third transistor layer is located on the third back-side connection structure. The third front-side connection structure is located on the third transistor layer. The third carrier is located on the front-side connection structure. This allows for signal transmission and power / ground connections, and can also separate signal transmission and power / ground connections to improve performance.

[0210] In some embodiments, the third chip is spaced apart from the first chip by a molding compound, or the third chip is spaced apart from the first chip by a molding compound and a thermal interface material (TIM) to improve heat dissipation.

[0211] In some embodiments, the third chip and the second chip are coupled via near-field coupling. Near-field coupling may include electrical coupling, magnetic coupling, and / or electromagnetic coupling. This allows for wireless transmission of signals using both the first and second chips.

[0212] In some embodiments, the second chip is connected to the first RDL via a first through-hole embedded in the molding compound. This establishes an electrical connection for transmitting signals and / or power / ground.

[0213] In some embodiments, the first carrier is located close to the first interconnect structure, and the first back-side connection structure is located close to and coupled to the first RDL. This enables electrical connection for transmitting signals and / or power / ground.

[0214] In some embodiments, the first carrier includes a through-hole (TV) that passes through the first carrier and connects between the first front-side connection structure and the first interconnect structure. This enables electrical connection for transmitting signals and / or power / ground.

[0215] In some embodiments, the semiconductor package further includes a second chip disposed between the first interconnect structure and the first chip. The second chip is spaced apart from the first chip by a molding compound. A first carrier is located above the second chip, thereby forming a multi-chip package structure to meet different needs.

[0216] This invention provides a semiconductor packaging assembly. The semiconductor packaging assembly includes a substrate and a semiconductor package mounted on the substrate. The semiconductor package includes a first interconnect structure, a first chip, a first redistribution layer (RDL), a molding compound, and a through-hole via (TMV). The first chip is disposed above and coupled to the first interconnect structure. The first redistribution layer (RDL) is disposed above and coupled to the first chip. The molding compound is disposed on the first interconnect structure and encapsulates the first chip and the first RDL. The through-hole via (TMV) passes through the molding compound and connects between the first RDL and the first interconnect structure. The first chip includes a first back-side connection structure, a first transistor layer, a first front-side connection structure, and a first carrier. The first back-side connection structure is connected to the first interconnect structure. The first transistor layer is located on the first back-side connection structure. The first front-side connection structure is located on the first transistor layer. The first carrier is located on the first front-side connection structure and coupled to the first interconnect structure. The first back-side connection structure is close to the first interconnect structure, and the first carrier is close to and coupled to the first RDL. Alternatively, the first carrier is close to the first interconnect structure, and the first back-side connection structure is close to and coupled to the first RDL.

[0217] In some embodiments, the semiconductor package assembly further includes a heat sink mounted on the semiconductor package to accelerate heat dissipation.

[0218] In some embodiments, the heat sink is mounted on the semiconductor package via a thermal interface material (TIM) to improve heat dissipation.

[0219] In some embodiments, the semiconductor package assembly further includes a thermally perforated molded plastic through the semiconductor package and connected to a first interconnect structure of the semiconductor package and a heat sink to improve heat dissipation.

[0220] In some embodiments, a through-hole via (TMV) is disposed around a first chip of a semiconductor package. The TMV is used to make electrical connections for transmitting signals and / or power / ground.

[0221] In some embodiments, the semiconductor package assembly further includes a voltage regulator disposed in the molding compound or in a first interconnect structure of the semiconductor package, thereby providing more design options.

[0222] In some embodiments, the semiconductor package assembly further includes at least one power delivery-related component disposed on the substrate, thereby providing more design options.

[0223] In some embodiments, the semiconductor packaging assembly further includes an electromagnetic (EM) shielding layer covering at least a portion of the semiconductor package surface and / or disposed within the semiconductor package to protect the internal chip from damage.

[0224] According to some embodiments of the present invention, semiconductor packages and semiconductor package assemblies employ an alternative type of BSPDN (Back Side Power Delivery Network) to address the aforementioned problems. For example, when a signal reaches the top metal layer of the back-end process on-chip (BEOL) metal system, the signal can be transmitted externally via wired or wireless and wired transmission to support critical signals. Furthermore, the chip can be placed face-up or face-down in a package employing 2D / 3D homogeneous and heterogeneous integration, either as a single chip or in a multi-chip stack. The structure and requirements of the chip, package, and substrate (e.g., PCB) are uniformly optimized. In some embodiments, elements for wired transmission may include bumps (optional), through-holes (TVs), redistribution layers (RDLs), and through-mold vias (TMVs) in epoxy molding compound (EMC) for fan-out wafer / panel-level packaging (FOW / PLP). In some embodiments, the elements for wireless and wired transmission may include bumps (optional), redistribution layers (RDL) and through-holes (TMV) in epoxy molding compound (EMC) using fan-out wafer / panel-level packaging (FOW / PLP), and near-field coupling between chips (including electrical (e.g., capacitive) coupling, magnetic (e.g., inductive) coupling, or electromagnetic (e.g., radiative) coupling).

[0225] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor package, characterized in that, include: First interconnect structure; A first chip is disposed on and coupled to the first interconnect structure; A first redistribution layer is disposed on the first chip and coupled to the first chip; A molding compound is disposed on the first interconnect structure and encapsulates the first chip and the first redistribution layer; as well as A through-hole passes through the molding compound and connects the first redistribution layer and the first interconnect structure; The first chip includes: A first back-side connection structure is coupled to the first interconnect structure; The first transistor layer is located on the first back-side connection structure; A first front-side interconnect structure is located on the first transistor layer; and A first carrier is located on and coupled to the first interconnect structure.

2. The semiconductor package according to claim 1, characterized in that, The semiconductor package also includes a second redistribution layer disposed between the first carrier and the first redistribution layer.

3. The semiconductor package according to claim 1, characterized in that, The semiconductor package also includes a second interconnect structure located between the first interconnect structure and the first chip.

4. The semiconductor package according to claim 1, characterized in that, The through-hole is positioned around the first chip.

5. The semiconductor package according to claim 1, characterized in that, The first rear connection structure is used for connection to a power source or to a power source and ground, or the first rear connection structure is used for connection to a power source or to a power source and ground, and is also used for signal transmission.

6. The semiconductor package according to claim 5, characterized in that, The first front connection structure is used for signal transmission.

7. The semiconductor package according to claim 1, characterized in that, Also includes: A second chip is disposed on and spaced apart from the first chip, wherein the second chip is encapsulated by molding compound.

8. The semiconductor package according to claim 7, characterized in that, The second chip is a transceiver chip.

9. The semiconductor package according to claim 8, characterized in that, It also includes a thermal interface material disposed between the first chip and the second chip.

10. The semiconductor package according to claim 8, characterized in that, The second chip and the first chip are coupled by near-field coupling, which includes electrical coupling, magnetic coupling and / or electromagnetic coupling.

11. The semiconductor package according to claim 8, characterized in that, The semiconductor package also includes a third chip disposed on the second chip, and the third chip is coupled to the first redistribution layer.

12. The semiconductor package according to claim 11, characterized in that, The third chip includes: The third back-side connection structure is connected to the first redistribution layer; The third transistor layer is located on the third back-side connection structure; A third front-side interconnect structure is located on the third transistor layer; and The third carrier is located on the front connecting structure.

13. The semiconductor package according to claim 11, characterized in that, The third chip is separated from the first chip by the molding compound, or the third chip is separated from the first chip by the molding compound and the thermal interface material.

14. The semiconductor package according to claim 11, characterized in that, The third chip and the second chip are coupled by near-field coupling, which includes electrical coupling, magnetic coupling and / or electromagnetic coupling.

15. The semiconductor package according to claim 11, characterized in that, The second chip is connected to the first redistribution layer through a first through-hole embedded in the molding compound.

16. The semiconductor package according to claim 1, characterized in that, The first carrier is close to the first interconnect structure, and the first back-side connection structure is close to and connected to the first redistribution layer.

17. The semiconductor package according to claim 16, characterized in that, The first carrier includes a through-hole that passes through the first carrier and connects between the first front connection structure and the first interconnect structure.

18. The semiconductor package according to claim 17, characterized in that, Also includes: A second chip is disposed between the first interconnect structure and the first chip, the second chip being spaced apart from the first chip by the molding compound, and the first carrier being located above the second chip.

19. A semiconductor packaging assembly, characterized in that, include: Base; as well as A semiconductor package mounted on the base, wherein the semiconductor package includes: First interconnect structure; A first chip is disposed on and coupled to the first interconnect structure; A first redistribution layer is disposed on the first chip and coupled to the first chip; A molding compound, disposed on the first interconnect structure and encapsulating the first chip and the first redistribution layer; and A through-hole passes through the molding compound and connects the first redistribution layer and the first interconnect structure. The first chip includes: A first back-side connection structure is connected to the first interconnect structure; The first transistor layer is located on the first back-side connection structure; A first front-side interconnect structure is located on the first transistor layer; and The first carrier is located on the first front connection structure and coupled to the first interconnection structure; Wherein, the first back-side connection structure is close to the first interconnect structure, and the first carrier is close to and coupled to the first redistribution layer; or, the first carrier is close to the first interconnect structure, and the first back-side connection structure is close to and coupled to the first redistribution layer.

20. The semiconductor packaging assembly according to claim 19, characterized in that, The semiconductor package assembly also includes a thermal via that passes through the molding compound of the semiconductor package and is connected to the first interconnect structure and the heat sink of the semiconductor package.

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