Stacked integrated circuit device

Abstract

A stacked integrated circuit (IC) device (100) includes a first die (110) having a first face (112), a first active region (116) adjacent the first face, and a first die interconnect contact (122) disposed on the first face and connected to a first circuit. The stacked IC device includes a second die (130) having a second face (132), a second active region (136) adjacent the second face, and a second die interconnect contact (142) disposed on the second face and connected to a second circuit. The first face is oriented toward the second face, and the first die interconnect contact is connected to the second die interconnect contact. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face (124), the second face (144), or both. The stacked IC device also includes an interconnect conductor connected to the redistribution layer to provide a signal path from the first die (122), the second die (142), or both to a set of external contacts (162).

Description

[0001] Cross-references to related applications

[0002] This application claims priority to jointly owned U.S. non-provisional patent application No. 18 / 451,971, filed August 18, 2023, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] Various features are involved in stacked integrated circuit devices. Background Technology

[0004] Electrical connections exist at every level of a system hierarchy. This hierarchy includes interconnections of active devices at the lowest system level, all the way up to system-level interconnections at the highest level. For example, interconnect layers connect different devices on an integrated circuit. As integrated circuits become more complex, more interconnect layers are used to provide electrical connections between devices. Recently, due to the sheer number of interconnected devices in modern electronic devices, the number of interconnect levels used in circuits has substantially increased. The increased number of interconnect layers to support this increased number of devices involves more complex manufacturing processes.

[0005] During the design of modern integrated circuit devices, conflicts often arise between various design goals. For example, some applications require limiting the size of the integrated circuit package and improving heat dissipation. However, smaller integrated circuit packages typically have a smaller area for heat removal. Therefore, reducing the package size often reduces heat dissipation. A similar conflict can arise between heat dissipation and processing performance, as higher-performance processors tend to generate more heat. Furthermore, the goal of reducing cost may conflict with almost any other improvement goal. Therefore, providing high-performance integrated circuit devices that can meet a variety of design goals is challenging. Such challenges are particularly important for mobile applications, where power constraints, device size, processing performance, heat dissipation, cost, and many other factors all come into play simultaneously. Summary of the Invention

[0006] Various features are involved in integrated circuit (IC) devices.

[0007] One example provides a stacked IC device comprising: a first die having a first side, a first active region adjacent to the first side, a first circuit disposed in the first active region, and a first die interconnect contact disposed on the first side and electrically connected to the first circuit. The stacked IC device further comprises a second die having a second side, a second active region adjacent to the second side, a second circuit disposed in the second active region, and a second die interconnect contact disposed on the second side and electrically connected to the second circuit. The first side is oriented toward the second side, and the first die interconnect contact is electrically connected to the second die interconnect contact. The stacked IC device includes a set of redistribution layers electrically connected to the redistribution contacts on the first side, the second side, or both. The stacked IC device also includes interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide a signal path from the first die, the second die, or both to the set of external contacts.

[0008] Another example provides an apparatus including a stacked IC device located on a first side of a substrate, wherein the substrate has a set of external contacts on a second side. The stacked IC device includes a first die having a first surface, a first active region adjacent to the first surface, a first circuit disposed in the first active region, and a first die interconnect contact disposed on the first surface and electrically connected to the first circuit. The stacked IC device includes a second die having a second surface, a second active region adjacent to the second surface, a second circuit disposed in the second active region, and a second die interconnect contact disposed on the second surface and electrically connected to the second circuit. The first surface is oriented toward the second surface, and the first die interconnect contact is electrically connected to the second die interconnect contact. The stacked IC device includes a set of redistribution layers electrically connected to the redistribution contacts on the first surface, the second surface, or both. The stacked IC device includes interconnect conductors that are external to the first die and the second die and electrically connected to the redistribution layer to provide a signal path from the first die, the second die, or both to the set of external contacts.

[0009] Another example provides a method for manufacturing a stacked IC device. The method includes electrically connecting a first die to a second die face-to-face using first die interconnect contacts disposed on a first side of a first die and second die interconnect contacts disposed on a second side of a second die, wherein the face of the die corresponds to a surface of the die defining an active region of the die, the active region including circuitry. The method includes forming a set of redistribution layers electrically connected to the redistribution contacts on the first side, the second side, or both. The method includes forming interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide a signal path from the first die, the second die, or both to the set of external contacts. Attached Figure Description

[0010] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0011] FIG. 1 A schematic cross-sectional view illustrating an example of an exemplary stacked IC device is shown.

[0012] FIG. 2 Examples FIG. 1 A schematic cross-sectional view of another example of an exemplary stacked IC device.

[0013] FIG. 3 Examples FIG. 1 A schematic cross-sectional view of another example of an exemplary stacked IC device.

[0014] FIG. 4A , FIG. 4B and FIG. 4C Together, examples are shown for manufacturing FIG. 1 An exemplary process of an exemplary stacked IC device.

[0015] FIG. 5 Examples include FIG. 1 A schematic cross-sectional view of an example of an exemplary stacked IC device.

[0016] FIG. 6 Examples include FIG. 1 A schematic cross-sectional view of an example of an exemplary stacked IC device.

[0017] FIG. 7 Examples include FIG. 1 A schematic cross-sectional view of an example of an exemplary stacked IC device.

[0018] FIG. 8 Examples include FIG. 1 A schematic cross-sectional view of an example of an exemplary stacked IC device.

[0019] FIG. 9 Examples include FIG. 1 A schematic cross-sectional view of an example of an exemplary stacked IC device.

[0020] FIG. 10 An exemplary flowchart illustrating a method for manufacturing an exemplary stacked IC device is shown.

[0021] FIG. 11 Examples are provided of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0022] Specific aspects of this disclosure describe integrated circuit (IC) devices and manufacturing methods using a face-to-face stacked die configuration to achieve various IC design goals. In this context, a “face” of a die refers to the surface of the die adjacent to an active region of the die that includes active circuitry. For example, the active region may include various layers and structures defining circuit elements, such as transistors, conductors, passive circuit elements (e.g., resistors, inductors, capacitors, etc.). In this example, a face of the die corresponds to a side of the die that defines the active region. Conversely, a “back” of the die refers to the opposite side of the die that defines a non-active region of the die. For example, a non-active region typically includes undoped single-crystal semiconductor material and other passive layers (e.g., passivation layers).

[0023] Face-to-face die stacking enables the use of short, high-density (e.g., fine-pitch) interconnects between dies. Shorter interconnects typically experience lower resistive losses, thus improving power efficiency and reducing heat generation. Additionally, shorter interconnects allow for faster signal exchange compared to longer interconnects. Furthermore, the high-density interconnects between dies result in smaller IC package sizes and / or an increase in the area available for heat exchange.

[0024] In the specific implementation described herein, two or more dies are stacked face-to-face, and the circuitry of these two or more dies is electrically interconnected via die interconnect conductors. External connectivity of any one or two dies is provided via external contacts on a package substrate (e.g., an array of solder balls). For example, the external contacts may be electrically connected to one or more stacked dies via interconnect conductors (e.g., through-silicon vias or vias of interposer devices) and a set of redistribution layers. In this arrangement, the stacked dies may not have through-silicon vias (TSVs), which simplifies die fabrication. Avoiding the use of TSVs for inter-die signaling also makes more efficient use of the footprint of each die, as there is no area on the die dedicated to accommodating TSVs.

[0025] In various specific implementations, the face-to-face stacked die arrangement disclosed herein is a low-cost and technically feasible way to provide packaged ICs with small form factor while also achieving other technical benefits such as improved die interconnect density, simplified die fabrication, improved thermal management, and improved power distribution network performance. For example, the faces of the electrically connected dies enable the use of small, densely packaged die interconnect contacts and conductors between the dies. For example, microbumps or similar techniques can be used to interconnect the dies, thereby providing short, high-density interconnects between them. As another example, electrically connecting the dies to external contacts via a set of redistribution layers coupled to the faces of the dies avoids the need for through-silicon vias in one or more of these dies, which reduces die fabrication costs, allows for more efficient use of die footprint, improves die yield, and simplifies die design. As yet another example, when the dies are stacked face-to-face in an offset arrangement, the heat-generating portions of the dies can be offset from each other, thereby providing improved thermal management. Further, in this example, devices providing additional benefits can be located in the offset region adjacent to the dies. For illustration, a device including one or more capacitors can be positioned in such an offset region and electrically connected to the power distribution network of the stacked dies. This provides a short signal path between the power distribution network and the capacitors, improving the performance of the power distribution network. The face-to-face stacked die arrangement disclosed herein can also shorten the signal path between one or more dies and one or more other devices, such as between processing dies and memory devices, thereby improving the performance of the packaged IC device.

[0026] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0027] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In this description, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing particular embodiments and are not intended to limit the scope of the embodiments. For example, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some embodiments and plural in others. For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in the singular or optional plural form (as indicated by “(multiple)”), unless the aspect relating to multiples of features is being described.

[0028] As used herein, the terms “comprise,” “comprises,” and “comprising” are used interchangeably with “include,” “includes,” or “including.” As used herein, “exemplary” indicates an example, specific implementation, and / or aspect, and should not be construed as limiting or indicating a preference or preferred specific implementation. As used herein, ordinal numbers (e.g., “first,” “second,” “third,” etc.) used to modify elements such as structures, components, operations, etc., do not themselves indicate any priority or order of that element relative to another element, but merely distinguish that element from another element with the same name (but using an ordinal number). As used herein, the term “set” refers to one or more elements within a specific set, and the term “multiple” refers to multiple (e.g., two or more) elements within a specific set.

[0029] Improvements in manufacturing technology and the demand for lower-cost and more capable electronic devices have led to increased complexity in ICs. Typically, more complex ICs have more complex interconnect schemes to enable interaction between ICs within a device. Due to the sheer number of interconnected devices in today's state-of-the-art mobile applications, the number of interconnect layers in the circuitry has also increased substantially.

[0030] These interconnects include back-end process (BEOL) interconnect layers, which can refer to conductive interconnect layers used for electrical coupling to front-end process (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, where lower BEOL interconnect levels typically use a thinner metal layer than upper BEOL interconnect levels. BEOL interconnect layers can be electrically coupled to middle-end process (MOL) interconnect layers, which interconnect to the IC's FEOL active devices.

[0031] State-of-the-art mobile applications demand small form factor, low cost, tight power budgets, and high electrical performance. Mobile packaging designs have evolved to meet these diverse objectives, enabling multimedia-enhanced mobile applications. For example, fan-out (FO) wafer-level packaging (WLP), or FO-WLP process technology, is an evolution in packaging technology for mobile applications. This chip-first FO-WLP process technology solution provides flexibility for fan-in and fan-out connections from the die to the package ball. Furthermore, this solution reduces the height of the first-level interconnect between the die and package ball in mobile application devices. However, when multiple dies are arranged within a small form factor, these mobile applications are susceptible to power and signal routing challenges.

[0032] Stacked die and chiplet architectures have become increasingly prevalent as power performance area (PPA) yields have significantly improved across product lines. As used herein, “stacked die” and / or “stacked IC” refers to an arrangement in which one die (e.g., the first die) is positioned on top of (including directly on top of) another die (e.g., the second die). In stacked die or stacked IC devices, one or more of these dies may also be positioned on top of one or more other devices, such as integrated capacitor devices, as further described below. Unfortunately, stacked die solutions can involve high power density targets, which can lead to significant power distribution inefficiencies. Various aspects of this disclosure provide stacked IC devices arranged to provide improved integration of capacitors with a power distribution network (PDN), resulting in improved PDN performance.

[0033] As used herein, the term "layer" includes films and is not construed as indicating vertical or horizontal thickness unless otherwise stated. As used herein, the term "chiplet" can refer to a block of integrated circuits, a block of functional circuitry, or other similar circuitry specifically designed to work with one or more other chiplets to form a larger, more complex chiplet architecture.

[0034] 3D integrated circuits (3D ICs) comprise a set of stacked and interconnected dies. Typically, 3D IC architectures offer higher performance, increased functionality, lower power consumption, and / or a smaller footprint compared to providing the same circuitry in a monolithic die or two-dimensional (2D) IC structure. Unfortunately, capacitive decoupling of the power distribution network (PDN) for 3D ICs to suppress power distribution noise is challenging. Specifically, due to the smaller footprint of 3D ICs, the available space for landside capacitors (LSCs) in die shadows within the 3D IC is limited. For example, different logic blocks of a 3D IC may be placed overlapping each other in a stack of dies, making it more challenging to provide decoupling for the circuitry within that stack. Furthermore, the electrical paths of conventional landside capacitor placements on the package substrate can exhibit large parasitic inductance, which can degrade the decoupling performance of the landside capacitors.

[0035] Exemplary stacked IC device

[0036] FIG. 1 A schematic cross-sectional view illustrating an example of an exemplary stacked IC device 100 is shown. The stacked IC device 100 includes a plurality of dies (e.g., a first die 110 and a second die 130). As explained further below, the first die 110 and the second die 130 are stacked face-to-face to form the stacked IC device 100. The dies 110 and 130 are disposed on a first side 156 of a substrate 154, and a set of external contacts 162 (such as a ball grid array 160) are disposed on a second side 158 of the substrate 154.

[0037] The first die 110 includes a first active region 116 adjacent to a first side 112 of the first die 110 and a first passive region 118 adjacent to a back side 114 of the first die 110. The first active region 116 includes a first circuit, such as conductors, passive components, transistors, etc. For example, the first circuit may include conductors arranged to form a power distribution network (PDN) and multiple transistors, and / or other circuit elements arranged and interconnected to form logic cells, memory cells, etc. In the first active region 116, components of the first circuit may be formed in and / or on a semiconductor substrate by forming various insulating layers, conductive layers, and doped / undoped regions. Different implementations may use different types of transistors, such as field-effect transistors (FETs), planar FETs, finFETs, gate-all-around FETs, or hybrid transistor types. In some implementations, a front-end process (FEOL) may be used to fabricate the first circuit in and / or on the semiconductor substrate. Conversely, the first passive region 118 may include, for example, undoped semiconductor material, oxide or passivation layers, or another material that does not include circuit elements. For illustrative purposes, in some specific implementations, the first non-active region 118 has no conductor, no via, no contact, or any of these components.

[0038] The second die 130 includes a second active region 136 adjacent to a second side 132 of the second die 130 and a second passive region 138 adjacent to a back side 134 of the second die 130. The second active region 136 includes second circuitry, such as conductors, passive components, transistors, etc. For example, the second circuitry may include conductors arranged to form a PDN and multiple transistors and / or other circuit elements arranged and interconnected to form logic cells, memory cells, etc. In the second active region 136, components of the second circuitry may be formed in and / or on a semiconductor substrate by forming various insulating layers, conductive layers, and doped / undoped regions. Similar to the first passive region 118, the second passive region 138 may include, for example, an undoped semiconductor material, an oxide or passivation layer, or another material that does not include circuit elements. For illustration, in some specific embodiments, the second passive region 138 has no conductors, no vias, no contacts, or none of these components.

[0039] The first circuitry of the first die 110 and the second circuitry of the second die 130 are configured to cooperate in performing various operations. For example, in some embodiments, the first circuitry includes one or more first functional circuit blocks, and the second circuitry includes one or more second functional circuit blocks, and the first functional circuit block(s) and the second functional circuit block(s) are operationally interdependent. In some such embodiments, the first die is a first chiplet, and the second die is a second chiplet designed to operate in conjunction with the first chiplet. In other examples, one of the dies 110 and 130 includes circuitry arranged to form logic blocks, and the other of the dies 110 and 130 includes circuitry arranged to form functional blocks to support logic blocks such as memory cells, additional logic blocks, etc. In an exemplary example, the first circuitry of the first die 110 includes functional blocks arranged to operate as one or more cores of a central processing unit (CPU) (e.g., configured to perform general processing tasks using sequential instructions), and the second circuitry of the second die 110 includes functional blocks arranged to operate as one or more cores of a graphics processing unit (GPU) (e.g., configured to perform high-throughput parallel processing tasks).

[0040] The first surface 112 of the first die 110 includes a set of electrical contacts connected to a first circuit, and the second surface 132 of the second die 130 includes a set of electrical contacts connected to a second circuit. FIG. 1 In this context, the contacts on the first side 112 of the first die 110 include a first die interconnect contact 122 and a first redistribution contact 124. Similarly, the contacts on the second side 132 of the second die 130 include a second die interconnect contact 142 and a second redistribution contact 144. In this context, "die interconnect contact" includes a contact for supporting electrical connections between dies 110 and 130, and "redistribution contact" includes a contact for supporting electrical connections between die 110, die 130, or both, and the stacked IC device 100 or other devices outside the stacked IC device 100.

[0041] In the stacked IC device 100, a first die interconnect contact 122 is electrically connected to a second die interconnect contact 142 to provide a set of conductive paths (such as exemplary signal path 168) between the first circuit and the second circuit. For example, one or more first transistors of the first circuit can be connected to one or more second transistors of the second circuit via the first die interconnect contact 122 and the second die interconnect contact 142. As another example, the PDN of the first circuit can be connected to the PDN of the second circuit via the first die interconnect contact 122 and the second die interconnect contact 142.

[0042] In a particular aspect, a set of redistribution layers 150 are electrically connected to a first redistribution contact 124 on a first surface 112, a second redistribution contact 144 on a second surface 132, or both. Further, interconnecting conductors 152 outside the first die 110 and the second die 130 are electrically connected to the redistribution layers 150 to provide a signal path from the first die 110, the second die 130, or both to the external contact 162. For example, in FIG. 1 In this configuration, a first interconnect conductor 152A provides a conductive signal path 164 between a first redistribution contact 124 and an external contact 162, and a second interconnect conductor 152B provides a conductive signal path 166 between a second redistribution contact 144 and an external contact 162. Signal paths 164 and 166 are configured to provide power connection, external input / output (I / O) connection, or both. FIG. 1 In the illustrated example, interconnect conductor 152 includes a through-mold via (TMV) extending through a molding compound 170 that at least partially encapsulates the first die 110 and the second die 130. In other examples, interconnect conductor 152 may include conductive vias formed of other materials, such as through-silicon vias or through-glass vias formed in an interposer device (e.g., a third die).

[0043] FIG. 1 The illustrated face-to-face stacked dies 110, 130 enable the use of short, high-density (e.g., fine-pitch) interconnects 172 between dies 110, 130. Interconnects 172 provide short signal paths 168, which typically experience lower resistive losses (compared to longer signal paths such as signal paths 164, 166 or typical redistributed connections) (resulting in improved power efficiency and better thermal management), enabling faster signal switching, and achieving higher connection density (enabling the use of smaller dies 110, 130 and / or smaller stacked IC devices 100, increased heat exchange area, or both). Furthermore, the biased dies 110 and 130 are such that the overlapping areas of faces 112 and 132 of dies 110 and 130 include die interconnect contacts 122 and 142, and the non-overlapping areas of faces 112 and 132 include redistribution contacts 124 and 144. This allows power and I / O connections to be routed to external contacts 162 without using vias (e.g., through-silicon vias) in the dies 110 and 130 themselves. For example, interconnect conductor 152 may be disposed adjacent to a second die 130 in the stacked IC device 100 and electrically connected to the redistribution contacts 124, 144, or both of the dies 110 and 130 via the redistribution layer 150. Avoiding the use of vias in dies 110 and 130 improves die yield, reduces the fabrication cost of dies 110 and 130, and enables the use of smaller dies and / or more efficient use of die footprint.

[0044] FIG. 1 The illustrations shown are merely schematic and intended to highlight specific features of the stacked IC device 100. For example, the specific number of contacts and interconnects is illustrative and not limiting. Typically, each die 110, 130 will include dozens or hundreds of contacts. Similarly, a typical stacked IC device 100 will include dozens or hundreds of external contacts 162 and dozens or hundreds of interconnect conductors 152. Furthermore, FIG. 1 Certain internal structures are omitted. For example, redistribution layer 150 includes internal conductive traces and vias interconnected to form conductive paths. Similarly, substrate 154 typically also includes internal conductive traces and vias interconnected to form conductive paths to external contacts 162. Substrate 154 may also include other internal features (such as embedded cores, embedded passive devices, etc.), other external features (e.g., landside passive devices), or both. Further, in FIG. 1 In this embodiment, the interconnects between dies 110 and 130 (e.g., to form signal path 168) and the interconnects between dies 110 and 130 and the redistribution layer 150 are illustrated as being formed using solder bumps, simply to highlight the approximate location of the electrically connected components. In other embodiments, the interconnects between dies 110 and 130, the interconnects between dies 110 and 130 and the redistribution layer 150, or both, are formed using other techniques (other than or replacing solder bumps), such as copper pillars or pad-to-pad bonding.

[0045] As described above, in some embodiments, dies 110 and 130 include chiplets. For example, in some embodiments, the first die 110 is a first chiplet, and the second die 130 is a second chiplet designed to operate in conjunction with the first chiplet. For illustration, in some embodiments, the circuitry of the first chiplet / first die 110 includes one or more first functional circuit blocks, and the circuitry of the second chiplet / second die 130 includes one or more second functional circuit blocks, wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally interdependent.

[0046] Using arranged and interconnected chiplets as 3D stacked ICs to form the stacked IC device 100 offers various benefits compared to providing the same functional circuitry in a single monolithic chip. For example, each chiplet is smaller than a single monolithic die containing all the functional circuitry blocks that share the same functionalities. Since yield losses in IC manufacturing (and the costs associated with those losses) tend to increase with die size, using smaller dies reduces yield losses in the IC manufacturing process (i.e., increases yield). Another benefit is that the chiplets can be manufactured at different locations and / or by different manufacturers, and in some cases, using different manufacturing technologies (e.g., different manufacturing technology nodes). As an example, one die of a chiplet-based integrated device (e.g., the first die 110 of the stacked IC device 100) may include components with a first minimum size (e.g., interconnects, transistors, etc.), and another die of a chiplet-based integrated circuit (e.g., the second die 130 of the stacked IC device 100) may include components with a second minimum size (e.g., interconnects, transistors, etc.), wherein the second minimum size is larger than the first minimum size. In contrast, all circuitry in a monolithic die is manufactured using the same manufacturing techniques and equipment. As a result, when manufacturing a monolithic die, the entire die is subject to the most stringent manufacturing constraints on the most complex components. However, when using chiplets, different chiplets can be manufactured using different manufacturing techniques (e.g., different manufacturing technology nodes), and only one or more chiplets containing the most complex components are subject to the most stringent manufacturing constraints. In this arrangement, chiplets manufactured using less expensive and / or higher-yield manufacturing techniques can be integrated with chiplets manufactured using more expensive and / or lower-yield manufacturing techniques to form ICs (e.g., stacked IC devices 100), resulting in overall savings. Furthermore, in some cases, the design of chiplets can be changed as technology improves. Chiplet stacking allows such new chiplet designs to be integrated with older chiplet designs to form stacked IC devices, improving manufacturing flexibility and reducing design costs.

[0047] FIG. 2 A schematic cross-sectional view illustrating an example of an exemplary stacked IC device 200 is shown. FIG. 2 The stacked IC device 200 is FIG. 1 An example of a stacked IC device 100. Therefore, FIG. 2 The stacked IC device 200 includes FIG. 1 Each component and feature in the stacked IC device 100. To highlight other components and features, certain components and features among these are... FIG. 2 Shown or not shown. FIG. 1 The components and features of the stacked IC device 100 are only FIG. 2 The label indicates that it is used in conjunction with... FIG. 1 Same reference numerals as shown in the attached figures.

[0048] exist FIG. 2 In the first active region 116, a first circuit 210, such as a PDN 212, and a set of transistors 214 arranged to form functional circuitry powered by the PDN 212. Similarly, a second active region 136 includes a second circuit 230, such as a PDN 232, and a set of transistors 234 arranged to form functional circuitry powered by the PDN 232. The PDNs 212 and 232 include, for example, one or more power rails, one or more ground rails, etc. The transistors 214 and 234 are arranged and interconnected to form active circuitry including, for example, processing logic blocks (e.g., transistor blocks), memory blocks, etc.

[0049] In some implementations, the PDN 212 of the first die 110 is electrically connected to the PDN 232 via the first die interconnect contact 122 and the second die interconnect contact 142. For example, signal path 168 can connect the ground rail of the PDN 212 to the ground rail of the PDN 232. As another example, signal path 168 can connect the power rail of the PDN 212 to the power rail of the PDN 232. In the same or different implementations, the PDN 212 of the first die 110, the PDN 232 of the second die 130, or both, are electrically connected to external contact 162 via redistribution layer 150 and interconnect conductor 152 (e.g., to provide power and ground paths to the stacked IC device 200).

[0050] exist FIG. 2 In the illustrated example, the stacked IC device 200 includes one or more other devices disposed adjacent to one or both of the dies 110, 130. For example, in FIG. 2 In this context, the stacked IC device 200 includes one or more integrated capacitor devices (ICDs) 220 disposed adjacent to the first die 110 (e.g., on the redistribution layer 150). As another example, in... FIG. 2 In this configuration, the stacked IC device 200 includes one or more ICDs 240 disposed adjacent to the second die 110 (e.g., between the first die 110 and the substrate 154). Although FIG. 2 Examples of ICDs 220 and 240 arranged adjacent to dies 110 and 130 are shown, but in other embodiments, stacked IC devices 200 may include other components (e.g., additional devices) as alternatives to or supplements to ICDs 220 and 240 arranged adjacent to one or both of dies 110 and 130.

[0051] Multiple ICDs 220, 240 include one or more capacitors formed on or embedded in a substrate. For example, in some embodiments, the capacitors include one or more trench capacitors (e.g., deep trench capacitors (DTC)) in a semiconductor substrate. As another example, the capacitors include or correspond to one or more multilayer ceramic capacitors. In embodiments where the stacked IC device 200 includes ICDs (e.g., one or more of ICDs 220, 240), the ICDs may be electrically connected to one or both of the PDNs 212, 232 to suppress distribution noise of the PDN. In conventional embodiments, the PDN may be coupled to one or more landside capacitors disposed on a second side 158 of substrate 154, one or more embedded capacitors within substrate 154, or both, to provide distribution noise suppression. While one benefit of using stacked IC devices (such as stacked IC device 200) is the reduction in the footprint of such capacitors compared to comparable monolithic IC devices, this reduced footprint may present challenges in the positioning of noise suppression capacitors. For example, noise suppression capacitors should be positioned as close as possible to the PDN to provide a low-inductance electrical connection between the noise suppression capacitor and the PDN. Higher inductance leads to inefficient use of capacitors, resulting in degraded PDN performance; therefore, lower-inductance electrical connections are generally preferred, especially in low-power devices (e.g., mobile communication devices or other battery-powered devices). However, arranging the ICD(s) adjacent to the dies 110, 130 of the stacked IC devices 200 allows for short, low-inductance electrical connections between the capacitors of the ICD(s) and one or both of the PDNs 212, 232. For example, the capacitors of the ICD(s) 240 can be connected to the PDN 212 of the first die 110 via signal path 264, and the capacitors of the ICD(s) 220 can be connected to the PDN 232 of the second die 130 via signal path 266, or both, thereby providing improved PDN performance.

[0052] In some implementations, the transistor(s) 214 of the first die 110 are electrically connected to the transistor(s) 234 of the second die 130 via the first die interconnect contact 122 and the second die interconnect contact 142. For example, signal path 168 may connect one or more transistors of the transistor(s) 214 and one or more transistors of the transistor(s) 234.

[0053] FIG. 2 The illustrations shown are merely schematic and intended to highlight specific features of the stacked IC device 200. For example, the specific number of contacts and interconnects is illustrative and not limiting. Furthermore, FIG. 2Some internal structures are omitted. For example, the redistribution layer 150 and substrate 154 include internal conductive traces and vias interconnected to form conductive paths. Furthermore, in FIG. 3 In this embodiment, the interconnects between dies 110 and 130 (e.g., to form signal path 168), the interconnects between dies 110 and 130 and the redistribution layer 150, and the interconnects of conductive ICDs 220 and 240 are illustrated using solder bumps, solely to highlight the locations where individual components of the electrical connections are positioned. Other interconnect techniques are used in other embodiments.

[0054] FIG. 3 A schematic cross-sectional view illustrating an example of an exemplary stacked IC device 300 is shown. FIG. 1 The stacked IC device 300 is FIG. 2 Examples of stacked IC devices 100 and / or FIG. 3 Example of a stacked IC device 200. FIG. 1 The stacked IC device 300 includes FIG. 3 Each component and feature in the stacked IC device 100. To highlight other components and features, some of these components and features are... FIG. 1 Not shown or not marked. FIG. 3 The components and features of the stacked IC device 100 are only FIG. 1 The label indicates that it is used in conjunction with... FIG. 3 Same reference numerals as shown in the attached figures.

[0055] exist FIG. 3 In this stacked IC device 300, a first die 110, a second die 130, and one or more additional devices are included. For example, the stacked IC device 300 may include one or more additional devices 320 disposed adjacent to the first die 110, one or more additional devices 310 disposed adjacent to the second die 130, and additional devices disposed above the top die (e.g., the first die 110) of the stacked IC device 300. FIG. 3 One or more additional devices 330, or combinations thereof, in the illustrated orientation. Additional devices 310, 320, 330 may include or correspond to other dies, passive electrical components (e.g., capacitors, inductors, etc.), interposer devices, or combinations thereof. For example, one or more of additional devices 310, 320, 330 may include a memory die or a packaged memory device. For illustration, additional device 330 may include a dynamic random access memory (DRAM) device coupled to a first die 110, a second die 130, or both.

[0056] Additional devices (such as one of the additional devices 310) disposed adjacent to the second die 130 can be electrically connected via the substrate 154 to one or more external contacts in the external contacts 162. For example, in FIG. 3 In this example, the (multiple) additional devices 310 include contacts 312 electrically connected to one or more conductors of the substrate 154. In this example, the contacts 312 and the (multiple) conductors of the substrate 154 provide a signal path between the (multiple) additional devices 310 and the external contacts 162.

[0057] Additionally or alternatively, the additional devices 310 may be electrically connected via the redistribution layer 150 to the first die 110, the second die 130, the additional devices 320, the additional devices 330, or combinations thereof. For example, in FIG. 3 In this example, the (multiple) additional devices 310 include contacts 314 electrically connected to one or more conductors of the redistribution layer 150. In this example, the contacts 314 and the conductors of the redistribution layer 150 provide signal paths between the (multiple) additional devices 310 and the first die 110, the second die 130, the (multiple) additional devices 320, or combinations thereof. As another example, the stacked IC device 300 optionally includes interconnect conductors 362 (e.g., interconnect conductors 362A and 362B) electrically connected to the redistribution layer 150 and to one or more conductors of the second substrate 350 above the first die 110. In this example, the contacts 314, the conductors of the redistribution layer 150, the interconnect conductors 362, and the conductors of the second substrate 350 provide signal paths between the (multiple) additional devices 310 and the (multiple) additional devices 330.

[0058] Additional devices (such as one of the additional devices in additional device 320) disposed adjacent to the first die 110 can be electrically connected to additional device 330 via the second substrate 350. For example, in FIG. 3 In this embodiment, the (multiple) additional devices 320 include contacts 324 electrically connected to one or more conductors of the second substrate 350. In this example, the contacts 324 and the (multiple) conductors of the second substrate 350 can provide a signal path between the (multiple) additional devices 320 and the (multiple) additional devices 330.

[0059] Additionally or alternatively, multiple additional devices 320 may be electrically connected via redistribution layer 150 to the first die 110, the second die 130, multiple additional devices 310, or combinations thereof. For example, in FIG. 3In this example, the (multiple) additional devices 320 include contacts 322 electrically connected to one or more conductors of the redistribution layer 150. In this example, the contacts 322 and the conductors of the redistribution layer 150 provide signal paths between the (multiple) additional devices 320 and the first die 110, the second die 130, the (multiple) additional devices 310, or combinations thereof. As another example, the stacked IC device 300 optionally includes interconnect conductors 352 (e.g., interconnect conductors 352A and 352B) electrically connected to the redistribution layer 150 and to one or more conductors of the substrate 154. In this example, the contacts 322, the conductors of the redistribution layer 150, the interconnect conductors 352, and the conductors of the substrate 154 provide signal paths between the (multiple) additional devices 320 and external contacts 162.

[0060] Although FIG. 3 The additional devices 310 and 320 are illustrated as including contacts on two opposing surfaces (e.g., contact 312 on one side of additional device 310 and contact 314 on the opposite side of additional device 310, and contact 322 on one side of additional device 320 and contact 324 on the opposite side of additional device 320), but in some embodiments, additional devices 310, 320, or both include contacts on only one side. For example, in some embodiments, contact 312 of additional device 310 is omitted, and the signal path to additional device 310 is routed through redistribution layer 150. In some such embodiments, the signal path between contact 314 of additional device 310 and external contact 162 is routed through interconnect conductor 352. As another example, in some embodiments, contact 314 of additional device 310 is omitted, and the signal path to additional device 310 is routed through substrate 154. In some such implementations, the signal paths between the contacts 312 of the (multiple) additional devices 310 and the second die 130, the first die 110, the (multiple) additional devices 320, or the (multiple) additional devices 330 are routed via interconnect conductors 352.

[0061] As another example, in some embodiments, the contacts 324 of the multiple attachments 320 are omitted, and the signal paths to the multiple attachments 320 are routed through the redistribution layer 150. In some such embodiments, the signal paths between the contacts 322 of the multiple attachments 320 and the multiple attachments 330 are routed through interconnect conductors 362. As yet another example, in some embodiments, the contacts 322 of the multiple attachments 320 are omitted, and the signal paths to the multiple attachments 320 are routed through the second substrate 350. In some such embodiments, the signal paths between the contacts 324 of the multiple attachments 320 and the first die 110, the second die 130, the multiple attachments 310, or the external contacts 162 are routed through interconnect conductors 362.

[0062] exist FIG. 3 The illustrated examples show several different types of interconnect conductors. For example, interconnect conductors 352A and 362A correspond to or include through-mold vias (TMVs), such as copper pillars or other conductive pillars extending through molding compound 170. Interconnect conductors 352B and 362B are components of interposer devices 358 and 368, respectively. Interposer devices 358 and 368 may include dies or similar discrete components comprising an interposer substrate and conductive vias extending through the interposer substrate. For example, interposer device 358 includes a conductive via 354 extending through interposer substrate 356, and interposer device 368 includes a conductive via 364 extending through interposer substrate 366. Interposer substrates 356 or 366 may include semiconductor materials, glass or ceramic materials, or organic materials (e.g., polymers). Typically, interconnect conductors can be more tightly packaged in interposer devices 358 and 368 (e.g., having smaller spacing) compared to interconnect conductors formed as TMVs. Therefore, the interposer devices 358 and 368 can be used in specific implementations that require a greater number of interconnect conductors than might be easily accommodated using a TMV, in specific implementations that require a denser interconnect conductor package than might be easily accommodated using a TMV, or subject to other similar constraints.

[0063] FIG. 3 The illustrations shown are merely schematic and intended to highlight specific features of the stacked IC device 300. For example, the specific number of contacts and interconnects is illustrative and not limiting. Furthermore, FIG. 3 Some internal structures are omitted. For example, the redistribution layer 150, substrate 154, and second substrate 350 include internal conductive traces and vias interconnected to form conductive paths. Further, in FIG. 3In this embodiment, the interconnects between dies 110 and 130, the interconnects between dies 110 and 130 and the redistribution layer 150, and the interconnects to (multiple) additional devices 310, 320, and 330 are illustrated using solder bumps, solely to highlight the locations where individual components of the electrical connections are positioned. In other embodiments, other interconnect technologies are used.

[0064] Furthermore, although FIG. 5 to FIG. 9 Examples illustrate both TMVs and interposer devices 358 and 368 used as interconnect conductors in stacked IC devices 300; however, in other embodiments, the interconnect conductors may route all or all TMVs through the interposer device. Similarly, [the following can be used]... Exemplary process for manufacturing a stacked IC device Different combinations of TMV and interposer devices are illustrated. For example, the connection between redistribution layer 150 and the second substrate 350 may be provided by the interposer device, and the connection between redistribution layer 150 and substrate 154 may be provided by the TMV, or vice versa.

[0065] Although FIG. 4A to FIG. 4C An example is illustrated of multiple additional devices 330 coupled to dies 110, 130 via a second substrate 350. However, in other embodiments, one or more of the additional devices 330 are connected to the dies 110, 130 in different ways. For example, in some embodiments, the second substrate 350 is omitted, and a set of redistribution layers is provided between the additional devices 330 and the first die 110. As another example, in some embodiments, the second substrate 350 is omitted, and an interconnect conductor 362 disposed adjacent to the first die 110 is positioned to align with the contacts of the additional devices 330. Further reference FIG. 1 to FIG. 3 These and other examples describe arrangements for connecting any of the stacked IC devices 100, 200, or 300 to one or more additional devices.

[0066] FIG. 4A to FIG. 4C

[0067] In some specific implementations, manufacturing stacked IC devices (e.g., any one of stacked IC devices 100, 200, or 300) involves several processes. FIG. 1 to FIG. 3 Exemplary processes for providing or manufacturing stacked IC devices are illustrated, as shown in references. FIG. 4A to FIG. 4C As described by any of them. In some specific implementations, FIG. 4A to FIG. 4C The process can be used to provide (e.g., during manufacturing). FIG. 4A to FIG. 4C One or more of the stacked IC devices 100, 200, and 300.

[0068] It should be noted that FIG. 4AThe processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the scope of this disclosure. In the description below, reference is made to various exemplary stages of the processes, which are... FIG. 4C Number them using the circled numbers. FIG. 3 Each of the various stages of the illustrated process shows a single stacked IC device being formed. In other specific implementations, multiple stacked IC devices may be formed together concurrently.

[0069] FIG. 1 Stage 1 illustrates the state after the redistribution layer 404 has been formed on substrate 402. In some specific embodiments, substrate 402 is a carrier substrate not included in the final device comprising stacked IC devices (e.g., not included in...). FIG. 2 (In the device 400 illustrated in stage 9). In other embodiments, substrate 402 is the top substrate of the final device. For example, substrate 402 may correspond to FIG. 1 The second substrate 350. In such embodiments, the redistribution layer 404 may be omitted or may be formed within the substrate 402. In some embodiments, such as in FIG. 2 and FIG. 3 In the illustrated example, no redistribution layer or top substrate is disposed above the stacked IC devices in the final device. In such an implementation, the redistribution layer 404 may be omitted. Various deposition and patterning operations can be used to form the redistribution layer 404 to form alternating dielectric and metal layers, wherein the metal layers are patterned to form traces, and selected traces of one metal layer are electrically connected to corresponding selected traces of another metal layer to form signal paths.

[0070] Stage 2 illustrates the state after contacts 406 and interconnect conductors 408 have been formed on redistribution layer 404 (or on substrate 402 if redistribution layer 404 is omitted). For example, one or more electroplating processes and one or more patterning processes can be used to form contacts 406, interconnect conductors 408, or both. In some embodiments, contacts 406 are formed as part of the formation of redistribution layer 404 in stage 1. Contacts 406 and interconnect conductors 408 comprise metals such as copper, silver, tin, another conductor, or alloys thereof, or combinations thereof. In embodiments where no redistribution layer or top substrate is disposed above the stacked IC devices in the final device, contacts 406 and interconnect conductors 408 may be omitted. For example, in the formation of… FIG. 1 and FIG. 2Contacts 406 and interconnect conductors 408 may be omitted during the stacking of IC devices 100 and 200, respectively. In some specific embodiments, interposer devices are used to provide signal paths to the redistribution layer 404 or the substrate 402. For example, FIG. 2 The additional devices 320 may include interposer devices with through-holes. In such embodiments, interconnect conductors 408 may be omitted and additional contacts 406 may be formed for connection to the interposer devices.

[0071] Phase 3 illustrates the state after the first die 410 and optional one or more additional devices 416 are disposed (e.g., attached to) the redistribution layer 404 (or, if the redistribution layer 404 is omitted, on the substrate 402). The first die 410 is positioned such that the active region 412 of the first die 410 faces away from the substrate 402 and the non-active region 414 of the first die 410 faces the substrate 402. The first die 410, the additional devices(s) 416, or combinations thereof can be positioned using automated processes (such as using a robot performing pick-and-place operations) as illustrated in Phase 3. In some specific implementations, the first die 410 is attached to the surface of the redistribution layer 404 (or the substrate 402). If the signal path to the additional devices(s) 416 is routed through contact 406, the additional devices(s) 416 can be coupled to contact 406 using solder. However, if the signal path to the additional devices(s) 416 (e.g., respectively formed in the formation of...) FIG. 3 and FIG. 4B If, during the stacking of IC devices 100 and 200, the routing is not via contact 406, then (a plurality of) additional devices 416 may be attached to the surface of redistribution layer 404 (or substrate 402). (A plurality of) additional devices 416 may correspond to... FIG. 1 to FIG. 3 (Multiple) ICD 220 or FIG. 1 to FIG. 3 Any of the (multiple) additional devices 320.

[0072] FIG. 1 to FIG. 3 Phase 4 illustrates the state after molding compound 418 has been used to at least partially encapsulate the first die 410 and any other optional components attached to the redistribution layer 404 or substrate 402. Molding compound 418 may include, corresponding to FIG. 4C The molding compound 170 may be any of the molding compounds 170 or may be included within the molding compound (e.g., representing a portion thereof). In a particular example, a deposition process, spin coating process, or similar process may be used to apply the molding compound 418, and the molding compound 418 may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners.

[0073] Stage 5 illustrates the state after the formation of the redistribution layer 420 and the formation of the contact 422 and optionally the interconnecting conductor 424. The redistribution layer 420 corresponds to... FIG. 3 A redistribution layer 150 is provided for any of the following: A redistribution layer 420 is electrically connected to circuitry disposed in the active region 412 of the first die 410 and provides signal paths 426 to connect that circuitry to circuitry of another die (e.g., the second die 430 illustrated in stage 6). When interconnect conductor 408 is present, redistribution layer 420 is electrically connected to interconnect conductor 408 and provides signal paths 426 to the first die 410, to contact 422, to one or more of the additional devices 416, or combinations thereof. Additionally, when additional devices 416 are present, redistribution layer 420 may be electrically connected to additional devices 416 and provide signal paths 426 to the first die 410, to contact 422, to interconnect conductor 408, or combinations thereof. Various deposition and patterning operations can be used to form the redistribution layer 420 to form alternating dielectric and metal layers, wherein the metal layers are patterned to form traces, and selected traces of one metal layer are electrically connected to corresponding selected traces of another metal layer to form signal paths. One or more electroplating processes and one or more patterning processes can be used to form contacts 422, interconnect conductors 424, or both, on the redistribution layer 420. Contacts 422 and interconnect conductors 424 comprise metals such as copper, silver, tin, another conductor, or alloys thereof, or combinations thereof. In some specific embodiments, an interposer device is used to provide access from the redistribution layer 420 to external contacts (e.g., FIG. 4C External contact 162, or FIG. 1 to FIG. 3 The signal path of the external contact 444 illustrated in stage 8. For example, FIG. 4C The additional devices 310 may include interposer devices with through-holes. In such embodiments, interconnect conductors 424 may be omitted and additional contacts 422 may be formed for connection to the interposer devices.

[0074] Phase 6 illustrates the state after the second die 430 and optionally one or more additional devices 436 are disposed (e.g., attached) to the redistribution layer 420. The second die 430 is positioned such that the active region 432 of the second die 430 faces the redistribution layer 420 (i.e., the first die 410 and the second die 430 face each other) and the non-active region 434 is oriented away from the redistribution layer 420. The second die 430, the additional devices(s) 436, or combinations thereof may be positioned using automated processes (such as using a robot performing pick-and-place operations) as illustrated in Phase 6. In some specific implementations, the second die 430 is electrically connected to at least a first subset of the contacts 422 of the redistribution layer 420 (e.g., using solder, copper pillars, pad-to-pad bonding, or similar processes) to provide a signal path between the circuitry in the active region 432 of the second die 430 and the circuitry in the active region 412 of the first die 410. The second die 430 is also electrically connected to at least a second subset of the contacts 422 of the redistribution layer 420 (e.g., using solder, copper pillars, pad-to-pad bonding, or a similar process) to provide signal paths between the circuitry in the active region 432 of the second die 430 and other components. For example, the second die 430 may be electrically connected to contacts 422 that provide multiple signal paths between the second die 430 and additional devices 436, 416, interconnect conductors 424, 408, one or more interposer devices, or any combination thereof.

[0075] FIG. 5 to FIG. 9 Phase 7 illustrates the state after the second die 430 has been at least partially encapsulated with molding compound 440 and attached to any other optional components of redistribution layer 420 (e.g., additional devices 436 and / or interconnect conductors 424). Molding compound 440 may include, corresponding to Exemplary package device including a stacked IC device The molding compound 170 may be any of the molding compounds 170 or may be included within the molding compound (e.g., representing a portion thereof). In a particular example, a deposition process, spin coating process, or similar process may be used to apply the molding compound 440, and the molding compound 440 may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners.

[0076] Phase 8 illustrates a state after a substrate 442, including external contacts 444, has been formed on or coupled to the assembly assembly of Phase 7. In some embodiments, the substrate 442 is preformed, and the state illustrated at Phase 8 is achieved by physically and electrically connecting the preformed substrate 442 to the assembly assembly of Phase 7. For example, interconnect conductors 424 may be electrically connected to conductors of the substrate 442 to provide signal paths from interconnect conductors 424 to appropriate external contacts among the external contacts 444. In other embodiments, various deposition and patterning operations are used to form the substrate 442 to form alternating dielectric and metal layers, wherein the metal layers are patterned to form traces, and selected traces of one metal layer are electrically connected to corresponding selected traces of another metal layer to form signal paths.

[0077] Phase 9 illustrates the state after substrate 402 has been removed from device 400 and optionally after solder balls have been attached to external contacts 444 to form ball grid array 450. If multiple instances of device 400 are formed concurrently, customized operations (e.g., cutting to separate the device) may also be performed between phases 8 and 9. In some specific embodiments, device 400 includes a second substrate, in which case substrate 402 may not be removed between phases 8 and 9. FIG. 5 to FIG. 9 After stage 9, the formation of device 400 is complete. However, in some specific embodiments, one or more devices in device 400 may be integrated into a larger device (e.g., FIG. 5 to FIG. 9 Within one of the devices 500, 600, 700, 800 or 900.

[0078] FIG. 1 to FIG. 3

[0079] FIG. 5 to FIG. 9 Various examples of packaged IC devices including stacked IC devices 502 and one or more additional devices 504 are illustrated. FIG. 5 In each of the stacked IC devices 502, there may be or correspond to FIG. 5 Any of the stacked IC devices 100, 200, and 300. For example, FIG. 6The stacked IC device 502 includes a first die 110 and a second die 130, face-to-face coupled, a redistribution layer 150, and interconnect conductors 152. These components are external to the first die 110 and the second die 130 and electrically connected to the redistribution layer 150 to provide a signal path from the first die 110, the second die 130, or both to external contacts 162 of the substrate 154. Further, the additional devices 504 may correspond to or include any of the following: additional devices 310, 320, 330; multiple ICDs 220, 240; other passive devices; other semiconductor dies; or combinations thereof. For example, one of the additional devices 504 may include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a memory device, a processor, a communication device, or other circuitry.

[0080] FIG. 7 An example of a packaged IC device 500 with a dual-substrate configuration is illustrated. For example, in... FIG. 7 In this configuration, one or more of the stacked IC device 502 and additional devices 504 are disposed between the substrate 154 and the second substrate 510. The second substrate 510 may, for example, harden the packaged IC device 500 to reduce warpage. The second substrate 510 is optional and may be omitted in some specific embodiments.

[0081] FIG. 8 An example of a packaged IC device 600 is illustrated, wherein a redistribution layer 150 is extended to enable stacking of additional devices 504. In this example, interconnect conductors 152 may include interconnect conductor 152A for routing signals between the stacked IC device 502 and external contacts 162, and interconnect conductor 152B for routing signals between the additional devices 504 and external contacts 162.

[0082] FIG. 8 An example of a packaged IC device 700 with a molded embedded package (MEP) structure is illustrated. For example, in FIG. 8 In this packaged IC device 700, a stacked IC device 502 and one or more additional devices among a plurality of additional devices 504 optionally disposed between a substrate 154 and a second substrate 702. Optionally, the second substrate 702 may include a set of redistribution layers. Interconnect conductors 704 are electrically connected to the redistribution layers 150 and the second substrate 702 and are configured to provide signal paths between one or more additional devices 706 mounted on the second substrate 702 and other devices of the packaged IC device 700, external contacts 162, or other components thereof. For example, interconnect conductors 704 may provide signal paths between additional devices 706 and one or more of the additional devices 504, or combinations thereof, including a first die 110, a second die 130, or a plurality of additional devices 504.

[0083] FIG. 9 Another example is illustrated by a packaged IC device 800 having a molded embedded package (MEP) structure. For example, in FIG. 5 to FIG. 9 In the packaged IC device 800, there are stacked IC devices 502 and one or more additional devices 504 optionally disposed between substrate 154 and second substrate 702. FIG. 1 to FIG. 9 (Not shown in the image). Optionally, the second substrate 702 may include a set of redistribution layers. Interconnect conductors 802 are electrically connected to substrate 154 and the second substrate 702 and are configured to provide signal paths between one or more additional devices 706 mounted on the second substrate 702 and other devices of the packaged IC device 800, external contacts 162, or both. For example, interconnect conductors 802 may provide signal paths between additional devices 706 and one or more of the following additional devices: first die 110, second die 130, (a plurality of) additional devices 504, or combinations thereof.

[0084] Exemplary flowchart of a method for manufacturing a stacked IC device An example of a packaged IC device 900 is illustrated, wherein interconnect conductors 902 coupled to redistribution layer 150 are coupled to additional devices 706. In some specific implementations of the packaged IC device 900, molding compound 170 is omitted from at least a portion of the region between redistribution layer 150 and additional devices 706, which provides improved thermal management.

[0085] FIG. 10 The specific examples illustrated herein are merely illustrative and not limiting. In other specific implementations, the stacked IC device 502 may be used with package structures other than those specifically illustrated.

[0086] Although FIG. 10 Each of these examples illustrates a stacked IC device comprising at least two dies, but in other examples, the stacked IC device may comprise more than two dies, and any two such dies may be positioned and interconnected as described herein. Further, an apparatus comprising one or more of the stacked IC devices disclosed herein may include: components such as power management integrated circuits (PMICs), application processors, modems, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, transmitters, receivers, gallium arsenide (GaA) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memories, power management processors, and / or combinations thereof. In such apparatuses, the stacked IC device may operate as any of these components (or combinations thereof) including active circuitry.

[0087] FIG. 1 to FIG. 9

[0088] In some specific implementations, manufacturing stacked IC devices involves several processes. FIG. 10 An exemplary flowchart illustrating a method 1000 for providing or manufacturing stacked IC devices is shown. In some specific implementations, FIG. 1 to FIG. 3 Method 1000 can be used to provide or manufacture FIG. 5 to FIG. 9 Any of the stacked IC devices 100, 200, 300, 400 or 502.

[0089] It should be noted that FIG. 1 Method 1000 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated devices. In some specific implementations, the order of the processes may be changed or modified.

[0090] Method 1000 includes electrically connecting a first die to a second die face-to-face at a frame 1002 via a first set of die interconnect contacts disposed on a first surface of a first die and a second set of die interconnect contacts disposed on a second surface of a second die, wherein the face of the die corresponds to the surface of the die defining an active region of the die, the active region including circuitry. For example, FIG. 3 or FIG. 1 to FIG. 3 The first die 110 of either of them can be electrically connected face-to-face with the second die 130. For example... FIG. 5 to FIG. 9 and FIG. 4B As illustrated, in this arrangement, the first die interconnect contact 122 of the first die 110 is electrically connected to the second die interconnect contact 142 of the second die 110.

[0091] Method 1000 further includes forming at frame 1004 one or more redistribution layers electrically connected to a set of redistribution contacts on the first surface, the second surface, or both. For example, FIG. 4B or FIG. 1 The redistribution layer 150 of any of them may be electrically connected to the redistribution contact 124 of the first die 110, the redistribution contact 144 of the second die 130, or both.

[0092] Phases 4 to 6 illustrate and describe examples of operations for electrically connecting the first die to the second die face-to-face via a first set of die interconnect contacts disposed on a first surface of the first die and a second set of die interconnect contacts disposed on a second surface of the second die, and for forming one or more redistribution layers electrically connected to a set of redistribution contacts on the first surface, the second surface, or both. For example, the first die 410 may be positioned face-up (to... FIG. 2(The orientation illustrated in stage 4), and the redistribution layer 420 may be formed on the first die 410 and electrically connected to the first die 410. A contact 422 may be formed on the redistribution layer 420, and the second die 430 may be positioned face down (to...). FIG. 3 (The orientation illustrated in stage 6) and electrically connected to contact 422, such that signal path 426 is formed between the die interconnect contacts of the first die and the second die, and such that signal path 426 is formed between other contacts of the first die, the second die, or both, and other components such as (a plurality of) additional devices 416, (a plurality of) additional devices 436, external contact 444, or combinations thereof.

[0093] Method 1000 further includes forming a set of interconnects at block 1006, the set of interconnects being external to the first die and the second die and electrically connected to the redistribution layer to provide a signal path from the first die, the second die, or both to a set of external contacts. For example, the set of interconnects external to the first die and the second die may include or correspond to FIG. 3 or FIG. 1 The interconnect conductor 152. As another example, the set of interconnects outside the first die and outside the second die may include or correspond to FIG. 4C Interconnecting conductors 352 or 362, or FIG. 4B The through-hole (e.g., through-silicon via or through-glass via) of one of the interposer devices 358 and 368.

[0094] In some embodiments, method 1000 includes coupling the back side of the second die (where the back side of the second die is opposite to the second surface) to a first side of the substrate. In such embodiments, the external contact is coupled to a second side of the substrate. For example, in FIG. 4C In this process, the back side 134 of the second die 130 is coupled to the first side 156 of the substrate 154, and the external contact 162 is disposed on the second side 158 of the substrate 154. FIG. 4A Stages 8 and 9 illustrate and describe the operation for coupling the back side of the second die to the first side of the substrate.

[0095] In some embodiments, the first die does not have through-silicon vias (TSVs). In some such embodiments, the first die includes a first back surface and a first non-active region adjacent to the first back surface, and the first back surface does not have electrical contacts. Further, in some embodiments, the second die also does not have, or alternatively does not have, TSVs. In some such embodiments, the second die includes a second back surface and a second non-active region adjacent to the second back surface, and the second back surface does not have electrical contacts.

[0096] In some embodiments, method 1000 further includes electrically connecting the first die, the second die, or both to one or more additional devices. In some such embodiments, the signal path between the first die and one of the additional devices(s), the signal path between the second die and one of the additional devices(s), or both, can be routed through the redistribution layer. For example, the first die 110, the second die 130, or both can be electrically connected to any of the additional devices(s) 310, 320, 330 via conductors of the redistribution layer 150. In some such embodiments, the signal path between the first die and one of the additional devices(s), the signal path between the second die and one of the additional devices(s), or both, can be routed through a substrate. For example, the first die 110, the second die 130, or both can be electrically connected to any of the additional devices(s) 310, 320, 330 via conductors of substrate 154 or substrate 350. The (multiple) additional devices 310, 320, 330 may include, for example, additional dies (e.g., memory), passive components (e.g., integrated capacitors), interposer devices, etc.

[0097] In some embodiments, method 1000 further includes encapsulating the first die, the second die, the one or more redistribution layers, and the set of interconnects at least partially in a molding compound. (Reference) FIG. 4B Phase 4 and Exemplary electronic device Phase 7 describes examples of operations for forming molding compounds 418 and 440. In some embodiments, method 1000 further includes forming one or more through-holes. For example, at least one of the interconnects in the set may include a through-hole. (Reference) FIG. 11 Phase 2 and FIG. 1 to FIG. 9 Phase 5 describes an example of the operation used to form interconnect conductors 408 and 424 as through-holes.

[0098] FIG. 11

[0099] FIG. 1 to FIG. 11 Examples include FIG. 1 to FIG. 11 Device 1100 may include any of the stacked IC devices 100, 200, 300, 400, 502, or various electronic devices integrated therewith. For example, mobile phone device 1102, laptop computer device 1104, fixed-location terminal device 1106, wearable device 1108, or vehicle 1110 (e.g., automotive or aerial equipment) may include device 1100. Device 1100 may include, for example, any of the devices 500, 600, 700, 800, or 900 described herein and / or any of 100, 200, 300, 400, or 502. FIG. 1 to FIG. 11The devices 1102, 1104, 1106, and 1108 illustrated herein, as well as vehicle 1110, are merely exemplary. Other electronic devices may also feature device 1100, including but not limited to groups of devices (e.g., groups of electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0100] ​ One or more of the illustrated components, processes, features, and / or functions may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that in this disclosure… ​ The corresponding descriptions are not limited to bare dies and / or ICs. In some specific implementations, ​ The descriptions and their corresponding information can be used to manufacture, create, supply, and / or produce devices and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, IC devices, device packages, IC packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0101] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0102] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, then object A and object C can still be considered coupled to each other, even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrical coupling” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms “enclosing,” “enclosing,” and / or any derivative meaning can refer to an object that partially or completely encloses another object. The terms “top” and “bottom” are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component can mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. Values ​​from about X to XX can refer to values ​​between X and XX, including both X and XX. Values ​​between X and XX can be discrete or continuous. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X".For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "Multiple" components can include all possible components or only some of all possible components. For example, if a device comprises ten components, the term "multiple components" can refer to all ten components or a subset of those ten components.

[0103] In some embodiments, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0104] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0105] Further examples are described below to facilitate understanding of this disclosure.

[0106] According to Embodiment 1, a stacked integrated circuit (IC) device includes: a first die having a first surface, a first active region adjacent to the first surface, a first circuit disposed in the first active region, and a first die interconnect contact disposed on the first surface and electrically connected to the first circuit; a second die having a second surface, a second active region adjacent to the second surface, a second circuit disposed in the second active region, and a second die interconnect contact disposed on the second surface and electrically connected to the second circuit, wherein the first surface is oriented toward the second surface, and wherein the first die interconnect contact is electrically connected to the second die interconnect contact; a set of redistribution layers electrically connected to the redistribution contacts on the first surface, the second surface, or both; and interconnect conductors located outside the first die and outside the second die and electrically connected to the redistribution layers to provide a signal path from the first die, the second die, or both to the set of external contacts.

[0107] Example 2 includes a stacked IC device according to Example 1, the stacked IC device further including a substrate, wherein the back side of the second die is coupled to a first side of the substrate, and the external contact is coupled to a second side of the substrate, wherein the back side of the second die is opposite to the second side.

[0108] Example 3 includes a stacked IC device according to Example 1 or Example 2, wherein the first die has no through-silicon vias.

[0109] Example 4 includes a stacked IC device according to any one of Examples 1 to 3, wherein the first die further includes a first back surface and a first non-active region adjacent to the first back surface, and wherein the first back surface has no electrical contacts.

[0110] Example 5 includes a stacked IC device according to any one of Examples 1 to 4, wherein the second die has no through-silicon vias.

[0111] Example 6 includes a stacked IC device according to any one of Examples 1 to 5, wherein the second die further includes a second back surface and a second non-active region adjacent to the second back surface, and wherein the second back surface has no electrical contacts.

[0112] Example 7 includes a stacked IC device according to any one of Examples 1 to 6, wherein the first circuit includes one or more first transistors and a first power distribution network (PDN), and wherein the second circuit includes one or more second transistors and a second PDN.

[0113] Example 8 includes a stacked IC device according to Example 7, wherein the first PDN is electrically connected to the second PDN via the first die interconnect contact and the second die interconnect contact.

[0114] Example 9 includes a stacked IC device according to Example 7 or Example 8, wherein one or more first transistors are electrically connected to one or more second transistors via the first die interconnect contact and the second die interconnect contact.

[0115] Example 10 includes a stacked IC device according to any one of Examples 7 to 9, and further includes at least one first integrated capacitor device (ICD) disposed between the first surface and the set of external contacts and electrically connected to the first PDN.

[0116] Example 11 includes a stacked IC device according to any one of Examples 7 to 10, and further includes at least one second ICD, which is disposed adjacent to the first die and electrically connected to the second PDN.

[0117] Example 12 includes a stacked IC device according to any one of Examples 1 to 11, and further includes an interposer device comprising a plurality of conductive vias electrically connected to the redistribution layer and the plurality of external contacts.

[0118] Example 13 includes a stacked IC device according to any one of Examples 1 to 12, and further includes a molding compound that at least partially encapsulates the first die, the second die, the redistribution layer, and the interconnect conductor.

[0119] Example 14 includes a stacked IC device according to Example 13, wherein at least one of the interconnect conductors includes a through-hole.

[0120] Example 15 includes a stacked IC device according to any one of Examples 1 to 14, and further includes at least one additional device disposed adjacent to the first die and electrically connected to the first circuit, the second circuit, or both through the redistribution layer.

[0121] Example 16 includes a stacked IC device according to any one of Examples 1 to 15, and further includes at least one additional device disposed adjacent to the second die and electrically connected to the first circuit, the second circuit, or both via the interconnect conductor and the redistribution layer.

[0122] Example 17 includes a stacked IC device according to any one of Examples 1 to 16, and further includes at least one additional device and a second interconnect conductor, wherein the first die is disposed between the at least one additional device and the redistribution layer, and wherein additional circuitry of the at least one additional device is electrically connected to the first circuit, the second circuit, or both via the second interconnect conductor and the redistribution layer.

[0123] Example 18 includes a stacked IC device according to any one of Examples 1 to 17, wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet.

[0124] Example 19 includes a stacked IC device according to Example 18, wherein the first circuit includes one or more first functional circuit blocks, and the second circuit includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

[0125] According to embodiment 20, a method includes: electrically connecting a first die and a second die face-to-face using a first die interconnect contact disposed on a first surface of a first die and a second die interconnect contact disposed on a second surface of a second die, wherein the face of the die corresponds to a surface of the die defining an active region of the die, the active region including circuitry; forming a set of redistribution layers electrically connected to redistribution contacts on the first surface, the second surface, or both; and forming interconnect conductors outside the first die and outside the second die and electrically connected to the redistribution layers to provide a signal path from the first die, the second die, or both to the set of external contacts.

[0126] Example 21 includes the method according to Example 20, the method further comprising coupling the back side of the second die to a first side of a substrate, wherein the external contact is coupled to a second side of the substrate, and wherein the back side of the second die is opposite to the second side.

[0127] Example 22 includes the method according to Example 20 or Example 21, wherein the first die has no through-silicon vias.

[0128] Example 23 includes the method according to any one of Examples 20 to 22, wherein the first die further includes a first back surface and a first non-active region adjacent to the first back surface, and wherein the first back surface has no electrical contacts.

[0129] Example 24 includes the method according to any one of Examples 20 to 23, wherein the second die has no through-silicon vias.

[0130] Example 25 includes the method according to any one of Examples 20 to 24, wherein the second die further includes a second back surface and a second non-active region adjacent to the second back surface, and wherein the second back surface has no electrical contacts.

[0131] Example 26 includes the method according to any one of Examples 20 to 25, wherein the first active region of the first die includes a first circuit including one or more first transistors and a first power distribution network (PDN), and wherein the second active region of the second die includes a second circuit including one or more second transistors and a second PDN.

[0132] Example 27 includes the method according to Example 26, wherein the face-to-face electrical connection between the first die and the second die includes electrically connecting the first PDN to the second PDN through the first die interconnect contact and the second die interconnect contact.

[0133] Example 28 includes the method according to Example 26 or Example 27, wherein electrically connecting the first die to the second die face-to-face includes electrically connecting the one or more first transistors to the one or more second transistors via the first die interconnect contact and the second die interconnect contact.

[0134] Example 29 includes the method according to any one of Examples 26 to 28, and further includes electrically connecting at least one first integrated capacitor device (ICD) disposed between the first surface and the set of external contacts to the first PDN.

[0135] Example 30 includes the method according to any one of Examples 26 to 29, and further includes electrically connecting at least one second ICD disposed adjacent to the first die to the second PDN.

[0136] Example 31 includes the method according to any one of Examples 26 to 30, and further includes electrically connecting an interposer device to the redistribution layer and the plurality of external contacts, wherein the interposer device includes a plurality of conductive vias.

[0137] Example 32 includes the method according to any one of Examples 20 to 31, and further includes encapsulating the first die, the second die, the redistribution layer and the interconnect conductor at least partially in a molding compound.

[0138] Example 33 includes the method according to Example 32, and further includes forming one or more through-holes, wherein at least one of the interconnect conductors includes a through-hole.

[0139] Example 34 includes the method according to any one of Examples 20 to 33, and further includes electrically connecting at least one additional device to a first circuit of the first die, a second circuit of the second die, or both, through the redistribution layer.

[0140] According to embodiment 35, an apparatus includes: a substrate having a set of external contacts on a second side; and a stacked integrated circuit (IC) device located on a first side of the substrate, the stacked IC device including: a first die having a first surface, a first active region adjacent to the first surface, a first circuit disposed in the first active region, and a first die interconnect contact disposed on the first surface and electrically connected to the first circuit; a second die having a second surface, a second active region adjacent to the second surface, a second circuit disposed in the second active region, and a second die interconnect contact disposed on the second surface and electrically connected to the second circuit, wherein the first surface is oriented toward the second surface, and wherein the first die interconnect contact is electrically connected to the second die interconnect contact; a set of redistribution layers electrically connected to the redistribution contacts on the first surface, the second surface, or both; and interconnect conductors outside the first die and outside the second die and electrically connected to the redistribution layers to provide a signal path from the first die, the second die, or both to the set of external contacts.

[0141] Example 36 includes the device according to Example 35, wherein the back side of the second die is coupled to the first side of the substrate, and wherein the back side of the second die is opposite to the second side.

[0142] Example 37 includes the device according to Example 35 or Example 36, wherein the first die has no through-silicon vias.

[0143] Example 38 includes the device according to any one of Examples 35 to 37, wherein the first die further includes a first back surface and a first non-active region adjacent to the first back surface, and wherein the first back surface has no electrical contacts.

[0144] Example 39 includes the device according to any one of Examples 35 to 38, wherein the second die has no through-silicon vias.

[0145] Example 40 includes the device according to any one of Examples 35 to 39, wherein the second die further includes a second back surface and a second non-active region adjacent to the second back surface, and wherein the second back surface has no electrical contacts.

[0146] Example 41 includes the device according to any one of Examples 35 to 40, wherein the first circuit includes one or more first transistors and a first power distribution network (PDN), and wherein the second circuit includes one or more second transistors and a second PDN.

[0147] Example 42 includes the device according to Example 41, wherein the first PDN is electrically connected to the second PDN via the first die interconnect contact and the second die interconnect contact.

[0148] Example 43 includes the device according to Example 41 or Example 42, wherein one or more first transistors are electrically connected to one or more second transistors via the first die interconnect contact and the second die interconnect contact.

[0149] Example 44 includes a device according to any one of Examples 41 to 43, wherein the stacked IC device further includes at least one first integrated capacitor device (ICD) disposed between the first surface and the first side of the substrate and electrically connected to the first PDN.

[0150] Example 45 includes a device according to any one of Examples 41 to 44, wherein the stacked IC device further includes at least one second ICD, the at least one second ICD being disposed adjacent to the first die and electrically connected to the second PDN.

[0151] Example 46 includes a device according to any one of Examples 41 to 45, wherein the stacked IC device further includes an interposer device, the interposer device including a plurality of conductive vias electrically connected to the redistribution layer and the plurality of external contacts.

[0152] Example 47 includes a device according to any one of Examples 35 to 46, wherein the stacked IC device further includes a molding compound that at least partially encapsulates the first die, the second die, the redistribution layer, and the interconnect conductor.

[0153] Example 48 includes the device according to Example 47, wherein at least one of the interconnect conductors includes a through-hole.

[0154] Example 49 includes a device according to any one of Examples 35 to 48, wherein the stacked IC device further includes at least one additional device disposed adjacent to the first die and electrically connected to the first circuit, the second circuit, or both through the redistribution layer.

[0155] Example 50 includes a device according to any one of Examples 35 to 49, wherein the stacked IC device further includes at least one additional device disposed adjacent to the second die and electrically connected to the first circuit, the second circuit, or both via the interconnect conductor and the redistribution layer.

[0156] Example 51 includes the device according to any one of Examples 35 to 50, and further includes at least one additional device coupled to the stacked IC device via a second interconnect conductor, wherein the first die is disposed between the at least one additional device and the redistribution layer, and wherein additional circuitry of the at least one additional device is electrically connected to the first circuit, the second circuit, or both via the second interconnect conductor and the redistribution layer.

[0157] Example 52 includes the device according to any one of Examples 35 to 51, wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet.

[0158] Example 53 includes the device according to Example 52, wherein the first circuit includes one or more first functional circuit blocks, and the second circuit includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

[0159] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be exemplary and not to limit the scope of the appended claims. Therefore, the teachings herein can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A stacked integrated circuit (IC) device, the stacked integrated circuit (IC) device comprising: A first die, the first die having a first surface, a first active region adjacent to the first surface, a first circuit disposed in the first active region, and a first die interconnect contact disposed on the first surface and electrically connected to the first circuit; The second die has a second surface, a second active region adjacent to the second surface, a second circuit disposed in the second active region, and a second die interconnect contact disposed on the second surface and electrically connected to the second circuit, wherein the first surface is oriented toward the second surface, and wherein the first die interconnect contact is electrically connected to the second die interconnect contact. A set of redistribution layers, the set of redistribution layers being electrically connected to redistribution contacts on the first surface, the second surface, or both; and Interconnect conductors are located outside the first die and outside the second die and are electrically connected to the redistribution layer to provide a signal path from the first die, the second die, or both to a set of external contacts.

2. The stacked IC device of claim 1, further comprising a substrate, wherein the back side of the second die is coupled to a first side of the substrate, and the external contact is coupled to a second side of the substrate, wherein the back side of the second die is opposite to the second side.

3. The stacked IC device of claim 1, wherein the first die and the second die have no through-silicon vias.

4. The stacked IC device of claim 1, wherein the first die further includes a first back surface and a first non-active region adjacent to the first back surface, and wherein the first back surface has no electrical contacts.

5. The stacked IC device of claim 1, wherein the second die further includes a second back surface and a second non-active region adjacent to the second back surface, and wherein the second back surface has no electrical contacts.

6. The stacked IC device of claim 1, wherein the first circuit includes one or more first transistors, and the second circuit includes one or more second transistors, and wherein the one or more first transistors are electrically connected to the one or more second transistors via the first die interconnect contact and the second die interconnect contact.

7. The stacked IC device of claim 1, further comprising at least one first integrated capacitor device (ICD) disposed between the first surface and the set of external contacts and electrically connected to the power distribution network (PDN) of the first die.

8. The stacked IC device of claim 1, further comprising at least one second ICD, the at least one second ICD being disposed adjacent to the first die and electrically connected to the PDN of the second die.

9. The stacked IC device of claim 1, further comprising an interposer device, the interposer device including a plurality of conductive vias electrically connected to the redistribution layer and the plurality of external contacts.

10. The stacked IC device of claim 1, further comprising a molding compound that at least partially encapsulates the first die, the second die, the redistribution layer, and the interconnect conductor.

11. The stacked IC device of claim 10, wherein at least one of the interconnect conductors comprises a through-hole.

12. The stacked IC device of claim 1, further comprising at least one additional device, the at least one additional device being disposed adjacent to the first die and electrically connected to the first circuit, the second circuit, or both through the redistribution layer.

13. The stacked IC device of claim 1, further comprising at least one additional device disposed adjacent to the second die and electrically connected to the first circuit, the second circuit, or both via the interconnect conductor and the redistribution layer.

14. The stacked IC device of claim 1, further comprising at least one additional device and a second interconnect conductor, wherein the first die is disposed between the at least one additional device and the redistribution layer, and wherein additional circuitry of the at least one additional device is electrically connected to the first circuitry, the second circuitry, or both via the second interconnect conductor and the redistribution layer.

15. The stacked IC device of claim 1, wherein the first die is a first chiplet, and the second die is a second chiplet designed to operate in conjunction with the first chiplet.

16. The stacked IC device of claim 15, wherein the first circuit includes one or more first functional circuit blocks, and the second circuit includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

17. A method, the method comprising: The first die and the second die are electrically connected face to face using a first die interconnect contact disposed on a first surface of the first die and a second die interconnect contact disposed on a second surface of the second die, wherein the face of the die corresponds to the surface of the die that defines the active region of the die, and wherein the active region includes a circuit. A set of redistribution layers is formed, the set of redistribution layers being electrically connected to redistribution contacts on the first surface, the second surface, or both; as well as Interconnect conductors are formed outside the first die and outside the second die and electrically connected to the redistribution layer to provide a signal path from the first die, the second die, or both to a set of external contacts.

18. The method of claim 17, further comprising coupling the back side of the second die to a first side of a substrate, wherein the external contact is coupled to a second side of the substrate, and wherein the back side of the second die is opposite to the second side.

19. The method of claim 17, further comprising electrically connecting an interposer device to the redistribution layer and the plurality of external contacts, wherein the interposer device includes a plurality of conductive vias.

20. The method of claim 17, further comprising encapsulating at least partially the first die, the second die, the redistribution layer, and the interconnect conductor in a molding compound.

21. The method of claim 20, further comprising forming one or more through-holes, wherein at least one of the interconnect conductors includes a through-hole.

22. The method of claim 17, further comprising electrically connecting at least one additional device to a first circuit of the first die, a second circuit of the second die, or both, through the redistribution layer.

23. An apparatus, the apparatus comprising: Substrate, the substrate having a set of external contacts on a second side; and A stacked integrated circuit (IC) device, the stacked integrated circuit (IC) device being located on a first side of the substrate, the stacked IC device comprising: A first die, the first die having a first surface, a first active region adjacent to the first surface, a first circuit disposed in the first active region, and a first die interconnect contact disposed on the first surface and electrically connected to the first circuit; The second die has a second surface, a second active region adjacent to the second surface, a second circuit disposed in the second active region, and a second die interconnect contact disposed on the second surface and electrically connected to the second circuit, wherein the first surface is oriented toward the second surface, and wherein the first die interconnect contact is electrically connected to the second die interconnect contact. A set of redistribution layers, said set of redistribution layers being electrically connected to redistribution contacts on the first surface, the second surface, or both; and Interconnect conductors, located outside the first die and outside the second die and electrically connected to the redistribution layer, provide a signal path from the first die, the second die, or both to the set of external contacts.

24. The device of claim 23, wherein the back side of the second die is coupled to the first side of the substrate, and wherein the back side of the second die is opposite to the second side.

25. The device of claim 23, wherein the stacked IC device further comprises an interposer device, the interposer device comprising a plurality of conductive vias electrically connected to the redistribution layer and the plurality of external contacts.

26. The device of claim 23, wherein the stacked IC device further comprises a molding compound that at least partially encapsulates the first die, the second die, the redistribution layer, and the interconnect conductor.

27. The device of claim 26, wherein at least one of the interconnecting conductors comprises a through-hole.

28. The device of claim 23, wherein the stacked IC device further comprises at least one additional device disposed adjacent to the first die and electrically connected to the first circuit, the second circuit, or both through the redistribution layer.

29. The device of claim 23, wherein the stacked IC device further comprises at least one additional device disposed adjacent to the second die and electrically connected to the first circuit, the second circuit, or both via the interconnect conductor and the redistribution layer.

30. The device of claim 23, further comprising at least one additional device coupled to the stacked IC device via a second interconnect conductor, wherein the first die is disposed between the at least one additional device and the redistribution layer, and wherein additional circuitry of the at least one additional device is electrically connected to the first circuitry, the second circuitry, or both via the second interconnect conductor and the redistribution layer.

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