A power cycling test method and apparatus for a power semiconductor device

Abstract

This invention provides a power cycle testing method and apparatus for power semiconductor devices, relating to the field of semiconductor device testing technology. It is applied to a test circuit containing multiple power units. The method includes: applying a periodic switching drive signal to the test circuit, causing the switching transistors within the test circuit to operate in a dynamic switching mode simulating actual operating conditions, thereby applying cyclic electrothermal stress to the power semiconductor device under test (DUT) contained in the test circuit; for the same test circuit, changing the drive signal to a measurement drive signal to switch the test circuit to a static conduction mode, thereby forming a DC current path for measuring the on-state voltage drop of the DUT; and measuring the on-state voltage drop of the DUT when a stable current flows through it in the static conduction mode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing technology, and in particular to a power cycle testing method and apparatus for power semiconductor devices. Background Technology

[0002] Power modules such as IGBTs (Insulated Gate Bipolar Transistors) are core components of power electronic systems, and their reliability directly affects the long-term stable operation of the entire system. In special applications such as accelerator pulse power supplies, IGBT modules need to withstand periodically changing pulse currents, causing repeated fluctuations in their junction temperature, which in turn leads to aging failures such as solder layer fatigue and bond wire detachment. Therefore, conducting power cycle aging tests on IGBT modules to evaluate their lifespan and reliability is of significant engineering importance.

[0003] Currently, the internationally accepted method is the power cycling test method specified in standards such as IEC 60747-9:2007. This method is typically based on a DC test circuit, applying a periodic large current to the IGBT to cause its junction temperature to cycle within a set range until the device fails. Although this method is simple and easy to implement, its test conditions differ significantly from the complex electrothermal stress environment experienced by IGBTs in actual applications. Especially in accelerator pulse power supplies, where IGBTs operate in AC chopper or H-bridge topologies and are subjected to AC pulse currents, their current change rate and temperature gradient are drastically different from DC test conditions. Therefore, test results based on DC testing often fail to accurately reflect the aging behavior and lifespan characteristics of the device under actual operating conditions, reducing the engineering reference value of the test.

[0004] Furthermore, most existing power cycling test devices focus on implementing the aging process, but they still fall short in terms of real-time and accurate monitoring of device status (such as on-state voltage drop) during the aging process. On-state voltage drop is a key parameter reflecting the aging degree of IGBTs, but it is difficult to measure accurately under AC operating conditions. It is often affected by factors such as circuit topology, switching noise, and measurement timing, resulting in unstable or unreliable measurement results. Summary of the Invention

[0005] This invention provides a power cycling test method and apparatus for power semiconductor devices, which solves the defects of existing power cycling test methods that are disconnected from the actual working state of the devices, resulting in limited reference value of test results, and difficulty in accurately measuring aging characteristic parameters in dynamic tests simulating real working conditions, thereby achieving reliable measurement of power semiconductor devices under near-real working conditions.

[0006] This invention provides a power cycling test method for power semiconductor devices, applied to a test circuit comprising multiple power units, the method comprising:

[0007] A periodic switching drive signal is applied to the test circuit to make the switching transistor in the test circuit work in a dynamic switching mode that simulates actual working conditions, so as to apply cyclic electrothermal stress to the power semiconductor device under test contained in the test circuit.

[0008] For the same test circuit, the drive signal is changed to a measurement drive signal to switch the test circuit to a static conduction mode, thereby forming a DC current path for measuring the on-state voltage drop of the power semiconductor device under test, wherein:

[0009] When the test circuit is a circuit including multiple H-bridge units connected in a cascade manner, the step of switching the test circuit to a static conduction mode includes: controlling the two power semiconductor devices on the diagonal of each H-bridge unit to a constant conduction state, and applying a positive DC voltage to the cascaded H-bridge units to form the DC current path through all the constant conduction devices.

[0010] When the test circuit is a three-phase full-bridge circuit, the step of switching the test circuit to the static conduction mode includes: selecting two phases of the three phases of the three-phase full-bridge circuit to apply a positive DC voltage, and controlling the power semiconductor devices in at least two bridge arms to a constant conduction state, so as to form the DC current path flowing through the at least two bridge arms using the DC bus.

[0011] When the test circuit is a circuit including multiple H-bridge units connected in parallel, the step of switching the test circuit to a static conduction mode includes: switching one of the multiple parallel H-bridge units to the static conduction mode in a time-sequential manner, while disabling other H-bridge units, so as to form the DC current path flowing through the H-bridge unit switched to the static conduction mode.

[0012] When the test circuit is a DC-DC chopper circuit, the step of switching the test circuit to the static conduction mode includes: configuring one or more switching devices in the DC-DC chopper circuit to establish a stable DC current path in the power semiconductor device under test;

[0013] In the static conduction mode, the on-state voltage drop of the power semiconductor device under test is measured when a stable current flows through it.

[0014] According to the power cycling test method for power semiconductor devices provided by the present invention, when the test circuit is a circuit including multiple H-bridge units connected in a cascaded manner, the step of applying a positive DC voltage to the cascaded H-bridge units specifically includes:

[0015] A positive DC voltage is applied to both ends of the cascaded H-bridge unit chain so that the DC current path passes through all power semiconductor devices controlled to a constant conduction state.

[0016] According to the power cycling test method for power semiconductor devices provided by the present invention, the dynamic switching mode specifically includes switching between at least three operating states:

[0017] The state in which two switching devices on any diagonal of the H-bridge topology are turned on;

[0018] The state where the upper transistor of the first arm of the H-bridge is turned on, and the current freewheels through the anti-parallel diode of the lower transistor of the second arm;

[0019] The state where the lower diode of the first arm of the H-bridge is turned on, and the current freewheels through the anti-parallel diode of the upper diode of the second arm.

[0020] According to the power cycling test method for power semiconductor devices provided by the present invention, when the test circuit is a three-phase full-bridge circuit, the step of controlling the power semiconductor devices in at least two bridge arms to a constant conduction state specifically includes:

[0021] The upper tube of the first phase bridge arm and the lower tube of the second phase bridge arm are controlled to a constant conducting state to form the DC current path flowing through the upper tube of the first phase bridge arm and the lower tube of the second phase bridge arm.

[0022] According to the power cycling test method for power semiconductor devices provided by the present invention, after measuring the on-state voltage drop of the power semiconductor device under test when a steady current flows through it, the method further includes:

[0023] Based on the currently measured on-state voltage drop, calculate its rate of change relative to the initial value or the previous measurement value;

[0024] When the rate of change exceeds a preset threshold, it is determined that the power semiconductor device under test has reached the preset aging endpoint.

[0025] The present invention also provides a power cycling test apparatus for power semiconductor devices, used to implement the power cycling test method for power semiconductor devices as described in any of the preceding claims, the apparatus comprising:

[0026] The test circuit contains at least one power semiconductor device under test and multiple controllable switching devices.

[0027] The control module is connected to the control terminals of each switching device in the test circuit and is configured to enable the test circuit to selectively operate in a dynamic switching mode that simulates actual working conditions or in a static conduction mode specifically for measurement by outputting different drive signal sequences.

[0028] The measurement unit is used to measure the on-state voltage drop of the power semiconductor device under test in the static on-state mode.

[0029] The power cycling test apparatus for power semiconductor devices provided by the present invention further includes an aging judgment unit connected to the measurement unit and the control module, the aging judgment unit being configured to:

[0030] Receive the on-state voltage drop measured by the measurement unit and calculate its rate of change; and

[0031] When the rate of change exceeds a preset threshold, an instruction signal is output to the control module to cause the control module to stop outputting the periodic switching drive signal for the dynamic switching mode, thereby terminating the power cycling process.

[0032] The present invention provides a power cycling test method and apparatus for power semiconductor devices. By applying periodic switching drive signals to a test circuit, the circuit operates in a dynamic switching mode simulating actual operating conditions to age the device. Furthermore, by changing the drive signal, the same test circuit is switched to a stable static conduction mode, where the on-state voltage drop of the device can be conveniently and accurately measured. By achieving seamless switching between dynamic aging and static measurement within the same circuit, the test conditions are highly realistic, and the measurement results are reliable. This provides accurate experimental basis for the lifetime prediction and reliability design of power semiconductor devices and is applicable to various topologies such as H-bridge and three-phase bridge. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 This is a schematic flowchart of the power cycle testing method for power semiconductor devices provided by the present invention.

[0035] Figure 2 This is a schematic diagram of the power cycle testing device for power semiconductor devices provided by the present invention.

[0036] Figure 3 This is a schematic diagram of the first stage of the power cycling test method in Embodiment 1 of the present invention.

[0037] Figure 4 This is the output current diagram of the power cycle test method in Embodiment 1 of the present invention.

[0038] Figure 5This is a schematic diagram of the second stage of the power cycling test method in Embodiment 1 of the present invention.

[0039] Figure 6 This is a flowchart of the power cycling test method in Embodiment 1 of the present invention.

[0040] Figure 7 This is a schematic diagram of the first stage of the power cycling test method in Embodiment 2 of the present invention.

[0041] Figure 8 This is a schematic diagram of the second stage of the power cycling test method in Embodiment 2 of the present invention.

[0042] Figure 9 This is a schematic diagram of the first stage of the power cycling test method in Embodiment 3 of the present invention.

[0043] Figure 10 This is a schematic diagram of the second stage of the power cycling test method in Embodiment 3 of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0045] The present invention will now be described in detail with reference to the accompanying drawings. The specific operation methods in the method embodiments can also be applied to the device embodiments or system embodiments. In the description of the present invention, unless otherwise stated, "at least one" includes one or more. "Multiple" refers to two or more. For example, at least one of A, B, and C includes: A existing alone, B existing alone, A and B existing simultaneously, A and C existing simultaneously, B and C existing simultaneously, and A, B, and C existing simultaneously. In the present invention, " / " means "or". For example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.

[0046] Accelerator pulse power supplies often require outputting periodically varying pulse currents. As the current rises and falls, the electrothermal stress on the IGBT, the core component of the circuit structure, also changes. After long-term operation, IGBT devices will experience aging damage. Accelerated aging testing is a life test method that places the device under pressure levels higher than normal to accelerate the aging process, improving experimental efficiency and reducing costs. Currently, the accelerated aging test specified in the IEC 60747-9:2007 standard typically involves applying a constant high current to a single IGBT, causing the IGBT junction temperature to rise; then disconnecting the high current, causing the IGBT junction temperature to drop; this process is repeated continuously with high current switching on and off until the device fails. Existing power cycle aging tests are based on DC aging tests, which have simple circuits and are easy to measure, but the IGBT module differs from actual operating conditions. The operating conditions of accelerator pulse power supplies are unique and differ from those in other application areas, making accelerated aging test measurements using AC power cycle test circuits more complex.

[0047] To address the aforementioned problems, the present invention aims to provide a power cycling test apparatus and method for IGBT power modules based on the actual circuit topology of an accelerator pulse power supply. This test method employs an AC power cycling approach, and the test results closely approximate the operating conditions of the power supply.

[0048] The present invention will now be described in detail with reference to specific embodiments.

[0049] In some specific embodiments of the present invention, such as Figure 1 As shown, this solution provides a power cycle testing method for power semiconductor devices, applied to a test circuit containing multiple power units. The method includes:

[0050] Step S100: Apply a periodic switching drive signal to the test circuit to make the switching transistor in the test circuit work in a dynamic switching mode that simulates actual working conditions, so as to apply cyclic electrothermal stress to the power semiconductor device under test contained in the test circuit.

[0051] Step S200: For the same test circuit, the drive signal is changed to a measurement drive signal to switch the test circuit to a static conduction mode, thereby forming a DC current path for measuring the on-state voltage drop of the power semiconductor device under test, wherein:

[0052] When the test circuit is a circuit including multiple H-bridge units connected in a cascade manner, the step of switching the test circuit to a static conduction mode includes: controlling the two power semiconductor devices on the diagonal of each H-bridge unit to a constant conduction state, and applying a positive DC voltage to the cascaded H-bridge units to form the DC current path through all the constant conduction devices.

[0053] When the test circuit is a three-phase full-bridge circuit, the step of switching the test circuit to the static conduction mode includes: selecting two phases of the three phases of the three-phase full-bridge circuit to apply a positive DC voltage, and controlling the power semiconductor devices in at least two bridge arms to a constant conduction state, so as to form the DC current path flowing through the at least two bridge arms using the DC bus.

[0054] When the test circuit is a circuit including multiple H-bridge units connected in parallel, the step of switching the test circuit to a static conduction mode includes: switching one of the multiple parallel H-bridge units to the static conduction mode in a time-sequential manner, while disabling other H-bridge units, so as to form the DC current path flowing through the H-bridge unit switched to the static conduction mode.

[0055] When the test circuit is a DC-DC chopper circuit, the step of switching the test circuit to the static conduction mode includes: configuring one or more switching devices in the DC-DC chopper circuit to establish a stable DC current path in the power semiconductor device under test;

[0056] Step S300: In the static conduction mode, measure the on-state voltage drop of the power semiconductor device under test when a stable current flows through it.

[0057] It should be noted that existing power cycling test schemes for power semiconductor devices operate under conditions that significantly deviate from the actual working conditions of these devices in many practical applications (such as H-bridge and three-phase bridge topologies). Aging data and lifetime models derived from these methods are difficult to accurately map to real-world applications, resulting in low guidance value and predictive accuracy for engineering applications. While current schemes employ AC testing to simulate actual operating conditions, this approach typically faces technical challenges, including complex circuit topologies, high control difficulty, and the difficulty in accurately and stably measuring minute changes in aging characteristic parameters such as on-state voltage drop under dynamic AC conditions.

[0058] Therefore, this invention switches the drive signal output by the control module in the same physical test circuit, allowing it to switch between two functional modes: one is a dynamic switching mode, used to simulate the real working environment of the device to apply cyclic electrothermal stress; the other is a static conduction mode, used to create a stable and simple DC environment to facilitate accurate measurement of aging characteristic parameters (such as conduction voltage drop).

[0059] In some specific embodiments of the present invention, please refer to Figure 2 This invention provides a power cycling test apparatus for power semiconductor devices, used to implement the power cycling test method for power semiconductor devices as described above. The apparatus includes:

[0060] The test circuit 110 contains at least one power semiconductor device under test and multiple controllable switching devices.

[0061] The control module 120 is connected to the control terminals of each switching device in the test circuit and is configured to enable the test circuit to selectively operate in a dynamic switching mode that simulates actual working conditions or in a static conduction mode specifically for measurement by outputting different drive signal sequences.

[0062] The measurement unit 130 is used to measure the on-state voltage drop of the power semiconductor device under test in the static conduction mode.

[0063] In some possible embodiments of the present invention, the power cycling test apparatus for power semiconductor devices provided by the present invention further includes an aging judgment unit 140 connected to the measurement unit 130 and the control module 120, wherein the aging judgment unit 140 is configured to:

[0064] Receive the on-state voltage drop measured by the measuring unit 130 and calculate its rate of change; and

[0065] When the rate of change exceeds a preset threshold, an instruction signal is output to the control module 120 to stop the control module 120 from outputting the periodic switching drive signal for the dynamic switching mode, thereby terminating the power cycling process.

[0066] This invention divides the test scheme into two stages. The first stage circuit aims to perform power cycle aging of the IGBT module. During this stage, the power supply switches between different states, the circuit outputs pulse current, and energy flows from the front end to the load. The current flowing through the load is a positive current. AC power cycling is used to accelerate the aging of the power semiconductor device under test, realizing aging tests based on the application conditions of accelerator pulse power supplies. The second stage circuit aims to measure the aging characteristic quantity, namely the on-state voltage drop of the IGBT module. By adopting the above-mentioned innovative dynamic aging-static measurement cycle method, the contradiction between authenticity and measurability is resolved on the same test platform, providing a powerful technical means for the reliability assessment of power semiconductor devices.

[0067] In some possible embodiments of the present invention, the power semiconductor device under test is an IGBT module or a MOSFET module. The topology of the test circuit is an H-bridge topology, a DC-DC chopper circuit topology, or a three-phase bridge topology.

[0068] The above steps will be explained in detail below through specific embodiments.

[0069] In some possible embodiments of the present invention, the topology of the test circuit is an H-bridge topology, and the static conduction mode is achieved by controlling two power semiconductor devices on any diagonal of the H-bridge topology to a constant conduction state.

[0070] Preferably, when the test circuit is a circuit comprising multiple H-bridge units connected in a cascaded manner, the step of applying a positive DC voltage to the cascaded H-bridge units specifically includes:

[0071] A positive DC voltage is applied to both ends of the cascaded H-bridge unit chain so that the DC current path passes through all power semiconductor devices controlled to a constant conduction state.

[0072] Furthermore, the dynamic switching mode specifically includes switching between at least three operating states:

[0073] The state in which two switching devices on any diagonal of the H-bridge topology are turned on;

[0074] The state where the upper transistor of the first arm of the H-bridge is turned on, and the current freewheels through the anti-parallel diode of the lower transistor of the second arm;

[0075] The state where the lower diode of the first arm of the H-bridge is turned on, and the current freewheels through the anti-parallel diode of the upper diode of the second arm.

[0076] As shown in Embodiment 1 of the present invention:

[0077] This embodiment discloses an implementation scheme suitable for H-bridge topologies. This embodiment uses a common H-bridge topology as an example to illustrate the invention. (Refer to...) Figure 3 and Figure 4 In this embodiment, the power cycling test device for power semiconductor devices includes a DC voltage source 1, a bus capacitor bank 2, a test circuit composed of the power semiconductor device under test, and a load module 11 composed of a load inductor and a load resistor. The test circuit is an H-bridge, including a first bridge arm composed of a first switch S11 (composed of a first IGBT 3 and a first anti-parallel diode 4) and a second switch S12 (composed of a second IGBT 5 and a second anti-parallel diode 6), and a second bridge arm composed of a third switch S13 (composed of a third IGBT 7 and a third anti-parallel diode 8) and a fourth switch S14 (composed of a fourth IGBT 9 and a fourth anti-parallel diode 10).

[0078] In this embodiment, the following two steps are performed alternately during the experimental process:

[0079] Step 1: Power Cyclic Aging (Dynamic Switching Mode):

[0080] Reference Figure 3 The control module applies periodic switching drive signals to S11-S14, causing the test circuit to operate in dynamic switching mode, generating signals on the load module 11 such as... Figure 4 The pulsed current is shown. Specifically, this mode may include cyclically switching between the following three states to simulate actual operating conditions:

[0081] State 1: S11 and S14 are on, S12 and S13 are off. The current flows sequentially through DC voltage source 1, S11, load module 11, and S14 back to supply power to the load.

[0082] State 2: S11 remains on, S14 is off. The load current freewheels through the third anti-parallel diode 8 of S11 and S13.

[0083] State 3: S14 remains on, S11 is off. The load current freewheels through the second anti-parallel diode 6 connected to S14 and S12.

[0084] By rapidly switching between these states, the devices under test (S11-S14) and their internal anti-parallel diodes are subjected to dynamic electrothermal stresses, such as switching, conduction, freewheeling, and reverse recovery, which are highly consistent with those in actual applications, thus accelerating aging.

[0085] Step 2, Characteristic Measurement (Static On-Mode):

[0086] After a predetermined number of power cycles (e.g., 1000), the aging process is paused, and the measurement phase begins. (Refer to...) Figure 5The control module changes the drive signal, outputting a measurement drive signal to S11 and S14 to keep them constantly conducting, while ensuring that S12 and S13 remain off. At this point, the complex switching circuit transforms into a simple DC circuit, with DC voltage source 1 forming a stable DC current path through the constantly conducting S11, load module 11, and S14. In this stable static conduction mode, the measurement unit can conveniently and accurately measure the on-state voltage drop of S11 and S14.

[0087] In some possible embodiments of the present invention, after measuring the on-state voltage drop of the power semiconductor device under test when a steady current flows through it, the method further includes:

[0088] Based on the currently measured on-state voltage drop, calculate its rate of change relative to the initial value or the previous measurement value;

[0089] When the rate of change exceeds a preset threshold, it is determined that the power semiconductor device under test has reached the preset aging endpoint.

[0090] In other words, the experimental process also includes experimental procedures and termination criteria:

[0091] Reference Figure 6 The flowchart illustrates the entire test process, which is a loop of steps one and two. After each measurement, the aging judgment unit (which can be integrated into the control module or used as a standalone module) compares the measured on-state voltage drop with the initial value or the previous measurement value and calculates its rate of change. When the rate of change exceeds a preset threshold (e.g., 5%), the device is determined to have reached the preset aging endpoint, and the test automatically terminates.

[0092] This embodiment provides a power cycle test process for power semiconductor devices in an IGBT module, including a power cycle test section and a characteristic quantity measurement section. Based on a practical H-bridge circuit topology, an aging cycle test circuit and a characteristic quantity measurement circuit were designed. The aging cycle test circuit switches between three operating states, while the characteristic quantity measurement circuit operates in one state. The test conditions closely resemble actual operating conditions, thus the test results have significant reference value for the expected lifespan of the power semiconductor devices. The on-state voltage drop measurement method used in the test is reliable and can effectively observe the aging increase trend of the on-state voltage drop of power semiconductor devices such as switching transistors. It is also easy to operate in practical engineering; furthermore, the test method is applicable to other switching transistors, such as MOSFETs.

[0093] In some possible embodiments of the present invention, the topology of the test circuit is a three-phase bridge topology, and switching the test circuit to static conduction mode further includes:

[0094] By randomly selecting two phases from the three phases, and controlling a pair of power semiconductor devices that form a DC current path between these two phases to maintain a constant on state.

[0095] Preferably, when the test circuit is a three-phase full-bridge circuit, the step of controlling the power semiconductor devices in at least two bridge arms to a constant on-state specifically includes:

[0096] The upper tube of the first phase bridge arm and the lower tube of the second phase bridge arm are controlled to a constant conducting state to form the DC current path flowing through the upper tube of the first phase bridge arm and the lower tube of the second phase bridge arm. As shown in Embodiment 2 of the present invention:

[0097] This embodiment discloses an implementation scheme suitable for PWM rectifiers and three-phase voltage-source inverters, referring to... Figure 7 , 8 This invention is also applicable to three-phase bridge topologies (such as PWM rectifiers or three-phase inverters). The test circuit consists of six switching devices, S21-S26.

[0098] Dynamic switching mode: refer to Figure 7 The control module applies a drive signal of three-phase SVPWM or other modulation strategy to make S21-S26 work in dynamic switching mode to perform power cycle aging.

[0099] Static conduction mode: refer to Figure 8 To measure, for example, the on-state voltage drop of phase A's upper transistor S21 and phase B's lower transistor S24, the control module keeps S21 and S24 constantly on, while keeping all other switches (S22, S23, S25, S26) off. This creates a stable DC current path between phases A and B, facilitating measurement. Similarly, their on-state voltage drop can be measured by controlling S23 and S22 to remain constantly on.

[0100] In some possible embodiments of the present invention, the test circuit includes a plurality of H-bridge units connected in parallel or in cascade.

[0101] For a parallel H-bridge structure, the static conduction mode is achieved through the following steps:

[0102] In each H-bridge unit, the two power semiconductor devices on the diagonal are controlled to a constant on-state; and...

[0103] Apply a DC voltage of the same polarity to the parallel H-bridge units so that the measuring current is shunt through each H-bridge unit;

[0104] For the cascaded H-bridge structure, the test circuit includes multiple H-bridge units connected in a cascaded manner, and the static conduction mode is achieved through the following steps:

[0105] The two power semiconductor devices on the diagonal of each H-bridge unit are controlled to a constant on state; and a positive DC voltage is applied to the cascaded H-bridge units to form a single serial DC current path through all the on devices.

[0106] As shown in Embodiment 3 of the present invention:

[0107] This embodiment discloses an implementation scheme suitable for cascading and paralleling of chopper H-bridges, referring to... Figure 9 , 10 To improve testing efficiency, multiple H-bridge units can be connected in parallel or cascaded.

[0108] Dynamic switching mode: refer to Figure 9 All H-bridge units (such as H-bridge 1 and H-bridge 2) have their switching transistors (S31-S34, S41-S44) aged in dynamic switching mode.

[0109] Static conduction mode:

[0110] Parallel connection (e.g.) Figure 10 (As shown in the right figure): The diagonal devices (such as S31 / S34 and S41 / S44) of each H-bridge unit (H-bridge 1 and H-bridge 2) are controlled to be constantly on. A DC voltage of the same polarity is applied to the parallel system, causing the measurement current to be shunt through each H-bridge unit, thus allowing the parameters of all on-state devices to be measured simultaneously.

[0111] Cascading situations (such as) Figure 10 (As shown in the left figure): The diagonal devices of each H-bridge unit are controlled to be constantly conducting. A positive DC voltage is applied to the cascaded H-bridges, thereby forming a single series DC current path through all conducting devices, enabling simultaneous measurement of all series devices.

[0112] In some possible embodiments of the present invention, the topology of the test circuit is a DC-DC chopper circuit topology, and switching the test circuit to a static conduction mode further includes:

[0113] By configuring one or more switching devices in the DC-DC chopper circuit, a stable DC conduction path is established in the power semiconductor device under test.

[0114] As provided in Embodiment 4 of this invention:

[0115] This embodiment discloses an implementation scheme applied to a DC-DC chopper circuit topology, meaning the invention is also applicable to various types of DC-DC chopper circuits. In this case, the static conduction mode is implemented by configuring one or more switches in the circuit to establish a stable DC conduction path in the device under test.

[0116] For a Buck circuit, to test the main switch, simply keep it constantly on.

[0117] For Boost circuits, the main switch is kept constantly on to test; however, the main switch is kept constantly off to allow current to flow through the freewheeling path under test to test the freewheeling diode or synchronous rectifier switch. The method of this invention establishes a DC path by configuring the circuit state, rather than limiting the operation of a specific switch, thus possessing excellent versatility.

[0118] The power cycling test method and apparatus for power semiconductor devices provided by this invention offer highly realistic test conditions and valuable results. Employing a test circuit consistent with actual application topologies for dynamic stress aging, it fully replicates the dynamic electrothermal stresses experienced by the device under all operating states, including switching, conduction, and freewheeling. This ensures that the test results accurately reflect the aging patterns of the device in practical applications, significantly improving the accuracy of lifespan prediction. The measurement method is ingenious, reliable, and easy to implement in engineering. By changing the control signal, the complex dynamic test circuit is cleverly "transformed" into a simple static DC circuit during the measurement phase, enabling convenient, stable, and accurate measurement of key aging parameters such as on-state voltage drop, solving the technical challenge of measurement difficulties under dynamic conditions. It boasts strong compatibility and a wide range of applications, not only suitable for H-bridges but also flexibly applicable to various mainstream topologies such as DC-DC chopper circuits, three-phase bridges, and cascaded / parallel H-bridges. Furthermore, it is compatible with different types of power semiconductor devices such as IGBTs and MOSFETs, exhibiting exceptional versatility. Moreover, by connecting multiple test units in parallel or cascade, this invention allows for simultaneous aging tests on multiple devices, significantly shortening the test cycle and improving test efficiency.

[0119] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0120] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power cycle test method of a power semiconductor device, characterized by, The method, applied to a test circuit containing multiple power units, includes: A periodic switching drive signal is applied to the test circuit to make the switching transistor in the test circuit work in a dynamic switching mode that simulates actual working conditions, so as to apply cyclic electrothermal stress to the power semiconductor device under test contained in the test circuit. For the same test circuit, the switch drive signal is changed to a measurement drive signal to switch the test circuit to a static conduction mode, thereby forming a DC current path for measuring the on-state voltage drop of the power semiconductor device under test, wherein: When the test circuit is a circuit including multiple H-bridge units connected in a cascade manner, the step of switching the test circuit to a static conduction mode includes: controlling the two power semiconductor devices on the diagonal of each H-bridge unit to a constant conduction state, and applying a positive DC voltage to the cascaded H-bridge units to form the DC current path through all the constant conduction devices. When the test circuit is a three-phase full-bridge circuit, the step of switching the test circuit to the static conduction mode includes: selecting two phases of the three phases of the three-phase full-bridge circuit to apply a positive DC voltage, and controlling the power semiconductor devices in at least two bridge arms to a constant conduction state, so as to form the DC current path flowing through the at least two bridge arms using the DC bus. When the test circuit is a circuit including multiple H-bridge units connected in parallel, the step of switching the test circuit to a static conduction mode includes: switching one of the multiple parallel H-bridge units to the static conduction mode in a time-sequential manner, while disabling other H-bridge units, so as to form the DC current path flowing through the H-bridge unit switched to the static conduction mode. When the test circuit is a DC-DC chopper circuit, the step of switching the test circuit to the static conduction mode includes: configuring one or more switching devices in the DC-DC chopper circuit to establish a stable DC current path in the power semiconductor device under test; In the static conduction mode, the on-state voltage drop of the power semiconductor device under test is measured when a steady current flows through it.

2. The power cycle test method of a power semiconductor device according to claim 1, characterized by, When the test circuit is a circuit comprising multiple H-bridge units connected in a cascaded manner, the step of applying a positive DC voltage to the cascaded H-bridge units specifically includes: A positive DC voltage is applied to both ends of the cascaded H-bridge unit chain so that the DC current path passes through all power semiconductor devices controlled to a constant conduction state.

3. The power cycle test method of a power semiconductor device according to claim 2, characterized by, The dynamic switching mode specifically includes switching between at least three operating states: The state in which two switching devices on any diagonal of the H-bridge topology are turned on; In the H-bridge topology, the upper transistor of the first bridge arm is turned on, and the current freewheels through the anti-parallel diode of the lower transistor of the second bridge arm. In the H-bridge topology, the lower diode of the first bridge arm is turned on, and the current freewheels through the anti-parallel diode of the upper diode of the second bridge arm.

4. The power cycle test method of a power semiconductor device according to claim 1, characterized by, When the test circuit is a three-phase full-bridge circuit, the step of controlling the power semiconductor devices in at least two bridge arms to a constant on-state specifically includes: The upper tube of the first phase bridge arm and the lower tube of the second phase bridge arm are controlled to a constant conducting state to form the DC current path flowing through the upper tube of the first phase bridge arm and the lower tube of the second phase bridge arm.

5. The power cycle test method of a power semiconductor device according to claim 1, characterized by, After measuring the on-state voltage drop of the power semiconductor device under test when a steady current flows through it, the method further includes: Based on the currently measured on-state voltage drop, calculate its rate of change relative to the initial value or the previous measurement value; When the rate of change exceeds a preset threshold, it is determined that the power semiconductor device under test has reached the preset aging endpoint.

6. A power cycling test apparatus for power semiconductor devices, characterized in that, For implementing the power cycling test method for the power semiconductor device as described in any one of claims 1-5, the apparatus comprises: The test circuit contains at least one power semiconductor device under test and multiple controllable switching devices. The control module is connected to the control terminals of each switching device in the test circuit and is configured to enable the test circuit to selectively operate in a dynamic switching mode that simulates actual working conditions or in a static conduction mode specifically for measurement by outputting different drive signal sequences. The measurement unit is used to measure the on-state voltage drop of the power semiconductor device under test in the static on-state mode.

7. The power cycling test apparatus for a power semiconductor device according to claim 6, wherein It also includes an aging determination unit connected to the measurement unit and the control module, the aging determination unit being configured to: Receive the on-state voltage drop measured by the measurement unit and calculate its rate of change; as well as When the rate of change exceeds a preset threshold, an instruction signal is output to the control module to cause the control module to stop outputting the periodic switching drive signal for the dynamic switching mode, thereby terminating the power cycling process.

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