Chip aging system and method based on distributed network

Abstract

The invention relates to a chip burn-in system and method based on a distributed network, through software and hardware collaborative design of chip burn-in boards, burn-in information processing boards, a network switch and a PC end upper computer, an IP-based Ethernet architecture is adopted, each burn-in information processing board is an independent network node, and each burn-in information processing board is an independent network node. A systematic architecture of multi-dimensional state sensing, networked remote monitoring and hierarchical decision protection is formed, and a pure signal sensing unit located in a high-temperature box, an intelligent processing unit located outside the high-temperature box and a centralized management unit located remotely are decoupled and connected through a standard network. According to the invention, physical and logic separation and cooperation of monitoring, control and decision making are realized, spanning from extensive aging management to refined aging management, evolution from passive recording to active protection, upgrade from rigid concentration to elastic distribution and evolution from data islands to intelligent decision making are realized, and the comprehensive efficiency of chip aging testing is greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of chip aging and testing technology, and relates to a chip aging system and method based on a distributed network. Background Technology

[0002] Chip aging testing, also known as reliability life testing, is a crucial part of the integrated circuit screening process. Its core purpose is to accelerate the exposure of potential internal defects (such as gate oxide defects, metal electromigration, and poor contact) by placing the chip under harsh conditions of high temperature (usually 125°C or even higher), high voltage, and dynamic workload. This allows for the elimination of early-failure products before the chips leave the factory, ensuring that the chips delivered to customers have high reliability and long life.

[0003] With the rapid development of integrated circuit technology, chips are becoming increasingly integrated, complex in function, and more diversified (multi-voltage domain) in power systems. This poses unprecedented challenges to chip aging testing technology. Traditional aging monitoring systems mostly focus on monitoring the ambient temperature of the high-temperature chamber and making basic judgments about the chip's power-on / power-off status. They lack effective synchronous and real-time monitoring methods for some key dynamic parameters, such as the real-time operating current of the chip core and various functional modules, dynamic voltage fluctuations, and whether the internal program is running on the expected track. Most aging monitoring systems are designed with data logging as their core function. When an anomaly is detected in a chip, such as a sharp increase in current (possibly caused by latch-up) or abnormal voltage, the aging monitoring system usually only records the event in the log or waits until a scan cycle is completed before reporting it.

[0004] Many aging monitoring systems employ a centralized master-slave architecture, where a central controller connects to multiple aging boards via a massive cabling bundle and complex interfaces. System capacity is fixed from the outset, resulting in numerous cables and complex wiring. Data management in these systems is limited to simple data recording and static report generation, creating information silos between systems with inconsistent data formats, hindering centralized management and in-depth analysis. Therefore, traditional aging monitoring systems exhibit significant shortcomings in testing depth (refined monitoring), system security (real-time protection), architectural flexibility (scalability), and intelligent management (information technology). Improving the overall efficiency of chip aging testing has become a pressing technical challenge. Summary of the Invention

[0005] To address the problems existing in the above-mentioned traditional methods, this invention proposes a chip aging system based on a distributed network and a chip aging test method, which can improve the overall efficiency of chip aging test.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a chip aging system based on a distributed network is provided, including... The PC host computer, network switch 12, old refinement information processing board and chip old refinement board, one chip old refinement board and one old refinement information processing board are connected by connectors to form a board group, and there is no less than one board group. The PC host computer is connected to each old refinement information processing board through network switch 12. Each chip aging board is installed in a high-temperature chamber and is equipped with multiple aging stations and multiple current monitors. Each aging station is used to mount one chip under test. Each current monitor is used to measure the electrical signal of each power supply of each chip under test and transmit it back to the aging information processing board. The onboard connectors of the aging station are used to connect to the communication interfaces of the chip under test. Each aging information processing board is installed outside the high-temperature chamber and is equipped with a unique IP address. Each aging information processing board is used to independently execute all signal interactions of the corresponding chip aging board and to convert the collected electrical signals into high-precision digital values. All signal interactions include test program distribution, test program operation monitoring based on heartbeat and command frames, data frame uploading to the PC host computer, and instruction control of the chip under test. The PC-based host computer provides a human-machine interface and performs global monitoring, data storage, and intelligent decision-making for the aging test of the chip under test based on Socket communication. The intelligent decision-making includes monitoring the status of the chip under test, issuing alarms, and issuing emergency shutdown commands based on the network data frames uploaded by the aging information processing board.

[0007] On the other hand, a chip aging test method is also provided. Based on the aforementioned distributed network-based chip aging system, this chip aging test method may include the following test steps: After the test is started, the PC host computer applies test stimuli to the chip under test on the chip aging board through the aging information processing board, and collects the operating current, voltage and program running status data of the chip under test in real time. The collected data is packaged using the old-fashioned information processing board and uploaded to the PC host computer in real time via the local area network; The PC-based host computer monitors the status of the chip under test based on the received data. If the program runs abnormally, the PC-based host computer will issue an alarm. If the current or voltage exceeds the set threshold, an emergency shutdown command will be immediately sent to the corresponding old information processing board via the local area network. After receiving an emergency shutdown command, the old-fashioned information processing board performs power-off protection on the tested chip that has malfunctioned.

[0008] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned chip aging system and method based on a distributed network, through the collaborative hardware and software design of the chip aging board, aging information processing board, network switch, and PC-based host computer, adopts an IP-based Ethernet architecture. Each aging information processing board is an independent network node, forming a systematic architecture of multi-dimensional state perception, networked remote monitoring, and hierarchical decision protection. The pure signal sensing unit (chip aging board) located inside the high-temperature chamber, the intelligent processing unit (aging information processing board) located outside the high-temperature chamber, and the centralized management unit (PC-based host computer) located remotely are decoupled and connected through a standard network. This achieves physical and logical separation and coordination of monitoring, control, and decision-making, realizing a leap from extensive to refined aging management, an evolution from passive recording to active protection, an upgrade from rigid centralization to flexible distribution, and an evolution from data silos to intelligent decision-making, significantly improving the overall efficiency of chip aging testing. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the overall framework of a chip aging system based on a distributed network in one embodiment; Figure 2 This is a schematic diagram of a chip aging board in one embodiment (containing 16 aging test stations). Figure 3 This is a schematic diagram of the panel of the Laolian Information Processing Board in one embodiment; Figure 4 This is a schematic diagram of the execution flow of the alarm and protection rule engine in one embodiment; Figure 5 This is a flowchart illustrating a chip aging test method in one embodiment. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0012] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0013] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0014] In one embodiment, such as Figure 1 As shown, a chip aging system based on a distributed network is provided, including a PC host computer 11, a network switch 12, an aging information processing board 13, and a chip aging board 14. A chip aging board 14 and an aging information processing board 13 are connected via connectors to form a board group. There is at least one board group. The PC host computer 11 is connected to each aging information processing board 13 via the network switch 12. There can generally be multiple board groups, and each board group can have an independent IP address as a unique identifier.

[0015] Each chip aging board 14 is installed in a high-temperature chamber 102 and is equipped with multiple aging stations and multiple precision sampling resistors. Each aging station is used to mount one chip under test. The multiple precision sampling resistors are used by the aging information processing board 13 to collect and monitor the electrical signals of each power supply of each chip under test. The onboard connector of the chip aging board is used to connect with the aging information processing board to respectively power the chip aging board 14, collect the analog voltage and current values ​​of each chip on the chip aging board 14, provide the startup code of the aging chip, and collect the normal operation signal and heartbeat signal of the aging chip. Each aging information processing board 13 is installed outside the high-temperature chamber 102 and is configured with a unique IP address. Each aging information processing board 13 is used to independently execute all signal interactions of the corresponding chip aging board 14 and to convert the collected electrical signals into high-precision digital values. All signal interactions include test program distribution, test program operation monitoring based on heartbeat and command frames, data frame uploading to the PC host computer 11, and instruction control of the chip under test. The PC-based host computer 11 provides a human-machine interface and performs global monitoring, data storage, and intelligent decision-making for the aging test of the chip under test based on Socket communication. The intelligent decision-making includes monitoring the status of the chip under test, issuing alarms, and issuing emergency shutdown commands based on the network data frames uploaded by the aging information processing board 13.

[0016] It is understood that the chip aging board 14, as the execution layer of the chip aging test, is installed inside the high-temperature chamber 102 to directly support the chip under test. One chip aging board 14 can be configured with multiple aging stations to support multiple chips under test respectively. The aging information processing board 13, as the control and data acquisition layer of the chip aging test, is located outside the high-temperature chamber 102. Each aging information processing board 13 independently executes all signal interactions and data acquisition for one chip aging board 14. The network switch 12, as the system's data path backbone, connects all aging information processing boards 13 to the PC host computer 11, forming a local area network. The PC host computer 11, as the management and decision-making layer of the chip aging test, provides a human-machine interface for global monitoring, data storage, and intelligent decision-making regarding the chip aging test.

[0017] The aforementioned chip aging system based on a distributed network, through the collaborative hardware and software design of the chip aging board 14, aging information processing board 13, network switch 12, and PC host computer 11, adopts an IP-based Ethernet architecture. Each aging information processing board is an independent network node, forming a systematic architecture of multi-dimensional state perception, networked remote monitoring, and hierarchical decision protection. The pure signal sensing unit (chip aging board 14) located inside the high-temperature chamber 102, the intelligent processing unit (aging information processing board) located outside the high-temperature chamber 102, and the centralized management unit (PC host computer 11) located remotely are decoupled and connected through a standard network. This achieves physical and logical separation and coordination of monitoring, control, and decision-making, realizing a leap from extensive to refined aging management, an evolution from passive recording to active protection, an upgrade from rigid centralization to flexible distribution, and an evolution from data silos to intelligent decision-making, significantly improving the overall efficiency of chip aging testing.

[0018] Specifically, the aforementioned system supports synchronous and real-time acquisition of the operating current, voltage, and program running status of each chip under test, achieving multi-parameter synchronous acquisition and providing unprecedented multi-dimensional data support for assessing chip health. The LaoLian Information Processing Board 13 accurately captures subtle changes in the current of the tested chip, enabling earlier and more precise failure screening and improving product quality before shipment. Through a unique "heartbeat" or status monitoring mechanism, the system can effectively distinguish between chips that are powered on but have failed, chips with abnormal contact at the LaoLian station, and normal chips, solving the blind spots of traditional technologies in functional testing and providing more thorough screening. The system establishes an automated closed loop of monitoring-decision-execution. When hardware danger signals such as excessive current / voltage are detected, the system can complete the entire process from data upload to shutdown command within milliseconds, a response speed several orders of magnitude faster than traditional technologies. This rapid proactive protection capability can isolate faults instantly, completely avoiding testing risks and property losses caused by short circuits or overcurrents in a single chip.

[0019] Furthermore, when increased testing capacity is required, simply connect the new aging information processing board to the network switch 12 and assign an IP address; no changes to the core architecture or complex wiring are needed, perfectly adapting to product batch fluctuations and production ramp-up requirements. Different aging information processing boards can manage different types or batches of chips, offering flexible test task configuration. Failure of a single aging information processing board or chip aging board 14 does not affect the normal operation of other boards in the system, achieving excellent fault isolation and improving the overall availability and maintainability of the system. The system uses standard network cables to replace a large number of analog signal and control lines, significantly simplifying the system structure, reducing wiring complexity and cost, and minimizing the risk of signal interference. The PC-based host computer 11 serves as a unified control center, providing aging engineers with a global, real-time, and visualized view of the test status, greatly improving monitoring efficiency and human-computer interaction experience. The system automatically records all test process data (including the final results and every frame of data during the process) and stores it in the database, providing a data foundation for subsequent failure analysis, reliability trend prediction and test process optimization. This promotes the transformation of chip aging quality management from "experience-driven" to "data-driven". Furthermore, every test start-up, operation, alarm and protection action is fully recorded, forming a traceable electronic record, which meets the stringent quality traceability requirements of high-end chip manufacturing.

[0020] In one embodiment, the communication interface of the chip under test includes at least one of UART, I2C, SPI and GPIO, and the chip aging board 14 and the aging information processing board 13 are connected to each other through a power supply connector, a digital signal connector and an analog signal connector, respectively.

[0021] It is understandable that the core improvement of the chip aging board 14 lies in its refined monitoring circuit design. A precise current monitor is set on the chip aging board 14 for each power supply (such as Core, IO and PLL) of each chip under test. It can be used by the aging information processing board 13 to measure the electrical signal (such as current signal or voltage signal) of each power supply of the chip under test. The connector of the chip aging board 14 transmits the signal to the aging information processing board 13 outside the high temperature chamber 102 through high temperature cables for analog signal acquisition and digital conversion, so as to realize the monitoring of the power supply current and operating voltage of each chip under test. Meanwhile, the digital signal connectors on the chip aging board 14 connect to the digital interfaces (such as UART, I2C, SPI, or GPIO interfaces) of each aging chip, allowing the aging chip to obtain the startup code sent by the aging information processing board 13 through this connector. This code is used to start the functional program of the chip under test. After the chip under test starts, it can transmit the current status signals (such as "heartbeat" signals, current program status signals, and error flags) of the chip under test to the aging information processing board 13 in real time through its UART, I2C, SPI, or GPIO interfaces.

[0022] The power supply connector of the chip aging board 14 is connected to the power supply connector of the aging information processing board 13. The digital signal connector of the chip aging board 14 is connected to the digital signal connector of the aging information processing board 13. The analog signal connector of the chip aging board 14 is connected to the analog signal connector of the aging information processing board 13. The power supply connector is used to provide power to the chip under test, the digital signal connector is used to transmit digital signals to the chip under test, and the analog signal connector is used to transmit analog signals to the chip under test.

[0023] Understandable, such as Figure 2 As shown, the chip aging board 14 can adopt a three-connector design: The first set of connectors are power supply connectors, used to provide power to the chip under test. These include necessary power supplies for mature testing such as chip core power, chip I / O power, chip PLL power, and auxiliary power. In order to be able to expand and adapt to larger chips in the future, a power supply connector with feedback signal and high current is selected here.

[0024] The second set of connectors are digital signal connectors, used to transmit digital signals to the chip under test, including digital signals such as the chip under test's reset signal, clock signal, UART interface signal, SPI interface signal, and I2C interface signal, so as to provide the chip under test's startup code and feedback of the chip under test's status information after startup.

[0025] The third set of connectors are analog signal connectors, used to transmit analog signals to the chip under test, including real-time acquisition of current and voltage signals from various power supplies of the chip under test.

[0026] The chip aging board 14 and the aging information processing board 13 are connected by the above three sets of connectors to ensure reliable power supply and communication between all tested chips and the chip aging board 14 and the aging information processing board 13.

[0027] In this embodiment, optionally, the current monitor is a sampling resistor, and a high-precision sampling resistor is connected in series with each power supply of each chip under test.

[0028] It is understood that in this embodiment, a high-precision, low-temperature-drift sampling resistor is connected in series with each power supply of each chip under test on the chip aging board 14. The sampling resistor converts the current signal into a small voltage signal that can be measured. After passing through the onboard connector on the chip aging board 14, it is transmitted to the aging information processing board 13 through a high-temperature cable for corresponding signal acquisition and conversion.

[0029] In one embodiment, the sampling resistor is a surface-mount resistor with a resistance of 20mΩ, an accuracy of 0.1%, and a temperature drift coefficient of less than 50ppm / °C.

[0030] It is understandable that a surface-mount resistor with a resistance of 20mΩ, an accuracy of 0.1%, and a temperature drift coefficient of less than 50ppm / °C is connected in series with each power supply of the aging chip as a sampling resistor. A single chip aging board 14 can be designed with 16 aging fixtures (i.e., Figure 2 The aging station GW shown can simultaneously perform more efficient aging screening on 16 chips under test. Multiple voltage analog signals are connected to the aging signal processing board through analog signal connectors, and then connected to the AD on the aging information processing board 13 for acquisition, conversion and calculation through the multi-channel analog switch on the board.

[0031] In another embodiment, optionally, the current monitor is a non-contact current sensor, with one non-contact current sensor installed on each power line of each chip under test.

[0032] It is understood that in this embodiment, a non-contact current sensor (such as a Hall effect current sensor or a current transformer) is used instead of a traditional sampling resistor: a miniaturized Hall effect current sensor is installed on each power line of each chip under test on the chip aging board 14 (the current transformer is set up similarly). This Hall effect current sensor does not need to be connected in series in the power line, but measures the current signal on the power line by sensing the magnetic field generated around the power line. When the Hall effect current sensor directly converts the measured current signal into a voltage signal output, the signal has usually been internally amplified and calibrated. This voltage signal output can be transmitted to the aging information processing board 13 for corresponding signal acquisition and conversion via the onboard connector on the chip aging board 14 and a high-temperature cable. Data upload from multiple non-contact current sensors can also be accessed to the aging information processing board 13 for acquisition and conversion via a multi-channel analog switch.

[0033] Because the non-contact current sensor is not connected in series in the circuit of the chip under test, it avoids the power consumption and heat generation of the sampling resistor itself. This is especially advantageous for high-precision measurements and high-temperature environments, thus reducing sources of system error. The introduction of the non-contact current sensor provides native electrical isolation, making it easy to measure high-side power supplies and effectively suppressing common-mode interference, improving the system's anti-interference capability and safety. Moreover, for established chip refining boards, circuit modifications related to current measurement are more convenient.

[0034] In one embodiment, such as Figure 3 As shown, the old-fashioned information processing board 13 is the technical hub of the entire system. Its core is a high-performance FPGA chip, around which the following functional circuits are integrated: an excitation signal generation circuit, a high-precision analog signal acquisition circuit, a digital status monitoring circuit, and a data framing and network communication circuit. The FPGA chip is connected to the excitation signal generation circuit, the high-precision analog signal acquisition circuit, the digital status monitoring circuit, and the data framing and network communication circuit, respectively.

[0035] Excitation signal generation circuit: used to generate signals of different voltages (V3.3, V1.8 or V1.5) (such as dedicated clock signal, reset signal) from the BANK-IO interface of the FPGA chip, and to send the test program code stored in the Flash memory attached to the FPGA chip to each chip under test on the chip refining board 14 through interfaces such as UART, SPI and I2C.

[0036] High-precision analog signal acquisition circuit: This circuit consists of an operational amplifier, a multiplexer, and a high-resolution ADC. The operational amplifier amplifies the electrical signal output from the current monitor; the multiplexer, under the control of the FPGA chip, cyclically selects each amplified signal; finally, the signal is processed by a high-resolution ADC (e.g., a 16-bit ADC). An analog-to-digital converter (ADC) converts electrical signals in analog form into high-precision digital values.

[0037] Digital Status Monitoring Circuit: The FPGA chip captures the current status signals (such as "heartbeat" signals and UART command frames) from the chip under test in real time through its BANK-IO interface, and determines whether the "heartbeat" signal appears within a preset time window and whether the UART command frame indicates that the chip under test is in a normal state through internal logic, thereby determining whether the test program is running normally.

[0038] Data framing and network communication circuitry: Collected data (such as current, voltage, program status flags, chip location encoded ID identifiers, and timestamps) is encapsulated into custom, structured network data frames. These network data frames are then sent via an integrated network hardware protocol stack chip (such as an Ethernet chip) to a designated IP address within the local area network (i.e., the address of the PC host computer 11) according to the TCP / IP protocol. Each aging information processing board 13 is assigned a unique IP address when the FPGA software is embedded, thus establishing its identity within the network.

[0039] It is understandable that the underlying circuit structure of the FPGA chip and its peripheral functional circuits integrated in the old information processing board 13 can be understood by referring to the underlying structure of existing FPGA chips and similar functional circuits in this field. It is only necessary to make adaptive circuit connections according to their respective interfaces and the above-mentioned signal and data flow requirements.

[0040] Furthermore, the core controller of the Laolian Information Processing Board 13 can be selected from existing FPGA chips. By utilizing its parallel processing capabilities, it can efficiently support the synchronous acquisition and processing of multi-channel data, thereby reducing the hardware design cost of the Laolian Information Processing Board 13.

[0041] For example, the ADC of the old-fashioned information processing board 13 can be a single-channel 18-bit synchronous sampling ADC. The ADC, characterized by high precision and anti-interference capabilities, can directly communicate with the FPGA chip via the I2C interface. The data framing and network communication circuits on the aging information processing board 13 can utilize existing Ethernet chips. These chips integrate MAC and PHY layer functions and can connect to the FPGA chip via the SPI interface. The FPGA chip can initialize the Ethernet chip and perform data read / write operations, enabling 100Mbps Ethernet communication. For power management implemented by the excitation signal generation circuit on the aging information processing board 13, multiple digitally controllable existing power supply chips can be integrated on the aging information processing board 13. The FPGA chip can directly control the output voltage of each power supply chip or directly shut it down via the I2C bus, thereby achieving power control for each tested chip on the aging board 14.

[0042] Furthermore, the firmware of the old information processing board 13 can be designed within the FPGA chip using Verilog / VHDL. For example, the design implementation includes a state machine, a precise timer, and a data encapsulation module. The state machine is used for command parsing and response with the PC host computer 11. The timer is used to generate a time window for monitoring the "heartbeat" signal and to parse the status data packets fed back from the UART, SPI, and I2C interfaces of the chip under test. The data encapsulation module uses a TCP / IP data packet network data frame format as shown below: [Frame header 0xAA55] [Status flag of the chip under test] [Power supply input voltage value of the chip aging board] [Power supply detection point voltage value of the chip under test].

[0043] The host computer software can calculate the current value of the power supply using the input power supply voltage value of the chip aging board 14, the power supply detection point voltage value of the chip under test, and the resistance value of the sampling resistor (calculation formula: (input voltage value - detection point voltage value) / resistance value of the sampling resistor).

[0044] In one embodiment, multiple 24-port and 4-port gigabit industrial Ethernet switches can be selected as network switches 12 to build the required local area network, thereby balancing network construction costs and test data transmission requirements while achieving a higher chip concurrent aging test volume.

[0045] In one embodiment, the PC-based host computer 11 can be deployed by installing host computer software on an industrial computer (e.g., equipped with an Intel i5 processor, 8GB of memory, and a 256GB SSD) or other PCs, and its core functional modules may include: Device connection to Laolian Information Processing Board 13: Based on Socket communication, after the PC host computer 11 starts up, it automatically builds the corresponding host computer server. After the Laolian Information Processing Board 13 in the local area network is powered on, it will automatically try to connect to the host computer server and establish a stable data connection with the PC host computer 11.

[0046] Multi-threaded data receiving and parsing engine: Creates an independent communication thread for each connected old refinement information processing board 13 to receive and parse network data frames from each old refinement information processing board 13 in real time, ensuring that massive amounts of data are not blocked or lost.

[0047] Real-time data visualization interface: The interface can dynamically display the real-time parameters of all tested chips on the PC host computer 11 in the form of lists, graphs, and dashboards. The visualization interface can be hierarchically organized according to the IP address of the aging information processing board 13, the high-temperature chamber 102, and the slots of the chip aging board 14.

[0048] Configurable alarm and protection rule engine: Users can set corresponding upper and lower limit thresholds for each parameter (such as current, voltage and status). The alarm and protection rule engine is used to continuously judge the alarm and protection rules of the incoming data stream: (1) When an abnormal program status is detected (such as heartbeat timeout, abnormal data packet returned by the chip under test, current or voltage reaching the (upper or lower limit) threshold), the real-time parameters of the corresponding chip under test are highlighted on the visualization interface, and the alarm log is recorded, but no emergency hardware action is taken. (2) When the current or voltage exceeds the (upper or lower limit) threshold, the alarm and protection rule engine will immediately (or in the next communication cycle) generate an emergency shutdown command and send it to the corresponding old information processing board 13 through the local area network.

[0049] Data storage and traceability module: All data uploaded by the Laolian Information Processing Board 13, alarm logs generated by the alarm and protection rule engine, and instruction operation logs are stored in real time in the memory database of the host computer server. It supports historical data query and statistical analysis by time, chip batch, and fault type.

[0050] It is understandable that the host computer software can be developed using C++, and its visual interface can be developed using QT. The communication layer of the host computer software can use asynchronous sockets to receive TCP / IP packets and send commands. The data processing layer of the host computer software is used to put the data packets uploaded by the old information processing board 13 into a queue, which are then parsed and updated to the in-memory database by a background thread.

[0051] The business logic layer of the host computer software includes an alarm and protection rule engine, which runs as an independent service. Its software execution flow can be summarized as follows: The alarm and protection rule engine extracts the board status data packets (including voltage, current, and status information of the chip under test) parsed by the background thread from the memory database in real time. Then, according to the set upper and lower limit thresholds, the alarm and protection rule engine performs anomaly judgment on the board status data packets. If the alarm rules are met, the alarm and protection rule engine immediately triggers the visualization interface to highlight the alarm and record the alarm log. If the protection rules are met, the alarm and protection rule engine immediately triggers the generation of protection instructions and sends them to the aging information processing board 13 through the IP address corresponding to the protection instructions, so that the aging information processing board 13 can perform protection control on the corresponding chip under test on the chip aging board 14.

[0052] After the alarm and protection rule engine completes the analysis of the board status data packets, it triggers an update to the visualization interface and stores the alarm logs and command operation logs in the in-memory database. Once the alarm and protection rule engine has processed all the board status data packets to be analyzed in the in-memory database, it automatically enters a sleep state. It will be automatically awakened when new, unprocessed board status data packets appear in the in-memory database. The specific process is as follows: Figure 4 As shown.

[0053] Furthermore, the workflow and protection mechanism of the chip aging based on distributed networks can be described as follows: Initialization and Configuration: Experienced test engineers can configure the experience test tasks and alarm thresholds (such as upper and lower limits of various parameters) and start the system on the PC host computer 11. The PC host computer 11 automatically builds a host computer server TCP Server (Transmission Control Protocol Server - a software or computer that uses the TCP protocol to listen for network connections and provide specific services to connected clients) in the local area network, waiting for the experience information processing board 13 to connect via the TCP protocol.

[0054] Test Startup: After the old information processing board 13 is powered on, a reset signal and clock are applied sequentially to the chip old board 14. The test program of the chip under test is downloaded through the UART interface, SPI interface and I2C interface. The network port and communication interface are initialized and an attempt is made to connect to the host computer 11 built in the local area network as the host computer TCP Server.

[0055] Cyclic Monitoring and Reporting: The aging information processing board 13 enters the main loop of aging test and periodically executes: polling and collecting the current and voltage of all aging channels (corresponding to all tested chips), checking the "heartbeat" status of all tested chips, checking whether the command frames sent by all tested chips to the aging information processing board 13 through the UART interface, SPI interface and I2C interface are normal, and finally packaging the data and uploading it to the PC host computer 11 through the TCP / IP protocol.

[0056] Real-time decision-making and protection: PC host computer 11 parses the board status data packet and sends it to the alarm and protection rule engine: (1) Functional abnormality: If the "heartbeat" of the chip under test is lost, or the command frame sent to the old information processing board 13 by the UART interface, SPI interface and I2C interface is abnormal, an alarm will be triggered on the visualization interface and the failure information (alarm log) will be recorded. (2) Hardware abnormality: If the current of a certain chip under test is found to be over-limit, an emergency shutdown command containing the "target channel" and "shutdown" command will be sent to the old information processing board 13 through the TCP protocol (high reliability).

[0057] Emergency Response: Upon receiving an emergency shutdown command, the BANK-IO interface of the FPGA chip on the Laolian Information Processing Board 13 will directly control the enable switch of the corresponding power supply chip on the board, cutting off the power supply to the faulty chip (i.e., the aforementioned chip under test that has exceeded the current limit), thus completing the rapid protection of the chip under test. The entire closed-loop response time from detection to execution can be controlled within 100 milliseconds.

[0058] In some implementations, an example of one system workflow is also provided to further illustrate the working process of the above system: Suppose that a chip aging system based on a distributed network needs to test a batch of 320 chips (deployed with 20 aging information processing boards 13 and 20 chip aging boards 14, each chip aging board 14 can carry 16 chips under test).

[0059] System power-on: The experienced test engineer opens the host computer software on the PC host computer 11 to complete the host computer server initialization and configures the matching information of the IP address of the aging information processing board 13 and the box-board serial number (i.e. the serial number correspondence between the high temperature box 102 and the chip aging board 14, which is used to accurately identify which chip aging boards 14 are installed in each high temperature box 102).

[0060] Start testing: Power on all old and refined information processing boards 13. After the old and refined information processing boards 13 have completed power supply initialization, they will automatically establish a network connection with the host computer server.

[0061] Normal operation: The old-processing information processing board 13 performs cyclic monitoring and reporting on each tested chip. For example, the old-processing information processing board 13 monitors the tested chip in channel 5, and its operating current is stable at 3A, with the heartbeat signal flipping every second. The data processed by the old-processing information processing board 13 is stably uploaded to the host computer server, and the visualization interface of the PC host computer 11 displays channel 5 in green.

[0062] Sudden anomaly: For example, a certain old information processing board 13 detected that the current of the chip under test in channel 12 suddenly rose to 6A within 1ms due to an internal short circuit (the upper limit threshold of current is set to 4.5A).

[0063] Protection Trigger: The ADC chip of a certain refurbished information processing board 13 collects the abnormal current value and reports it to the host computer server in the next data frame. The host computer server receives the corresponding TCP / IP data packet after about 10ms, and the alarm and protection rule engine immediately identifies that the current exceeds the limit. After about 5ms, the host computer server sends an emergency shutdown command to shut down channel 12 to 192.168.1.115 (i.e., the IP address of the refurbished information processing board 13) through the established TCP connection. The FPGA chip of the refurbished information processing board 13 parses the emergency shutdown command and controls the power management chip on the refurbished information processing board 13 to cut off the power supply to the chip under test in channel 12 within 1ms.

[0064] The handling of the above-mentioned abnormal situations can be collectively referred to as abnormal handling logic. The total response time from current abnormality to power cutoff is less than 20ms. The faulty chip under test is successfully isolated, and the chip aging board 14, the other 15 normal chips under test on the same chip aging board 14, and the power system are all promptly protected. The PC host computer 11 generates an alarm log at the corresponding chip location and notifies the aging test engineer.

[0065] The aforementioned chip aging system based on a distributed network enables multi-dimensional, synchronous, and real-time status monitoring of each chip under test, including but not limited to monitoring the chip's power supply current, operating voltage, core temperature (if measurable), and most importantly, program running status. This addresses the technical blind spot where functional failures cannot be detected in a timely manner. It also establishes a millisecond-level response mechanism from monitoring to protection, automatically and quickly cutting off the power to the faulty unit when hardware parameters exceed limits, preventing the fault from escalating and protecting test assets. A distributed system architecture based on standard Ethernet is constructed, allowing the system to linearly expand test capacity by simply adding 13 aging information processing units, while simultaneously achieving fault isolation between modules. A centralized host computer software has also been developed for unified management and visualization of all test data, providing intelligent alarm, data recording and analysis functions, and logging (electronic notepad) status files for each chip under test, realizing full-process information management of the aging test.

[0066] Compared to traditional technologies, the aforementioned chip aging system based on a distributed network has leaped from simply judging whether the chip is "powered on" to a comprehensive perception of its dynamic operating status, providing rich data support for failure analysis and achieving unprecedented depth of monitoring. It transforms traditional "post-event recording" into "in-event intervention," significantly reducing the risk of physical damage and economic losses during testing through a rapid protection mechanism that integrates hardware and software, establishing a proactive security defense system. The system's IP-based network architecture makes adding test channels as simple as plugging a network cable into a switch, easily adapting to the needs of modern mass production testing and giving the system high elasticity and scalability. Furthermore, centralized data management breaks down information silos, laying a solid foundation for predictive maintenance and intelligent diagnostics using big data, and improving the informatization and intelligence level of the testing process.

[0067] Overall, the aforementioned chip aging system based on distributed networks, through the organic combination of four core advantages—refined monitoring, proactive protection, distributed architecture, and information management—not only directly solves the pain points of existing aging test systems, but also generates significant synergistic benefits in improving test quality, ensuring test security, reducing test costs, and optimizing test processes. It provides an efficient, reliable, and future-oriented complete solution for the reliability screening of modern integrated circuits.

[0068] In one embodiment, such as Figure 5 As shown, a chip aging test method is also provided. Based on the above-mentioned distributed network-based chip aging system, the chip aging test method may include the following test steps S10 to S16: S10, after the test is started, the test stimulus is applied to the chip under test on the chip aging board through the aging information processing board, and the working current, voltage and program running status data of the chip under test are collected in real time. S12, through the old-fashioned information processing board, packages the collected data and uploads it to the PC host computer in real time via the local area network; S14, the PC host computer monitors the status of the chip under test based on the received data; if the program running status is abnormal, the PC host computer will issue an alarm prompt; if the current or voltage exceeds the set threshold, an emergency shutdown command will be immediately sent to the corresponding old information processing board through the local area network. S16, after receiving the emergency shutdown command, the old-fashioned information processing board performs power-off protection on the tested chip that has malfunctioned.

[0069] The aforementioned chip aging test method, through the hardware and software collaborative design based on the chip aging board, aging information processing board, network switch 12 and PC host computer, adopts an IP-based Ethernet architecture, realizing the physical and logical separation and coordination of monitoring, control and decision-making. It achieves a leap from extensive to intensive aging management, an evolution from passive recording to proactive protection, an upgrade from rigid centralization to flexible distribution, and an evolution from data silos to intelligent decision-making, significantly improving the overall efficiency of chip aging testing.

[0070] In one embodiment, when monitoring the program running status of the chip under test, a aging information processing board monitors heartbeat signals and data frame status signals. If no valid heartbeat signal or data frame status signal is detected within a preset time window, the program running status is determined to be abnormal. The test program for the chip under test incorporates periodically sent heartbeat signals and data frame status signals. Through this unique heartbeat or status monitoring mechanism, the system can effectively distinguish between a powered-on but frozen chip and a normal chip, overcoming the blind spots of traditional methods in functional testing and making aging failure screening more thorough.

[0071] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A chip burn-in system based on a distributed network, characterized by, The system comprises a PC host computer, a network switch 12, a burn-in information processing board and a chip burn-in board, one chip burn-in board and one burn-in information processing board are connected through a connector as a board card group, the board card group is not less than one, and the PC host computer is connected with each burn-in information processing board through the network switch 12; Each chip burn-in board is installed in a high-temperature box and is provided with a plurality of burn-in stations and a plurality of current monitors, one burn-in station is used for carrying one measured chip, each current monitor is used for measuring the electric signal of each power supply of each measured chip and feeding back to the burn-in information processing board, and the on-board connector of the burn-in station is used for connecting each communication interface of the measured chip; Each burn-in information processing board is installed outside the high-temperature box and is configured with a unique IP address, each burn-in information processing board is used for independently executing all signal interactions of the corresponding chip burn-in board and converting the electric signal into a high-precision digital value after collection, and the all signal interactions include test program issuing, test program running monitoring based on heartbeat and command frame, data frame uploading to the PC host computer and instruction control on the measured chip; The PC host computer is used for providing a man-machine interactive interface, globally monitoring, data storing and intelligently deciding the burn-in test of the measured chip based on Socket communication, and the intelligent decision includes state monitoring, alarm and emergency shutdown instruction issuing on the measured chip according to the network data frame uploaded by the burn-in information processing board.

2. The distributed network-based chip burn-in system of claim 1, wherein, The communication interface of the measured chip comprises at least one of UART, I2C, SPI and GPIO, the chip burn-in board and the burn-in information processing board are connected through a power supply connector, a digital signal connector and an analog signal connector respectively, the power supply connector is used for providing power supply for the measured chip, the digital signal connector is used for transmitting digital signals to the measured chip, and the analog signal connector is used for transmitting analog signals to the measured chip.

3. The distributed network-based chip burn-in system of claim 1 or 2, wherein, The current monitor is a sampling resistor, and each power supply of each measured chip is connected with a sampling resistor in series.

4. The distributed network-based chip burn-in system of claim 3, wherein, The sampling resistor is a patch resistor with a resistance of 20 mΩ, an accuracy of 0.1% and a temperature drift coefficient of less than 50 ppm / °C.

5. The distributed network-based chip burn-in system of claim 1 or 2, wherein, The current monitor is a non-contact current sensor, and one non-contact current sensor is installed on each power supply line of each measured chip.

6. The distributed network-based chip burn-in system of claim 2, wherein, The burn-in information processing board comprises an FPGA chip, an excitation signal generating circuit, a high-precision analog signal collecting circuit, a digital state monitoring circuit and a data framing and network communication circuit, and the FPGA chip is connected with the excitation signal generating circuit, the high-precision analog signal collecting circuit, the digital state monitoring circuit and the data framing and network communication circuit respectively; The excitation signal generating circuit is used for generating a clock signal and a reset signal from a BANK-IO interface of the FPGA chip and issuing a test program code stored in a Flash memory externally connected with the FPGA chip to each measured chip through a communication interface; The high-precision analog signal collecting circuit is used for amplifying the electric signal controlled and gated by the FPGA chip and then performing high-resolution ADC sampling and conversion; The digital state monitoring circuit is used for monitoring the state of the measured chip according to the state signal of the measured chip captured by the FPGA chip through the BANK-IO interface in real time. The data framing and network communication circuit is used for encapsulating the collected data into a network data frame and sending the network data frame to a specified IP address in the local area network according to the TCP / IP protocol.

7. The distributed network-based chip burn-in system of claim 6, wherein, The format of the network data frame is: [frame header 0xAA55] [measured chip state flag bit] [power supply input voltage value of the chip burn-in board] [power supply detection point voltage value of the measured chip].

8. The distributed network-based chip burn-in system of claim 1, wherein, The PC terminal host computer is based on Socket communication and is deployed with a multi-threaded data receiving and analysis engine, a real-time data visualization interface, an alarm and protection rule engine and an in-memory database.

9. A method of chip burn-in testing, the method comprising: The chip burn-in test method based on the chip burn-in system based on the distributed network according to any one of claims 1 to 8 comprises the steps of: After the test is started, the burn-in information processing board applies a test excitation to the measured chip on the chip burn-in board and collects the working current, voltage and program running state data of the measured chip in real time; The burn-in information processing board packs the collected data and uploads the data to the PC terminal host computer through the local area network in real time; The PC terminal host computer monitors the state of the measured chip based on the received data; if the program running state is abnormal, the PC terminal host computer gives an alarm prompt, and if the current or voltage exceeds the set threshold, the PC terminal host computer immediately issues an emergency shutdown instruction to the corresponding burn-in information processing board through the local area network; After receiving the emergency shutdown instruction, the burn-in information processing board performs power-off protection on the measured chip that has an abnormality.

10. The chip burn-in test method of claim 9, wherein, When monitoring the program running state of the measured chip, the burn-in information processing board monitors the heartbeat signal and the data frame state signal; if no valid heartbeat signal or data frame state signal is detected within a preset time window, it is determined that the program running state is abnormal; wherein the test program of the measured chip is implanted with the periodically sent heartbeat signal and data frame state signal.

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