Slot address identification method, device and equipment and computer readable storage medium
By identifying slot addresses using frequency ratios or multiple differences, this technology solves the problems of high cost, low reliability, and poor anti-interference in existing slot address identification technologies. It achieves high-precision, low-cost, and clock-bias-free slot address identification, which is suitable for power supply systems in the field of electrical measurement and control technology.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-11
- Publication Date
- 2026-03-17
AI Technical Summary
Existing slot address identification methods have shortcomings in terms of cost, reliability, anti-interference and scalability, especially in the case of electromagnetic interference and clock deviation, where it is difficult to achieve high-precision and high-reliability slot address identification.
The frequency ratio or frequency multiple difference is used as the identification basis. The periodic signal is obtained through the GPIO external interrupt function. The minimum error matching or rational number fitting algorithm is used to identify the slot address in a complex electromagnetic environment, avoiding the dependence on high-precision ADC.
It achieves high-precision, high-reliability, and low-cost slot address identification, is immune to clock skew, has excellent anti-interference capabilities and fast response, and is suitable for cost-sensitive large-scale applications.
Smart Images
Figure CN121679307A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electrical measurement and control technology, specifically to a slot address identification method, device, equipment, and computer-readable storage medium. Background Technology
[0002] Modular design has become a mainstream trend in power distribution and supply systems for modern data centers, industrial automation, and smart grids. This system typically consists of a backplane with multiple slots and several hot-swappable functional modules. Each slot is also equipped with a circuit breaker, which protects the functional modules within each slot. The circuit breaker acts as an automatic safety switch; when an overload (excessive current) or short circuit (extremely high current) occurs in the circuit, the circuit breaker automatically detects the abnormal current and quickly disconnects (trips) the circuit of the corresponding functional module, thus preventing overheating of wires, fires, or equipment burnout.
[0003] In order to achieve accurate power monitoring, load management, fault location and remote operation and maintenance, the system must be able to automatically and reliably identify the slot address of each circuit breaker, that is, assign a unique logical address to each circuit breaker.
[0004] Currently, the most common slot address identification method in the industry is the resistor voltage divider method. Its basic principle is: a set of precision resistors with different resistance values are pre-configured in each different slot on the base plate, forming a unique voltage divider network. When the circuit breaker module is inserted into the slot, the controller inside the module reads the voltage value output by this voltage divider network and converts the analog voltage into a digital value through its built-in analog-to-digital converter (ADC). The controller can then determine the current slot address of the circuit breaker by consulting a preset voltage-address mapping table.
[0005] However, the above methods have several inherent defects in practical applications, making it difficult to meet the application requirements of high reliability, high real-time performance, and complex electromagnetic environments. The specific defects are as follows: 1. High hardware dependence, high cost and power consumption: This method mandates that each circuit breaker module must have an ADC circuit of sufficient accuracy. This not only increases the bill of materials (BOM) cost and board area of a single module, but also significantly increases the overall cost for systems requiring a large number of circuit breakers. Furthermore, the operation of the ADC circuit generates additional power consumption, which is a disadvantage for systems seeking high energy efficiency.
[0006] 2. Poor anti-interference capability and low identification reliability: The power distribution and power supply system itself is a strong electromagnetic interference (EMI) environment, especially during high current switching. ADC sampling is extremely sensitive to analog signals and is easily affected by this noise, causing fluctuations or deviations in the sampled voltage values. Once the sampled value deviates from its correct voltage range, it will cause misjudgment of the slot address, which may lead to incorrect circuit breaker control, false alarms, or system management chaos, threatening the safe and stable operation of the entire power distribution system.
[0007] 3. Poor system compatibility due to clock skew: In some variant schemes that achieve identification by measuring pulse width or period, the accuracy depends on the accuracy of the circuit breaker's internal local clock. However, circuit breakers from different batches, manufacturers, or operating temperatures may have slight deviations in their local clock frequencies. This clock skew directly translates into timing errors, affecting the accuracy of address identification and leading to decreased system compatibility and stability across different modules.
[0008] 4. Limited Scalability and Accuracy: The number of addressable slots in this method is directly limited by the ADC resolution, the accuracy of the reference voltage, and the accuracy and temperature drift of the voltage divider resistors. To increase address capacity, the interval between adjacent voltage levels must be reduced, but this places more stringent demands on the ADC resolution and resistor accuracy, and amplifies the effects of temperature drift and noise. Therefore, under the premise of ensuring a certain level of reliability, there is a theoretical upper limit to the number of slots that this method can support, which restricts the scalability of large-scale modular systems.
[0009] In summary, existing slot address identification methods based on resistor voltage divider have inherent technical limitations and are insufficient in terms of cost, reliability, anti-interference, and scalability. Summary of the Invention
[0010] This application provides a slot address identification method, device, equipment, and computer storage medium, which can solve the technical problem of unreliable slot address identification caused by clock deviation and electromagnetic interference in power distribution and power supply systems in fields such as intelligent power distribution systems and industrial automation. It achieves the technical effect of high-precision, high-reliability, low-cost, and clock-deviation-immune automatic slot address identification.
[0011] In a first aspect, embodiments of this application provide a slot address identification method, the slot address identification method comprising: The first periodic signal from the X-channel output and the second periodic signal from the Y-channel output of the base plate are acquired, wherein the frequencies of the first periodic signal and the second periodic signal are both integer multiples of the frequency of a preset reference periodic signal; Based on the first periodic signal and the second periodic signal, the slot address is determined, which is used to indicate the address of the slot for inserting the functional module.
[0012] The above method solves the technical problem of unreliable slot address identification caused by clock deviation and electromagnetic interference in industrial sites, and achieves the technical effect of high-precision, high-reliability, low-cost, and completely clock-deviation-immune automatic slot address identification.
[0013] In conjunction with the first aspect, in one implementation, determining the slot address based on the first periodic signal and the second periodic signal includes: Obtain the frequency ratio of the first-cycle signal and the second-cycle signal; The frequency ratio is matched with each preset standard frequency ratio to determine the slot address.
[0014] In conjunction with the first aspect, in one embodiment, matching the frequency ratio with each preset standard frequency ratio to determine the slot address includes: Determine the degree of matching between the frequency ratio and each preset standard frequency ratio, and select the one with the highest degree of matching as the matching result; Based on the matching results, the slot address is determined.
[0015] In conjunction with the first aspect, in one embodiment, after determining the matching degree between the frequency ratio and each preset standard frequency ratio, the method further includes: If the matching degree is lower than the preset minimum matching degree, the matching is determined to be a failure, and a new identification is performed.
[0016] In conjunction with the first aspect, in one implementation, determining the slot address based on the first periodic signal and the second periodic signal includes: Obtain a first multiple and a second multiple, wherein the first multiple is a multiple of the frequency of the first period signal relative to the frequency of the preset reference period signal, and the second multiple is a multiple of the frequency of the second period signal relative to the frequency of the preset reference period signal. Determine the difference between the first multiple and the second multiple; The difference is matched with a preset frequency set to determine the slot address.
[0017] In conjunction with the first aspect, in one implementation, after obtaining the first multiple and the second multiple, the method further includes: Perform rational number fitting on the first multiple and the second multiple; Determine the difference between the fitted first multiple and the fitted second multiple.
[0018] In conjunction with the first aspect, in one implementation, both the first periodic signal and the second periodic signal are acquired through the GPIO (General Purpose Input / Output) interface on the baseboard.
[0019] Secondly, embodiments of this application provide a slot address identification device, the slot address identification device comprising: The acquisition module is used to acquire the first periodic signal output by the X-channel and the second periodic signal output by the Y-channel of the base plate, wherein the frequencies of the first periodic signal and the second periodic signal are both integer multiples of the frequency of a preset reference periodic signal; The determining module is used to determine the slot address based on the first periodic signal and the second periodic signal, wherein the slot address is used to indicate the address of the slot for inserting the functional module.
[0020] Thirdly, this application provides a slot address identification device, which includes a processor, a memory, and a slot address identification program stored in the memory and executable by the processor. When the slot address identification program is executed by the processor, it implements the steps of the above-described slot address identification method.
[0021] Fourthly, embodiments of this application provide a computer-readable storage medium storing a slot address identification program, wherein when the slot address identification program is executed by a processor, it implements the steps of the above-described slot address identification method.
[0022] The beneficial effects of the technical solutions provided in this application include: 1. Use frequency ratios (e.g.) The frequency ratio or frequency multiple difference (such as mn) is used as the identification basis. Since the integer multiples m and n of the preset reference frequency are fixed constants, the measured frequency ratio or theoretical value of the multiple difference remains unchanged regardless of the speed deviation of the circuit breaker's local clock. This fundamentally eliminates the identification error caused by the difference in clock accuracy between different circuit breakers, ensuring a high degree of consistency in the identification results of all units within the system.
[0023] 2. Pulse counting or period measurement is performed solely through external interrupts via GPIO, eliminating the need for an analog-to-digital converter (ADC). This approach eliminates the need for expensive analog components such as high-precision ADCs, reducing hardware costs. Simultaneously, it simplifies signal conditioning circuit design, resulting in a more compact system architecture and higher reliability, making it particularly suitable for deployment in cost-sensitive, large-scale applications.
[0024] 3. Minimum error matching or rational number fitting algorithms are used to match the measured values with predefined integer multiple standard combinations. In real-world environments with noise and interference, these algorithms can effectively filter out random errors in the measurement data, accurately "pulling" the disturbed measured values back to the theoretical integer ratios or differences, thereby resisting electromagnetic interference and significantly reducing the probability of misjudgment and identification failure.
[0025] 4. The set of integer multiples of the frequencies selected for X and Y channels (such as MX, MY) should preferably be coprime or have values that avoid simple harmonic relationships. This design avoids integer multiple relationships between the frequencies of signals from different slots, preventing circuit harmonics or signal crosstalk from causing a measurement value of one channel to be incorrectly matched to the characteristics of another slot. This reduces potential confusion at the signal source and improves the inherent robustness of the system. Attached Figure Description
[0026] Figure 1 This is a flowchart illustrating an embodiment of the slot address identification method of this application; Figure 2 This is a functional module diagram of an embodiment of the slot address identification device of this application; Figure 3 This is a schematic diagram of the hardware structure of the slot address identification device involved in the embodiment of this application. Detailed Implementation
[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0028] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0029] In a first aspect, embodiments of this application provide a slot address identification method.
[0030] In one embodiment, reference is made to Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the slot address identification method of this application. Figure 1 As shown, the slot address identification method includes: Step S10: Obtain the first periodic signal output from the X-channel and the second periodic signal output from the Y-channel of the base plate, wherein the frequencies of the first periodic signal and the second periodic signal are both integer multiples of the preset reference periodic signal frequency.
[0031] In some embodiments, a first cycle signal and a second cycle signal are output on the X and Y paths of the base plate, respectively. The GPIO1 port of the circuit breaker can receive the first cycle signal, and the GPIO2 port of the circuit breaker can receive the second cycle signal; the frequency of the first cycle signal... and the second periodic signal The frequencies are all preset reference period signal frequencies. Integer multiples of, that is: in, and They are taken from a predefined set of X-channel frequencies. and Y-channel frequency set Each slot corresponds to a unique Combination, set and In the selection of values, coprime values should be preferred or simple harmonic relationships should be avoided (e.g., avoiding...). ).
[0032] For example, the preset reference period signal frequency is set to ; X-channel frequency set: ; Y-channel frequency set: ; Each slot is assigned a unique frequency combination, such as slot 1 corresponding to Slot 2 corresponds to Slot 3 corresponds to wait.
[0033] Step S20: Determine the slot address based on the first periodic signal and the second periodic signal. The slot address is used to indicate the address of the slot for inserting the functional module.
[0034] In some embodiments, determining the slot address based on the first periodic signal and the second periodic signal includes: obtaining the frequency ratio of the first periodic signal and the second periodic signal; and matching the frequency ratio with each preset standard frequency ratio to determine the slot address.
[0035] It should be noted that each slot is equipped with a circuit breaker, which can be used to receive the first and second cycle signals. Functional modules include industrial I / O modules, communication gateways, or power supply modules. The specific addresses of the functional modules and circuit breakers on each slot can be determined by their slot addresses.
[0036] For example, the circuit breakers in each slot receive the first cycle signal of the X channel and the second cycle signal of the Y channel through GPIO1 and GPIO2 ports respectively, and are configured in external interrupt mode. Within a fixed time window (e.g., 1 ms), the processor in the circuit breaker counts the number of pulses in the X and Y channels, and records them as follows: and .
[0037] Processor calculation frequency ratio Since frequency is directly proportional to the number of pulses (within a fixed time window), this ratio directly corresponds to the frequency ratio of the X-channel and Y-channel signals, i.e. .
[0038] The measured frequency ratio The ratio of the pre-stored standard frequency (i.e., the X-channel frequency set) and Y-channel frequency set The matching is performed. The standard ratio is based on a predefined... The combined calculations yield the results, which are then stored in the circuit breaker's non-volatile memory.
[0039] For example, a minimum error matching algorithm can be used for matching. The specific steps include: 1. Calculate the measured ratio Ratio to each standard absolute error and They are taken from a predefined set of X-channel frequencies. and Y-channel frequency set .
[0040] 2. Select absolute error The smallest standard ratio is used as the matching result.
[0041] 3. If the minimum error is lower than the preset threshold (e.g., 0.01), the matching is considered successful and the corresponding slot address is output; otherwise, the matching is considered unsuccessful and a retest mechanism is triggered (e.g., re-acquiring the signal or enabling the backup address identification scheme).
[0042] Optionally, to improve robustness, a rational number fitting method can also be used. When the measured ratio When the noise or interference deviates from the theoretical value, the processor will Fit to the closest rational number (in and (The value is an integer), and then matched with a standard ratio. For example, the measured ratio is obtained when the circuit breaker's local clock is 1% faster than the reference clock. Map it to using a fitting algorithm This matches slot 2. Theoretically, if the local clock is synchronized with the reference clock, R should be measured as... Therefore, regardless of whether the local clock deviates from the reference clock, the final frequency ratio is the same. This embodiment brings the following technical effects: 1. Due to the frequency ratio Only depends on integer multiples and And the frequency of the preset reference period signal Regardless of the local clock deviation (e.g., 1% fast or slow), it is offset in the ratio calculation, thus ensuring that address identification is not affected by the circuit breaker clock accuracy.
[0043] 2. By using minimum error matching or rational number fitting, measurement errors and environmental interference can be effectively overcome, thus meeting real-time control requirements.
[0044] 3. The entire recognition process relies solely on GPIO external interrupts and processor software algorithms, eliminating the need for an analog-to-digital converter (ADC), thus reducing system cost and complexity.
[0045] 4. Predefined sets and In the selection of values, coprime values should be preferred or simple harmonic relationships should be avoided (e.g., avoiding...). This reduces the risk of misjudgment caused by frequency harmonic interference.
[0046] In some embodiments, determining the slot address based on the periodic signal includes: obtaining a first multiple and a second multiple, wherein the first multiple is a multiple of the frequency of the first periodic signal relative to the frequency of the preset reference periodic signal, and the second multiple is a multiple of the frequency of the second periodic signal relative to the frequency of the preset reference periodic signal; determining the difference between the first multiple and the second multiple; and matching the difference with a preset frequency set to determine the slot address.
[0047] For example, using a preset reference period signal frequency With 1kHz as the reference, the X-channel output frequency of the baseboard is... For signals that are integer multiples of m, the Y-channel output frequency is Signals that are integer multiples of n. The correspondence between predefined slot addresses and (m,n) combinations is shown in Table 1: Table 1 The circuit breaker acquires the first cycle signal of the X channel and the second cycle signal of the Y channel via an external GPIO interrupt. This is done within a precise measurement window. Inside: Count the number of X-channel pulses Calculate the measured frequency ; Count the number of pulses in the Y channel Calculate the measured frequency ; Calculate the measured multiples: , .
[0048] Optionally, in some embodiments, after obtaining the first multiple and the second multiple, the method further includes: performing rational number fitting on the first multiple and the second multiple; and determining the difference between the fitted first multiple and the fitted second multiple.
[0049] The processor calculates the measured multiple difference d' = m' - n'.
[0050] The measured difference d' is matched with a pre-stored set of standard deviations. The standard deviations are calculated based on predefined (m,n) combinations and stored as theoretical multiples in Table 1.
[0051] A hierarchical matching strategy is adopted: 1. Coarse matching stage: Calculate |d' - d_i (preset standard deviation)|, and filter out the top k candidate slots with the smallest difference (k≥2); 2. Fine matching stage: Within the candidate slots, verification is performed by combining the integer properties of m' and n'; 3. Final determination: Select the slot that simultaneously satisfies the condition that the difference is closest to the standard deviation and the multiple is closest to the integer as the recognition result.
[0052] When the minimum matching error exceeds the threshold δ=0.5, the matching is deemed to have failed, and the retest process is automatically started, with a maximum of 3 retries.
[0053] This embodiment brings the following technical effects: 1. This method effectively overcomes common electromagnetic interference problems in industrial environments by employing a frequency multiple difference matching mechanism. Even in complex electromagnetic environments, the system maintains stable identification performance, demonstrating excellent anti-interference capabilities and ensuring the accuracy and reliability of address identification.
[0054] 2. Based on the calculation characteristics of frequency multiple differences, this method inherently possesses the ability to eliminate the influence of clock deviation. When a clock frequency deviation exists in the system, the measured values of each frequency change proportionally, and the difference remains unchanged, thus fundamentally solving the identification error problem caused by insufficient clock accuracy.
[0055] 3. Through optimized algorithm design and efficient matching strategy, this method achieves rapid address identification. The entire identification process is completed in a very short time, fully meeting the stringent real-time requirements of industrial control systems and ensuring timely system response.
[0056] 4. Compared to traditional frequency ratio calculation methods, this method employs a difference matching mechanism, significantly reducing computational complexity and minimizing processor resource consumption. This characteristic makes this method particularly suitable for resource-constrained embedded systems, providing a technical foundation for the implementation of low-cost hardware platforms.
[0057] 5. The system employs a hierarchical matching strategy and a multi-verification mechanism to effectively avoid misidentification. When encountering abnormal measurement results, the system can automatically initiate a retest process, ensuring high operational reliability even under non-ideal operating conditions.
[0058] 6. The entire identification process only requires basic GPIO interrupt functions and processor computing power, without relying on high-precision clock sources or complex analog-to-digital conversion circuits, which significantly reduces system hardware costs and design complexity.
[0059] Secondly, embodiments of this application also provide a slot address identification device 00.
[0060] In one embodiment, reference is made to Figure 2 , Figure 2 This is a functional module diagram of an embodiment of the slot address identification device of this application. Figure 2 As shown, the slot address identification device includes: Acquisition module 01 is used to acquire the first periodic signal output by the X-channel and the second periodic signal output by the Y-channel of the base plate, wherein the frequencies of the first periodic signal and the second periodic signal are both integer multiples of the preset reference periodic signal frequency; The determining module 02 is used to determine the slot address based on the first periodic signal and the second periodic signal, wherein the slot address is used to indicate the address of the slot for inserting the functional module.
[0061] Furthermore, in one embodiment, the slot address identification device further includes a new module, wherein the determining module 02 is also used for: Obtain the frequency ratio of the first-cycle signal and the second-cycle signal; The frequency ratio is matched with each preset standard frequency ratio to determine the slot address.
[0062] Furthermore, in one embodiment, the slot address identification device further includes a new module, wherein the determining module 02 is also used for: Determine the degree of matching between the frequency ratio and each preset standard frequency ratio, and select the one with the highest degree of matching as the matching result; Based on the matching results, the slot address is determined.
[0063] Furthermore, in one embodiment, the slot address identification device further includes a new module, wherein the determining module 02 is also used for: If the matching degree is lower than the preset minimum matching degree, the matching is determined to be a failure, and a new identification is performed.
[0064] Furthermore, in one embodiment, the slot address identification device further includes a new module, wherein the determining module 02 is also used for: Obtain a first multiple and a second multiple, wherein the first multiple is a multiple of the frequency of the first period signal relative to the frequency of the preset reference period signal, and the second multiple is a multiple of the frequency of the second period signal relative to the frequency of the preset reference period signal. Determine the difference between the first multiple and the second multiple; The difference is matched with a preset frequency set to determine the slot address.
[0065] Furthermore, in one embodiment, the slot address identification device further includes a new module, wherein the determining module 02 is also used for: Perform rational number fitting on the first multiple and the second multiple; Determine the difference between the fitted first multiple and the fitted second multiple.
[0066] Furthermore, in one embodiment, the slot address identification device further includes a new module, wherein the determining module 02 is also used for: Both the first periodic signal and the second periodic signal are obtained through the GPIO (General Purpose Input / Output) interface on the baseboard.
[0067] The functions of each module in the above slot address identification device correspond to the steps in the above slot address identification method embodiment, and their functions and implementation processes will not be described in detail here.
[0068] Thirdly, embodiments of this application provide a slot address identification device, which can be a personal computer (PC), laptop computer, server, or other device with data processing capabilities.
[0069] Reference Figure 3 , Figure 3 This is a schematic diagram of the hardware structure of the slot address identification device involved in the embodiment of this application. In this embodiment, the slot address identification device 20 may include a processor 21, a memory 22, a communication interface 23, and a communication bus 24.
[0070] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.
[0071] The communication interface includes input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within the slot address identification device, as well as interfaces used for interconnecting the slot address identification device with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.
[0072] Memory can be various types of storage media, such as random-access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.
[0073] The processor can be a general-purpose processor, which can call a slot address identification program stored in memory and execute the slot address identification method provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the slot address identification program is called can be referred to in various embodiments of the slot address identification method of this application, and will not be repeated here.
[0074] Those skilled in the art will understand that Figure 3 The hardware structure shown does not constitute a limitation of this application and may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0075] Fourthly, embodiments of this application also provide a computer-readable storage medium.
[0076] The present application has a slot address identification program stored on a computer-readable storage medium, wherein when the slot address identification program is executed by a processor, it implements the steps of the slot address identification method described above.
[0077] The method implemented when the slot address identification program is executed can be referred to in various embodiments of the slot address identification method of this application, and will not be repeated here.
[0078] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0079] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.
[0080] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.
[0081] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.
[0082] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.
[0083] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.
[0084] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A slot address identification method, characterized by, The slot address identification method comprises: obtaining a first periodic signal of X output of a bottom plate and a second periodic signal of Y output, wherein the frequency of the first periodic signal and the second periodic signal is an integer multiple of a preset reference periodic signal frequency; determining a slot address according to the first periodic signal and the second periodic signal, wherein the slot address is used to indicate the address of a slot for plugging a functional module.
2. The slot address identifying method of claim 1, wherein, The determining a slot address according to the first periodic signal and the second periodic signal comprises: obtaining a frequency ratio of the first periodic signal and the second periodic signal; matching the frequency ratio with each preset standard frequency ratio to determine the slot address.
3. The slot address identifying method of claim 2, wherein, The matching the frequency ratio with each preset standard frequency ratio to determine the slot address comprises: determining the matching degree between the frequency ratio and each preset standard frequency ratio, and selecting the one with the highest matching degree as the matching result; determining the slot address according to the matching result.
4. The slot address identifying method of claim 3, wherein, After the determining the matching degree between the frequency ratio and each preset standard frequency ratio, the method further comprises: if the matching degree is lower than a preset minimum matching degree, determining that the matching fails, and re-identifying.
5. The slot address identification method of claim 1, wherein, The determining a slot address according to the first periodic signal and the second periodic signal comprises: obtaining a first multiple and a second multiple, wherein the first multiple is the multiple of the frequency of the first periodic signal relative to the preset reference periodic signal frequency, and the second multiple is the multiple of the frequency of the second periodic signal relative to the preset reference periodic signal frequency; determining the difference between the first multiple and the second multiple; matching the difference with a preset frequency set to determine the slot address.
6. The slot address identifying method of claim 5, wherein, After the obtaining the first multiple and the second multiple, the method further comprises: rational number fitting the first multiple and the second multiple; determining the difference between the fitted first multiple and the fitted second multiple.
7. The slot address identification method of claim 1, wherein, The first periodic signal and the second periodic signal are obtained through a GPIO (General Purpose Input / Output) interface on the bottom plate.
8. A slot address identifying apparatus, characterized by comprising: The slot address identification device comprises: an obtaining module, configured to obtain a first periodic signal of X output of a bottom plate and a second periodic signal of Y output, wherein the frequency of the first periodic signal and the second periodic signal is an integer multiple of a preset reference periodic signal frequency; a determining module, configured to determine a slot address according to the first periodic signal and the second periodic signal, wherein the slot address is used to indicate the address of a slot for plugging a functional module.
9. A slot address identifying apparatus, characterized by comprising: The slot address identification device comprises a processor, a memory, and a slot address identification program stored in the memory and executable by the processor, wherein when the slot address identification program is executed by the processor, the steps of the slot address identification method in any one of claims 1 to 7 are implemented.
10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a slot address identification program, wherein when the slot address identification program is executed by a processor, the steps of the slot address identification method in any one of claims 1 to 7 are implemented.