Wide temperature range mosfet threshold voltage stabilization method and system

Abstract

The application provides a wide-temperature-range MOSFET threshold voltage stabilization method and system, a temperature self-adaptive floating gate unit is embedded in a gate medium, the unit is in thermal coupling with a main channel but is electrically isolated, the charge change law of the unit has matched thermodynamic characteristics with an interface state relaxation process; meanwhile, a specific combined double-frequency-band gate bias signal is applied, a local electromagnetic field excited by a high-frequency component accelerates the interface charge redistribution, a low-frequency component realizes dynamic anchoring of the channel potential; and a distributed thermal-electricity collaborative calibration node is additionally used for real-time compensation; the threshold voltage path dependence caused by the interface state charge relaxation is effectively eliminated, the stabilization time after temperature change is significantly shortened, and the MOSFET realizes stable control of the threshold voltage in a wide-temperature-range range, thereby providing a reliable device basis for a low-temperature electronic system.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method and system for stabilizing the threshold voltage of a wide-temperature-range MOSFET. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are fundamental components of modern electronic systems, and the temperature stability of their threshold voltage is crucial for applications in extreme environments. In cutting-edge fields such as deep space exploration, cryogenic electronics, and quantum computing, MOSFETs need to maintain stable electrical characteristics over extremely wide temperature ranges. Existing technologies typically employ uniform channel doping structures, single-layer gate dielectrics, and fixed bias strategies to improve temperature characteristics. Some solutions also incorporate external temperature compensation circuits, achieving certain results within conventional temperature ranges.

[0003] However, under low-temperature operating conditions, existing technologies face a fundamental challenge: the thermal relaxation process of interface state charges slows down significantly as the temperature decreases, with its relaxation time constant increasing exponentially with decreasing temperature. When the device experiences temperature changes, the interface state charges cannot reach thermal equilibrium in time, resulting in a significant hysteresis effect. This non-equilibrium charge distribution causes the MOSFET's threshold voltage to depend not only on the current temperature but also on its previous thermal history, manifesting as significant threshold voltage differences at the same temperature due to different heating and cooling paths. Furthermore, even after the temperature stabilizes, the threshold voltage continues to drift for a considerable period. This threshold voltage instability caused by the relaxation hysteresis of interface state charges renders traditional static compensation methods ineffective, severely limiting the reliable application of MOSFETs in low-temperature environments. Summary of the Invention

[0004] The present invention aims to provide a method and system for stabilizing the threshold voltage of a wide-temperature-range MOSFET, which effectively eliminates the threshold voltage path dependence caused by interface state charge relaxation and significantly shortens the stabilization time after temperature changes.

[0005] To achieve the above objectives, the technical solution adopted by this invention is: a method for stabilizing the threshold voltage of a wide-temperature-range MOSFET, comprising:

[0006] A channel structure with longitudinal and lateral boron concentration gradients is constructed on the surface of a silicon substrate, and an asymmetric gate dielectric stack composed of alumina, silicon dioxide with gradually varying oxygen content and lanthanum oxide is formed on the surface of the channel structure.

[0007] A dual-band gate bias signal of 15kHz low frequency and 120MHz high frequency is applied to the asymmetric gate dielectric stack;

[0008] A silicon-germanium buffer layer with a germanium composition gradient is implanted at the interface between the channel and the gate dielectric, and phosphorus ions are injected on both sides of the silicon-germanium buffer layer to form a charge compensation region on the channel sidewall.

[0009] The nickel-chromium alloy floating gate unit is embedded inside the gate dielectric. The floating gate unit is connected to the gate feedback circuit. Calibration nodes are set at the four corners of the chip. Each calibration node integrates a heater, a temperature sensor and a MOSFET sensing unit.

[0010] The calibration node and MOSFET structure are encapsulated in a sealed cavity containing a mixture of nitrogen and hydrogen.

[0011] Preferably, the channel structure for constructing longitudinal and transverse boron concentration gradient distributions includes:

[0012] A single-crystal silicon epitaxial layer is grown on the surface of a silicon substrate, and the first round of boron ion implantation is performed on the epitaxial layer to form an initial acceptor distribution;

[0013] Based on the initial acceptor distribution, a second round of tilted boron ion implantation was performed to cause boron atoms to shift along the channel length direction;

[0014] The implanted structure is subjected to rapid thermal annealing to create a linear concentration gradient of boron atoms. A silicon nitride cap layer is then deposited on the surface of the annealed structure, followed by nitrogen-containing plasma treatment.

[0015] Preferably, the rapid thermal annealing increases the concentration at the source end and decreases the concentration at the drain end, forming a linear concentration gradient along the channel length direction. This gradient causes the channel carrier density to change gradually at low temperatures.

[0016] Preferably, forming the asymmetric gate dielectric stack composed of alumina, silicon dioxide with gradually varying oxygen content, and lanthanum oxide includes:

[0017] An aluminum oxide layer is deposited on the surface of the silicon nitride cap layer, and the aluminum oxide layer is subjected to in-situ oxygen plasma treatment.

[0018] A silica layer with a gradually varying oxygen content is grown on the treated alumina layer, and fluorine ions are implanted onto the surface of the silica layer to form a negative charge distribution.

[0019] A lanthanum oxide layer is deposited on the structure after fluorine ion implantation, forming a stepped conduction band shift structure.

[0020] Preferably, the silicon dioxide layer with gradually varying oxygen content has a linearly increasing bandgap, which makes the electron tunneling path change gradually with temperature at low temperatures, avoiding sudden changes in threshold voltage.

[0021] Preferably, applying a dual-band gate bias signal of 15kHz low frequency and 120MHz high frequency to the asymmetric gate dielectric stack includes:

[0022] A polycrystalline silicon gate electrode is formed on the lanthanum oxide layer, and the polycrystalline silicon gate electrode is connected to a dual-band voltage source.

[0023] High-frequency components are used to excite a local electromagnetic field within the silicon dioxide layer, thereby shortening the interface state release time.

[0024] By introducing phase modulation of the low-frequency envelope, the channel surface potential is forced to lock into a periodic steady state.

[0025] Then, a gate voltage feedback loop is constructed to maintain the first derivative of the threshold voltage with respect to temperature at a preset value.

[0026] Preferably, the phase modulation causes the center of the channel surface potential resonance peak to fall at a preset frequency, corresponding to a time constant, so that the average temperature coefficient of the surface potential is significantly lower than that of the unmodulated state.

[0027] Preferably, the silicon-germanium buffer layer with a germanium composition gradient implanted at the channel-gate dielectric interface comprises:

[0028] A silicon-germanium buffer layer is epitaxially grown on the surface of a silicon nitride cap layer, and the germanium content in the silicon-germanium buffer layer increases linearly from bottom to top.

[0029] Helium ion pre-irradiation was applied to the surface of the silicon-germanium buffer layer to form nanoscale void clusters.

[0030] A silicon nitride intercalation layer was deposited on the irradiated silicon-germanium buffer layer, and a boron surface redistribution annealing was performed on the surface of the silicon nitride intercalation layer to form a boron-enriched layer.

[0031] Preferably, the nanoscale void clusters formed by helium ion pre-irradiation serve as stress relaxation centers, absorbing lattice contraction differences and reducing residual stress at low temperatures.

[0032] On the other hand, the present invention proposes a wide-temperature-range MOSFET threshold voltage stabilization system, comprising:

[0033] A dual-gradient doped channel structure unit is formed on the surface of a silicon substrate and has a longitudinal and lateral boron concentration gradient distribution.

[0034] An asymmetric gate dielectric stack unit is disposed on the surface of a dual-gradient doped channel structure unit and is composed of an aluminum oxide layer, a silicon dioxide layer with gradually varying oxygen content, and a lanthanum oxide layer stacked sequentially.

[0035] A dual-band gate bias sequence unit is connected to an asymmetric gate dielectric stack unit to generate a 15kHz low-frequency component and a 120MHz high-frequency component.

[0036] The silicon-germanium strain-matching buffer layer unit is located at the interface between the channel structure and the asymmetric gate dielectric stack. The germanium composition in the silicon-germanium strain-matching buffer layer unit gradually changes along the thickness direction.

[0037] The channel sidewall charge compensation band unit is disposed on both sides of the silicon-germanium buffer layer and is formed by phosphorus ion implantation;

[0038] Temperature-adaptive floating gate cell, embedded inside an asymmetric gate dielectric stack, is made of nickel-chromium alloy thin film and connected to the gate feedback circuit;

[0039] The multi-node thermal-electric co-calibration network unit includes calibration nodes arranged at the four corners of the chip, and each calibration node includes a heater, a temperature sensor and a MOSFET sensing unit;

[0040] The wide-temperature-range closed-loop packaging system unit includes a substrate, an electromagnetic shielding layer, a humidity sensor, a pressure sensor, and a sealed cavity filled with a mixture of nitrogen and hydrogen.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0042] This invention embeds a temperature-adaptive floating gate unit inside the gate dielectric. This unit is thermally coupled but electrically isolated from the main channel, and its charge change law has thermodynamic characteristics that match the interface state relaxation process. Simultaneously, a specific combination of dual-band gate bias signals is applied, and the interface charge redistribution is accelerated by the local electromagnetic field excited by the high-frequency component, while the low-frequency component achieves dynamic anchoring of the channel potential. This is further supplemented by distributed thermo-electrical co-calibration nodes for real-time compensation. This effectively eliminates the threshold voltage path dependence caused by interface state charge relaxation, significantly shortens the settling time after temperature changes, and enables stable threshold voltage control of the MOSFET over a wide temperature range, providing a reliable device foundation for low-temperature electronic systems. Attached Figure Description

[0043] Figure 1 This is a flowchart of the wide-temperature-range MOSFET threshold voltage stabilization method of the present invention;

[0044] Figure 2 This is a block diagram of the wide-temperature-range MOSFET threshold voltage stabilization system of the present invention. Detailed Implementation

[0045] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0046] like Figure 1 As shown, this invention proposes a method for stabilizing the threshold voltage of a wide-temperature-range MOSFET. The core of this method lies in identifying and compensating for the non-monotonic threshold voltage transition phenomenon in the low-temperature range, which is caused by the abrupt change in the ionization state of shallow-level doped atoms in the silicon-based channel and the reconstruction of the direct tunneling path of carriers in the thin oxide layer of the gate. Specifically, it includes the following:

[0047] Constructing a channel structure with longitudinal and lateral boron concentration gradients on a silicon substrate surface specifically includes: growing a single-crystal silicon epitaxial layer on the silicon substrate surface; performing a first round of boron ion implantation on the epitaxial layer to form an initial acceptor distribution; performing a second round of tilted boron ion implantation based on the initial acceptor distribution to cause boron atoms to shift along the channel length direction; performing rapid thermal annealing on the implanted structure to form a linear concentration gradient of boron atoms; depositing a silicon nitride cap layer on the surface of the annealed structure; and performing nitrogen-containing plasma treatment.

[0048] As described above, rapid thermal annealing increases the concentration at the source end and decreases the concentration at the drain end, forming a linear concentration gradient along the channel length. This gradient causes the channel carrier density to change gradually at low temperatures. This linear concentration gradient enables the ionization behavior of shallow-level acceptors in the channel to exhibit a continuous and smooth temperature response over a wide temperature range, effectively suppressing threshold voltage jumps caused by carrier freezing at low temperatures and improving the turn-on consistency and operational stability of the MOSFET in the low-temperature region.

[0049] An asymmetric gate dielectric stack consisting of alumina, silicon dioxide with gradually varying oxygen content, and lanthanum oxide is formed on the surface of the channel structure. Specifically, this includes: depositing an alumina layer on the surface of a silicon nitride cap layer and subjecting the alumina layer to in-situ oxygen plasma treatment; growing a silicon dioxide layer with gradually varying oxygen content on the treated alumina layer and implanting fluorine ions into the surface of the silicon dioxide layer to form a negative charge distribution; and depositing a lanthanum oxide layer on the structure after fluorine ion implantation to form a stepped conduction band offset structure.

[0050] As described above, the silicon dioxide layer with gradually varying oxygen content has a linearly increasing bandgap, which makes the electron tunneling path change gradually with temperature at low temperatures, avoiding sudden changes in threshold voltage. This gradually varying bandgap structure significantly reduces the temperature sensitivity of the direct tunneling current at low temperatures, suppresses the sharp threshold voltage change caused by the tunneling mechanism, and ensures the continuous controllability of the MOSFET's subthreshold characteristics and switching behavior in the low-temperature region.

[0051] Applying dual-band gate bias signals of 15kHz low frequency and 120MHz high frequency to an asymmetric gate dielectric stack; specifically including: forming a polysilicon gate electrode on a lanthanum oxide layer and connecting the polysilicon gate electrode to a dual-band voltage source; using the high-frequency component to excite a local electromagnetic field in the silicon dioxide layer to shorten the interface state release time; introducing phase modulation of the low-frequency envelope to force the channel surface potential to be locked in a periodic steady state; and then constructing a gate voltage feedback loop to maintain the first derivative of the threshold voltage with respect to temperature at a preset value.

[0052] As described above, phase modulation ensures that the center of the channel surface potential resonance peak falls at a preset frequency, corresponding to a time constant, resulting in a significantly lower average temperature coefficient of the surface potential compared to the unmodulated state. This dual-band bias synergy enables the channel surface potential to maintain a dynamic steady state during temperature changes, effectively decoupling the timing mismatch between interface state relaxation hysteresis and channel potential response, significantly reducing the dependence of the threshold voltage on the rate of temperature change, and improving the transient stability of the device under varying temperature conditions.

[0053] A silicon-germanium buffer layer with a germanium composition gradient is implanted at the interface between the channel and the gate dielectric, and phosphorus ions are injected on both sides of the silicon-germanium buffer layer to form a charge compensation region on the channel sidewall.

[0054] The process of implanting a silicon-germanium buffer layer with a gradually increasing germanium composition at the channel-gate interface includes: epitaxially growing a silicon-germanium buffer layer on the surface of a silicon nitride cap layer, with the germanium composition increasing linearly from bottom to top; pre-irradiating the surface of the silicon-germanium buffer layer with helium ions to form nanoscale void clusters; depositing silicon nitride intercalations on the irradiated silicon-germanium buffer layer; and performing boron surface redistribution annealing on the surface of the silicon nitride intercalations to form a boron-rich layer. The nanoscale void clusters formed by helium ion pre-irradiation act as stress relaxation centers, absorbing lattice contraction differences and reducing residual stress at low temperatures. This structure effectively alleviates band distortion caused by increased lattice mismatch at low temperatures, suppresses the abnormal increase in interface state density caused by stress concentration, thereby stabilizing the effective barrier height of the channel region and reducing the nonlinear shift of the threshold voltage at low temperatures.

[0055] A nickel-chromium alloy floating gate unit is embedded inside the gate dielectric. This floating gate unit is connected to the gate feedback circuit, and calibration nodes are positioned at the four corners of the chip. Each calibration node integrates a heater, a temperature sensor, and a MOSFET sensing unit. The calibration nodes and MOSFET structure are encapsulated in a sealed cavity containing a nitrogen and hydrogen mixture. This integrated structure achieves on-chip real-time sensing, dynamic compensation, and environmental disturbance isolation of threshold voltage drift, enabling the device to possess self-calibration capabilities and long-term operational stability over a wide temperature range, significantly improving parameter consistency and robustness in system-level applications.

[0056] On the other hand, this invention proposes a wide-temperature-range MOSFET threshold voltage stabilization system, such as... Figure 2 As shown, it includes:

[0057] A dual-gradient doped channel structure unit is formed on the surface of a silicon substrate and has a longitudinal and lateral boron concentration gradient distribution.

[0058] An asymmetric gate dielectric stack unit is disposed on the surface of a dual-gradient doped channel structure unit and is composed of an aluminum oxide layer, a silicon dioxide layer with gradually varying oxygen content, and a lanthanum oxide layer stacked sequentially.

[0059] A dual-band gate bias sequence unit is connected to an asymmetric gate dielectric stack unit to generate a 15kHz low-frequency component and a 120MHz high-frequency component.

[0060] The silicon-germanium strain-matching buffer layer unit is located at the interface between the channel structure and the asymmetric gate dielectric stack. The germanium composition in the silicon-germanium strain-matching buffer layer unit gradually changes along the thickness direction.

[0061] The channel sidewall charge compensation band unit is disposed on both sides of the silicon-germanium buffer layer and is formed by phosphorus ion implantation;

[0062] Temperature-adaptive floating gate cell, embedded inside an asymmetric gate dielectric stack, is made of nickel-chromium alloy thin film and connected to the gate feedback circuit;

[0063] The multi-node thermal-electric co-calibration network unit includes calibration nodes arranged at the four corners of the chip, and each calibration node includes a heater, a temperature sensor and a MOSFET sensing unit;

[0064] The wide-temperature-range closed-loop packaging system unit includes a substrate, an electromagnetic shielding layer, a humidity sensor, a pressure sensor, and a sealed cavity filled with a mixture of nitrogen and hydrogen.

[0065] Specifically, each unit in this system is also used to implement the following steps:

[0066] Step 1: Construct a dual-gradient doped channel structure to achieve a smooth transition in the temperature response of the shallow-level ionization state;

[0067] This step aims to address the issue of low boron / phosphorus acceptor / donor atom ionization rate in traditional uniformly doped channels at low temperatures. The effective carrier concentration in the channel decreases sharply. The problem of discontinuous collapse. When the temperature drops below 180K, silicon experiences a significant ionization energy... Corresponding Boltzmann factor The decay to 0.037 causes over 96% of the acceptor atoms to enter a frozen state, resulting in a wide depletion region. A sudden increase drives the threshold voltage to jump upwards. This step introduces a concentration gradient simultaneously in the channel longitudinally (perpendicular to the gate dielectric direction) and laterally (source-drain direction), causing the ionization annealing process to unfold along two dimensions, extending the ionization rate variation range, thereby... The transition zone expands from a single point into a continuous temperature range.

[0068] Step 1.1: Grow a material with a thickness of [thickness value missing] on the surface of the silicon substrate. A single-crystal silicon epitaxial layer is used as the channel host material; subsequently, source and drain implantation windows are defined on the epitaxial layer, and the first round of boron ion implantation is performed with a dose of [missing value]. The energy was 3.2 keV, and the injection direction was perpendicular to the surface, forming the initial acceptor distribution. ,in For source and drain directions, In the horizontal width direction, The implantation is performed vertically, with the origin located at the gate dielectric / silicon interface; this implantation results in a peak acceptor concentration at the center of the channel body region reaching [value missing]. However, due to limitations in injected energy, the concentration is... The orientation follows a Gaussian distribution, with a full width at half maximum (FWHM) of 100%. This distribution forms the spatial benchmark for subsequent gradient regulation.

[0069] Step 1.2: Based on the results obtained in Step 1.1 Distribution, implementing the second round of tilt angle is Boron ion implantation, dose of The energy is 4.8 keV, and the injection direction is... In-plane; this injection causes boron atoms to have a displacement component along the channel length direction. and in Directional penetration deepens, full width at half maximum (FWHM) expands to The resulting superimposed acceptor concentration distribution becomes...

[0070]

[0071] in For the equivalent longitudinal displacement, this equation shows that the new distribution is not a simple superposition, but rather a shift of the original distribution along... and The superposition of the two axes after rigid translation results in the overall concentration field being... The direction exhibits an asymmetry, with the left shoulder raised and the right shoulder lowered. The direction is manifested as the concentration in the shallow layer being diluted and the concentration in the deep layer being enhanced; this asymmetry becomes the basis for the subsequent spatial separation of ionized states.

[0072] Step 1.3: The structure obtained in Step 1.2 was subjected to rapid thermal annealing at a peak temperature of 920℃ for 7 seconds in a nitrogen atmosphere. During the annealing process, boron atoms underwent Fick diffusion, and their diffusion coefficient satisfied... ,in Because the boron concentration in step 1.2 is... There is a gradient in direction, and the diffusion flux... The flow rate is negative (net inflow) on the left side of the channel (near the source) and positive (net outflow) on the right side (near the drain), causing boron atoms to migrate directionally from the drain to the source; the migration distance is obtained from the diffusion equation: ,in For mobility, Since there is a built-in electric field, but no external electric field is applied during the annealing stage, the dominant term is diffusion drift driven by the concentration gradient, and the calculated source-end concentration increase is... Drain end reduction , forming along Linear concentration gradient in the direction This gradient causes the proportion of ionized atoms at the source end to be higher than that at the drain end at the same temperature, and the ionized state is no longer concentrated at a single temperature point, but spreads along the channel length.

[0073] Step 1.4: Deposit a layer with a thickness of [thickness missing] on the surface of the structure completed in Step 1.3. The silicon nitride cap layer was then subjected to nitrogen-containing plasma treatment at a power of 180W for 90 seconds, using a gas of... This treatment allows nitrogen atoms to diffuse into the silicon surface layer. A nitrogen-doped correction layer is formed in the interval, with a nitrogen concentration distribution as follows: ,in Nitrogen atoms occupy substitutional positions in silicon, introducing shallow donor levels. Its ionization rate With boron acceptor ionization rate They exhibit complementary properties at low temperatures: when hour, Approaching zero, and It remains within the 0.18–0.33 range; therefore, in the uppermost layer of the channel... Within the channel, effective charge carriers are provided by nitrogen donors, compensating for the hole loss caused by the freezing of boron acceptors; this compensation effect makes the top region of the channel... The rate of decay is reduced by 57% in the 120–160K range, thereby suppressing the upward expansion of the depletion region and laying the space charge foundation for subsequent gate control stability.

[0074] Step 2: Design an asymmetric gate dielectric stack and control the progressive reconstruction of the direct tunneling path at low temperatures;

[0075] In the established dual-gradient channel structure, another dominant factor in the low-temperature range—the direct electron tunneling probability in the gate dielectric—is addressed. The problem of nonlinear increase with decreasing temperature. In traditional In gate dielectrics, when the temperature is below 180K, lattice vibrations weaken, phonon-assisted tunneling contributions disappear, and electrons tunnel through the barrier solely via quantum mechanical means; at this point, the tunneling current density... ,in For the effective barrier height, It represents the oxide layer thickness; however, this formula implicitly includes... and This is based on the assumption of constants, but in reality at low temperatures, Interface state charge The accumulation of deep-level traps due to their decreased release rate leads to an enhanced interface dipole moment. A reduction of approximately 0.15–0.22 eV, making A 2.8-fold jump near 150K induces a negative shift in the threshold voltage superimposed on the aforementioned positive jump, exacerbating nonlinearity. This step involves constructing an upper-layer high... The asymmetric stacking of the dielectric and the underlying gradient bandgap oxide allows the tunneling path to gradually shift along the thickness direction as the temperature decreases, avoiding abrupt changes in the barrier parameters.

[0076] Step 2.1: On the surface of the silicon nitride cap layer formed in Step 1.4, a first dielectric layer is grown using atomic layer deposition. The material is... Thickness control is The deposition temperature is This layer serves as the upper high-dielectric-constant dielectric, and its relative permittivity is... Electron affinity The position of the conduction band bottom relative to the vacuum level After deposition, the structure was subjected to in-situ oxygen plasma treatment at a power of 120W for 45 seconds. The surface layer is approximately 0.2 nm thick. The oxygen vacancy density in the transition layer is controlled at... This vacancy, acting as a shallow donor center, can provide a fixed negative charge at low temperatures. This is used to counteract the accumulation of positive interface charge that may occur in subsequent steps.

[0077] Step 2.2: On the structure obtained in Step 2.1, a second dielectric layer is grown using low-pressure chemical vapor deposition (LPCVD), with the material being a gradient composition. The deposition temperature is The gas is and The air-fuel mixture is dynamically adjusted. The flow rate causes the oxygen content to decrease along the thickness direction from the bottom. Linearly increasing to the top The corresponding bandgap width is from Increase to This gradient makes the total thickness of the second layer... Its bandgap width distribution is expressed as

[0078] ;

[0079] in The origin of the coordinate system is set at... Interface; This formula shows that at low temperatures, when the electron tunneling initiation point is located At the bottom, the height of the barrier that needs to be crossed is ( The potential barrier is related to silicon's electron affinity. If the tunneling path shifts upwards to the middle, the barrier rises to 4.98 eV, and to 5.06 eV at the top. Therefore, as the temperature decreases, electrons preferentially choose the path with the lower barrier, and the tunneling initiation depth increases. It will move slowly from bottom to top, increasing the effective barrier height. It shows a continuous upward trend, rather than a step change.

[0080] Step 2.3: Completed in step 2.2 Fluorine ion implantation was performed on the surface of the layer, with a dose of [missing information]. The energy is 5.6 keV, incident perpendicularly; fluorine atoms in A Si–F bond is formed in the fluorine, with a bond energy of 5.2 eV, which is much higher than the dissociation energy of the Si–O bond (7.7 eV). However, the strong electronegativity of fluorine (3.98) allows it to capture electrons and form a stable negatively charged center. After injection, the fluoride concentration is at The layer exhibits a Gaussian distribution, with the peak value located at... standard deviation This distribution results in a negative charge surface density. exist A concave negative charge cloud forms in the middle section; since the bandgap gradient was established in step 2.2, the electric field generated by this negative charge cloud will repel electrons, forcing tunneling electrons at low temperatures to avoid the high negative charge region in the middle section and turn towards the top region where the potential barrier is slightly higher but the charge density is lower; thus, The upward movement rate is further modulated, and its temperature derivative... The original design was in the 150–120K range. Reduce to This enables deceleration control during tunnel path migration.

[0081] Step 2.4: On the structure obtained in Step 2.3, deposit a third medium layer, the material of which is Thickness is Electron beam evaporation was used, with a deposition rate of 0.18 nm / s; LaO has an extremely high dielectric constant ( ) and low electron affinity ( ), its conductor bottom Compare The energy level difference is 1.23 eV lower; this energy level difference creates a stepped conduction band shift at the interface of the three dielectric layers, and electrons starting from the silicon channel must traverse the following steps: ;in, There is in the interface The conduction band depression forms a local potential well; the depth of this potential well increases as the temperature decreases, because... Lattice thermal expansion coefficient ( (greater than) ( ), during cooling right This generates compressive stress, causing the conduction band bottom to shift further downwards; consequently, electrons at low temperatures reach... The tunneling initiation level has been captured and redistributed by the potential well, and the tunneling initiation level is at the bottom of the silicon conduction band. Transformation into bound state energy levels in a potential well ,in , , , This transformation improved the effective quality of the tunnel. With barrier width All evolve continuously with temperature, avoiding the problems found in the original model. and Caused by mutation Jump.

[0082] Step 3: Configure a dual-band gate bias sequence to achieve dynamic anchoring of the channel potential profile;

[0083] This step, based on the asymmetric gate dielectric stack constructed in step two, addresses the issue of channel surface state charge at low temperatures. With interface state charge Surface potential induced by release kinetic mismatch Oscillation problem. In the 120–160K range, the fast interface states (time constant) The interface state is frozen, while the slow interface state is frozen. It can still respond to changes in gate voltage, resulting in the following at the same gate voltage: Significant drift with measurement history; traditional DC gate voltage cannot distinguish between the two types of responses, making... The extraction results diverge. This step separates the fast and slow response channels at the physical level by applying a composite bias signal containing a high-frequency carrier and a low-frequency envelope, so that the channel surface potential is locked at a steady-state operating point that is weakly correlated with temperature at low temperatures.

[0084] Step 3.1: On the LaO layer completed in step 2.4, deposit a layer with a thickness of [thickness missing]. The work function of the polycrystalline silicon gate electrode. Subsequently, metal pads are led out at both ends of the gate electrode and connected to a dual-band voltage source; the output signal of this voltage source is ,in , , , , This parameter combination ensures: high-frequency component period Much smaller than the fast interface state response time Therefore, the fast state only perceives its root mean square value. Used to maintain the balance of interface charge perturbations; low-frequency component periodicity. Between and Between these parameters, it can drive the fast state to fully follow, while only producing an integral effect on the slow state; the DC component sets the static operating point.

[0085] Step 3.2: Based on the settings in Step 3.1 Waveform, calculate displacement current density in gate dielectric. ,in The electric field is in the vertical direction, by The voltage is obtained after voltage division by three dielectric layers; the three dielectric layers are connected in series, and the total capacitance is... Capacitors in each layer , For unit area; substituting the parameters, we get ;therefore The equivalent dielectric thickness Therefore, the displacement current contains three terms: , , The amplitude of the high-frequency displacement current reaches Its Joule heat power density ( (only) It does not cause the medium to heat up; however, this current in Intralayer local electromagnetic field is excited, causing the metastable silicon dangling bonds in the slow interface state to... Stimulated transitions occur, and the transition rate increases to ,in , The activation energy is reduced by the high-frequency field; this effect causes the slow-state release time constant to change from shortened to This reduces the time scale gap between it and the fast state.

[0086] Step 3.3: Based on the high-frequency excitation established in Step 3.2, introduce phase modulation of the low-frequency envelope, that is, let ,in , , This modulation causes the instantaneous frequency of the low-frequency voltage to be at... Slow sweeping within the range; due to the surface potential of the channel The response to the gate voltage has inertia, and its time constant is... Channel capacitance With interface charge relaxation resistance Decide, When the sweeping frequency is close to hour, Resonance amplification occurs; by adjusting and This causes the center of the resonance peak to fall on ,correspond ;at this time, Forced to be locked into a temperature-independent periodic steady state, its average value... ,in Much smaller than the unmodulated state The quadratic form indicates that the linear temperature drift has been suppressed, and the residual term is a predictable curvature term.

[0087] Step 3.4: Based on the results obtained in Step 3.3 Temperature response characteristics, constructing a gate voltage feedback loop: real-time acquisition of source current It is converted into voltage by a transimpedance amplifier. ,in ;Will The signal is fed into a lock-in amplifier to extract its value. In-phase component at the location Orthogonal components Define the error signal ,in As a calibration reference; Output via proportional-integral controller ,in , ;Should Superimposed on step 3.1 Above, a closed-loop adjustable DC bias is formed. ;because Proportional to the surface charge density of the channel inversion layer ,and ( (For Fermi potential), therefore the closed loop is essentially to... Anchored to make A constant value; when the temperature changes, Automatic compensation The residual curvature term makes Fluctuations within the 120–180 K range are less than ±0.8%, thus stabilizing the first derivative of the threshold voltage with respect to temperature. This eliminates the divergence of derivatives in the transition intervals.

[0088] Step 4: Implant a strain-matching buffer layer to suppress band distortion induced by lattice mismatch stress at low temperatures;

[0089] This step, based on the dynamic potential anchoring state achieved in step three, addresses the last type of low-temperature disturbance source—the abrupt change in interfacial stress caused by the difference in the thermal expansion coefficients of the silicon substrate, epitaxial channel, and gate dielectric multilayer materials. When the temperature drops from 300K to 120K, the Si substrate shrinkage is approximately 0.124%, while... The shrinkage rate is only 0.038%. It is 0.041%. The difference is 0.053%; this difference is reflected in the cumulative stress at the Si / SiO interface. This leads to the splitting of the valence band peak, creating an energy difference between the light and heavy holes. The effective hole mass is changed by compressing the hole from 44 meV at room temperature to 29 meV at 120 K. and This leads to an additional shift in the threshold voltage that is directly related to the band structure. This step involves inserting a strain gradient buffer layer between the silicon channel and the first dielectric layer to allow thermal stress to be released gradually along the thickness direction, thus avoiding stress concentration at the interface.

[0090] Step 4.1: On the surface of the silicon nitride cap layer completed in Step 1.4, a layer with a thickness of [thickness missing] is grown using molecular beam epitaxy. of Buffer layer, in which germanium component Along the thickness direction from the bottom Linearly increasing to the top The growth temperature is The beam current ratio Si:Ge = 1:0.21; the gradient composition design is based on the thermal expansion coefficient of Si. Ge is alloy Therefore, the bottom of the buffer layer ,top This value is between Si (2.6) and Between (0.8), a continuous transition in the coefficient of thermal expansion is formed, which reduces stress during the cooling process. satisfy:

[0091] ;

[0092] in The Young's modulus of the buffer layer also follows The stress increases from 130 GPa to 152 GPa. The equation shows that the stress gradient is driven by the thermal strain gradient, which in turn is protected by the composition gradient, thus avoiding abrupt changes in stress at a certain interface.

[0093] Step 4.2: The surface of the SiGe buffer layer obtained in Step 4.1 is pre-irradiated with helium ions at a dose of [missing value]. The energy is 120 keV; helium ions form nanoscale void clusters in SiGe, with an average diameter of areal density These voids, acting as stress relaxation centers, preferentially absorb lattice contraction differences during cooling, causing microplastic deformation within the buffer layer; their strain relaxation... ,in Cooling time, For relaxation time, The viscosity coefficient, This is the shear modulus; calculations show that after holding at 120K for 1 hour, That is, 73% of the thermal strain is absorbed by the void clusters, and the remaining stress is reduced to It was only 27.6% of the unirradiated structure.

[0094] Step 4.3: On the irradiation buffer layer completed in Step 4.2, deposit a layer with a thickness of [thickness missing]. The silicon nitride intercalation layer was constructed using plasma-enhanced chemical vapor deposition at a radio frequency power of 160W and a temperature of 280℃; the nitrogen content of this intercalation layer was controlled to be... The corresponding Si–N bond ratio is 68%, and the Si–Si bond ratio is 32%. The shortening of bond length introduced by nitrogen atoms (Si–N bond length is 1.74, Si–Si is 2.35) causes compressive stress in the intercalation. The compressive stress is related to the remaining tensile stress from step 4.2. Superposition reduces the net stress at the SiGe / intercalation interface to Although the numerical value increases, the sign changes from tensile to compressive, altering the sign of valence band stress splitting: tensile stress causes the light hole energy valley to shift downwards, while compressive stress causes it to shift upwards; thus... It recovered to 38.2 meV at 120K, deviating from the room temperature value by only 13%, which is a 31.7% improvement compared to 29 meV without intercalation.

[0095] Step 4.4: On the surface of the silicon nitride intercalation layer obtained in Step 4.3, perform boron surface redistribution annealing at a temperature of 760℃ for 120s, under the following atmosphere: This annealing process causes boron atoms to segregate from the channel bulk region to the intercalation / SiGe interface, forming a boron-enriched layer with a boron surface concentration reaching [value missing]. Boron atoms occupy interstitial sites in SiN, generating acceptor-type stress dipoles, whose stress moment tensor components... The dipole induces a non-uniform stress field within the intercalation layer. ( (for Poisson's ratio), in Additional compressive stress is generated at the location This stress, combined with the net stress from step 4.3, causes the stress distribution within the intercalation layer to change from uniform to gradient: surface compressive stress. Interface ,gradient The gradient stress field applies spatially varying strain to the valence band apex, causing the energy difference between the light and heavy hole valleys. The standard deviation of the width along the thickness direction This is much greater than the 1.2 meV under a single field; therefore, within the entire inversion layer thickness (≈4.5 nm) involved in threshold voltage extraction, It is no longer a single value, but a statistical distribution with its mean. The standard deviation suppresses the deterministic perturbation of the threshold voltage by band distortion, making No more jump features caused by band abrupt changes appear in the 120–180K range.

[0096] Step 5: Arrange charge compensation bands on the channel sidewalls to balance the threshold shift caused by the lateral widening of the depletion region at low temperatures;

[0097] This step, based on the strain-matching buffer structure completed in step four, addresses the lateral expansion of the depletion region after carrier freezing, which occurs at the channel sidewall (i.e., the junction between the source / drain extension region and the channel)—a third type of disturbance source in the low-temperature range. When the temperature drops below 160K, the hole concentration in the channel body region drops sharply, the gate control capability weakens, and the electric field lines bend more towards the sidewall, causing the source / drain junction depletion region to expand laterally (…). (Direction) Distance of intrusion into the trench The increase from 3.2nm at room temperature to 9.7nm at 130K resulted in an increase in the effective channel width. A 21% contraction is equivalent to a positive threshold voltage drift of +33mV; this effect is particularly significant in narrow-channel devices and cannot be suppressed by the aforementioned longitudinal modulation. This step provides a fixed surface charge with opposite sign and density to the sidewall depletion charge by precisely implanting charge compensation bands on both sides of the channel, thus counteracting its disturbance to the electric field distribution. It remains constant across the entire temperature range.

[0098] Step 5.1: On the silicon nitride intercalation surface completed in step 4.4, the channel region is defined by photolithography, and on both sides of the channel ( (Direction) Leave a width of The blank area was then filled; subsequently, phosphorus ion implantation was performed at a dose of [missing information]. The energy was 2.1 keV, and the injection angle was 0° (vertical); this injection allowed phosphorus atoms to enter the upper part of the silicon-germanium buffer layer. The interval forms the initial donor distribution within the blank area of ​​the sidewall. Its peak value is located at At this location, the surface density is Due to low injected energy, exist The orientation is rectangular with steep edges, and half the width is... This geometric feature serves as the spatial reference for subsequent charge matching.

[0099] Step 5.2: The structure obtained in Step 5.1 is subjected to medium-temperature annealing at 680℃ for 90s in an argon atmosphere; during annealing, phosphorus atoms undergo lateral diffusion, and their diffusion coefficient... At 680℃ The diffusion equation shows that phosphorus in... The standard deviation of the direction is expanded to Therefore, the sidewall donor surface charge distribution changes from rectangular to a Gaussian modified form:

[0100] ;

[0101] in This is the error function; this equation shows that the charge is no longer concentrated in... Within the hard boundary, and along Directional smooth decay, maximum value still located (Channel centerline), but the edge slope changes from infinity to a finite value. The finite slope ensures continuous electric field perturbation and avoids the singularity effect of hard boundaries.

[0102] Step 5.3: On the structure obtained in Step 5.2, deposit a layer with a thickness of [thickness missing]. The silica sidewall dielectric is grown using the in-situ vapor generation (ISSG) method at a growth temperature of 850°C. This dielectric covers the channel sidewalls and the top exposed area, but not the source / drain areas. The dielectric constant of silica is... A fixed positive charge exists at the interface between it and the silicon-germanium buffer layer. This positive charge originates from oxygen vacancies during the oxidation process; this positive charge interacts with the negative charge provided by the phosphorus donor in step 5.2. A mirror charge pair is formed in the sidewall region; the distance between the two is... Therefore, the potential disturbance generated at the center of the channel is ;

[0103] This formula is based on a two-dimensional mirror charge model, and in the denominator... Ensure the integral converges; substitute The expression and numerical integration yield: at the center of the channel Place, Its absolute value exactly offsets the surface potential rise caused by the depletion region of the sidewalls. (Obtained by solving the Poisson equation at 130K), achieving first-order potential balance.

[0104] Step 5.4: Perform a second fluoride ion implantation on the silica sidewall surface completed in Step 5.3, with a dosage of [dosage missing]. The energy was 3.8 keV, and the injection direction was at a 12° angle to the channel normal, towards the channel center; fluorine atoms were formed in silicon dioxide. The center, its surface density of negative charge Due to tilted injection The orientation exhibits an asymmetrical distribution: the peak value is located in... (That is, slightly biased towards the inside of the channel); this bias brings the center of gravity of the negative charge closer to the channel, enhancing the shielding efficiency against the sidewall electric field; the corrected total surface charge density is calculated to be , its in integral value within the interval This corresponds to a net negative line charge; this line charge induces a radial electric field within the channel. ,in , The distance to the center of the ditch. The effective dielectric constant of silicon; this electric field is in the opposite direction to the electric field in the sidewall depletion region, in (i.e., original) The position completely cancels out, making Fluctuations within the 120–180K range are less than ±0.35nm, eliminating threshold jumps caused by lateral broadening.

[0105] Step 6: Embed temperature-adaptive floating gate units to compensate for the thermal relaxation hysteresis effect of interface state charge;

[0106] This step, based on the sidewall charge balance state established in step five, addresses the last type of dynamic perturbation at low temperatures—interface state charge. During the cooling process, due to thermal relaxation time The problem of significantly lagging behind the thermal equilibrium value with increasing temperature exponentially. At 150 K, deep-level interface states... The period is much longer than the typical measurement period (<100ms), resulting in The actual value is lower than the thermal equilibrium value. Reaching 38%, causing the threshold voltage to be generated. The spurious positive offset; this offset varies with the cooling rate and is not reproducible. This step involves embedding an electrically isolated, thermally coupled floating gate cell in the gate dielectric, causing its charge... Evolving according to the same thermodynamic laws, and then through capacitive coupling... The hysteresis characteristic is mapped to real-time compensation for the main gate voltage, realizing the physical mirror cancellation of the interface state relaxation hysteresis effect.

[0107] Step 6.1: Inside the LaO layer completed in step 2.4, a region with a size of [missing information] is defined by electron beam lithography and reactive ion etching. A rectangular window with a depth of Located directly below the center of the gate; subsequently, a layer with a thickness of [thickness missing] is deposited within this window. The work function of the nickel-chromium alloy thin film Fermi level position (Relative to the top of the silicon valence band); this thin film serves as a floating gate electrode, its area... , with the upper level and lower levels Constitutes dual dielectric isolation, total equivalent oxide thickness Therefore, its capacitance to ground This tiny capacitance value ensures the floating gate charge. The effect on the main gate capacitance is negligible, but it is highly sensitive to temperature changes.

[0108] Step 6.2: Vacuum anneal the floating gate structure obtained in Step 6.1 at 320℃ for 150s; annealing causes nickel-chromium atoms to diffuse slightly into the structure. Forming a depth of approximately A doped transition layer is formed, in which acceptor-type defect states are introduced, and the energy level is located at... ( (LaO conduction band bottom); this defect state serves as the charge trapping center of the floating gate, and its occupancy probability follows: ;

[0109] in , (because Therefore Substituting, we get That is, only 0.17% of the defect states are occupied by electrons, corresponding to the net charge of the floating gate. ,in For defect density; this relationship indicates that: It has the same bandgap parameter as the interface state occupancy probability, and therefore its evolution trend is consistent.

[0110] Step 6.3: Deposit a layer with a thickness of [thickness missing] above the floating gate completed in Step 6.2. An alumina coating is applied, and then metal leads are fabricated on top of it to connect to a charge sensing circuit. This circuit includes a high-gain transimpedance amplifier with a floating gate at its input and a voltage output. ,in This is the gain coefficient; because The interface state charge hysteresis Also satisfied ,and and Sharing the same activation energy Therefore, their time evolution functions have the same form; thus... Characterizable The transient amplitude; actual measurements showed that within 100ms after cooling to 130K, Rise to ,and Threshold offset caused They exhibit a linear proportional relationship, with a proportionality constant of 1. .

[0111] Step 6.4: Take the result obtained in Step 6.3 The gate voltage feedback loop constructed in signal access step 3.4 is superimposed as a feedforward compensation term onto the signal. Above, the final DC bias is formed: ;

[0112] in To calibrate the scaling factor, from step 6.3... The ratio of the measured value to the threshold offset is obtained; this formula shows that: the floating gate output It directly reflects the interface state relaxation hysteresis, and after proportional scaling, it cancels out its influence on the threshold voltage in real time; when the temperature stabilizes at 130K, Decays over time, Synchronous decay, making Automatic recovery drives the channel potential back to its thermal equilibrium point; thus... During the cooling process, the transient offset is suppressed to within ±0.9mV, and the steady-state value is restored to the theoretical design value, completely eliminating the jump caused by relaxation hysteresis.

[0113] Step 7: Deploy a multi-node thermal-electrical collaborative calibration network to achieve path-independent convergence of threshold voltage across the entire temperature range;

[0114] This step, based on the floating gate dynamic compensation state completed in step six, addresses a system-level problem: while all the aforementioned local controls are effective individually, the thermal history dependence of each subsystem may lead to different cooling / heating paths. Path hysteresis occurs, meaning that at the same temperature point, the measured temperature decreases... The temperature measured The phase difference reaches ±4.2mV. This hysteresis stems from the irreversible accumulation of processes such as stress relaxation of the silicon-germanium buffer layer, interface state charging and discharging, and release of floating gate defect states. This step addresses this by deploying four thermo-electric calibration nodes at the chip edge. Each node contains a micro-heater, a platinum resistance thermometer, and a MOSFET sensing unit, forming a closed-loop calibration network. This physically erases path memory and forces... After any thermal cycle, it converges to a unique function curve.

[0115] Step 7.1: Four calibration nodes are fabricated around the active region of the chip, located at each of the four corners. Each node contains: a calibration node with a size of... Nickel-chromium thin film heater, sheet resistance A width of Platinum bar thermometer, length ,in ; and an n-type MOSFET sensing unit manufactured using the same process as the main device, with a channel width-to-length ratio The four nodes are evenly distributed on the chip plane, and their geometric centers are located at distances from the center of the main device, respectively. This layout ensures the time constant for thermal disturbances to propagate to the main components. All are between 1.8 and 2.1 s, forming the basis for synchronous thermal excitation.

[0116] Step 7.2: Perform two-point calibration on the four platinum resistance thermometers from Step 7.1: measure their resistance at 273.15K (freezing point) and 373.15K (boiling point) respectively, and obtain the actual resistance. and The calibration parameters are then written to the on-chip read-only memory; at any temperature Below, the node temperature is from The inversion yielded an accuracy of ±0.018K, which is superior to the sensitivity of the main device threshold voltage to temperature (0.42mV / K corresponds to 0.024K resolution), ensuring that there is no cumulative error in the temperature reference.

[0117] Step 7.3: After calibration in step 7.2, apply pulsed current to the heaters of the four calibration nodes. The duration is This causes the node temperature to rise instantaneously. This slight temperature increase does not change the operating point of the main device, but is sufficient to excite short-time responses in the interface state and floating gate defect state; the threshold voltage change of the sensing MOSFET. The data is collected in real time, and its average value is... This value reflects the residual hysteresis of each subsystem under the current thermal history and serves as the input for calibration instructions.

[0118] Step 7.4: Take the result obtained in Step 7.3 Send to the calibration logic unit and execute the instruction: If Then the global thermal equalization program is initiated—applying an amplitude of [value missing] to all four heaters simultaneously. A constant current, in which Duration This current causes the overall chip temperature to rise slowly. and in At the end, it is allowed to cool naturally; this perturbation process causes all temperature-sensitive elements (channels, dielectrics, interfaces, floating gates) to cross the same thermal activation barrier, resetting their internal states; this process is repeated until... At this time, the main device It converges to the standard curve under any thermal path, and path hysteresis is eliminated.

[0119] Step 8: Integrate a wide-temperature-range closed-loop packaging system to ensure long-term stability of threshold voltage and environmental robustness;

[0120] This step addresses the final engineering constraint—the device must withstand multiple stresses in real-world application environments, including humidity, air pressure, mechanical vibration, and long-term aging. These stresses will slowly alter the physical parameters of all the aforementioned precision-controlled structures, leading to… Drift occurs on a thousand-hour scale. This step involves designing a hermetically sealed package cavity with triple thermal-mechanical-humidity feedback to place the chip in a controlled microenvironment. This ensures that the physical conditions of all control elements (such as interface state density, stress distribution, and charge mobility) are maintained within the design window, achieving [the desired effect]. Decade-scale stability within the temperature range of 120–400 K.

[0121] Step 8.1: Fabricate the packaging substrate using alumina ceramic as the material, with a thermal expansion coefficient of [missing information]. A cavity with dimensions of 1.8 mm × 1.8 mm and a depth of 0.42 mm is created in the center of the substrate; a layer with a thickness of [missing information] is sputtered onto the inner wall of the cavity. A copper film is used as both an electromagnetic shielding layer and a heat conduction layer; a layer of copper film is electroplated on its surface. A thick gold layer prevents oxidation; this substrate provides mechanical support and heat sink functionality. The thermal expansion mismatch between it and the chip's silicon substrate is absorbed by the SiGe buffer layer in step four, thus ensuring that the cavity-chip interface stress remains consistently below [value missing] within the range of -60°C to +125°C. .

[0122] Step 8.2: Install a miniature humidity sensor and a piezoelectric pressure sensor inside the cavity from Step 8.1; the humidity sensor is capacitive, with an alumina sensing membrane, and the capacitance change... ,in The pressure sensor is a quartz crystal type with a resonant frequency of [missing information]. The outputs of the two sensors are connected to an external conditioning circuit to monitor the relative humidity inside the cavity in real time. With absolute pressure ;when or At that time, the purification process is triggered.

[0123] Step 8.3: Fill the cavity from Step 8.2 with a mixture of dry nitrogen and hydrogen gas, with a volume ratio of [missing information]. The total pressure is maintained at The hydrogen component is used to passivate newly formed interface states, and its surface reaction rate constant... At 120K, This is sufficient to reduce the density of newly generated interface states to [a certain value] within 10 seconds. Below the design threshold .

[0124] Step 8.4: Flip-chip solder the calibrated chip from Step 7.4 to the bottom of the substrate cavity from Step 8.1. The solder is gold-tin eutectic (AuSn), with a melting point of 280℃ and a thermal conductivity of [missing information]. After welding, the cavity is sealed with glass solder (softening point 420℃) to form an airtight cavity; during the sealing process, the gas in the cavity is configured with the composition and pressure as set in step 8.3; after encapsulation, an integral structure is formed; under the protection of the encapsulation system, wide temperature range, long life, and path-independent threshold voltage stabilization are achieved.

[0125] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.

Claims

1. A method for stabilizing the threshold voltage of a wide-temperature-range MOSFET, characterized in that, include: A channel structure with longitudinal and lateral boron concentration gradients is constructed on the surface of a silicon substrate. An asymmetric gate dielectric stack composed of alumina, silicon dioxide with varying oxygen content, and lanthanum oxide is formed on the surface of the channel structure. Dual-band gate bias signals of 15kHz low frequency and 120MHz high frequency are applied to the asymmetric gate dielectric stack. A silicon-germanium buffer layer with varying germanium composition is implanted at the interface between the channel and the gate dielectric. Phosphorus ions are injected on both sides of the silicon-germanium buffer layer to form a charge compensation region on the channel sidewall. Nickel-chromium alloy floating gate units are embedded inside the gate dielectric. The floating gate units are connected to the gate feedback circuit. Calibration nodes are set at the four corners of the chip. Each calibration node integrates a heater, a temperature sensor, and a MOSFET sensing unit. The calibration nodes and MOSFET structure are encapsulated in a sealed cavity containing a nitrogen and hydrogen mixture.

2. The method for stabilizing the threshold voltage of a wide-temperature-range MOSFET according to claim 1, characterized in that, The construction of the channel structure with longitudinal and transverse boron concentration gradient distribution includes: growing a single-crystal silicon epitaxial layer on the surface of a silicon substrate; performing a first round of boron ion implantation on the epitaxial layer to form an initial acceptor distribution; performing a second round of tilted boron ion implantation based on the initial acceptor distribution to cause boron atoms to shift along the channel length direction; performing rapid thermal annealing on the implanted structure to form a linear concentration gradient of boron atoms; depositing a silicon nitride cap layer on the surface of the annealed structure; and performing nitrogen-containing plasma treatment.

3. The method for stabilizing the threshold voltage of a wide-temperature-range MOSFET according to claim 2, characterized in that, The rapid thermal annealing increases the concentration at the source end and decreases the concentration at the drain end, forming a linear concentration gradient along the channel length. This gradient causes the channel carrier density to change gradually at low temperatures.

4. The method for stabilizing the threshold voltage of a wide-temperature-range MOSFET according to claim 1, characterized in that, The formation of the asymmetric gate dielectric stack consisting of alumina, silicon dioxide with gradually varying oxygen content, and lanthanum oxide includes: depositing an alumina layer on the surface of a silicon nitride cap layer, and subjecting the alumina layer to in-situ oxygen plasma treatment; growing a silicon dioxide layer with gradually varying oxygen content on the treated alumina layer, and implanting fluorine ions into the surface of the silicon dioxide layer to form a negative charge distribution; and depositing a lanthanum oxide layer on the fluorine ion implanted structure to form a stepped conduction band offset structure.

5. The method for stabilizing the threshold voltage of a wide-temperature-range MOSFET according to claim 4, characterized in that, The silicon dioxide layer with gradually varying oxygen content has a linearly increasing bandgap, which makes the electron tunneling path change gradually with temperature at low temperatures, avoiding sudden changes in threshold voltage.

6. The method for stabilizing the threshold voltage of a wide-temperature-range MOSFET according to claim 1, characterized in that, The application of a dual-band gate bias signal of 15kHz low frequency and 120MHz high frequency to the asymmetric gate dielectric stack includes: forming a polysilicon gate electrode on the lanthanum oxide layer and connecting the polysilicon gate electrode to the dual-band voltage source; using the high frequency component to excite a local electromagnetic field in the silicon dioxide layer to shorten the interface state release time; introducing phase modulation of the low frequency envelope to force the channel surface potential to be locked in a periodic steady state; and then constructing a gate voltage feedback loop to maintain the first derivative of the threshold voltage with respect to temperature at a preset value.

7. The method for stabilizing the threshold voltage of a wide-temperature-range MOSFET according to claim 6, characterized in that, The phase modulation causes the center of the resonance peak of the channel surface potential to fall at a preset frequency, corresponding to a time constant, so that the average temperature coefficient of the surface potential is significantly lower than that of the unmodulated state.

8. The method for stabilizing the threshold voltage of a wide-temperature-range MOSFET according to claim 1, characterized in that, The method of implanting a silicon-germanium buffer layer with a gradually changing germanium composition at the interface between the channel and the gate dielectric includes: epitaxially growing a silicon-germanium buffer layer on the surface of a silicon nitride cap layer, wherein the germanium composition in the silicon-germanium buffer layer increases linearly from bottom to top; pre-irradiating the surface of the silicon-germanium buffer layer with helium ions to form nanoscale void clusters; depositing a silicon nitride intercalation layer on the irradiated silicon-germanium buffer layer; and performing boron surface redistribution annealing on the surface of the silicon nitride intercalation layer to form a boron-enriched layer.

9. The method for stabilizing the threshold voltage of a wide-temperature-range MOSFET according to claim 8, characterized in that, The nanoscale void clusters formed by helium ion pre-irradiation serve as stress relaxation centers, absorbing lattice contraction differences and reducing residual stress at low temperatures.

10. A wide-temperature-range MOSFET threshold voltage stabilization system for implementing the method as described in any one of claims 1-9, characterized in that, include: A dual-gradient doped channel structure unit is formed on the surface of a silicon substrate and has a longitudinal and lateral boron concentration gradient distribution. An asymmetric gate dielectric stack unit is disposed on the surface of a dual-gradient doped channel structure unit, and is composed of an aluminum oxide layer, a silicon dioxide layer with gradually varying oxygen content, and a lanthanum oxide layer stacked sequentially. A dual-band gate bias sequence unit is connected to the asymmetric gate dielectric stack unit to generate a 15kHz low-frequency component and a 120MHz high-frequency component. A silicon-germanium strain-matching buffer layer unit is located at the interface between the channel structure and the asymmetric gate dielectric stack unit, and the germanium composition in the silicon-germanium strain-matching buffer layer unit gradually varies along the thickness direction. A channel sidewall charge compensation band unit is disposed on both sides of the silicon-germanium buffer layer and is formed by phosphorus ion implantation. Temperature-adaptive floating gate cell, embedded inside an asymmetric gate dielectric stack, is made of nickel-chromium alloy thin film and connected to the gate feedback circuit; The multi-node thermo-electric co-calibration network unit includes calibration nodes arranged at the four corners of the chip, each calibration node containing a heater, a temperature sensor, and a MOSFET sensing unit; the wide-temperature-range closed-loop packaging system unit includes a substrate, an electromagnetic shielding layer, a humidity sensor, a pressure sensor, and a sealed cavity filled with a mixture of nitrogen and hydrogen.

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