Method and apparatus for high performance page error handling for multi-tenant scalable accelerators

Abstract

The invention discloses a method and apparatus for high performance page error handling for a multi-tenant scalable accelerator. An apparatus and method for high performance page error handling. For example, one embodiment of an apparatus includes one or more accelerator engines to process work descriptors submitted by a client to a plurality of work queues; error handling hardware logic associated with the one or more accelerator engines, the error handling hardware logic to implement a specified page error handling mode for each of the plurality of work queues, the page error handling modes including a first page error handling mode and a second page error handling mode.

Description

[0001] This application is a divisional application of the invention patent application filed on June 24, 2022, with application number 202210729401.5, entitled "Method and apparatus for high-performance page fault handling for multi-tenant scalable accelerators". Technical Field

[0002] This invention generally relates to the field of computer processors. More specifically, this invention relates to methods and apparatus for high-performance page fault handling for multi-tenant scalable accelerators. Background Technology

[0003] The instruction set, or instruction set architecture (ISA), is the programming-related part of a computer architecture, including primitive data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" in this article generally refers to macro-instructions—that is, instructions provided to the processor for execution—rather than micro-instructions or micro-operations—that is, the result of the processor's decoder decoding macro-instructions. Micro-instructions or micro-operations can be configured for execution units on the instruction processor to perform operations to implement the logic associated with macro-instructions.

[0004] An ISA differs from a microarchitecture, which is a collection of processor design techniques used to implement an instruction set. Processors with different microarchitectures can share a common instruction set. For example, the Intel® Pentium 4 processor, the Intel® Core™ processor, and processors from Advanced Micro Devices, Inc. in Sunnyvale, California implement nearly the same version of the x86 instruction set (with some extensions added with later versions), but have different internal designs. For instance, the same register architecture of an ISA can be implemented differently in different microarchitectures using known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using register renaming mechanisms (e.g., using register alias tables (RATs), reorder buffers (ROBs), and retired register files). Unless otherwise specified, the phrases “register architecture,” “register file,” and “register” are used herein to refer to the register architecture, register file, and register as visible to the software / programmer and to the way registers are specified in instructions. Where differentiation is required, the adjectives “logical,” “architectural,” or “software-visible” will be used to indicate registers / register files in a register architecture, while different adjectives will be used to specify registers in a given microarchitecture (e.g., physical registers, reorder buffers, retired registers, register pools). Attached Figure Description

[0005] A better understanding of the present invention can be obtained from the following detailed embodiments, in conjunction with the accompanying drawings, wherein: Figure 1 The diagram illustrates a computer system architecture; Figure 2 The diagram shows a processor with multiple cores; Figure 3A The diagram illustrates multiple stages of a processing pipeline; Figure 3B Details of one embodiment of the illustrated core; Figure 4 The diagram illustrates an execution circuit according to one embodiment; Figure 5 The diagram illustrates an embodiment of a register architecture; Figure 6 An example of a graphical instruction format; Figure 7 The diagram illustrates an addressing technique according to one embodiment; Figure 8 An example of an instruction prefix is ​​illustrated; Figure 9A - Figure 9D The illustration shows an example of how to use the prefixed R, X, and B fields; Figure 10A - Figure 10B An example of a second instruction prefix is ​​shown in the diagram; Figure 11 The illustration shows the payload byte of one embodiment of the instruction prefix; Figure 12 The diagram illustrates the implementation of instruction conversion and binary transformation; Figure 13 The illustration shows a scalable device according to an embodiment of the present invention; Figure 14 The diagram illustrates an example of a method for handling page errors; Figure 15 The illustration shows another example of a method for handling page errors according to an embodiment of the present invention; Figure 16 The diagram illustrates an accelerator with a work receiving unit, a work dispatcher, and a work execution unit. Figure 17 The diagram illustrates the transactions between the accelerator and the host root complex. Figure 18 The illustration shows an accelerator with error handling logic according to an embodiment of the present invention; Figure 19A The figure illustrates a descriptor according to an embodiment of the present invention; Figure 19B The figure illustrates a batch descriptor according to an embodiment of the present invention; Figure 20 The image shows the completion record generated by the accelerator; Figure 21 The illustration shows an event log entry generated by an accelerator according to an embodiment of the present invention; Figure 22 The diagram shows an accelerator with multiple control registers; Figure 23 An example of a batch completion record is shown in the diagram; Figure 24 The illustration shows the discharge descriptor and discharge completion record; Figure 25 The diagram illustrates an accelerator with multiple engines and work queues, at least some of which utilize a page request service; and Figure 26 The illustration shows a method according to an embodiment of the present invention. Detailed Implementation

[0006] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the embodiments of the invention described below. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are illustrated in block diagram form to avoid obscuring the fundamental principles of embodiments of the invention.

[0007] Exemplary computer architecture

[0008] The following is a detailed description of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are generally suitable.

[0009] Figure 1 The illustration illustrates an embodiment of an example system. The multiprocessor system 100 is a point-to-point interconnect system and includes multiple processors, including a first processor 170 and a second processor 180 coupled via point-to-point interconnect 150. In some embodiments, the first processor 170 and the second processor 180 are homogeneous. In some embodiments, the first processor 170 and the second processor 180 are heterogeneous.

[0010] Processors 170 and 180 are shown as including integrated memory controller (IMC) unit circuitry 172 and 182, respectively. Processor 170 also includes point-to-point (PP) interfaces 176 and 178 as part of its interconnect controller unit; similarly, the second processor 180 includes PP interfaces 186 and 188. Processors 170 and 180 can exchange information via PP interconnect 150 using point-to-point (PP) interface circuitry 178 and 188. IMCs 172 and 182 couple processors 170 and 180 to corresponding memories, namely memories 132 and 134, which may be portions of the main memory locally attached to the respective processor.

[0011] Processors 170 and 180 can each exchange information with chipset 190 via respective PP interconnects 152 and 154 using point-to-point interface circuits 176, 194, 186, and 198. Chipset 190 can optionally exchange information with coprocessor 138 via high-performance interface 192. In some embodiments, coprocessor 138 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0012] A shared cache (not shown) may be included in either processor 170, 180, or external to either processor but connected to them via a PP interconnect, such that if the processors are placed in a low-power mode, the local cache information of either or both processors may be stored in the shared cache.

[0013] Chipset 190 may be coupled to a first interconnect 116 via interface 196. In some embodiments, the first interconnect 116 may be a peripheral component interconnect (PCI) interconnect or an interconnect such as a PCI quick interconnect or another I / O interconnect. In some embodiments, one of these interconnects is coupled to a power control unit (PCU) 117, which may include circuitry, software, and / or firmware for performing power management operations in relation to processors 170, 180, and / or coprocessor 138. PCU 117 provides control information to a voltage regulator to cause the voltage regulator to generate an appropriate regulated voltage. PCU 117 also provides control information to control the generated operating voltage. In various embodiments, PCU 117 may include various power management logic units (circuitry) for performing hardware-based power management. Such power management may be entirely processor-controlled (e.g., controlled by various processor hardware, and may be triggered by workload and / or power, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (such as a platform or management power source or system software).

[0014] PCU 117 is illustrated as logic separate from processor 170 and / or processor 180. In other cases, PCU 117 may execute on one or more cores (not shown) of processor 170 or 180. In some cases, PCU 117 may be implemented as a (dedicated or general-purpose) microcontroller or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In yet another embodiment, the power management operations performed by PCU 117 may be implemented outside the processor, such as through a separate power management integrated circuit (PMIC) or another component outside the processor. In yet another embodiment, the power management operations performed by PCU 117 may be implemented within the BIOS or other system software.

[0015] Various I / O devices 114 may be coupled to a first interconnect 116 via an interconnect (bus) bridge 118, which in turn couples the first interconnect 116 to a second interconnect 120. In some embodiments, one or more additional processors 115, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array (FPGA), or any other processor, are coupled to the first interconnect 116. In some embodiments, the second interconnect 120 may be a low pin count (LPC) interconnect. Various devices may be coupled to the second interconnect 120, including, for example, a keyboard and / or mouse 122, a communication device 127, and a memory cell circuit 128. In some embodiments, the memory cell circuit 128 may be a disk drive or other mass storage device that may include instruction / code and data 130. Additionally, audio I / O 124 may be coupled to the second interconnect 120. Note that other architectures different from the point-to-point architecture described above are possible. For example, instead of a point-to-point architecture, a system such as a multiprocessor system 100 may implement a multi-branch interconnect or other such architecture.

[0016] Exemplary core architectures, processors, and computer architectures

[0017] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, such core implementations can include: 1) general-purpose ordered cores designed for general-purpose computing; 2) high-performance general-purpose out-of-order cores designed for general-purpose computing; and 3) dedicated cores designed primarily for graphics and / or scientific (throughput) computing. Different processor implementations can include: 1) CPUs, which include one or more general-purpose ordered cores and / or one or more general-purpose out-of-order cores designed for general-purpose computing; and 2) coprocessors, which include one or more dedicated cores designed primarily for graphics and / or scientific (throughput) computing. These different processors result in different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic or a dedicated core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system-on-a-chip that may include the described CPU (sometimes referred to as application cores or application processors), the coprocessors described above, and additional functionality on the same die. Exemplary core architectures are then described, followed by exemplary processors and computer architectures.

[0018] Figure 2 The diagram illustrates a block diagram of an embodiment of a processor 200 that may have more than one core, may have an integrated memory controller, and may have an integrated graphics device. Solid-lined boxes illustrate a processor 200 having a single core 202A, a system agent 210, and a set 216 of one or more interconnect controller unit circuits, while dashed-lined boxes optionally illustrate an alternative processor 200 having multiple cores 202(A)-(N), a set 214 of one or more integrated memory controller unit circuits in the system agent unit circuits 210, dedicated logic 208, and a set 216 of one or more interconnect controller unit circuits. Note that the processor 200 may be... Figure 1 One of the processors 170 or 180, or the coprocessor 138 or 115.

[0019] Therefore, different implementations of processor 200 may include: 1) a CPU, wherein dedicated logic 208 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 202(A)-(N) are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, wherein cores 202(A)-(N) are a large number of dedicated cores designed primarily for graphics and / or scientific (throughput); and 3) a coprocessor, wherein cores 202(A)-(N) are a large number of general-purpose ordered cores. Thus, processor 200 may be a general-purpose processor, coprocessor, or dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit circuit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 200 may be part of one or more substrates, and / or may be implemented on one or more substrates using any of a variety of process technologies (such as, for example, BiCMOS, CMOS, or NMOS).

[0020] The memory hierarchy includes one or more levels of cache cell circuitry 204(A)-(N) within cores 202(A)-(N), a set 206 of one or more shared cache cell circuitry, and external memory (not shown) coupled to a set 214 of integrated memory controller cell circuitry. The set 206 of one or more shared cache cell circuitry may include one or more intermediate-level caches (such as Level 2 (L2), Level 3 (L3), Level 4 (L4)) or other-level caches (such as the final level cache (LLC)) and / or combinations thereof. Although in some embodiments, ring-based interconnect network circuitry 212 interconnects dedicated logic 208 (e.g., integrated graphics logic), the set 206 of shared cache cell circuitry, and system proxy cell circuitry 210, alternative embodiments use any number of known techniques to interconnect these cells. In some embodiments, consistency is maintained between the shared cache cell circuitry 206 and one or more of cores 202(A)-(N).

[0021] In some embodiments, one or more of cores 202(A)-(N) are capable of multithreading. System agent unit circuitry 210 includes those components that coordinate and operate cores 202(A)-(N). System agent unit circuitry 210 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, the logic and components required to regulate the power state of cores 202(A)-(N) and / or dedicated logic 208 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0022] Cores 202(A)-(N) can be homogeneous or heterogeneous in terms of their instruction set architecture; that is, two or more cores in cores 202(A)-(N) may be able to execute the same instruction set, while other cores may be able to execute only a subset of that instruction set or a different instruction set.

[0023] Exemplary core architecture

[0024] Ordered and disordered kernel diagrams

[0025] Figure 3(A) is a block diagram illustrating both an exemplary ordered pipeline and an exemplary out-of-order release / execution pipeline with register renaming according to an embodiment of the present invention. Figure 3(B) is a block diagram illustrating both an exemplary embodiment of an ordered architecture core to be included in a processor and an exemplary out-of-order release / execution architecture core with register renaming according to an embodiment of the present invention. Figures 3(A)-3(B) The solid-line boxes in the diagram illustrate ordered pipelines and ordered cores, while the optional dashed-line boxes illustrate register renaming, out-of-order release / execution pipelines and cores. Since the ordered aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0026] In Figure 3(A), the processor pipeline 300 includes a fetch stage 302, an optional length-decode stage 304, a decode stage 306, an optional allocation stage 308, an optional rename stage 310, a scheduling (also known as dispatch or issue) stage 312, an optional register read / memory read stage 314, an execution stage 316, a write-back / memory write stage 318, an optional exception handling stage 322, and an optional commit stage 324. One or more operations can be performed in each of these processor pipeline stages. For example, during fetch stage 302, one or more instructions are fetched from instruction memory; during decode stage 306, one or more fetched instructions can be decoded; an address using the forwarded register port (e.g., a load-to-memory (LSU) address) can be generated; and branch forwarding (e.g., an immediate offset or link register (LR)) can be performed. In one embodiment, decode stage 306 and register read / memory read stage 314 can be combined into a single pipeline stage. In one embodiment, during execution level 316, decoded instructions can be executed, LSU address / data pipelines can be executed to the Advanced Microcontroller Bus (AHB) interface, multiplication and addition operations can be executed, arithmetic operations with branching results can be executed, and so on.

[0027] As an example, the exemplary register renaming out-of-order release / execution core architecture can implement pipeline 300 as follows: 1) Instruction fetch 338 executes fetch stage 302 and length decoding stage 304; 2) Decoding unit circuit 340 executes decoding stage 306; 3) Rename / allocator unit circuit 352 executes allocation stage 308 and rename stage 310; 4) (multiple) scheduler unit circuit 356 executes scheduling stage 312; 5) (multiple) physical register file unit circuit 358 and memory unit circuit 370 execute register read / memory read stage 314; execution cluster 360 executes execution stage 316; 6) memory unit circuit 370 and (multiple) physical register file unit circuit 358 execute write-back / memory write stage 318; 7) each unit (unit circuit) may be involved in exception handling stage 322; and 8) retirement unit circuit 354 and (multiple) physical register file unit circuit 358 execute commit stage 324.

[0028] Figure 3(B) illustrates processor core 390, which includes front-end unit circuitry 330 coupled to execution engine unit circuitry 350, and both are coupled to memory unit circuitry 370. Core 390 can be a Reduced Instruction Set Computing (RISC) core, Complex Instruction Set Computing (CISC) core, Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. Alternatively, core 390 can be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0029] Front-end unit circuitry 330 may include branch prediction unit circuitry 332 coupled to instruction cache unit circuitry 334, which is coupled to instruction translation lookaside buffer (TLB) 336, which is coupled to instruction fetch unit circuitry 338, which is coupled to decode unit circuitry 340. In one embodiment, instruction cache unit circuitry 334 is included in memory unit circuitry 370 instead of front-end unit circuitry 330. Decoding unit circuitry 340 (or decoder) can decode instructions and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as output, which are decoded from, or otherwise reflect, the original instruction or derived from the original instruction. Decoding unit circuitry 340 may further include address generation unit circuitry (AGU, not shown). In one embodiment, AGU generates LSU address using the forwarded register port and can further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). Decoding unit circuitry 340 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROMs), etc. In one embodiment, core 390 includes a microcode ROM (not shown) or other medium (e.g., in the decoding unit circuitry 340, or otherwise within the front-end unit circuitry 330) storing microcode for certain macro instructions. In one embodiment, the decoding unit circuitry 340 includes micro-ops or operation caches (not shown) to retain / cache decoded operations, microtags, or micro-operations generated during decoding stage 306 or other stages of the processor pipeline 300. The decoding unit circuitry 340 may be coupled to rename / allocator unit circuitry 352 within the execution engine unit circuitry 350.

[0030] The execution engine circuitry 350 includes a renaming / allocator unit circuitry 352 coupled to a retirement unit circuitry 354 and a collection 356 of one or more scheduler circuits. The scheduler circuits 356 represent any number of different schedulers, including reservation stations, central instruction windows, etc. In some embodiments, the scheduler circuits 356 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an arithmetic generation unit (AGU) scheduler / scheduling circuit, an AGU queue, etc. The scheduler circuits 356 are coupled to physical register file circuits 358. Each physical register file circuit in the physical register file circuits 358 represents one or more physical register files, wherein different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, compressed integers, compressed floating-point numbers, vector integers, vector floating-point numbers, states (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In one embodiment, the physical register file unit circuitry 358 includes vector register file unit circuitry, write mask register file unit circuitry, and scalar register file unit circuitry. These register units can provide architecture vector registers, vector mask registers, general-purpose registers, etc. The physical register file unit circuitry 358 is overlapped by retirement unit circuitry 354 (also referred to as retirement queues) to illustrate various ways register renaming and out-of-order execution can be implemented (e.g., using reorder buffers (ROBs) and retirement register files; using future files, history buffers, and retirement register files; using register mappings and register pools, etc.). Retirement unit circuitry 354 and the physical register file circuitry 358 are coupled to execution clusters 360. Execution clusters 360 include a set 362 of one or more execution unit circuits and a set 364 of one or more memory access circuits. Execution unit circuit 362 can perform various arithmetic, logical, floating-point, or other types of operations (e.g., shift, addition, subtraction, multiplication) and can be performed on various data types (e.g., scalar floating-point, compressed integer, compressed floating-point, vector integer, vector floating-point). Although some embodiments may include multiple execution units or execution unit circuits dedicated to a particular function or set of functions, other embodiments may include only one execution unit circuit or multiple execution units / execution unit circuits that all perform all functions.The scheduler circuits 356, physical register file unit circuits 358, and execution clusters 360 are shown as potentially multiple because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / compact integer / compact floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines each having their own scheduler circuitry, physical register file unit circuitry, and / or execution clusters—and in the case of separate memory access pipelines, some embodiments are implemented where only the execution cluster of that pipeline has multiple memory access unit circuits 364). It should also be understood that, in the case of separate pipelines, one or more of these pipelines may be out-of-order deployment / execution, and the remaining pipelines may be ordered.

[0031] In some embodiments, the execution engine unit circuit 350 can perform load memory unit (LSU) address / data pipeline to the advanced microcontroller bus (AHB) interface (not shown), as well as address phased and write-back, data phased loading, storage, and branching.

[0032] A set 364 of memory access circuitry is coupled to memory cell circuitry 370, which includes data TLB unit circuitry 372, coupled to data cache circuitry 374, which is coupled to level 2 (L2) cache circuitry 376. In one exemplary embodiment, memory access cell circuitry 364 may include load unit circuitry, memory address unit circuitry, and memory data unit circuitry, each coupled to data TLB circuitry 372 in memory cell circuitry 370. Instruction cache circuitry 334 is also coupled to level 2 (L2) cache unit circuitry 376 in memory cell circuitry 370. In one embodiment, instruction cache 334 and data cache 374 are combined into L2 cache unit circuitry 376, level 3 (L3) cache unit circuitry (not shown), and / or a single instruction and data cache (not shown) in main memory. L2 cache unit circuitry 376 is coupled to one or more other levels of cache and ultimately to main memory.

[0033] Core 390 may support one or more instruction sets (e.g., x86 instruction set (with some extensions added with newer versions); MIPS instruction set; ARM instruction set (with optional additional extensions such as NEON)), including the instructions described herein. In one embodiment, core 390 includes logic for supporting compressed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing the use of compressed data to perform operations used by many multimedia applications.

[0034] Exemplary (multiple) execution unit circuits

[0035] Figure 4 The illustration shows an embodiment of multiple execution unit circuits, such as the multiple execution unit circuits 362 of Figure 3(B). As shown, the multiple execution unit circuits 362 may include one or more ALU circuits 401, vector / SIMD unit circuits 403, load / store unit circuits 405, and / or branch / jump unit circuits 407. ALU circuit 401 performs integer arithmetic and / or Boolean operations. Vector / SIMD unit circuit 403 performs vector / SIMD operations on compressed data (such as SIMD / vector registers). Load / store unit circuit 405 executes load and store instructions to load data from memory into registers or store data from registers into memory. Load / store unit circuit 405 may also generate addresses. Branch / jump unit circuit 407 causes a branch or jump to a memory address depending on the instruction. Floating-point unit (FPU) circuit 409 performs floating-point arithmetic. The width of the multiple execution unit circuits 362 varies depending on the embodiment and can range from 16 bits to 1024 bits. In some embodiments, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0036] Exemplary Register Architecture

[0037] Figure 5 This is a block diagram of a register architecture 500 according to some embodiments. As shown, there is a vector / SIMD register 510, varying in width from 128 bits to 1024 bits. In some embodiments, the vector / SIMD register 510 is physically 512 bits, and depending on the mapping, only some of the lower bits are used. For example, in some embodiments, the vector / SIMD register 510 is a 512-bit ZMM register: the lower 256 bits are used for the YMM register, and the lower 128 bits are used for the XMM register. Thus, there is a stacking of registers. In some embodiments, the vector length field is selected between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the previous length. Scalar operations are performed on the lowest-order data element positions in the ZMM / YMM / XMM registers; depending on the embodiment, the higher-order data element positions remain the same as before the instruction or are zeroed out.

[0038] In some embodiments, register architecture 500 includes write mask / assertion register 515. For example, in some embodiments, there are eight write mask / assertion registers (sometimes referred to as k0 to k7), each with a size of 16 bits, 32 bits, 64 bits, or 128 bits. Write mask / assertion register 515 may allow merging (e.g., allowing any set of elements in the destination to be exempt from updating during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some embodiments, each data element position in a given write mask / assertion register 515 corresponds to a data element position in the destination. In other embodiments, write mask / assertion register 515 is scalable and consists of a set number of enable bits for a given vector element (e.g., eight enable bits for each 64-bit vector element).

[0039] The register architecture 500 includes multiple general-purpose registers 525. These registers can be 16-bit, 32-bit, 64-bit, etc., and can be used for scalar operations. In some embodiments, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0040] In some embodiments, register architecture 500 includes a scalar floating-point register 545, which is used for scalar floating-point operations on 32 / 64 / 80-bit floating-point data using x87 instruction set extensions, or as an MMX register to perform operations on 64-bit compressed integer data, and to store operands for some operations performed between the MMX and XMM registers.

[0041] One or more flag registers 540 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operation. For example, one or more flag registers 540 may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some embodiments, one or more flag registers 540 are referred to as program status and control registers.

[0042] Segment register 520 contains segment points for accessing memory. In some embodiments, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

[0043] Machine-Specific Register (MSR) 535 controls and reports processor performance. Most MSR 535 handles system-related functions and is not accessible to applications. Machine Check Register 560 consists of control, status, and error reporting MSRs used to detect and report hardware errors.

[0044] One or more instruction pointer registers 530 store instruction pointer values. Multiple control registers 555 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processors 170, 180, 138, 115, and / or 200) and the characteristics of the currently executing task. A debug register 550 controls and allows monitoring of debug operations on the processor or core.

[0045] Memory management register 565 specifies the location of data structures used for protected mode memory management. These registers may include the GDTR, IDRT, task register, and LDTR register.

[0046] Alternative embodiments of the invention may use wider or narrower registers. Furthermore, alternative embodiments of the invention may use more, fewer, or different register files and registers.

[0047] Instruction set

[0048] An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit positions) to specify the operation to be performed (e.g., opcode) and operand(s) and / or other data fields (e.g., mask) to which the operation will be performed, and so on. Some instruction formats are further decomposed by defining instruction templates (or subformats). For example, an instruction template for a given instruction format may be defined as a different subset of the fields of that instruction format (the included fields are generally in the same order, but at least some fields have different bit positions because fewer fields are included), and / or defined as a given field that is interpreted in a different way. Thus, each instruction in an ISA is expressed using a given instruction format (and, if defined, according to a given instruction template in the instruction template of that instruction format) and includes fields for specifying the operation and operands. For example, the exemplary ADD (addition) instruction has a specific opcode and instruction format, which includes an opcode field for specifying the opcode and an operand field for selecting operands (source 1 / destination and source 2); and the appearance of the ADD instruction in the instruction stream will cause the operand field to have specific content for selecting a specific operand.

[0049] Example instruction format

[0050] The embodiments of the instructions described herein can be embodied in different formats. Furthermore, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instructions can be executed on such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0051] Figure 6The illustration shows an embodiment of the instruction format. As shown, an instruction may include multiple components, including but not limited to one or more fields for the following: one or more prefixes 601, opcode 603, addressing information 605 (e.g., register identifier, memory addressing information, etc.), shift value 607, and / or immediate value 609. Note that some instructions utilize some or all of the fields in the format, while other instructions may use only the field for opcode 603. In some embodiments, the illustrated order is the order in which these fields are to be encoded; however, it should be understood that in other embodiments, these fields may be encoded, combined, etc., in different orders.

[0052] The (multiple) prefix fields 601 modify instructions during use. In some embodiments, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), provide segmented override control (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), perform bus locking operations, and / or change operands (e.g., 0x66) and address sizes (e.g., 0x67). Some instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes may be considered "traditional" prefixes. Other prefixes, one or more examples of which are detailed herein, indicate and / or provide further capabilities, such as specifying particular registers. Other prefixes typically follow traditional prefixes.

[0053] Opcode field 603 is used to at least partially define the operation to be performed when the instruction is decoded. In some embodiments, the length of the main opcode encoded in opcode field 603 is 1, 2, or 3 bytes. In other embodiments, the main opcode can be of different lengths. An additional 3-bit opcode field is sometimes encoded in another field.

[0054] Address field 605 is used to address one or more operands of an instruction, such as a location in memory or one or more registers. Figure 7 An embodiment of addressing field 605 is illustrated. In this illustration, an optional Mod R / M byte 702 and an optional Scale, Index, Base (SIB) byte 704 are shown. The Mod R / M byte 702 and SIB byte 704 are used to encode up to two operands of an instruction, each of which is a direct register or a valid memory address. Note that each of these fields is optional, as not all instructions include one or more of these fields. The Mod R / M byte 702 includes a Mod field 742, a register field 744, and an R / M field 746.

[0055] The content of the MOD field 742 distinguishes between memory access modes and non-memory access modes. In some embodiments, when the value of the MOD field 742 is b11, register direct addressing mode is used; otherwise, register indirect addressing is used.

[0056] Register field 744 may encode the destination register operand or the source register operand, or it may encode an opcode extension without being used to encode any instruction operand. The contents of register index field 744 specify the location of the source or destination operand (in a register or in memory) directly or through address generation. In some embodiments, register field 744 is supplemented with additional bits from a prefix (e.g., prefix 601) to allow for larger addressing.

[0057] The R / M field 746 can be used to encode instruction operands that reference memory addresses, or it can be used to encode destination register operands or source register operands. Note that in some embodiments, the R / M field 746 may be combined with the MOD field 742 to indicate the addressing mode.

[0058] SIB byte 704 includes a scaling field 752, an index field 754, and a base field 756 for address generation. The scaling field 752 indicates a scaling factor. The index field 754 specifies the index register to be used. In some embodiments, the index field 754 is supplemented with additional bits from a prefix (e.g., prefix 601) to allow for larger addressing. The base field 756 specifies the base address register to be used. In some embodiments, the base field 756 is supplemented with additional bits from a prefix (e.g., prefix 601) to allow for larger addressing. In practice, the content of the scaling field 752 allows scaling of the content of the index field 754 for memory address generation (e.g., for using 2...). 比例 Address generation using index + base address.

[0059] Some addressing schemes use bitwise shift values ​​to generate memory addresses. For example, they can be based on 2 比例 Index + Base Address + Displacement, Index Memory addresses are generated using scaling factor + displacement, r / m + displacement, instruction pointer (RIP / EIP) + displacement, register + displacement, etc. The displacement can be a value of 1 byte, 2 bytes, 4 bytes, etc. In some embodiments, the displacement field 607 provides this value. Furthermore, in some embodiments, a displacement factor is encoded in the MOD field of the addressing field 605, indicating a compressed displacement scheme for which the displacement value is calculated by multiplying disp8 by a scaling factor N determined based on the vector length, the value of B, and the input element size of the instruction. The displacement value is stored in the displacement field 607.

[0060] In some embodiments, the immediate number field 609 specifies the immediate value of the instruction. The immediate value can be encoded as a 1-byte value, a 2-byte value, a 4-byte value, and so on.

[0061] Figure 8 The illustration shows an embodiment of the first prefix 601(A). In some embodiments, the first prefix 601(A) is an embodiment of the REX prefix. Instructions using this prefix can specify general-purpose registers, 64-bit compact data registers (e.g., single-instruction multiple-data (SIMD) registers or vector registers), and / or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

[0062] Depending on the format, instructions using the first prefix 601(A) can specify up to three registers using 3-bit fields: 1) using the reg field 744 and the R / M field 746 of Mod R / M byte 702; 2) using Mod R / M byte 702 with SIB byte 704, including using the reg field 744 and the base field 756 and the index field 754; or 3) using the register field of the opcode.

[0063] In the first prefix 601(A), bits 7:4 are set to 0100. Bit 3 (W) can be used to determine the operand size, but may not be able to determine the operand width alone. Thus, when W = 0, the operand size is determined by the code segment descriptor (CS.D), and when W = 1, the operand size is 64 bits.

[0064] Please note that adding another bit allows addressing 16 (2 4 The MOD R / M reg field 744 and MOD R / MR / M field 746 can each address 8 registers, while the individual MOD R / M reg field 744 and MOD R / MR / M field 746 can each address 8 registers.

[0065] In the first prefix 601(A), bit position 2(R) can be an extension of the MOD R / M reg field 744, and can be used to modify the Mod R / M reg field 744 when this field encodes a general-purpose register, a 64-bit compact data register (e.g., an SSE register), or a control or debug register. R is ignored when the Mod R / M byte 702 specifies another register or defines an extended opcode.

[0066] Bit position 1 (X) X bits can modify the SIB byte index field 754.

[0067] Bit position B(B)B can modify the base address in Mod R / MR / M field 746 or SIB byte base address field 756; or it can modify the opcode register field used to access general-purpose registers (e.g., general-purpose register 525).

[0068] Figures 9(A)-9(D) The illustrations depict an embodiment of how the R, X, and B fields of the first prefix 601(A) are used. Figure 9(A) illustrates how the R and B from the first prefix 601(A) are used to extend the reg field 744 and R / M field 746 of the MOD R / M byte 702 when the SIB byte 704 is not used for memory addressing. Figure 9(B) illustrates how the R and B from the first prefix 601(A) are used to extend the reg field 744 and R / M field 746 of the MOD R / M byte 702 when the SIB byte 704 is not used (register-to-register addressing). Figure 9(C) illustrates how the R, X, and B from the first prefix 601(A) are used to extend the reg field 744, index field 754, and base address field 756 of the MOD R / M byte 702 when the SIB byte 704 is used for memory addressing. Figure 9(D) illustrates the reg field 744 of the first prefix 601(A) used to extend the MOD R / M byte 702 when the register is encoded in opcode 603.

[0069] Figures 10(A)-10(B) The illustration shows an embodiment of the second prefix 601(B). In some embodiments, the second prefix 601(B) is an embodiment of the VEX prefix. The second prefix 601(B) encoding allows instructions to have more than two operands and allows SIMD vector registers (e.g., vector / SIMD register 510) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of the second prefix 601(B) provides a syntax for three (or more) operands. For example, the previous two-operand instructions performed operations such as A = A + B, which overwrote the source operand. The use of the second prefix 601(B) allows operands to perform non-destructive operations such as A = B + C.

[0070] In some embodiments, the second prefix 601(B) has two forms—a two-byte form and a three-byte form. The two-byte second prefix 601(B) is primarily used for 128-bit, scalar, and some 256-bit instructions, while the three-byte second prefix 601(B) provides a compact replacement for the first prefix 601(A) and 3-byte opcode instructions.

[0071] Figure 10(A) illustrates an embodiment of the second prefix 601(B) in two-byte form. In one example, format field 1001 (byte 0 1003) contains the value C5H. In another example, byte 1 1005 includes the value “R” in bit [7]. This value is the complement of the same value of the first prefix 601(A). Bit [2] is used to indicate the length (L) of the vector (where value 0 is a scalar or 128-bit vector, and value 1 is a 256-bit vector). Bits [1:0] provide the opcode extensions, equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). Bits [6:3] are shown as vvvv and can be used to: 1) encode the first source register operand, specified in reverse (two's complement) form, and are valid for instructions with two or more source operands; 2) encode the destination register operand, specified in two's complement form, for certain vector shifts; or 3) not encode any operands, the field is reserved, and should contain a value such as 1111b.

[0072] Instructions using this prefix can use the Mod R / MR / M field 746 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0073] Instructions using this prefix can use the Mod R / M reg field 744 to encode destination register operands or source register operands, which are treated as opcode extensions and are not used to encode any instruction operands.

[0074] For instruction syntax that supports four operands, vvvv, Mod R / MR / M field 746, and Mod R / M reg field 744 encode three of the four operands. Then, bits [7:4] of immediate value 609 are used to encode the third source register operand.

[0075] Figure 10(B) illustrates an embodiment of the second prefix 601(B) in three-byte form. In one example, format field 1011 (byte 0 1013) contains the value C4H. Byte 1 1015 includes “R”, “X”, and “B” in bits [7:5], which are complements of the same values ​​of the first prefix 601(A). Bits [4:0] of byte 1 1015 (shown as mmmmm) include content for encoding one or more implicit preamble opcode bytes as needed. For example, 00001 implies a 0FH preamble opcode, 00010 implies a 0F38H preamble opcode, 00011 implies a 0F3AH preamble opcode, and so on.

[0076] Bits [7] of byte 2 1017 are used similarly to W of the first prefix 601(A), including to help determine the size of the operand that can be promoted. Bit [2] is used to indicate the length (L) of the vector (where a value of 0 is a scalar or a 128-bit vector, and a value of 1 is a 256-bit vector). Bits [1:0] provide the opcode extensions, equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). Bits [6:3] are shown as vvvv and can be used to: 1) encode the first source register operand, specified in reverse (two's complement) form, and valid for instructions with two or more source operands; 2) encode the destination register operand, specified in two's complement form, for some vector shift; or 3) not encode any operand, the field is reserved, and should contain a value such as 1111b.

[0077] Instructions using this prefix can use the Mod R / MR / M field 746 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0078] Instructions using this prefix can use the Mod R / M reg field 744 to encode destination register operands or source register operands, which are treated as opcode extensions and are not used to encode any instruction operands.

[0079] For instruction syntax that supports four operands, vvvv, Mod R / MR / M field 746, and Mod R / M reg field 744 encode three of the four operands. Then, bits [7:4] of immediate value 609 are used to encode the third source register operand.

[0080] Figure 11 The illustration shows an embodiment of the third prefix 601(C). In some embodiments, the first prefix 601(A) is an embodiment of the EVEX prefix. The third prefix 601(C) is a four-byte prefix.

[0081] The third prefix 601(C) can encode 32 vector registers in 64-bit mode (e.g., 128-bit, 256-bit, and 512-bit registers). In some embodiments, write masks / operation masks are used (see the discussion of registers in the preceding figures, such as...). Figure 5 Instructions that make assertions or statements utilize this prefix. The operation mask register allows conditional processing or selection control. Operation mask instructions are encoded using a second prefix 601(B), whose source / destination operands are operation mask registers, and whose contents are treated as a single value.

[0082] The third prefix 601(C) can encode functions specific to instruction classes (e.g., a compact instruction with "load + operation" semantics can support embedded broadcast functionality, a floating-point instruction with rounding semantics can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantics can support "suppress all exceptions" functionality, etc.).

[0083] The first byte of the third prefix 601(C) is the format field 1111, which in one example has a value of 62H. The subsequent bytes are called payload bytes 1115-1119, and together they form a 24-bit value P[23:0] that provides specific capabilities in the form of one or more fields (detailed in this document).

[0084] In some embodiments, P[1:0] of payload byte 1119 is identical to the lower two mmmm bits. In some embodiments, P[3:2] is reserved. Bit P[4] (R') allows access to the upper 16 vector register sets when combined with P[7] and Mod R / M reg field 744. P[6] can also provide access to the upper 16 vector registers when SIB type addressing is not required. P[7:5] consists of R, X, and B, which are operand specifier modifier bits for vector registers, general-purpose registers, and memory addressing, and when combined with Mod R / M register field 744 and Mod R / MR / M field 746, allows access to the next set of 8 registers beyond the lower 8 registers. P[9:8] provides opcode extensions equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). In some embodiments, P

[10] is a fixed value of 1. P[14:11] is shown as vvvv and can be used to: 1) encode the first source register operand, specified in reverse (two's complement) form, and is valid for instructions with two or more source operands; 2) encode the destination register operand, specified in two's complement form, for some vector shift; or 3) not encode any operand, the field is reserved, and should contain a value such as 1111b.

[0085] P

[15] is similar to W in the first prefix 601(A) and the second prefix 611(B), and can be used as an opcode extension bit or operand size boost.

[0086] P[18:16] specifies the index of a register in the operation mask (write mask) register (e.g., write mask / assertion register 515). In one embodiment of the invention, the specific value aaa = 000 has a special behavior that implies no operation mask is used for a particular instruction (this can be implemented in various ways, including using an operation mask that is hardwired to all one or hardware implementation that bypasses the mask hardware). When merged, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the extended operation); in another embodiment, the old value of each element in the destination where the corresponding mask bit has 0 is preserved. Conversely, when zeroed, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the extended operation); in one embodiment, the elements in the destination are set to 0 when the corresponding mask bit has a value of 0. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element being modified); however, the modified elements do not necessarily have to be consecutive. Thus, the operation mask field allows for partial vector operations, including load, store, arithmetic, logic, etc. Although an embodiment of the invention has been described in which the content of the operation mask field selects one of a plurality of operation mask registers containing the operation mask to be used (and thereby the content of the operation mask field indirectly identifies the mask to be performed), alternative embodiments, on the contrary or otherwise, allow the content of the mask write field to directly specify the mask to be performed.

[0087] P

[19] can be combined with P[14:11] to encode a second source vector register in nondestructive source syntax, which can access the high 16 vector registers using P

[19] . P

[20] encodes various functions that differ between different categories of instructions and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge-write masks (e.g., when set to 0) or support for zero-return and merge-write masks (e.g., when set to 1).

[0088] An exemplary embodiment of the encoding of registers in instructions using the third prefix 601(C) is detailed in the table below.

[0089]

[0090] Table 1: 32-register support in 64-bit mode

[0091] Table 2: Encoding Register Specifications in 32-bit Mode

[0092] Table 3: Encoding of Operation Mask Register Specifier

[0093] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0094] The program code can be implemented using a high-level procedural or object-oriented programming language to communicate with the processing system. Assembly or machine language can also be used if needed. In fact, the mechanisms described herein are not limited to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0095] The various embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention can be implemented as computer programs or program code executable on a programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0096] One or more aspects of at least one embodiment can be implemented by representational instructions stored on a machine-readable medium, which represent various logics in a processor, and which, when read by a machine, cause the machine to manufacture logic for performing the techniques described herein. Such representations, referred to as “IP cores,” can be stored on tangible machine-readable media and can be supplied to various customers or production facilities for loading into manufacturing machines that actually manufacture the logic or processor.

[0097] Such machine-readable storage media can include, but are not limited to, non-transitory, tangible arrangements of articles made or formed by a machine or device, including storage media such as hard disks; any other type of disk, including floppy disks, optical disks, compact disc read-only memory (CD-ROM), rewritable compact discs (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); phase-change memory (PCM); magnetic cards or optical cards; or any other type of medium suitable for storing electronic instructions.

[0098] Therefore, embodiments of the present invention also include a non-transitory tangible machine-readable medium containing instructions or design data, such as a hardware description language (HDL), that defines the architectures, circuits, devices, processors, and / or system features described herein. These embodiments may also be referred to as program products.

[0099] Simulation (including binary transformation, code transformation, etc.)

[0100] In some cases, instruction translators can be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction translator can transform instructions (e.g., using static binary transformation, including dynamically compiled binary transformation), modify, emulate, or otherwise convert them into one or more other instructions to be processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on the processor, off the processor, or partially on and partially off the processor.

[0101] Figure 12 The diagram illustrates a block diagram of using a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, according to a comparison of certain implementations. In the illustrated embodiment, the instruction converter is a software instruction converter; however, alternatively, the instruction converter can be implemented using software, firmware, hardware, or various combinations thereof. Figure 12 A program of the form of a high-level language 1202 can be compiled using a first ISA compiler 1204 to generate first ISA binary code 1206 that can be natively executed by a processor 1216 having at least one first ISA instruction set core. The processor 1216 having at least one first ISA instruction set core represents any processor capable of performing substantially the same functions as an Intel® processor having at least one first ISA instruction set core by compatiblely executing or otherwise processing the following: 1) a substantial portion of the instruction set of the first ISA instruction set core, or 2) a version of object code for an application or other software targeted to run on an Intel processor having at least one first ISA instruction set core, in order to achieve substantially the same results as the processor having at least one first ISA instruction set core. The first ISA compiler 1204 represents a compiler that can be used to generate the first ISA binary code 1206 (e.g., object code) that can be executed on the processor 1216 having at least one first ISA instruction set core, with or without additional linking processing.

[0102] Similarly, Figure 12A program of the form of a high-level language 1202 can be compiled using an alternative instruction set compiler 1208 to generate alternative instruction set binary code 1210 that can be natively executed by a processor 1214 that does not have a first ISA instruction set core. An instruction converter 1212 is used to convert the first ISA binary code 1206 into code that can be natively executed by a processor 1214 that does not have a first ISA instruction set core. This converted code is unlikely to be identical to the alternative instruction set binary code 1210 because an instruction converter capable of doing so would be difficult to manufacture; however, the converted code will perform general operations and consists of instructions from the alternative instruction set. Therefore, the instruction converter 1212 represents, through emulation, simulation, or any other process, software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first ISA instruction set processor or core to execute the first ISA binary code 1206.

[0103] In different embodiments, the device may serve or otherwise support different clients. However, the scalability of the device may be limited by its ability to maintain information about each of the different clients it is serving, which may in turn be limited by the silicon die area or other space available for storing such information. For example, Single Root Input / Output Virtualization (SR-IOV), as defined by the Peripheral Component Interconnect Fast (PCIe) specification, can implement a greater number of virtual functions (VFs) to support a greater number of clients. The device can also implement a greater number of queues and associated client-specific states to support a greater number of clients.

[0104] Figure 13 The illustration shows one embodiment of a scalable device 100, which can be implemented using logic gates, storage elements, and / or any other type of circuitry. All or part of the scalable device 100 can be included in discrete components and / or integrated into the circuitry of a processing device or any other means of a computer or other information processing system. For example, Figure 13 The device 1300 can be connected with Figure 1 The coprocessor 138 or Figure 2 This corresponds to the dedicated logic 208 in the code.

[0105] The scalable device according to one embodiment can use any number of work queues 1350, wherein a work queue is a data structure used to accept work from clients. The work queues can be dedicated work queues (DWQs) that accept work from a single client or shared work queues (SWQs) that accept work from multiple clients. For example, device 1300 is shown as including DWQs 1310 and 1314 and SWQ 1312, which accept work from clients 1320, 1322, 1324, 1326, and 1328.

[0106] Work queues can be implemented using memory within a device (e.g., device 1300) and / or memory not within the device (e.g., host memory, system memory, registers, or other storage locations not within the device). By using host memory, for example, work queue 1350 can be implemented using base registers, head registers, and tail registers that can be written to by software to notify the device of work submission. By using device memory, for example, work queue 1350 can be implemented using addresses that can be written to by software to submit work.

[0107] Work queue 1350 can be used to store work descriptors that include a client identifier (ID) and privileges. The client ID is used to identify the client (e.g., using a process address space identifier (PASID)), and the privileges indicate the address domain and privileges that the device can use to identify the client. The work descriptors can be populated by trusted hardware (e.g., a CPU in a secure environment) and / or trusted software (an operating system (OS) running on a CPU in a secure environment) to ensure they are not impersonated by unprivileged clients.

[0108] In all implementations, the job descriptor is fully self-describing, so that the device does not need to maintain any client-specific state and therefore does not require additional memory to support additional clients. A fully self-describing job descriptor contains all the information needed to perform the requested job.

[0109] For example, the work descriptor in the embodiment may include a pointer to a completion record in host memory, where a completion status (including any error status) may be written. The completion record may also contain any portion of the result that can be used by subsequent work descriptors, allowing data to be advanced through operations (e.g., a cyclic redundancy check calculation may use the result from each step as input to the next step). The completion record may also contain flags and / or any other information that can be used during operation execution. Therefore, no memory within the device will be used to store per-client states related to completion status, partial results, flags, etc.

[0110] In various implementations, job descriptors can also be used to avoid other limitations on device scalability. For example, any of the following approaches can avoid limiting the number of clients to one client for each message transmit / receive signaling interrupt in the PCI MSI-X table in the device. According to any approach, any client can have multiple interrupts configured so that the client can choose to specify different interrupts for different descriptors, thus allowing the client to perform interrupt rebalancing without involving the OS or other system software.

[0111] In an embodiment, the working descriptor may be designed to include interrupt message information (e.g., MSI address and data) passed in by the client. Since the interrupt message is provided by the client and is therefore untrusted, interrupt remapping hardware (e.g., an I / O memory management unit) can be responsible for ensuring that the client cannot request interrupts not assigned to it. For example, the PASID, along with the remappingable interrupt message, can be used to locate interrupt remapping table entries for the interrupt message (PASID-granular interrupt remapping). PASID-granular interrupt remapping allows the same message to have different meanings when used with different PASIDs, and it also allows system software to control which interrupt messages can be used by each client (as identified by the client's PASID). The device can then use the interrupt message information from the working descriptor to generate an interrupt when the device completes operation, while avoiding storing the interrupt message in the device.

[0112] In an embodiment, the working descriptor may be designed to include an interrupt handle (instead of the complete MSI message and data value). The interrupt handle in the descriptor specifies an entry in the interrupt message table. The device may implement the interrupt message table in host memory, where each interrupt table entry contains an MSI address and data. Because the interrupt message table is in host memory rather than device memory, this interrupt information table can be large enough to support any number of clients. The interrupt handle in the working descriptor can be used by the device to index into the interrupt table, thereby identifying the MSI address and data value for use in generating an interrupt when the device completes its operation. The device will first use the PASID to verify the interrupt handle to ensure that the client is allowed to use the specific interrupt handle. The device can verify the interrupt handle by using an interrupt message table with PASID granularity or by including the PASID in the interrupt table entry during interrupt setup and generation, matching the entry's PASID against the client's PASID. To avoid reading the interrupt table entry from host memory for every descriptor, an interrupt message cache within the device can cache frequently used interrupt entries.

[0113] In addition to reducing or eliminating per-client states on the device, some embodiments also provide efficient handling of work from a large number of clients. Embodiments can allow prioritization of work from time-sensitive clients while ensuring the forward progress of work from other clients. Embodiments can prevent errors or performance issues caused by some clients from negatively impacting other clients.

[0114] A work submission portal is a means by which clients can submit work requests to a device. In embodiments, a work submission portal (SWQ) may have more than one, to which clients can submit work, rather than a single, mapped work submission portal to all clients using that SWQ. Using a single work submission portal for each SWQ would cause clients to constantly retry work submissions as the SWQ becomes full, potentially making the use of the device difficult and unpredictable for other clients. In contrast, using multiple work submissions for each SWQ according to certain embodiments provides prioritization of work requests and prevents some clients from starving. In embodiments, a work submission portal may be implemented as a memory-mapped I / O (MMIO) address to which clients can write to submit work requests, so multiple work submission portals can be provided by allocating more than one MMIO address to the SWQ and providing different MMIO addresses to different clients, without requiring additional logic or storage in the device.

[0115] In various embodiments, the different job submission portals used for the SWQ may have different characteristics, such as different job acceptance priorities for different clients. For example, the SWQ may have a first submission portal designated as a restricted portal and a second submission portal designated as an unrestricted portal. The SWQ may have a configurable threshold that can be used to reserve some entries specifically for jobs submitted through the unrestricted portal. For example, the SWQ may be configured to use only up to 80% (the threshold) of the SWQ space for jobs submitted through the restricted portal, while jobs submitted through the unrestricted portal can use 100% of the SWQ space. Subsequently, privileged software (e.g., a device driver) can map the restricted portal to the user-space client and reserve the unrestricted portal for its own use. If the user-space client experiences a situation where the SWQ is full (e.g., when the SWQ is 80% full, the SWQ returns a 'retry' to the user-space client), the user-space client can request to submit jobs on behalf of the user-space client to the device driver, instead of the user-space client continuously retrying job submissions itself. The device driver can serialize requests from the user-space client and use the unrestricted portal to submit job requests. Because 20% of the SWQ space has been reserved for the unrestricted portal, the work submission for the device driver will likely succeed.

[0116] The embodiments may also provide handling of situations where the SWQ is 100% full (e.g., even the unrestricted portal returns 'retry'). In an embodiment, the device driver can respond to the client with a 'retry' as if the 'retry' had been received directly from the device. In an embodiment, the device driver can block the client until a job can be submitted, and the device driver may simultaneously schedule another client. In an embodiment, the device driver can place a job descriptor in a software-defined job queue until the job can be submitted to the device, but resume the client as if the job had been successfully submitted to the device. According to this latter approach, the client can continue operating while waiting for the device to catch up. The embodiments provide the use of this latter approach by ensuring that all descriptors to the device are independent of each other in terms of ordering, or by preventing the client from directly submitting any descriptors that can be processed before those queued by the device driver in the software to the device. This prevention can be achieved by removing the device submission portal from the client's memory mapping, making it impossible for the client to directly submit work to the device, or by locking the SWQ so that no client can submit work. In this locking method, all client job submissions will return to 'retry', and clients will have to request the device driver to submit their jobs. This provides fairness, but may also have high overhead due to the bottleneck of job submissions through the device driver (this high overhead may be acceptable because it only occurs when the shared work queue is completely full).

[0117] The implementation may also provide configurability of the work queues themselves. For example, any one of multiple work queues, or each work queue, can be configured as dedicated or shared at runtime based on client requirements. Work queues can be assigned different priorities and configured by software. The device can prioritize dispatching commands from higher-priority work queues relative to those from lower-priority work queues, without starving the lower-priority work queues. Some clients may have access to multiple work queues and thus the ability to prioritize their own work, while other clients may only have access to a single work queue, thus fixing the priority of all their submitted work.

[0118] The embodiments can also provide mitigation for a problem that occurs when a device is blocked while performing an operation because it is waiting for a response from another part of the system (e.g., completion of a memory read, address translation, or handling of a page fault). This problem is known as head-of-line blocking because an operation being performed on the device prevents other operations in the queue that follow from progressing.

[0119] In various embodiments, to alleviate head-of-line congestion, the device may include multiple operational components (engines), such as engines 1330, 1332, 1334, and 1336, which can process individual work descriptors in parallel. In embodiments, one or more work queues may be grouped together with one or more engines. The device may support several groups, such as groups 1340 and 1342. Each work queue and each engine may be software-configured as part of any one group. Work descriptors from one or more work queues in a group may be assigned to any engine within that group. Thus, if one engine in a group is waiting for an external response while processing a descriptor from a work queue, other engines in that group can continue processing other work descriptors from the same work queue or other work queues.

[0120] In an alternative embodiment, the device may implement an out-of-order processing engine that can suspend work descriptors waiting for external responses while simultaneously processing other work descriptors from the same work queue or other work queues.

[0121] Furthermore, in various embodiments, the device may have internal resources (e.g., device internal memory) used by engines to process work descriptors from various clients. If these resources are limited, the device may prioritize (or provide QoS) the use of these resources by different clients to ensure that work descriptors from one or more clients (e.g., relatively large or time-consuming work descriptors) do not consume most or all of the internal resources, thereby impacting the processing of other clients and the overall performance of the device. Prioritization can be accomplished using a credit-based system in which credits represent internal resources. Credits may be assigned to groups, individual work queues, or individual engines to control the amount of resources that each group, work queue, or engine is allowed to use to process its work descriptors. In embodiments, the device may define two credit thresholds for each group, work queue, or engine: a first threshold specifying the minimum number of credits reserved for a group, work queue, or engine (the minimum guaranteed or reserved credits); and a second threshold specifying the maximum number of credits allowed for a group, work queue, or engine (the maximum allowed credits).

[0122] The implementation also provides efficient handling of page faults. If the device supports virtual memory (e.g., shared virtual memory (SVM) or I / O virtual addressing (IOVA)), the address given to the device in the descriptor is not guaranteed to be mapped in physical memory. Before accessing host memory (e.g., via direct memory access (DMA)), the device may request address translation from the I / O Memory Management Unit (IOMMU) using, for example, the address translation service described in the PCIe specification. The IOMMU traverses the address translation table and, if a translation exists, returns the translated physical address to the device so that the device can access the data in memory. However, if the virtual address does not currently exist in main memory, the result is a translation error (I / O page fault). Page faults also occur when a page exists but the processor or device does not have the right to perform the requested type of access (e.g., the device attempts to write to a read-only page).

[0123] When a device encounters a page fault, it cannot handle the fault itself because the memory management system software is not running on that device. Therefore, according to Figure 14 In the method illustrated in Figure 1400, after the application submits a command to the device (1410), the device attempts to access the page (1420), and the IOMMU responds with a page fault (1430). The device sends a page fault notification to the OS via the IOMMU (1440) and blocks descriptor processing until the page fault is resolved. After the page fault is resolved (1450), the OS responds back to the device via the IOMMU that the page is available (1460). Subsequently, the device attempts to access the page again, and this time the access is successful (1470).

[0124] The device typically implements notifications of a limited number of concurrently pending I / O page faults to the OS. Therefore, when supporting a large number of clients, the device may encounter many page faults and may often be waiting for at least one page fault to be resolved, which will significantly degrade the device's performance.

[0125] Therefore, instead of blocking in the event of an I / O page fault, such as Figure 15 Some implementations of method 1500 may include (after the application submits a command to the device (1510), the device attempts to access the page (1520), and the IOMMU responds with a page fault (1530)), the device directly notifies the client of the page fault (1540), and terminates processing of the working descriptor that caused the page fault. The device can then continue processing other working descriptors without blocking, while the application can resolve the page fault or otherwise respond to it (as described below) (1550). After the page fault is resolved, the application can resubmit the command to the device (1560), and the device can attempt to access the page again (1570).

[0126] According to embodiments such as method 1500, page fault handling can be left to the client. For example, the client application can request the OS to resolve the page fault (e.g., by accessing the faulty page) and resubmit the work descriptor to resume work after the page fault is resolved. Alternatively, the client can decide to use some other method without using the device (e.g., by performing operations using the CPU) to complete the remaining work.

[0127] The mechanism by which a device notifies an application that it has encountered a page fault is called partial completion. In embodiments that include partial completion, the device may report the completion of an operation to the client in a normal manner (e.g., by setting device registers, modifying the tail pointer of a queue or a ring buffer, writing to a shared memory location, generating an interrupt, or any combination of these methods), but the completion log information may include additional elements such as: a status field indicating that a page fault was encountered, an indication of how much operation was completed before the page fault, the untranslatable virtual address, an indication of whether the device intended to read or write to the untranslatable virtual address, and any other information required for software recovery (see examples below).

[0128] As the name suggests, partial completion means that the device may have already performed part of the requested operation before encountering a page fault. By reporting partial completion to the client, the client (e.g., application software) can begin using the completed result even while the page fault is being resolved and the remaining part of the operation is being executed by the device.

[0129] In an embodiment, if, for example, the device encounters a page error on the first page required to begin operation, partial completion can report that no operation has been completed.

[0130] In this embodiment, depending on the type, length, and complexity of the operation, the device may restart the operation from its beginning rather than from the point where it encountered the page fault. In this case, the device may report that no operation has been completed even if the page fault was not previously on the first page (assuming that the partially completed operation has not overwritten any of its inputs).

[0131] In this embodiment, the partial completion information includes all the information required for the recovery operation. The client can recover the operation by submitting a new command that begins where the previous operation stopped. For operations that advance data throughout the operation (e.g., CRC calculation), if the page fault is encountered midway through the operation, intermediate results can be retained for use when the operation is recovered. The intermediate results, along with the page fault information, can be stored in the completion record. When the application recovers the operation after satisfying the page fault, it transmits the intermediate results along with the recovery operation command.

[0132] Method and apparatus for high-performance page fault handling for multi-tenant scalable accelerators

[0133] Accelerators are frequently configured to use shared virtual memory (SVM), providing a ubiquitous programming model between host / CPU and accelerator migrations. Meanwhile, there has been rapid growth in highly multi-tenant (VM or container) environments, making it challenging to support SVMs and I / O page faults in these environments.

[0134] These limitations have been addressed using accelerator patterns such as SVM Block-on-Fault and SVM Fault-and-Stream. With SVM Block-on-Fault, the accelerator / engine blocks until the I / O page fault is resolved by the OS / VMM software and a response is returned to continue the remaining work. With SVM Fault-and-Stream, the accelerator / engine context switches to another migration context, while the I / O page fault is resolved for the given context.

[0135] These existing models suffer from various limitations. SVM page faults present scaling and multi-tenancy challenges. If the accelerator only has four engines, I / O page faults cannot scale beyond four concurrent clients, or in multi-tenancy scenarios, there are challenges related to noisy neighbors (e.g., a page fault from one tenant will delay migration execution for other tenants). SVM page faults and flow present challenges in terms of increased device complexity and overhead associated with saving / restoring state. Moreover, previous techniques only support page faults on the data buffer and not page faults on the control structure.

[0136] Embodiments of the present invention include techniques for supporting high-performance I / O page fault handling for accelerator devices in highly multi-tenant and scalable environments while maintaining a low level of accelerator complexity and cost. Specifically, the implementations described herein provide page fault handling for accelerators with per-work-queue capabilities, directly notifying application / migration clients of accelerator page faults, and (when direct notification is not feasible / deprecated) providing an event logging mechanism to allow accelerator driver agents to notify migration clients of page fault handling / notification. Additionally, some embodiments can complete the execution of the faulty context early and immediately switch to the next context, allowing software to handle page faults and complete the remaining work on the host processor (e.g., CPU) or by migrating back to the accelerator. Furthermore, extensions for handling batch descriptors are described.

[0137] These embodiments address challenges related to scaling and complexity, making VM live migrations using assigned accelerators feasible and improving accelerator page fault handling performance. Therefore, the embodiments described herein make the use of SVMs in virtualization configurations more feasible and practical.

[0138] refer to Figure 16 One embodiment of the accelerator 1600 includes a job receiving unit 1610 comprising multiple job queues (WQs) 1601A-1601D, which can be grouped based on workload characteristics as described above. Multiple execution units or "engines" 1621A-1621D are assigned to process job descriptors from one or more job queues within the job queues 1601A-1601D. One or more job dispatchers 1630 will dispatch jobs specified in the descriptors from the job queues 1601A-1601D to job engines 1621A-1621D.

[0139] Execution engines 1621A-1621D are typically shared among multiple clients, which can be drives, applications, virtual machines (VMs), or any other functional software components. Resource sharing reduces the cost / burden of building a separate engine for each client. Work queues 1601A-1601D funnel work to these engines 1621A-1621D and are either assigned to individual clients (e.g., Figure 13 Dedicated work queues 1310 and 1314 in the client, or shared among these clients (e.g., Figure 13 Shared work queue 1312 in the middle.

[0140] refer to Figure 17 In the shared virtual memory programming model, as part of the processing of the working descriptor, the accelerator 1600 will attempt to obtain the address translation associated with the address specified in the working descriptor, for example, by using the PCIe address translation service. The accelerator 1600 may include a translation back buffer 1705 for caching virtual-to-physical address translations. If a particular translation is not found in the TLB 1705, a translation request 1750 is sent to the IOMMU 1725 within the root complex 1720 of the host processor 1710. The IOMMU will retrieve the translation from its TLB or from memory 1715, and will subsequently transmit a translation response 1751 to the accelerator 1600 with the translation.

[0141] The IOMMU 1725 and the accelerator 1600 must communicate to ensure that the TLB 1705 of the accelerator 1600 is consistent with the TLB of the IOMMU 1725 and the host processor 1710. Therefore, in response to certain events such as modification of a transition entry or a context switch, the IOMMU 1725 will send an invalidation request 1753 to the accelerator 1600, which will invalidate the relevant TLB entry and send an invalidation acknowledgment response 1754 back upon completion.

[0142] If the page is not present in memory 1715 or if insufficient permissions are available to access the page, translation request 1750 will generate a page request 1755, for example, using the PCIe page request service. This page request is received by IOMMU 1725 and passed to the system software (OS / VMM) to handle the I / O page error. The system software will correct the page error and return a successful page response 1756 to the accelerator device via IOMMU 1725. In the event that access to the page is denied, a page response with the corresponding error is returned to accelerator 1600.

[0143] During this operation sequence, the accelerator 1600 (or the accelerator's engine) may halt engine / execution until the I / O page fault is handled (similar to how an application running on a core is halted until a CPU page fault is resolved), which is known as "SVM fault-on-blocking mode". Alternatively, the accelerator / engine may generate a page request, save the current working context, and transition to the next working descriptor, then resume operation later once the page fault is handled, which is known as "SVM fault and flow mode".

[0144] As mentioned, page fault blocking presents challenges related to scaling and noisy neighbors. For example, in a scenario where four work queues associated with four different clients are mapped to the engine, a page fault from one client will cause the engine to stop, resulting in delayed execution for other clients. This becomes even more problematic for virtualization configurations where page fault handling latency is high and the behavior of one VM / tenant will affect the quality of service of other VM / tenants sharing the same engine.

[0145] Error and flow modes attempt to address this halting problem; however, they require sophisticated hardware capable of supporting the saving and restoring of workload contexts and present challenges in terms of cost / latency associated with context switching and save / restore operations.

[0146] Furthermore, for virtualization configurations where the arrival of a page fault will cause a virtual machine (VM) to exit and will also require another VM to exit for queuing page responses, these traditional methods introduce additional latency and overhead. Additional challenges arise when using assigned accelerator resources to support live VM migrations. For example, some VMMs first suspend virtual processors and then suspend virtual devices used by the VMs, which can lead to deadlocks due to circular dependencies.

[0147] Figure 18 An example of an accelerator 1800 on which embodiments of the present invention may be implemented is illustrated. Multiple engines 1821A-C process descriptors from multiple work queues 1801A-C. Each accelerator engine 1821A-C includes error handling logic 1805A-1805C as described herein in response to error conditions (but for simplicity, only engine 1821A is illustrated). Engines 1821A-1821C can be any type of processing engine for the accelerator, including but not limited to data replication engines, data compression engines, security engines, communication engines, and graphics engines.

[0148] In one implementation, instead of blocking until the I / O page fault is resolved, error handling logic 1805A directly notifies client 1801 and terminates working descriptor processing. This allows engine 1821A to continue processing other working descriptors without blocking; client 1801 can then potentially perform page fault handling via a driver, OS, or other privileged software. For example, the client application can then request the OS to resolve the page fault (e.g., by accessing the faulty page) and, after the page fault is resolved, resubmit the working descriptor to work queue 1801A to restart work. Alternatively, client application 1801 can decide to use some other method (such as performing the operation using host CPU 1710) instead of using accelerator 1800 to complete the remaining work.

[0149] In various embodiments, I / O page errors are reported via a designated mechanism such as event log 1812 and delegated to client application 1801. System software (such as a device driver or OS) can then repair the page error based on information received in the event log entry and continue to pass a completion record to client 1801 (acting as the agent). In some embodiments, completion record buffer 1811 is used to directly notify client 1801 of the page error and the corresponding message.

[0150] A single accelerator device 1800 may use any of the above techniques at different times or for different purposes.

[0151] The following are typical sources of page faults in an accelerator SVM environment: 1. Source / destination buffer: Most accelerator devices have multiple source / input buffers from which data is read, processed / manipulated, and subsequently written to multiple destination / output buffers.

[0152] 2. Completion record / response queue buffer Many high-performance and scalable devices rely on completion records or response queue slots, where memory writes are generated to notify the software that the job is complete.

[0153] 3. Descriptor list buffer / ring Many high-performance devices rely on descriptor lists or rings to utilize a single job submission / doorbell hit to transmit / execute multiple descriptors.

[0154] 4. Scatter-Cluster List Buffer Some accelerator devices transmit the addresses of a scatter-aggregate list instead of directly transmitting the source / destination addresses.

[0155] 5. Operate a specific buffer Some accelerator devices allow software to specify additional buffer addresses (e.g., CRC seed address, eject readback address, delta record address, etc.) depending on the operation.

[0156] 6. Configuration and control structure Some accelerator devices may also have configuration and control structures (e.g., migration / working context, license table, etc.) that may encounter page faults during workload execution.

[0157] Figure 19A The illustration shows an example of a job descriptor 1900, which can be submitted to a job queue 1801A and interpreted by an accelerator engine 1821A to execute a job. The job descriptor 1900 includes an operation field 1901 specifying the operation to be performed, multiple flags 1902 (e.g., completion record address valid, request completion record, request completion interruption), a process address space identifier (PASID) field 1903 for associating the job descriptor with the process / application that generated the job, a completion record address field 1904 indicating the memory location for the completion record (e.g., for storing metadata related to the job being performed), a source address field 1905 indicating the memory location for the source data, a destination address field 1906 indicating the memory location for the result data, a completion interrupt handle 1907, a transfer size field 1908, and (optionally) includes one or more operation-specific fields 1909 for specifying additional details of the operation to be performed.

[0158] Figure 19BThe example of batch descriptor 1950 shown in the figure includes many of the same fields as the working descriptor 1900, with the exception of descriptor list address 1951, which identifies the memory location of the descriptor list (descriptor batch), and descriptor count field 1952, which indicates the number of descriptors in the list.

[0159] Figure 20 The illustration shows an example of a completion record 2000. In one embodiment, an accelerator engine 1821A executing a job identified by a descriptor generates a completion record, which is stored in a completion record buffer 1811. The client 1801 that submits the job can then access the completion record from the buffer.

[0160] like Figure 20 As illustrated, in some implementations, the completion record 2000 is written to a 32-byte structure in buffer 1811 when the requested work is completed or an error is encountered. In some embodiments, engine 1821A writes sufficient information into the completion record 2000 to allow engine 1821A to continue the operation if it is only partially completed due to a page fault.

[0161] The completion status field 2004 indicates whether the operation has been completed. If the operation was completed successfully, depending on the type of operation, the completion record 2000 may (for example, in the operation-specific field 2006 or the result field 2003) contain the result of the operation (if any). The result may also be stored in different locations in memory and identified by the address in the completion record 2000. If the operation was not completed successfully, the completion record contains error or mishap information in the error information field 2003.

[0162] In one implementation, if the completion record 2000 is for a descriptor submitted as a part of a batch, the index field (not shown) contains an index in the batch that generated the descriptor of the completion record. For batch descriptors, this field can be 0xff. For any other descriptor that is not a part of a batch, this field can be left unused.

[0163] In one implementation, if an operation is partially completed due to a page fault, the completion byte field 2001 indicates the number of source bytes processed before the error occurred. All source bytes represented by this count are fully processed, and the results are written to the destination address as needed, depending on the operation type. For some operation types, this field may also be used when the operation stops before completion for some reason other than an error. If the operation completes fully, this field can be set to 0. For operation types where the output size cannot be readily determined from this value, the completion record 2000 also contains the number of bytes written to the destination address. If the operation is partially completed due to a page fault, the error address field 2005 contains the address that caused the error.

[0164] As mentioned, embodiments of the present invention use a completion record buffer 1811 to directly notify the client 1801 of page errors and provide corresponding information. For example, the error address field 2005 indicates the address associated with the page error, the error information field 2002 captures information associated with the page error (such as the type of buffer and whether the error address field 2005 is valid), and the status field 2004 transmits the associated status information.

[0165] However, when a page fault is observed above the completion record address itself, it may not be feasible to communicate this information to the client 1801 using the completion record buffer 1811. In this case, a memory-based event log 1812 can be used to log such events. This type of event log 1812 can be implemented per accelerator device 1800, per engine 1821A-1821C, and / or per work queue 1801A-1801C.

[0166] Figure 21 The diagram illustrates an example of event log entry 2100, which has multiple fields for providing information related to the associated descriptor and / or error condition. Errors concerning the completion record 2000 of a descriptor, or errors during the processing of a descriptor that does not have a valid completion record address, are typically reported in a register (software error register). Multiple such errors occurring before the software has processed the register result lead to an overflow condition.

[0167] In contrast, embodiments of the present invention support logging of such events in an event log 1812 in memory. For example... Figure 22 As shown in the diagram, the Event Log Configuration Register (EVLCFG) 2201 is configured to store the address and size of the event log memory region. This is done when the accelerator control register (in...) Figure 22When the Event Log Enable bit in the General Configuration Register (GENCFG) 2202 is set to 1, Event Log 1812 is enabled.

[0168] Compared to writing to the completion record buffer 1811, writing to the event log can be published as a translated or untranslated memory access. In some implementations, the software pins the memory page corresponding to the event log, and the event log write is performed when the traffic class (TC) value is 0.

[0169] In at least some embodiments, if the PASID enable field 2201C in EFLCFG 2201 is 1, a write to the event log 1812 is published as a write using the PASID and the corresponding privilege level (which is also stored in EFLCFG 2201 in some implementations). If the event log 1812 is enabled, the accelerator device 1800 initializes the header field 2203A and the tail field 2203B in the event log status register (EVLSTATUS) 2203 (when device 1800 is enabled). Once enabled, the hardware writes each event to the offset specified by the event log tail field 2203B and increments the tail value 2203B. When the tail reaches the end of the log, it wraps to a value of 0. The next event to be processed by the software is specified by the event log header field 2203A. After processing one or more events at the head of the event log, the software updates the header field 2203A. The log is full when the tail value + 1 mod log - size = header value.

[0170] When writing an event to event log 1812, if the event log interrupt enable field 2204A in accelerometer control register (GENCTRL) 2204 is 1 and the interrupt pending bit 2203C in EVLSTATUS is 0, the hardware sets the interrupt pending bit 2203C to 1, sets the event log field 2205A in interrupt cause register (INTCAUSE) 2205 to 1, and generates an interrupt (e.g., if accelerometer 1800 includes MSI-X, then MSI-X entry 0 is used). No further interrupts are generated for additional log entries until the software clears the interrupt pending bit 2203C. If event log 1812 is full when the hardware attempts to append an event, the hardware blocks until the software updates the event log header field 2203A after processing one or more events from the log header. Therefore, the software must ensure that the event log area in memory is sufficiently large and that event log entries are processed in a timely manner.

[0171] In various embodiments, if the hardware encounters a page fault at a completion record address when the Page Request Service (PRS) is disabled, it is reported as an error. If the event log 1812 is enabled, the hardware writes an entry to the event log with an appropriate error code indicating the cause of the page fault; otherwise, it is reported via field 2206A in the software error register (SWERROR) 2206. In the former case, the hardware also writes a completion record 2000 for that descriptor to the event log entry. The completion record 2000 written to the event log 1812 has the same format as described above. The software responsible for handling the event log 1812 is expected to perform the necessary actions to propagate the completion record 2000 to the software entity (e.g., client 1801) that submitted the faulty descriptor, if appropriate. The software may also generate a completion interrupt if requested.

[0172] refer to Figure 23 In cases where a completion record is required or completion is interrupted for a batch descriptor, if a completion record for any descriptor in the batch is written to event log 1812 due to a page fault at the completion address, then the batch completion record 2300 for the corresponding batch descriptor 1950 is also written to event log 1812. In this case, the error code in the event log entry for batch descriptor 1950 indicates that one or more descriptors in the batch have an associated event log entry containing a completion record 2000 that must be processed by software. In various embodiments, accelerator 1800 generates a batch identifier value to allow software to associate event log entries 1812 for descriptors within the batch with event log entries 1812 for the corresponding batch descriptor 1950, and this is reported in the batch identifier field of the event log 1812 entry. Once the event log entry for a batch descriptor has been written, the batch identifier can be reused by the hardware. An event log entry with a first error of 1 in the batch identifier identifies the first entry for that batch. This allows software to identify any outdated event log entries using the same batch identifier. If the software encounters an entry where the flag is 1, any pending page errors previously logged for the same batch of identifiers can be discarded.

[0173] exist Figure 24The diagram illustrates an example of an eject descriptor 2400 and an eject completion record 2401. An eject descriptor waits for the completion of certain prior descriptors in work queue 1801A to which it has been submitted. If eject descriptor 2400 is submitted to a dedicated work queue, it waits for the completion of all descriptors in that queue. If eject descriptor is submitted to a shared work queue 1801A, it waits for descriptors in the work queue submitted with the same PASID as the eject descriptor. To wait for all descriptors with a specific PASID, the software submits individual eject descriptors to each work queue associated with that PASID.

[0174] In some embodiments, if event log 1812 is enabled, the completion of the discharge descriptor 2400 is always written to event log 1812. If event log 1812 is not enabled, the discharge descriptor completion record 2401 is written to the completion record address.

[0175] like Figure 25 As illustrated, at least some embodiments of the present invention implement per-WQ Page Request Service (PRS) 2501-2502, which can be dynamically enabled and disabled per WQ. Figure 25 For example, PRS 2501 and PRS 2502 have been dynamically enabled for work queues 1801B and 1801C respectively and disabled for work queue 1801C, which uses the high-performance techniques described herein instead of PRS (e.g., terminating work and submitting entries to event log 1812 and / or completion record buffer 1811).

[0176] In one embodiment, a capability bit is provided in a control register to indicate whether the per-WQ PRS can be disabled on a given scalable accelerator 1800. The capability bit can be provided in any of the registers described above. When supported, the per-WQ control bit indicates whether the PRS is enabled or disabled for a specific WQ—even when it is enabled at the accelerator device 1800 level—thus providing fine-grained control over page fault handling. In some implementations, for example, one or more of the scalable page fault handling techniques described herein are used when the per-WQ control bit is set (i.e., set to 1) for a specific work queue. When cleared (i.e., binary 0), conventional page fault handling techniques are used.

[0177] Figure 26 The illustration shows a method according to an embodiment of the present invention. At 2601, a work descriptor is received in the work queue of the accelerator, and at 2602, a page error is detected for the work associated with the descriptor in the specific work queue.

[0178] Depending on the page fault mode configured for a specific work queue, as determined at 2603, page faults are handled differently. For example, when a page fault occurs and PRS 2501-2502 is enabled for the associated work queues 1801A-1801B ( Figure 26 In Mode 2), at 2611, work associated with the descriptor is suspended, and a page fault is reported as a PRS request to the IOMMU 1725 for servicing by the OS page fault handler. The IOMMU 1725 notifies the OS via an interrupt. At 2612, the OS verifies the address and, upon successful verification, creates a mapping in the page table and returns a PRS response via the IOMMU 1725. Descriptors encountering errors are blocked until a PRS response is received. Other operations following a descriptor with an error may also be blocked. If the OS is unable to create a mapping, it returns an error response, and the descriptor is completed with the error. Error reporting is the same as page fault reporting when PRS is disabled, as described in the next section.

[0179] As described above, for work queue 1801A where PRS is disabled ( Figure 26 In Mode 1 of the protocol, at 2604, the work associated with the descriptor is terminated. When a page fault is determined to have occurred at the completion record address at 2605, the error is reported in the event log (if enabled) at 2606 (or, in some embodiments, in the SWERROR register 2206). At 2607, the client resolves the page fault and determines the next steps based on the event log. A completion record error reported in event log 1812 is recoverable. The descriptor is completed, and the event log entry contains the completion record address and the contents of the completion record. After handling the page fault, the system software can copy the completion record to the completion record address. A completion record error reported in SWERROR may be unrecoverable: since only a single error can be logged, the error may be lost; and because some completion information is not logged, the descriptor is not completed and must be restarted.

[0180] When a page fault is determined at 2605 to have occurred for an address in the descriptor rather than the completion record address, at 2608, engine 1821A stops operating and writes the partial completion status, along with the faulty address and progress information, to the completion record in completion record buffer 1811 (as described above). When the client software receives the completion record indicating partial completion, at 2609, it resolves the page fault and determines the next steps based on the completion record. For example, the client has the option to fix the error on the host processor (e.g., by touching the page) and submit a new descriptor with remaining work. Alternatively, the software can complete the remaining work on the host processor.

[0181] The actions described above, where PRS is disabled and event logging is enabled, reduce the impact on other applications in the event of a page fault, thereby improving performance.

[0182] In some implementations, if a descriptor within batch descriptor 1950 receives an error due to a completion address, the entry is pushed to event log 1812. Before the event log entry can be processed (e.g., by device driver software), client 1801 may potentially observe updates to the entire batch descriptor completion record 2200—leading to inconsistent state or ordering / timing issues relative to the completion record updates. A similar problem applies to eject descriptor 2400.

[0183] The following embodiment addresses this problem. In the event that a completion record is required or completion is interrupted for batch descriptor 1950, if a completion record for any descriptor in the batch is written to event log 1812 (e.g., due to a page fault at the completion address), then completion for the corresponding batch descriptor 1950 is also written to the event log.

[0184] Each event log entry for a descriptor within a batch or for a batch descriptor with an error code associated with a page fault contains a batch identifier, which is used (e.g., by a kernel-mode driver (KMD)) to associate a completion record in the event log with the same batch.

[0185] If a page fault is stored at completion record address 2200 for a batch descriptor and no event log entry exists with error code ABC written for any descriptor in the batch, the event log entry for the batch descriptor is written with error code ABC. If a page fault is stored at completion record address 2200 for a batch descriptor and an event log entry exists with error code ABC written for any descriptor in the batch, the event log entry for the batch descriptor is written with error code XYZ. Using different error codes ABC / XYZ allows the software to distinguish between these two cases.

[0186] In some embodiments, when PRS 2501-2502 are disabled, page faults are handled by halting the operation and reporting a partial completion status in the completion record. Additionally, when event log 1812 is enabled, page faults at completion record addresses are reported through event log 1812. In at least one implementation, the kernel-mode driver (KMD) is responsible for configuring and enabling event log 1812. In these implementations, the KMD must ensure that event log 1812 is large enough and that entries are processed in a timely manner to prevent subsequent event log writes from the device from being blocked due to the event log being completely consumed.

[0187] If client 1801 is notified of a page fault directly through a completion record, the client can repair the (valid) page fault by accessing the page. Once the page fault is corrected, client 1801 has the option to complete the remaining work on the CPU or restart / continue work by migrating back to accelerator 1800 (e.g., storing a new work descriptor in work queue 1801A).

[0188] In various embodiments, when an entry in the page fault handling event log 1812 on the completion record is executed, the KMD or other privileged software component performs the following operations: 1. If the first error in the batch flag is 1, any previously logged errors associated with the batch identifier are discarded. This can occur if batch completion is lost due to an abort command or internal hardware error. Normally, errors are not logged and no action is required.

[0189] 2. Attempt to fix the page fault corresponding to the error address and PASID reported in event log entry 1812, and if successful, write a completion record to the error address, and generate a completion interrupt if the event log entry indicates that a completion interrupt should be generated.

[0190] 3. If an error occurs while writing a completion record and the completion record is for a descriptor in the batch, KMD (or other software component) associates the error with the batch descriptor of the event log entry and tracks it until the event log entry for the corresponding batch descriptor is observed. KMD does not need to track completion records that were successfully written.

[0191] When processing an event log entry for one or more descriptors in a batch where an error code indicates that a completion record for that batch descriptor should be written, the KMD or other privileged software component performs the following operations before writing the batch completion record to memory, taking into account that the error has already been recorded with a matching batch descriptor: 1. If the status of a completion record in an event log entry indicates that all descriptors succeeded, KMD (or other components) will change it to indicate that one or more descriptors failed.

[0192] 2. KMD or other components should subsequently clear the recorded errors when preparing for the next batch with the same batch descriptor.

[0193] If no errors are reported for the batch (all completion records have been successfully written), the KMD or other components write the batch completion record as is. If an event log entry indicates that an interrupt should be generated, the software should subsequently generate a completion interrupt.

[0194] When an application, user-mode driver (UMD), or other client 1801 receives a completion record indicating partial completion, it may choose to fix page faults and resubmit the descriptor to accelerator device 1800 to complete the remainder of the operation. In most cases, the original descriptor may need to be updated to adjust the transfer size field based on the amount of work already completed. For some operations, additional updates to the original descriptor may be required. When resubmitting a batch descriptor that was previously terminated, the software may set the batch error flag in the descriptor based on the status of the partially completed batch to ensure that the status of the final completion record for that batch reflects the correct status across all descriptors in that batch.

[0195] For virtualization configurations, the host software can expose virtual event logs to the guest machine and can (e.g., via the guest machine KMD) inject error information into the guest machine to manage page errors as described above.

[0196] The embodiments of the present invention described herein include one or more of the following: The choice of per-WQ page fault handling capabilities includes the choice between PRS-based page fault handling and high-performance page fault handling as described above.

[0197] The ability to directly notify application / migration clients of accelerator page faults (when possible) and to use event logs to allow the accelerator driver to delegate page fault handling / notification to the migration client (when direct notification is not feasible / recommended).

[0198] Early completion of the erroneous context is achieved by immediately switching to the next context.

[0199] The page fault is handled in the software and the remaining work is done on the host processor or by migrating back to the accelerator device.

[0200] Techniques used to handle batch descriptors.

[0201] Embodiments of the present invention may include the steps already described above. These steps may be embodied as machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform these steps. Alternatively, these steps may be performed by a specific hardware component containing hard-wired logic for performing these steps, or by any combination of programmed computer components and custom hardware components.

[0202] Example

[0203] The following are example implementations of different embodiments of the present invention.

[0204] Example 1. An apparatus comprising: one or more accelerator engines for processing work descriptors submitted by clients to a plurality of work queues; and error handling hardware logic associated with the one or more accelerator engines for implementing a specified page error handling mode for each of the plurality of work queues, the page error handling mode including a first page error handling mode and a second page error handling mode.

[0205] Example 2. The apparatus as described in Example 1, wherein, in the first page error handling mode, error handling hardware logic is used to notify the client and terminate the processing of the working descriptor associated with the page error.

[0206] Example 3. The apparatus as described in Example 2, wherein error handling hardware logic is used to submit information to a completion record buffer and / or event log in response to a page fault, the information being associated with the page fault and usable by client and / or system software to resolve the page fault.

[0207] Example 4. The apparatus as described in Example 3, wherein information is used to allow a client to continue processing or resubmit a job if the job associated with a job descriptor has only been partially completed due to a page fault.

[0208] Example 5. The apparatus as described in Example 4, wherein the information includes an error address and a completion byte field, the completion byte field indicating the number of source bytes processed before the page fault occurred.

[0209] Example 6. The apparatus as described in Example 3, wherein if a page fault occurs at an address associated with the completion record buffer, the information is submitted to the event log instead of the completion record buffer.

[0210] Example 7. The apparatus as described in Example 6, wherein the event log is used to associate with a specific accelerator engine in one or more accelerator engines or a specific work queue in multiple work queues.

[0211] Example 8. The apparatus as described in Example 1, wherein, in the second page error handling mode, the processing of the working descriptor is to be suspended, and the error handling hardware logic is to generate a page request to the memory management hardware logic, the processing of the working descriptor is to be to resume only after a response is received from the memory management hardware logic.

[0212] Example 9. A method comprising: processing a work descriptor by an accelerator engine, the work descriptor being submitted by a client to a plurality of work queues; and, in response to detecting a page fault associated with a work descriptor in a particular work queue, performing the following operations: determining a page fault handling mode associated with the work queue, and, if the page fault handling mode includes a first page fault handling mode, notifying the client and terminating processing of the work descriptor associated with the page fault.

[0213] Example 10. The method described in Example 9 further includes: if the page fault handling mode includes a second page fault handling mode, then performing the following operations: suspending the work associated with the work descriptor and transmitting a page fault request to the memory management hardware logic; and restarting the work associated with the work descriptor after receiving a response from the memory management hardware logic.

[0214] Example 11. The method described in Example 9 further includes: submitting information associated with a page fault to a completion record buffer and / or an event log in response to a page fault.

[0215] Example 12. The method described in Example 11, wherein, based on information, the client is used to continue processing or resubmit the job if the job associated with the job descriptor has only been partially completed due to a page fault.

[0216] Example 13. The method described in Example 12, wherein the information includes an error address and a completion byte field, which indicates the number of source bytes processed before the page fault occurred.

[0217] Example 14. The method described in Example 11, wherein if a page fault occurs at an address associated with the completion record buffer, the information is submitted to the event log instead of the completion record buffer.

[0218] Example 15. The method described in Example 11, wherein if a page fault message for the first working descriptor is committed to the event log, then a page fault message for the second working descriptor is also committed to the event log instead of the completion recording buffer.

[0219] Example 16. The method as described in Example 15, wherein at least one working descriptor includes a batch descriptor or an eject descriptor, the batch descriptor including a descriptor list address identifying a memory location of the batch of descriptors, the eject descriptor being used to cause the accelerator engine to wait for the completion of a prior descriptor specified in the working queue before processing the eject descriptor.

[0220] Example 17. A machine-readable medium having program code stored thereon that, when executed by a machine, causes the machine to: process work descriptors submitted by clients to multiple work queues by an accelerator engine; and, in response to detecting a page fault associated with a work descriptor in a particular work queue, to: determine a page fault handling mode associated with the work queue, and, if the page fault handling mode includes a first page fault handling mode, notify the client and terminate the processing of the work descriptor associated with the page fault.

[0221] Example 18. The machine-readable medium as described in Example 17 further includes, if the page fault handling mode includes a second page fault handling mode, performing the following operations: suspending the work associated with the working descriptor and transmitting a page fault request to the memory management hardware logic; and, after receiving a response from the memory management hardware logic, restarting the work associated with the working descriptor.

[0222] Example 19. The machine-readable medium as described in Example 17 further includes: submitting information associated with a page fault to a completion record buffer and / or an event log in response to a page fault.

[0223] Example 20. A machine-readable medium as described in Example 19, wherein, based on information, a client is used to continue processing or resubmit a job if the job associated with a job descriptor has been only partially completed due to a page fault.

[0224] Example 21. A machine-readable medium as described in Example 20, wherein the information includes an error address and a completion byte field indicating the number of source bytes processed before a page fault occurs.

[0225] Example 22. A machine-readable medium as described in Example 19, wherein if a page fault occurs at an address associated with the completion record buffer, the information is committed to the event log instead of the completion record buffer.

[0226] Example 23. A machine-readable medium as described in Example 19, wherein if a page fault message for a first working descriptor is submitted to the event log, a page fault message for a second working descriptor is also submitted to the event log, rather than to the completion recording buffer.

[0227] Example 24. A machine-readable medium as described in Example 23, wherein at least one working descriptor includes a batch descriptor or an eject descriptor, the batch descriptor including a descriptor list address identifying a memory location of a batch of descriptors, the eject descriptor being used to cause the accelerator engine to wait for the completion of a prior descriptor specified in the working queue before processing the eject descriptor.

[0228] As described herein, instructions can refer to a specific configuration of hardware such as an application-specific integrated circuit (ASIC) configured to perform certain operations or have a predetermined function, or software instructions stored in memory embodied as a non-transitory computer-readable medium. Thus, the techniques illustrated in the figures can be implemented using code and data stored on and executed on one or more electronic devices (e.g., terminal stations, network elements, etc.). Such electronic devices use computer-machine-readable media (internal and / or via a network with other electronic devices) to store and communicate code and data, such as non-transitory computer-machine-readable storage media (e.g., disks; optical disks; random access memory; read-only memory; flash memory devices; phase-change memory) and transient computer-machine-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagation signals—such as carrier waves, infrared signals, digital signals, etc.). Furthermore, such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connections. The coupling of the processor set with other components is typically via one or more buses and bridges (also referred to as bus controllers). Storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage devices of a given electronic device typically store code and / or data for execution on one or more processor sets of that electronic device. Of course, different combinations of software, firmware, and / or hardware can be used to implement one or more portions of embodiments of the invention. Throughout this detailed description, numerous specific details have been set forth for illustrative purposes in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without some of these specific details. In some instances, well-known structures and functions have not been described in detail to avoid obscuring the subject matter of the invention. Therefore, the scope and spirit of the invention should be determined based on the appended claims.

Claims

1. An apparatus comprising: an accelerator having one or more data replication engines to process a work descriptor submitted to a work queue, the work descriptor to identify a memory location for a list of work items to be processed by a plurality of data replication engines; wherein state information associated with the work descriptor is to be stored in both an event log and a completion record buffer associated with the work queue, the state information to indicate whether a work item failed to complete due to an error condition; and error handling hardware logic associated with the plurality of data replication engines to implement a specified page fault mode of a plurality of page fault modes for the work queue, the plurality of page fault modes including a first page fault mode and a second page fault mode; wherein upon a page fault occurring on an address associated with the completion record buffer, information associated with the page fault is submitted to the event log and not to the completion record buffer.

2. The apparatus of claim 1, wherein, In the first page fault mode, the error handling hardware logic is to generate a notification and terminate processing of the work descriptor.

3. The apparatus of claim 2, wherein, In the second page fault mode, processing of the work descriptor is to be temporarily suspended, processing of the work descriptor to be subsequently resumed.

4. The apparatus of claim 3, wherein, The state information includes partial completion information indicating completed work items in the list.

5. The apparatus of claim 4, wherein, The partial completion information is used to resume processing of work items in the list indicated as not completed.

6. The apparatus of claim 1, wherein, To resolve the page fault, the error handling hardware logic is to generate a request to memory management hardware logic for a page that caused the page fault and receive a response including an indication of the page.

7. The apparatus of claim 6, wherein, The memory management hardware logic includes an input / output memory management unit (IOMMU) to translate a virtual address associated with the page to a physical address associated with the page.

8. A method comprising: processing, by an accelerator having one or more data replication engines, a work descriptor submitted to a work queue, the work descriptor to identify a memory location for a list of work items to be processed by a plurality of data replication engines, wherein state information associated with the work descriptor is to be stored in both an event log and a completion record buffer associated with the work queue, the state information to indicate whether a work item failed to complete due to an error condition; and implementing, by error handling hardware logic associated with the plurality of data replication engines, a specified page fault mode of a plurality of page fault modes for the work queue, the plurality of page fault modes including a first page fault mode and a second page fault mode, wherein upon a page fault occurring on an address associated with the completion record buffer, information associated with the page fault is submitted to the event log and not to the completion record buffer.

9. The method of claim 8, wherein, In the first page fault mode, the error handling hardware logic is to generate a notification and terminate processing of the work descriptor. In the second page fault mode, processing of the work descriptor is to be temporarily suspended, processing of the work descriptor to be subsequently resumed.

10. The method of claim 9, wherein, In the second page fault mode, processing of the work descriptor is to be temporarily suspended, processing of the work descriptor is to be subsequently resumed.

11. The method of claim 10, wherein, The state information includes partial completion information indicating completed work items in the list.

12. The method of claim 11, wherein, The partial completion information is used to resume processing of work items in the list indicated as not completed.

13. The method of claim 8, wherein, To resolve the page fault, the error handling hardware logic is to generate a request for a page that caused the page fault to memory management hardware logic and receive a response including an indication of the page.

14. The method of claim 13, wherein, The memory management hardware logic includes an input / output memory management unit (IOMMU) to translate a virtual address associated with the page to a physical address associated with the page.

15. A non-transitory machine readable medium storing instructions that, when executed by an apparatus, are capable of causing the apparatus to perform the steps of: A work descriptor submitted to a work queue is processed by an accelerator having one or more data replication engines, the work descriptor identifying a memory location of a list of work items to be processed by the plurality of data replication engines, wherein, State information associated with the work descriptor is to be stored in both an event log and a completion record buffer associated with the work queue, the state information to indicate whether a work item failed to complete due to an error condition; and A specified page fault mode of a plurality of page fault modes for the work queue is implemented by error handling hardware logic associated with the plurality of data replication engines, the plurality of page fault modes including a first page fault mode and a second page fault mode, wherein upon a page fault occurring on an address associated with the completion record buffer, information associated with the page fault is committed to the event log and not to the completion record buffer.

16. The non-transitory machine readable medium of claim 15, wherein, In the first page fault mode, the error handling hardware logic is to generate a notification and terminate processing of the work descriptor.

17. The non-transitory machine readable medium of claim 16, wherein, In the second page fault mode, processing of the work descriptor is to be temporarily suspended, processing of the work descriptor is to be subsequently resumed.

18. The non-transitory machine readable medium of claim 17, wherein, The state information includes partial completion information indicating completed work items in the list.

19. The non-transitory machine readable medium of claim 18, wherein, The partial completion information is used to resume processing of work items in the list indicated as not completed.

20. The non-transitory machine readable medium of claim 15, wherein, To resolve the page fault, the error handling hardware logic is to generate a request for a page that caused the page fault to memory management hardware logic and receive a response including an indication of the page.

21. A method comprising: compiling a program in a high level programming language using an x86 compiler to generate x86 binary code that is natively executed by a first processor having at least one x86 instruction set core; using an instruction translator to translate the x86 binary code into alternative binary code that is natively executed by a second processor that does not have an x86 instruction set core.

22. An apparatus comprising: one or more accelerator engines to process work descriptors submitted by a guest to a plurality of work queues; and error handling hardware logic associated with the one or more accelerator engines, the error handling hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling mode including a first page fault handling mode and a second page fault handling mode.

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