I²C Equipment Control Methods and Systems

Abstract

This application provides an I²C device control method and system, relating to the field of hardware design technology. The method, applied to programmable logic devices, includes: acquiring interface signals from a processor; converting the interface signals into I²C bus protocol signals; determining the communication channel of the target I²C device; and transmitting the I²C bus protocol signals to the target I²C device based on the communication channel. This application solves the problem of system function interruption caused by a single point of failure in the BMC (Browser Control Center).

Description

Technical Field

[0001] This application relates to the field of hardware design technology, and in particular to an I²C device control method and system. Background Technology

[0002] In complex multi-board systems such as modern servers, industrial control equipment, and communication base stations, the I²C bus plays a crucial role in connecting peripherals such as sensors, power management units, and temperature monitoring devices due to its low speed and short range. Typically, the Baseboard Management Controller (BMC) and the Central Processing Unit (CPU) play different roles in the system: the BMC is responsible for low-level hardware monitoring and fault diagnosis, while the CPU handles system-level logic control and task scheduling. However, with the increasing complexity of systems, the number of I²C devices has surged, and these devices are distributed across multiple boards such as the motherboard, expansion cards, and power modules.

[0003] Currently, I²C device control schemes typically employ a BMC direct control mode. In this mode, the BMC acts as the I²C master controller, directly connecting to I²C devices on various boards via its integrated multi-channel I²C bus. The CPU sends instructions to the BMC through its internal network, and the BMC executes read and write operations on the I²C devices. However, in some scenarios, this control method has the following limitations: it makes it difficult for the processor to control the I²C devices. Summary of the Invention

[0004] This application provides an I²C device control method and system to avoid the problem that the processor cannot control the I²C device when the BMC fails.

[0005] In a first aspect, this application provides an I²C device control method, applied to a programmable logic device, comprising:

[0006] Obtain interface signals from the processor;

[0007] Convert the interface signals into I²C bus protocol signals;

[0008] Determine the communication channel of the target I²C device;

[0009] Based on the communication channel, I²C bus protocol signals are transmitted to the target I²C device.

[0010] In one possible implementation, determining the communication channel of the target I²C device includes:

[0011] Determine the operating status of the baseboard management controller;

[0012] Adjust the channel selection logic of the I²C switch according to the operating status;

[0013] Based on the channel selection logic, determine the communication channel of the target I²C device.

[0014] In one possible implementation, the channel selection logic of the I²C switch is adjusted according to the operating state, including:

[0015] When the operating status is normal, the control channel of the board management controller is enabled by the control signal of the I²C switch.

[0016] When the operating status is abnormal, the backup control channel is enabled by the control signal of the I²C switch.

[0017] In one possible implementation, before adjusting the channel selection logic of the I²C switch according to the operating state, the method further includes:

[0018] Obtain the connection status of the target I²C device;

[0019] When the connection status is abnormal, close the channel of the I²C switch corresponding to the target I²C device;

[0020] When the connection status is normal, the channel of the I²C switch corresponding to the target I²C device is turned on to perform the operation of adjusting the channel selection logic.

[0021] In one possible implementation, the operating state of the baseboard management controller is determined in the following manner:

[0022] Obtain the status code of the baseboard management controller through a standardized interface;

[0023] The running status is determined based on the status code.

[0024] In one possible implementation, before converting the interface signals into I²C bus protocol signals, the method further includes:

[0025] Based on a preset permission table, the processor's permissions are verified, and the verification result is obtained.

[0026] If the verification result indicates that the processor has the necessary permissions, then perform the interface signal conversion operation.

[0027] If the verification result indicates that the processor does not have the necessary permissions, record the interface signal.

[0028] In one possible implementation, acquiring interface signals from the processor includes:

[0029] Obtain interface signals based on a low pin count bus interface;

[0030] Alternatively, based on the enhanced serial peripheral interface, obtain the interface signals.

[0031] Secondly, this application provides an I²C device control device, comprising:

[0032] The acquisition module is used to acquire interface signals from the processor;

[0033] The conversion module is used to convert interface signals into I²C bus protocol signals;

[0034] The determination module is used to determine the communication channel of the target I²C device;

[0035] The transmission module is used to transmit I²C bus protocol signals to the target I²C device based on the communication channel.

[0036] In one possible implementation, the determining module is specifically used for:

[0037] Determine the operating status of the baseboard management controller;

[0038] Adjust the channel selection logic of the I²C switch according to the operating status;

[0039] Based on the channel selection logic, determine the communication channel of the target I²C device.

[0040] In one possible implementation, the I²C device control device further includes a processing module, which is specifically used for:

[0041] When the operating status is normal, the control channel of the board management controller is enabled by the control signal of the I²C switch.

[0042] When the operating status is abnormal, the backup control channel is enabled by the control signal of the I²C switch.

[0043] In one possible implementation, the processing module is specifically used for:

[0044] Obtain the connection status of the target I²C device;

[0045] When the connection status is abnormal, close the channel of the I²C switch corresponding to the target I²C device;

[0046] When the connection status is normal, the channel of the I²C switch corresponding to the target I²C device is turned on to perform the operation of adjusting the channel selection logic.

[0047] In one possible implementation, the determining module is specifically used for:

[0048] Obtain the status code of the baseboard management controller through a standardized interface;

[0049] The running status is determined based on the status code.

[0050] In one possible implementation, the processing module is further configured to:

[0051] Based on a preset permission table, the processor's permissions are verified, and the verification result is obtained.

[0052] If the verification result indicates that the processor has the necessary permissions, then perform the interface signal conversion operation.

[0053] If the verification result indicates that the processor does not have the necessary permissions, record the interface signal.

[0054] In one possible implementation, the acquisition module is specifically used for:

[0055] Obtain interface signals based on a low pin count bus interface;

[0056] Alternatively, based on the enhanced serial peripheral interface, obtain the interface signals.

[0057] Thirdly, this application provides an I²C device control system, comprising: a programmable logic device and a processor, wherein,

[0058] Programmable logic devices, connected to a processor via a low-pin-count bus interface or an enhanced serial peripheral interface, are used to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0059] In one possible implementation, the programmable logic device is a complex programmable logic device (CPLD).

[0060] In one possible implementation, it further includes: an I²C switch, wherein,

[0061] The input of the I²C switch is connected to the I²C interface of the programmable logic device and is used to select the communication channel of the target I²C device.

[0062] Fourthly, this application provides an electronic device, including: a memory and a processor;

[0063] The memory stores instructions that the computer executes;

[0064] The processor executes computer execution instructions stored in memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0065] Fifthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the first aspect and / or various possible embodiments of the first aspect.

[0066] In a sixth aspect, this application provides a computer program product, including a computer program that, when executed, implements the first aspect and / or various possible implementations of the first aspect.

[0067] This application provides an I²C device control method and system, relating to the field of hardware design technology. The method, applied to a programmable logic device (PLD), includes: acquiring interface signals from a processor; converting the interface signals into I²C bus protocol signals; determining the communication channel of the target I²C device; and transmitting the I²C bus protocol signals to the target I²C device based on the communication channel. This application achieves independent control of the I²C device by the processor using a PLD, solving the system function interruption problem caused by a single point of failure in the BMC. Specifically, the PLD converts the processor's interface signals into I²C bus protocol signals, determines the communication channel of the target I²C device, and directly transmits control signals to the target I²C device through the communication channel. This method decouples the control paths of the processor and the BMC through hardware, avoiding the problem of the processor being unable to control the I²C device when the BMC fails, thus ensuring the continuous availability of system functions. Furthermore, the low cost of the PLD significantly reduces hardware costs and eliminates the need for high-cost FPGAs or long-distance PCIe links, reducing complex signal connections between multiple boards. In summary, this application improves the reliability, flexibility, and economy of the system through hardware redundancy design and low-cost expansion. Attached Figure Description

[0068] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0069] Figure 1 A flowchart illustrating the existing I²C device control method provided in this application. Figure 1 ;

[0070] Figure 2 A flowchart illustrating the I²C device control method provided in the embodiments of this application. Figure 1 ;

[0071] Figure 3 A schematic flowchart of an existing I²C device control method provided in this application embodiment. Figure 2 ;

[0072] Figure 4 A flowchart illustrating the I²C device control method provided in the embodiments of this application. Figure 2 ;

[0073] Figure 5 This is a schematic diagram of the structure of the I²C device control device provided in the embodiments of this application;

[0074] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0075] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0076] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0077] Figure 1 A flowchart illustrating the existing I²C device control method provided in this application. Figure 1 .like Figure 1 As shown, the BMC is used as the I²C master controller, and its integrated multi-channel I²C bus (such as I²C1-I²C14) directly connects to the I²C devices on each board. The CPU sends instructions to the BMC through an internal network (such as the IPMI protocol), and the BMC performs read and write operations.

[0078] The advantage of this method is that the BMC can directly manage all I²C devices, but the disadvantage is that the BMC is a single point of control: if the BMC fails, the CPU cannot directly intervene in the I²C devices, resulting in limited system functionality. Furthermore, the BMC has a limited number of I²C interfaces, making it difficult to support a large number of device expansions.

[0079] To address this issue, this application provides an I²C device control method, which involves: acquiring interface signals from a processor; converting the interface signals into I²C bus protocol signals; determining the communication channel of the target I²C device; and transmitting the I²C bus protocol signals to the target I²C device based on the communication channel.

[0080] This application applies to multi-board systems, such as servers, industrial control equipment, and communication base stations, in which the BMC and CPU are located on different boards, and the I²C devices are distributed across multiple boards.

[0081] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0082] Figure 2 A flowchart illustrating the I²C device control method provided in the embodiments of this application. Figure 1 ,like Figure 2 As shown, this method is applied to a programmable logic device and includes:

[0083] S201, Obtain interface signals from the processor.

[0084] Interface signals refer to the raw control signals output by the processor through a specific interface, which need to be converted by the protocol before being used for I²C communication. For example, the raw control signals output by the CPU through a specific interface need to be converted by the protocol before being used for I²C communication.

[0085] S202. Convert the interface signals into I²C bus protocol signals.

[0086] I²C bus protocol signals refer to clock line signals and data line signals that conform to the I²C communication protocol and are used for data interaction with I²C devices.

[0087] Optionally, the clock line signals and data line signals are generated by hard-coding the timing logic of the I²C protocol in the programmable logic device. The timing logic refers to the generation sequence of the start bit, address bit, data bit, and stop bit in the I²C protocol.

[0088] In other words, programmable logic devices implement timing control of the I²C protocol through hard-coded logic circuits. For example, the internal logic units of the programmable logic device generate clock line signals and sample data line signals on the falling edge of the clock line signals, thereby ensuring the compatibility of the I²C bus protocol.

[0089] This step reduces the processor's software protocol processing burden through hardware acceleration.

[0090] S203. Determine the communication channel of the target I²C device.

[0091] Determining the communication channel for the target I²C device means that, before initiating data interaction with a specific I²C device, the physical paths for the main serial data line and the SCL serial clock line used to connect to that I²C device need to be identified and prepared.

[0092] In some complex systems, there may be multiple independent I²C buses, or multiple logical I²C channels may be simulated through I²C multiplexers. Therefore, to communicate with the target I²C device, it is necessary to first identify and activate or explicitly specify the SDA and SCL lines to ensure that the master control device can accurately address and establish a reliable data transmission link with the target I²C device.

[0093] S204. Based on the communication channel, transmit the I²C bus protocol signal to the target I²C device.

[0094] S204 describes how the I²C bus protocol transmits signals to the target I²C device via two signal lines. The process begins with sending a start signal, followed by a byte containing the target device's 7-bit or 10-bit address and a read / write bit to select the target I²C device. The selected device acknowledges receipt with an acknowledge signal. Subsequently, depending on the read / write instruction, the register address can be selectively transmitted, followed by the data to be written, or the target I²C device can transmit the data to be read. Throughout the communication process, the serial clock line synchronizes the data transmission, ensuring the accuracy of information on the serial data line. Finally, a stop signal is sent to end the communication.

[0095] This application's embodiments utilize programmable logic devices (PLDs) to achieve independent processor control of I²C devices, resolving the system function interruption problem caused by a single point of failure in the BMC. Specifically, the PLD converts the processor's interface signals into I²C bus protocol signals, determines the communication channel for the target I²C device, and directly transmits control signals to the target I²C device through the communication channel. This method decouples the processor's control path from the BMC in hardware, avoiding the problem of the processor being unable to control the I²C device when the BMC fails, thus ensuring the continuous availability of system functions. Furthermore, the low cost of PLDs significantly reduces hardware costs and eliminates the need for high-cost FPGAs or long-distance PCIe links, reducing complex signal connections between multiple boards. In summary, this application improves system reliability, flexibility, and economy through hardware redundancy design and low-cost expansion.

[0096] Based on the above embodiments, determining the communication channel of the target I²C device includes: determining the operating state of the baseboard management controller; adjusting the channel selection logic of the I²C switch according to the operating state; and determining the communication channel of the target I²C device according to the channel selection logic.

[0097] In this embodiment, it can be understood that the determination of the communication channel of the target I²C device is based on the operating status of the baseboard management controller. Different operating statuses will result in different determined communication channels. There are various ways to determine the operating status of the baseboard management controller. For example, a status monitoring module can be integrated into the baseboard management controller. This module monitors the operating status of the baseboard management controller via a heartbeat signal or via an IPMI interface. Here, the heartbeat signal is a periodically sent signal used to detect whether the processor is operating normally, and the IPMI interface is a standardized interface used for server management, supporting remote monitoring and control.

[0098] Multi-mode operational status monitoring enhances the reliability of redundant control. For example, heartbeat signals are suitable for local detection, while the IPMI interface is suitable for remote monitoring; combining the two can cover a wider range of fault scenarios. In other words, the above method enhances the system's fault tolerance through multi-dimensional monitoring logic.

[0099] After determining the operating status of the baseboard management controller, the channel selection logic of the I²C switch is adjusted according to the operating status of the baseboard management controller. The channel selection logic refers to the control signal generation logic of the I²C switch, which is used to dynamically select the communication channel of the target I²C device. For example, a specific channel of the I²C switch is enabled by output enable (OE) signal.

[0100] This application embodiment dynamically adjusts the channel selection logic of the I²C switch by adjusting the operating state of the substrate management controller, thereby achieving redundant control between the substrate management controller and the programmable logic device.

[0101] In one example, the channel selection logic of the I²C switch is adjusted according to the operating state, including: when the operating state is normal, enabling the control channel of the board management controller through the control signal of the I²C switch; when the operating state is abnormal, enabling the backup control channel through the control signal of the I²C switch.

[0102] In this example, when the baseboard management controller (BMD) is operating normally, the control signal of the I²C switch (such as the OE signal) enables the BMD control channel, ensuring that the I²C bus protocol signal is directly transmitted to the target device through the BMD. When the BMD malfunctions, the control signal switches to a backup control channel (such as transmitting the I²C bus protocol signal to an I²C device controlled by a programmable logic device), ensuring continuous access to the I²C device. For example, after the CPLD detects that the BMD signal has not been lost through the interface, it generates an OE signal to enable the BMD control channel, thus activating the BMD control channel and transmitting the I²C bus protocol signal to the I²C device controlled by the BMD. It should be noted that the control signal refers to the electrical signal used to configure the I²C switch channel selection, such as the OE signal or address selection signal.

[0103] This application embodiment achieves seamless switching of I²C device access paths by enabling the baseboard management controller's control channel and backup control channel in stages. Specifically, when the baseboard management controller is operating normally, the baseboard management controller's control channel is used first to avoid redundant occupation of baseboard management controller resources; when the baseboard management controller fails, it automatically switches to the backup control channel to ensure the continuity of system functions. In summary, the staged control logic optimizes resource utilization and improves the system's fault tolerance.

[0104] Based on the above embodiments, before adjusting the channel selection logic of the I²C switch according to the operating state, the method further includes: obtaining the connection status of the target I²C device; when the connection status is abnormal, closing the channel of the I²C switch corresponding to the target I²C device; when the connection status is normal, opening the channel of the I²C switch corresponding to the target I²C device to perform the operation of adjusting the channel selection logic.

[0105] In this embodiment, it can be understood that the connection status of the target I²C device must be determined before adjusting the channel selection logic. There are various ways to determine the connection status of the target I²C device. For example, hot-plug detection logic can be integrated into the programmable logic device to monitor the connection status of the I²C device in real time and dynamically adjust the channel configuration through the OE signal of the I²C switch. The programmable logic device determines the device status by detecting voltage changes or device response signals on the I²C bus, and closes the corresponding I²C switch channel when the removal of the target I²C device is detected, i.e., disconnecting the I²C switch channel corresponding to the target I²C device to avoid invalid access. For example, when the removal of a temperature sensor is detected, the programmable logic device automatically disconnects the corresponding I²C switch channel to prevent bus conflicts; when the device is inserted, the programmable logic device re-enables the channel and initializes the device to execute subsequent channel selection logic operations.

[0106] The above method enables hot-swapping support for I²C devices through dynamic channel management, improving system flexibility and maintenance efficiency. Furthermore, the automatic shutdown of invalid channels reduces power waste and optimizes system resource utilization. Ultimately, this method simplifies the device replacement process through hot-swapping management, enhancing system maintainability.

[0107] Based on the above embodiments, the operating status of the baseboard management controller is determined in the following way: the status code of the baseboard management controller is obtained through a standardized interface; the operating status is determined based on the status code.

[0108] Based on the above embodiments, the operating status of the baseboard management controller is determined in the following way: First, the status code of the baseboard management controller is obtained through a standardized interface, where the standardized interface can be the IPMI interface, which is only an example here. This standardized interface is designed to ensure that baseboard management controllers from different manufacturers and of different models can expose their operating information in a unified manner, thereby simplifying integration and interoperability. The status code, as a concise data representation, can directly reflect the performance, health status, or potential faults of the baseboard management controller at a specific point in time.

[0109] Next, based on the acquired status codes, the specific operating state of the baseboard management controller is further determined. This typically involves comparing the original status codes with a predefined operating state parsing table or rule set. For example, a particular status code might represent "normal operation," while another status code might indicate "overheating warning," "hardware failure," or "communication error." Through this mapping relationship, abstract status codes can be transformed into understandable operating state descriptions, providing a basis for subsequent fault diagnosis, performance optimization, or alarm notifications.

[0110] Obtaining the status code of the baseboard management controller (BMD) through a standardized interface is a crucial step in diagnosing and monitoring the hardware operation of the BMD. The status code itself, as a data representation, is the basis for determining the BMD's operational status. In the above embodiment, after the BMD's status code is obtained, a comparison and parsing process is initiated. This process associates each status code with its corresponding operational status according to preset logic.

[0111] This sophisticated status code parsing capability enables server administrators to understand the health status of the hardware in a timely and accurate manner and take necessary measures.

[0112] Based on the above embodiments, in some examples, before converting the interface signal into a signal conforming to the I²C bus protocol, the method further includes: verifying the processor's permissions based on a preset permission table and obtaining a verification result; if the verification result indicates that the processor has the permissions, performing the interface signal conversion operation; if the verification result indicates that the processor does not have the permissions, recording the interface signal.

[0113] Because existing methods may result in processors accidentally or maliciously accessing sensitive I²C devices (such as firmware memory), there are security risks. To address this issue, embodiments of this application implement access control logic in a programmable logic device, verifying the processor's access requests through a preset permission table (such as a mapping between device addresses and processor permissions), and allowing only authorized operations.

[0114] Specifically, the programmable logic device stores the mapping relationship between I²C device addresses and processor permissions (such as read-only and write-protected) through a permission table. Upon receiving an I²C instruction from the processor, the programmable logic device verifies the I²C device address against the permission table to determine whether the processor's operation is permitted. For example, if the processor attempts to write to a read-only I²C device (such as firmware memory), the programmable logic device will reject the operation and log the rejection.

[0115] This application embodiment enhances system security through hardware-level access control, preventing data corruption or system malfunctions caused by unauthorized operations. Furthermore, unauthorized access records can be reported to the baseboard management controller via the IPMI interface, facilitating security auditing and troubleshooting. Ultimately, this application embodiment implements hierarchical access control through permission management, enhancing system security and auditability.

[0116] Based on the above embodiments, obtaining interface signals from the processor includes: obtaining interface signals based on a low pin count bus interface; or obtaining interface signals based on an enhanced serial peripheral interface.

[0117] In this embodiment, it can be understood that the processor outputs raw control signals through a specific interface, which includes, but is not limited to, a low pin count bus interface and an enhanced serial peripheral interface. A low pin count bus interface (LPC) refers to a communication interface design characterized by using a very small number of physical connection pins. In electronic systems, pins are the channels through which chips connect to external circuits; a higher number of pins typically means more wires, more board space, and higher costs. Therefore, using a low pin count interface helps reduce device size, system complexity, and costs.

[0118] The Enhanced Serial Peripheral Interface (ECSPI) is a communication interface that improves and extends the traditional Serial Peripheral Interface (SPI). SPI is a high-speed, full-duplex, synchronous communication bus widely used between microcontrollers and peripheral devices. "Enhanced" typically means that new features or improved performance have been added to the original SPI functionality.

[0119] Furthermore, embodiments of this application also provide an I²C device control system, including: a programmable logic device and a processor, wherein the programmable logic device is connected to the processor via a low pin count bus interface or an enhanced serial peripheral interface, and is used to execute the methods described in the above embodiments.

[0120] Figure 3 A schematic flowchart of an existing I²C device control method provided in this application embodiment. Figure 2 .like Figure 3 As shown, in multi-board device designs, the physical layout of the Field-Programmable Gate Array (FPGA) is typically far from the board containing the processor (e.g., CPU) (board 2), and the two are not integrated on the same circuit board, resulting in a longer direct communication link. To control the I²C device on board 3 under these circumstances, data is usually transmitted to the FPGA on another board for I²C expansion via the high-speed serial computer extension bus standard (PCI Express, PCIE). Subsequently, the control signal returns via the FPGA and finally reaches board 3 to select the target I²C device.

[0121] However, this communication path spanning multiple boards and the FPGA significantly increases link length. Especially between board 3 and other boards, multiple additional I²C signal lines are required to support this indirect I²C communication. This leads to exceptionally complex board-to-board connector designs, a dramatic increase in pin count, and increases the difficulty and cost of hardware design, as well as potential signal integrity issues.

[0122] To address this issue, in some embodiments of this application, the FPGA will be removed and a programmable logic device will be introduced, wherein the programmable logic device is a complex programmable logic device. The reason for this is that: compared to the FPGA, the cost of the complex programmable logic device is lower; in addition, in a multi-board system, the CPLD is generally close to the CPU, which can solve the problem of complex links and interfaces.

[0123] Furthermore, in some embodiments, the system described above further includes an I²C switch, wherein the input of the I²C switch is connected to the I²C interface of the programmable logic device for selecting the communication channel of the target I²C device.

[0124] Next, taking the processor as a CPU and the programmable logic device as a complex programmable logic device as an example, we will explain how to use the I²C device control method provided in the embodiments of this application. Figure 4 A flowchart illustrating the I²C device control method provided in the embodiments of this application. Figure 2 .like Figure 4 As shown, the method includes the following steps:

[0125] Instruction reception and protocol conversion: The CPU sends I²C control instructions to the CPLD through the LPC or ESPI interface, and the CPLD converts the instructions into I²C bus protocol signals;

[0126] Channel selection and signal transmission: The CPLD selects the target channel through the OE signal of the I²C switch and transmits the I²C bus signal to the output port of the selected channel to connect to the target I²C device.

[0127] Furthermore, when the BMC fails, the CPU can select the backup control channel by driving the I²C switch through the CPLD, and the CPLD can independently control the I²C device; when the BMC is normal, the CPU can select the control channel of the substrate management controller by driving the I²C switch through the CPLD, and the BMC can control the I²C device.

[0128] This application embodiment uses a CPLD to realize the CPU's control of I²C devices, which solves the single point of failure problem of the prior art, and at the same time significantly reduces hardware costs and wiring complexity.

[0129] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0130] Figure 5 This is a schematic diagram of the structure of the I²C device control device provided in the embodiments of this application, as shown below. Figure 5 As shown, the I²C device control device provided in this embodiment includes:

[0131] Acquisition module 501 is used to acquire interface signals from the processor;

[0132] Conversion module 502 is used to convert interface signals into I²C bus protocol signals;

[0133] Module 503 is used to determine the communication channel of the target I²C device;

[0134] The transmission module 504 is used to transmit I²C bus protocol signals to the target I²C device based on the communication channel.

[0135] In one possible implementation, the determining module 503 is specifically used for:

[0136] Determine the operating status of the baseboard management controller;

[0137] Adjust the channel selection logic of the I²C switch according to the operating status;

[0138] Based on the channel selection logic, determine the communication channel of the target I²C device.

[0139] In one possible implementation, the I²C device control device further includes a processing module (not shown), which is specifically used for:

[0140] When the operating status is normal, the control channel of the board management controller is enabled by the control signal of the I²C switch.

[0141] When the operating status is abnormal, the backup control channel is enabled by the control signal of the I²C switch.

[0142] In one possible implementation, the processing module is specifically used for:

[0143] Obtain the connection status of the target I²C device;

[0144] When the connection status is abnormal, close the channel of the I²C switch corresponding to the target I²C device;

[0145] When the connection status is normal, the channel of the I²C switch corresponding to the target I²C device is turned on to perform the operation of adjusting the channel selection logic.

[0146] In one possible implementation, the determining module 503 is specifically used for:

[0147] Obtain the status code of the baseboard management controller through a standardized interface;

[0148] The running status is determined based on the status code.

[0149] In one possible implementation, the processing module is further configured to:

[0150] Based on a preset permission table, the processor's permissions are verified, and the verification result is obtained.

[0151] If the verification result indicates that the processor has the necessary permissions, then perform the interface signal conversion operation.

[0152] If the verification result indicates that the processor does not have the necessary permissions, record the interface signal.

[0153] In one possible implementation, the acquisition module 501 is specifically used for:

[0154] Obtain interface signals based on a low pin count bus interface;

[0155] Alternatively, based on the enhanced serial peripheral interface, obtain the interface signals.

[0156] The I²C device control device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0157] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, a processing module can be a separate processing element, or it can be integrated into an integrated circuit within the above device. Alternatively, it can be stored as program code in the device's memory, and its functions can be called and executed by a processing element. The implementation of other modules is similar. Moreover, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. During implementation, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0158] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). As another example, when a module is implemented by calling program code through a processing element, that processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together to implement a System-On-a-Chip (SOC).

[0159] Figure 6This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 6 As shown, the electronic device 600 provided in this application embodiment may include: a processor 601, and a memory 602 communicatively connected to the processor, wherein:

[0160] The memory stores instructions that the computer executes;

[0161] The processor executes computer execution instructions stored in memory to implement the method described in the foregoing method embodiments.

[0162] It should be understood that processor 601 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor. Memory 602 may include high-speed random access memory (RAM), and may also include non-volatile memory (NVM), such as at least one disk storage device, or a USB flash drive, external hard drive, read-only memory, disk, or optical disc, etc.

[0163] Optionally, the electronic device 600 may also include a communication interface 603. In specific implementations, if the communication interface 603, memory 602, and processor 601 are implemented independently, they can be interconnected via a bus to complete communication. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.

[0164] Optionally, in a specific implementation, if the communication interface 603, memory 602, and processor 601 are integrated on a single integrated circuit, then the communication interface 603, memory 602, and processor 601 can communicate through an internal interface.

[0165] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the methods described in any of the foregoing embodiments.

[0166] It is understood that the computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0167] An exemplary computer-readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the computer-readable storage medium. Of course, the computer-readable storage medium can also be a component of the processor. The processor and the computer-readable storage medium can reside in an ASIC. Alternatively, the processor and the computer-readable storage medium can exist as discrete components in an electronic device.

[0168] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a computer-readable storage medium, include several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application.

[0169] This application also provides a computer program product, including a computer program that, when executed, implements the method described in any of the foregoing embodiments.

[0170] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0171] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0172] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as these combinations of technical features do not contradict each other, they should be considered within the scope of this specification.

[0173] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0174] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for controlling an I²C device, characterized in that, Applied to programmable logic devices, including: Obtain interface signals from the processor; The interface signals are converted into I²C bus protocol signals; wherein, the I²C bus protocol signals refer to clock line signals and data line signals that conform to the I²C communication protocol, used for data interaction with I²C devices; Determine the operating status of the baseboard management controller; Based on the operating status, the channel selection logic of the I²C switch is adjusted; wherein, the channel selection logic refers to the control signal generation logic of the I²C switch, which is used to dynamically select the communication channel of the target I²C device; when the operating status is normal, the control signal of the I²C switch enables the board management controller to control the channel. When the operating state is abnormal, the backup control channel is enabled by the control signal of the I²C switch; the enabled backup control channel means that the CPU controls the I²C device through the programmable logic device. The communication channel of the target I²C device is determined based on the channel selection logic. Based on the communication channel, the I²C bus protocol signal is transmitted to the target I²C device.

2. The method according to claim 1, characterized in that, Before adjusting the channel selection logic of the I²C switch according to the operating state, the method further includes: Obtain the connection status of the target I²C device; When the connection status is abnormal, the channel of the I²C switch corresponding to the target I²C device is closed; When the connection status is normal, the channel of the I²C switch corresponding to the target I²C device is opened to perform the operation of adjusting the channel selection logic.

3. The method according to claim 1, characterized in that, The operating status of the baseboard management controller is determined in the following ways: The status code of the baseboard management controller is obtained through a standardized interface; The operating status is determined based on the status code.

4. The method according to any one of claims 1 to 3, characterized in that, Before converting the interface signal into an I²C bus protocol signal, the method further includes: Based on a preset permission table, the processor's permissions are verified to obtain the verification result; If the verification result indicates that the processor has the necessary permissions, the interface signal conversion operation is executed. If the verification result indicates that the processor does not have the necessary permissions, the interface signal is recorded.

5. The method according to any one of claims 1 to 3, characterized in that, The acquisition of interface signals from the processor includes: The interface signal is acquired based on a low pin count bus interface; Alternatively, the interface signal can be obtained based on the enhanced serial peripheral interface.

6. An I²C device control system, characterized in that, include: Programmable logic devices and processors, among which, The programmable logic device is connected to the processor via a low pin count bus interface or an enhanced serial peripheral interface, and is used to execute the method as described in any one of claims 1 to 5.

7. The system according to claim 6, characterized in that, The programmable logic device is a complex programmable logic device (CPLD).

8. The system according to claim 6, characterized in that, Also includes: An I²C switch, wherein the input terminal of the I²C switch is connected to the I²C interface of the programmable logic device, and is used to select the communication channel of the target I²C device.

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