Geometric processing pipeline, graphics processing core, processor and vertex processing method

Abstract

The invention discloses a geometric processing pipeline, a graphic processing core, a processor and a vertex processing method, and belongs to the field of chips. The geometric processing assembly line comprises a geometric task assembly unit, a shader and a primitive processing line unit, the geometric task assembly unit is used for splitting the vertex flow into a first vertex coloring task by adopting a first splitting strategy under the condition that the primitive topology of the input vertex flow is the banded topology; under the condition that the primitive topology of the input vertex stream is not the banded topology, a second splitting strategy is adopted to split the vertex stream into a second vertex coloring task, and the calculated amount of the first splitting strategy is smaller than that of the second splitting strategy; and the shader is used for processing the first vertex coloring task and / or the second vertex coloring task. According to the method and the device, the rapid task assembly algorithm is adopted for the vertex flow of the strip topology, so that the performance and the efficiency of graphic processing are enhanced.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a geometry processing pipeline, a graphics processing core, a processor, and a vertex processing method. Background Technology

[0002] Primitive assembly and vertex shading are two distinct stages in the GPU (Graphics Processing Unit) graphics rendering process. Primitive assembly transforms vertices into complete geometric primitives, while vertex shading performs shading calculations on the vertices. Before vertex shading, the GPU performs a hit test on each vertex to determine whether each vertex needs to be processed by the vertex processor or whether the results of previous processing should be used.

[0003] In related technologies, hit testing requires using a complete primitive as the basic unit and simultaneously performing hit testing on all vertices in this primitive to ensure that the vertex shading results of the assembled primitive can be simultaneously output by the GPU when assembling primitives.

[0004] This approach is not conducive to the separation of the various stages in the rendering process, and can easily lead to dependencies between different stages, such as primitive assembly, hit testing and vertex shading. In some scenarios, there are many redundant operations and low processing efficiency, which can become the performance bottleneck of the graphics processor in the geometry processing stage. Summary of the Invention

[0005] This application provides a geometry processing pipeline, a graphics processing core, a processor, and a vertex processing method, the technical solution of which is as follows: According to one aspect of this application, a geometry processing pipeline is provided, the geometry processing pipeline comprising: a geometry task assembly unit and a shader; The geometric task assembly unit is used to split the vertex flow into a first vertex coloring task by adopting a first splitting strategy when the primitive topology of the input vertex flow is a strip topology. If the primitive topology of the input vertex stream is not the strip topology, the vertex stream is split into a second vertex coloring task using a second splitting strategy. The computational cost of the first splitting strategy is less than that of the second splitting strategy. The shader is used to process the first vertex shading task and / or the second vertex shading task.

[0006] According to one aspect of this application, a graphics processing core is provided, the graphics processing core comprising: a geometry processing pipeline, the geometry processing pipeline being the aforementioned geometry processing pipeline.

[0007] According to one aspect of this application, a graphics processor is provided, the graphics processor comprising: N graphics processing cores, a system configuration unit, a system bus and a storage unit, where N is a positive integer; The N graphics processing cores are respectively connected to the system bus, and the system bus is connected to the storage unit; The system configuration unit is connected to each of the N graphics processing cores; Each graphics processing core includes the geometry processing pipeline.

[0008] According to one aspect of this application, a vertex processing method is provided, the method being executed by the aforementioned geometry processing pipeline, the geometry processing pipeline comprising: a geometry task assembly unit and a shader; The method includes: When the primitive topology of the input vertex stream is a strip topology, the vertex stream is split into a first vertex coloring task using a first splitting strategy. If the primitive topology of the input vertex stream is not the strip topology, the vertex stream is split into a second vertex coloring task using a second splitting strategy. The computational cost of the first splitting strategy is less than that of the second splitting strategy. Process the first vertex shading task and / or the second vertex shading task.

[0009] The beneficial effects of the technical solution provided in this application include at least the following: The geometry processing pipeline provided in this application implements rapid task assembly for strip topologies. Specifically, when the input primitive topology belongs to a strip topology, a first splitting strategy is used to generate the shading task; when the input primitive topology does not belong to a strip topology, a second splitting strategy is used to generate the shading task. The computational cost of the first splitting strategy is less than that of the second splitting strategy. Through the rapid task assembly proposed in this application, the vertex flow of a strip topology can use a simpler shading task generation method, thereby improving the processing efficiency of vertex flows for strip topologies and solving the low performance problem of the graphics processor's geometry processing stage when handling strip topologies. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1A schematic diagram of a geometric pipeline provided in an exemplary embodiment of this application is shown; Figure 2 This illustration shows a schematic diagram of vertex processing provided in an exemplary embodiment of this application; Figure 3 A waveform startup diagram with 16 threads is shown in an exemplary embodiment of this application; Figure 4 This illustration shows a waveform startup diagram of a triangular strip with 16 threads, provided in an exemplary embodiment of this application. Figure 5 This illustration shows a schematic diagram of the processing flow of a geometry processing pipeline provided in an exemplary embodiment of this application; Figure 6 This illustration shows a schematic diagram of the vertex partitioning process for a strip topology of type line strip provided in an exemplary embodiment of this application; Figure 7 This illustration shows a schematic diagram of the vertex division process for a strip topology of triangular strip provided in an exemplary embodiment of this application; Figure 8 This illustration shows a schematic diagram of the vertex partitioning process for a strip topology type of line strip with adjacent points provided in an exemplary embodiment of this application; Figure 9 This illustration shows a schematic diagram of the vertex division process for a triangular strip with adjacent points, which is a strip topology type provided in an exemplary embodiment of this application; Figure 10 This illustration shows a schematic diagram of the vertex partitioning process for a strip topology of triangular fan provided in an exemplary embodiment of this application; Figure 11 A schematic flowchart illustrating the processing procedure of a geometry processing pipeline provided in an exemplary embodiment of this application is shown. Figure 12 A schematic diagram of an image processing core provided in an exemplary embodiment of this application is shown; Figure 13 A schematic diagram of an image processor provided in an exemplary embodiment of this application is shown; Figure 14 A flowchart of a vertex processing method provided in an exemplary embodiment of this application is shown. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0013] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0014] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0015] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the settings and operation information involved in this application were obtained with full authorization.

[0016] It should be understood that although the terms first, second, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, a first parameter may also be referred to as a second parameter without departing from the scope of this disclosure, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0017] First, let me introduce the relevant terms used in this application: The rendering pipeline of a graphics processing unit (GPU) is a key concept in computer graphics. It is a stage in the GPU that is responsible for processing and transforming graphics data for rendering.

[0018] The primary task of the rendering pipeline is to convert input geometric primitives (such as points, lines, triangles, etc.) into pixels visible on the screen. It consists of multiple stages, each performing specific geometric calculations and transformations.

[0019] The following are typical geometric pipeline stages: (1) Vertex Input: This stage passes vertex data from the application to the geometry pipeline. Vertex data includes attributes such as position, color, and normal.

[0020] (2) Vertex Shader: In this stage, the vertex shader performs calculations on each input vertex and can perform various transformations and operations, such as model transformation, view transformation, projection transformation, etc. It can also calculate the vertex's lighting, texture coordinates, etc.

[0021] (3) Primitive Assembly: In this stage, the primitive assembler converts vertices into complete geometric primitives, such as points, line segments, triangles, etc.

[0022] (4) Geometry Shader: In the geometry shading stage, the geometry shader can manipulate and generate geometric primitives. It can create new primitives and change their shape, size, position, etc.

[0023] (5) Clipping: In this stage, the clipper compares the primitives with the screen boundary and discards the parts that are outside the view volume.

[0024] (6) Screen Mapping: This stage maps the clipped primitives to pixel coordinates in screen space.

[0025] (7) Rasterization: The rasterization stage converts geometric primitives into pixels on the screen and determines the position, color and other attributes of each pixel.

[0026] (8) Fragment Shader: In the fragment shading stage, the fragment shader performs calculations on each rasterized pixel. It can perform pixel-level lighting calculations, texture sampling, depth testing, and other operations.

[0027] (9) Pixel Operations: The last stage is pixel operations, which perform the final pixel processing, such as blending, dithering, anti-aliasing, etc.

[0028] The goal of the rendering pipeline is to process geometry and generate the final image in an efficient manner. Through parallel processing and specialized hardware support, GPUs are able to perform these calculations quickly, enabling real-time graphics rendering.

[0029] The rendering pipeline can generally be divided into two parts: the geometry processing section (i.e., the geometry pipeline) and the pixel processing section (also known as the fragment pipeline). The geometry processing section includes vertex input, vertex shading, primitive assembly, set shading, clipping, and screen mapping. The geometry pipeline mainly focuses on the processing and transformation of geometric data. It receives input geometric primitives (such as points, lines, triangles, etc.) and converts them into pixels on the screen after a series of stages. The geometry pipeline is responsible for performing geometric calculations such as model transformation, view transformation, and projection transformation, as well as generating new geometric primitives and changing the shape, size, and position of primitives.

[0030] The pixel processing section generally includes rasterization, fragment shading, and pixel manipulation. The fragment pipeline focuses on pixel-level processing. It receives the pixels on the screen generated during the rasterization stage and processes each pixel through a series of stages. The main stages include fragment shading, depth testing, stencil testing, and alpha blending. The fragment pipeline is responsible for performing pixel-level lighting calculations, texture sampling, depth testing, and other operations to determine the final color and attributes of each pixel.

[0031] These two pipelines are successive stages in the rendering pipeline; they are interdependent and work closely together to ultimately generate a visualized image. The geometry pipeline transforms geometric data into pixel data, while the fragment pipeline performs the final processing and computation on each pixel. Through parallel processing and specialized hardware support, the GPU is able to efficiently execute these pipeline stages to achieve real-time graphics rendering.

[0032] Vertex Cache: A cache used in a graphics processing unit (GPU) to store processed vertex data. In GPU geometry processing, vertex caches are generally used to reduce the number of vertices the GPU needs to process. In graphics rendering, vertices are the basic building blocks of a 3D model, each containing information such as position, normals, and texture coordinates. During rendering, the vertices of the model need to be used multiple times, and the vertex cache is used to temporarily store this vertex data.

[0033] The purpose of vertex caching is to reduce redundant calculations of vertex data during rendering. Once a vertex has been processed, its result is stored in the vertex cache. The next time the vertex is needed, it can be read directly from the cache without recalculation. This improves rendering efficiency, especially when processing large 3D models, significantly reducing the computational load and enhancing rendering performance.

[0034] Vertex buffers are typically implemented internally by the GPU. After a vertex is input and before vertex shading begins, the GPU performs a hit-test on the input vertex. If the input vertex matches a vertex already in the buffer, the GPU does not need to start a vertex shading process for this new input vertex; instead, it uses the processing results of previously existing vertices. If the input vertex does not match any vertex in the buffer, the GPU needs to start a vertex shading process for this new input vertex, and simultaneously inserts this vertex into the vertex buffer for subsequent vertex hit testing. Vertex hit testing is generally not performed on a single vertex, but rather on a complete primitive as the basic unit. All vertices in this primitive are simultaneously hit-tested to ensure that the vertex shading results of the assembled primitive can be output by the GPU simultaneously.

[0035] Wave / Warp: A group of consecutive threads in the shader processing. In GPU programming, "wave" / "warp" is a common concept in GPU architecture. This application uses wave as an example. A wave represents a group of consecutive threads in the shader processing that can execute the same instructions together. A wave usually contains a certain number of threads, but this number can vary depending on the GPU architecture. Different GPU architectures can use the SIMD (Single Instruction Multiple Data) execution model, where threads in one wave execute the same instructions, but the data they operate on may be different. Alternatively, they can use the SIMT (Single Instruction Multiple Threads) execution model. Waves are crucial for optimizing GPU program performance; maximizing the parallel execution capabilities of warps can improve program efficiency.

[0036] SIMD (Single Instruction Multiple Data) / SIMT (Single Instruction Multiple Threads): SIMD and SIMT in shaders are core architectures for achieving parallel computing, both improving efficiency by controlling multiple execution units with a single instruction. SIMD's core is that a single instruction simultaneously manipulates multiple data units. Its hardware includes multiple parallel data channels, sharing an instruction decoder and control unit, suitable for batch data processing such as vertex transformations and pixel calculations. SIMT, on the other hand, is a threaded optimization architecture based on SIMD, grouping multiple threads (such as thread bundles or wavefronts). Threads within a group share the instruction stream but have independent program counters, register files, and execution states, supporting thread-level branching and synchronization. During branching, masked execution ensures instruction stream consistency. The two are closely related at the underlying level. SIMT is essentially a threaded wrapper around SIMD. In practical applications, modern GPU shaders mostly adopt the SIMT architecture, retaining the instruction execution efficiency of SIMD while adapting to complex branching logic through threaded design, balancing parallel performance and programming flexibility.

[0037] Input Assemble: The entry unit of the geometry processing pipeline, responsible for receiving drawing commands issued by the user through the driver, and splitting or forwarding the vertex stream in the command according to the number of downstream geometry processing sub-pipelines.

[0038] Geometry task pack: Receives the vertex stream or vertex stream fragment sent by the input parsing unit, selects the corresponding task splitting method according to the primitive topology type, and assembles the vertex shading task and other possible shading tasks (including but not limited to geometry shading, shell shading and domain shading).

[0039] Vertex cache: Used to store processed vertex data. In non-strip topology processing, a hit test is used to determine whether a vertex has been cached in order to avoid duplicate processing.

[0040] Figure 1 A schematic diagram of a geometry processing pipeline provided in an exemplary embodiment of this application is shown. The geometry processing pipeline 100 includes a geometry task assembly unit 120, a shader 130, and a primitive processing unit 140; at the input end of the geometry processing pipeline 100, an input parsing unit 110 is also included.

[0041] The input parsing unit 110 is used to receive drawing instructions issued by the user through the driver, which carry a vertex stream.

[0042] In some embodiments, the input parsing unit 110 serves as an input interface unit for a geometry pipeline, used to receive and initially process externally sent drawing data. Specifically, the input parsing unit is used to receive drawing instructions sent by the user through the driver, which carry a vertex stream that needs to be processed.

[0043] Optionally, if there are multiple geometry processing pipelines 100, the input parsing unit 110 splits the vertex flow into one or more vertex flow segments according to the number of geometry processing pipelines to achieve load balancing and improve overall processing efficiency.

[0044] In some embodiments, a vertex stream can be a sequence of vertex data that defines attributes such as position, normals, and texture coordinates of the geometry to be rendered (e.g., primitives). Primitive topology can be a set of rules used to define how vertices in the vertex stream are connected to form basic geometry and / or primitives. Common primitive topologies include one or more of the following: point lists, line lists, line strips, triangle lists, and triangle strips.

[0045] Among them, strip topology is a special type of primitive topology, characterized by adjacent primitives sharing vertices.

[0046] For example, in the triangle strip, the nth triangle shares two vertices with the (n+1)th triangle. A shader is a program that runs on a graphics processor and processes graphics data.

[0047] Optionally, the shader in this embodiment can be a vertex shader, which performs a series of transformations on each input vertex and outputs the transformed vertex data.

[0048] Alternatively, if there is only one geometry processing pipeline, then the input parsing unit 110 does not need to split the specified vertex stream, but can directly send the vertex stream to the single geometry processing pipeline 100, which simplifies the data flow process.

[0049] Optionally, the geometry task assembly unit 120, as the scheduling unit of the geometry processing pipeline, is responsible for topology identification, task splitting and assembly of the vertex stream. It is used to receive vertex stream fragments sent from the input parsing unit 110, process these vertex stream fragments, and the processing includes: first identifying the primitive topology type of the vertex stream, then selecting the corresponding splitting strategy according to the topology type, splitting the vertex stream into shading tasks that can be executed by the shader, assembling the vertex shading tasks, as well as other possible shading tasks, and sending the assembled vertex shading tasks to the shader 130 to execute the corresponding shader program.

[0050] In some embodiments, the shader 130 serves as the core computing unit of the primitive processor, executing program instructions corresponding to the shading task, performing various graphics calculations on the vertex data, and outputting the processed vertex data for use in subsequent stages.

[0051] In some embodiments, other possible shading tasks include, but are not limited to, at least one of geometry shading, shell shading, and domain shading.

[0052] The geometry task assembly unit 120 is used to split the vertex flow into a first vertex coloring task by employing a first splitting strategy when the primitive topology of the input vertex flow is a strip topology.

[0053] Primitive topology defines the connection rules between vertices in a vertex flow, instructing the GPU how to combine discrete vertices into basic geometric shapes. These basic geometric shapes, or primitives, include at least one of points, lines, and triangles. Common primitive topologies include one or more of the following: a list of points, where each vertex is a separate point primitive; a list of lines, where every two vertices form an independent line segment; a line band, where adjacent vertices are connected sequentially to form continuous line segments, with each subsequent line segment sharing a vertex; a list of triangles, where every three vertices form an independent triangle; and a triangle band, where adjacent triangles share two vertices.

[0054] Strip topology is a special type of primitive topology with vertex reuse characteristics. Its features include one or more of the following: adjacent primitives share some vertices, eliminating the need to repeatedly store or process shared vertex data, thereby reducing data volume and computational load. Common primitive topologies include one or more of the following: triangular strips, line strips, line strips with adjacent vertices, triangular strips with adjacent vertices, and triangular fans.

[0055] The geometry task assembly unit 120 is used to split the vertex flow into a second vertex coloring task using a second splitting strategy when the primitive topology of the input vertex flow is not a strip topology. The computational cost of the first splitting strategy is less than that of the second splitting strategy.

[0056] Optionally, the efficiency of the first splitting strategy is higher than that of the second splitting strategy, and / or the computational cost of the first splitting strategy is less than that of the second splitting strategy, and / or the number of sub-processes of the first splitting strategy is less than that of the second splitting strategy. For example, compared with the second splitting strategy, the first splitting strategy does not require at least one of the primitive assembly process and the vertex cache hit process.

[0057] In some embodiments, the first splitting strategy refers to a task splitting strategy applicable to strip topologies. Its design leverages the vertex reuse rules of strip topologies to simplify the splitting logic and reduce computational overhead. Since adjacent primitives in a strip topology share vertices, there is no need to perform complex operations such as primitive assembly and vertex cache hit testing; task assembly can be completed simply by dividing intervals according to fixed rules.

[0058] Optionally, the first splitting strategy includes: dividing the vertex flow into multiple vertex intervals corresponding to the type of the strip topology according to the vertex interval partitioning rules, and splitting the vertices in the multiple vertex intervals into a first vertex coloring task.

[0059] In some embodiments, computational complexity is used to characterize the computational complexity of the geometry task assembly unit in processes such as splitting vertex flows and organizing tasks, including but not limited to the number and scale of operations such as comparisons, judgments, address calculations, and memory accesses that need to be performed. Lower computational complexity means lower processing overhead and potentially lower pipeline startup latency.

[0060] Because strip topology has a regular vertex reuse pattern, the first splitting strategy generally refers to various strategies that can utilize the aforementioned patterns of strip topology. That is, the first splitting strategy is a splitting strategy applicable to strip topology.

[0061] In some embodiments, the vertex flow can be divided into a set of non-overlapping, continuous vertex intervals according to the indexing rules of the strip topology, with each interval corresponding to an independent vertex shading task.

[0062] The second splitting strategy is applicable to non-strip topologies. For non-strip topologies, since there is no fixed reuse pattern between vertices, and each primitive's vertices are relatively independent, primitive splitting and vertex cache hit testing must be performed first, followed by the assembly task based on the deduplicated vertices. Therefore, the second splitting strategy is a more general but relatively complex method.

[0063] In some embodiments, primitive assembly can be performed based on an index buffer, identifying the vertices referenced by each primitive, and then a shading task can be created based on the set of vertex indices.

[0064] A vertex interval refers to a range of vertex indices divided from a continuous vertex stream according to specific rules. This range serves as an independent processing unit, corresponding to a vertex shading task. Each vertex interval contains multiple consecutive vertices, and the vertices within the interval are processed synchronously and in parallel by the shader. For example, if the vertex stream index is 0 to 100, the divided vertex intervals may include one or more of the following: [0, 7], [6, 13], [12, 19], and each interval corresponds to a first vertex shading task.

[0065] The vertex interval partitioning rules include: the vertex index range of the kth vertex interval among multiple vertex intervals is [S*k, S*k+W), where k is a non-negative integer, W is the number of vertices processed in parallel in a single operation or an integer multiple of the number of vertices processed in parallel in a single operation, and S is the step size determined according to the type of the strip topology, and S is a positive integer less than W.

[0066] Optionally, the vertex index range is used to define the boundary of the vertex interval, represented in the form of a start index and an end index interval, i.e., [S*k, S*k+W), where: • The starting index is S*k: representing the index position of the first vertex in the vertex flow of the k-th interval; • The ending index is S*k+W: This represents the index position of the next vertex after the end vertex of the k-th interval. It should be noted that the vertex corresponding to this index does not belong to the current interval. In some embodiments, when k=0, S=1, W=8, the vertex index range is [0, 8), corresponding to 8 vertices with indices 0 to 7; when k=1, the index range is [1, 9), corresponding to 8 vertices with indices 1 to 8.

[0067] Optionally, the step size S is used to define the offset of the starting index of the next interval relative to the starting index of the previous interval when dividing vertex intervals. Its value is determined by the specific type of strip topology and directly reflects the vertex reuse span of that type of strip topology. The main function of the step size is to control the degree of overlap between adjacent vertex intervals, that is, the number of shared vertices, to ensure that shared vertices can be correctly identified in subsequent primitive processing.

[0068] Optionally, the number of points processed in parallel in a single run, W, refers to the total number of vertices that the shader can process synchronously in parallel at one time. This value is determined by the shader's hardware architecture design and is usually an integer power of 2. Since the shader uses a single instruction multiple data or single instruction multiple thread architecture, multiple threads can be started in one run, and each thread processes one vertex. Therefore, W is also equal to the number of threads in a single run of the shader or an integer multiple thereof.

[0069] Optionally, S equals W minus C. Here, the length of the vertex interval is W, and adjacent intervals need to share C vertices. Therefore, the starting index of the next interval needs to be shifted forward by (WC) positions to achieve the overlap of C vertices.

[0070] In some embodiments, W=8, that is, 8 vertices are processed at a time, C=2, that is, the strip topology type is a triangle strip, then S=8-2=6, the index range of adjacent intervals is [0, 8), [6, 14), [12, 20), and the overlapping part is the two vertices with indices 6 and 7, which is consistent with the vertex reuse rule of the triangle strip.

[0071] Where C is the number of shared vertices determined according to the type of strip topology, and adjacent vertex intervals in multiple vertex intervals share C consecutive vertices.

[0072] Optionally, the shared vertex number C refers to the number of overlapping vertices between two adjacent vertex intervals. This value is determined by the type of strip topology and directly corresponds to the vertex reuse rules of strip topology. Since adjacent primitives in strip topology share C vertices, adjacent vertex intervals must also maintain an overlap of C vertices to ensure that the colored data can be correctly pieced together into a complete primitive.

[0073] In some embodiments, adjacent primitives of a triangular band share two vertices (C=2). Therefore, adjacent vertex intervals need to share two vertices to ensure that continuous triangular structures can be identified during subsequent primitive processing.

[0074] The types of strip topology include one or more of the following: triangular strip, line strip, line strip with adjacent points, and triangular strip with adjacent points.

[0075] When the type of the zonal topology is triangular zonal, C is 2.

[0076] When the type of the strip topology is line strip, C is 1.

[0077] In the case of a strip topology of line strip with adjacent nodes, C is 3.

[0078] In the case of a strip topology of triangular strip with adjacent points, C is 4.

[0079] Alternatively, the type of strip topology also includes triangular fans.

[0080] In the case of a strip topology of type linear strip with adjacencies, the vertex index range is {0, [S*k+1, S*k+W)}, where k is a non-negative integer; and S is the vertex index of W. 2. Adjacent vertex intervals in multiple vertex intervals share two consecutive non-center vertices, with the center vertex being the vertex with index 0.

[0081] For example, in a strip topology with adjacent points, each vertex is associated with at least one vertex of a non-adjacent line segment as an adjacent point, based on the vertex connection of the strip.

[0082] Alternatively, in the case where the strip topology is a triangular strip with adjacent vertices, adjacent vertex intervals share 7 consecutive vertices.

[0083] For example, in a strip topology with adjacent triangles, each vertex is associated with at least one vertex of a non-adjacent triangle as an adjacent vertex.

[0084] Optionally, in the case of a strip topology of the triangular fan strip, adjacent vertex intervals share two consecutive vertices.

[0085] For example, in a triangular sector of a strip topology, all triangles share the same central vertex. The nth triangle is composed of the central vertex, the (n-1)th non-central vertex, and the nth non-central vertex, where n is a positive integer greater than 1.

[0086] Where W is the number of vertices processed in a single parallel operation by the shader component or an integer multiple thereof, and k is a non-negative integer.

[0087] Optionally, the second splitting strategy includes: performing primitive splitting operations and vertex cache hit tests on vertices in the vertex flow that do not belong to the strip topology, and assembling a second vertex shading task based on the vertices already cached in the vertex cache.

[0088] Optionally, the primitive splitting operation is the operation of splitting a non-strip topologically associated vertex flow into independent basic primitives that can be directly drawn by the GPU; the vertex cache hit test is a test to check whether a vertex already exists in the vertex cache to avoid duplicate processing.

[0089] Optionally, a vertex cache hit means that the vertex index of the vertex is already stored in the vertex index cache; a vertex cache miss means that the vertex index of the vertex does not exist in the vertex index cache.

[0090] Optionally, shader 130 is used to handle the first vertex shading task and / or the second vertex shading task. Shader 130 generally adopts a SIMD and / or SIMT structure and can run multiple threads at once.

[0091] Alternatively, a single shader running under different hardware architectures or technical contexts may be called a single wave (commonly used in AMD architectures), warp (commonly used in NVIDIA architectures), or wavefront. All three essentially refer to the core thread group unit for parallel execution of shaders.

[0092] In some embodiments, the number of threads within a wave in shader 130 is determined by the image processing core design, with each thread corresponding to the computational task of one vertex, and multiple threads synchronously executing the same shader program instructions.

[0093] Optionally, the primitive processing unit 140 is used to receive additional information about vertices in the first vertex shading task, perform subsequent processing operations at the primitive level, and ensure that the rendering result meets the graphics requirements.

[0094] The additional information refers to primitive-related information required by the primitive processing unit when performing primitive processing. For example, the additional information of a vertex includes one or more of the following: the primitive ID of the primitive to which the vertex belongs, the triangle orientation of the triangle to which the vertex belongs, the drawing instance ID, and the vertex adjacency relationship.

[0095] Optionally, additional information refers to auxiliary information related to vertices that is used by primitive processing units to perform subsequent operations. This information cannot be directly obtained from the basic attributes of vertices and needs to be calculated and generated synchronously during vertex shading.

[0096] Here, the primitive ID is a unique identifier for each primitive, used to distinguish different basic geometric shapes. Triangle orientation refers to the direction of the triangle's normal in 3D space, determined by the order of the vertices, and is used for subsequent face / back face culling operations. Drawing instance ID is a unique identifier for each instance when performing multi-instance drawing (such as batch drawing multiple identical objects), used to associate the vertex data corresponding to the instance; vertex adjacency refers to the association between the current vertex and other non-adjacent vertices, used for primitive topology verification.

[0097] Optionally, primitive processing refers to performing primitive-related processing on the first primitive. Primitive processing includes, but is not limited to, at least one of: rasterization; primitive shading; and surface subdivision. Surface subdivision is a method for further subdividing a primitive to obtain a smooth surface.

[0098] In summary, the geometry processing pipeline provided in this application enables rapid task assembly for strip topologies. Specifically, when the input primitive topology belongs to a strip topology, a first splitting strategy is used to generate the shading task; when the input primitive topology does not belong to a strip topology, a second splitting strategy is used to generate the shading task. Through the rapid task assembly proposed in this application, the vertex flow of a strip topology can use a simpler shading task generation method, thereby improving the processing efficiency of vertex flows for strip topologies and solving the low performance problem of the graphics processor's geometry processing stage when processing strip topologies.

[0099] The following shows the overall structure and workflow of the geometry processing pipeline, such as... Figure 2 As shown.

[0100] Optionally, the overall structure of this application includes an input parsing unit 110 and one or more geometry processing pipelines, including geometry pipeline 1 and geometry pipeline 2. Each geometry pipeline includes a task assembly unit, a shader component, and a primitive processing unit. Geometry pipeline 1 includes a geometry task assembly unit 120, a shader 130, and a primitive processing unit 140, while geometry pipeline 2 includes a geometry task assembly unit 220, a shader 230, and a primitive processing unit 240. The specific workflow is as follows: Optionally, the input parsing unit 110 is used to receive drawing instructions issued by the user through the driver, which contain the vertex stream to be processed.

[0101] In some embodiments, if there are multiple geometry processing pipelines downstream, the input parsing unit splits the vertex stream into vertex fragments that match the number of pipelines, and each fragment is sent to the corresponding geometry processing pipeline.

[0102] In some embodiments, if there is only one geometry processing pipeline downstream, the complete vertex stream is sent directly to that geometry processing pipeline.

[0103] Optionally, the geometry processing task assembly unit 120 and / or the geometry processing task assembly unit 220 are used to receive vertex streams and / or vertex stream fragments, obtain primitive topology information of vertex streams and / or vertex stream fragments, and determine whether they belong to strip topology.

[0104] Optionally, in the case of a strip topology, a first splitting strategy is adopted to split the vertices. Based on the vertex interval partitioning rules, the vertex flow is divided into multiple vertex intervals corresponding to the type of the strip topology, and the vertices within these intervals are split into first vertex shading tasks. Simultaneously, while shader 130 and / or shader 230 are processing the first vertex shading tasks, additional vertex information is computed and sent in parallel. This additional information includes one or more of the following: the primitive ID of the primitive to which the vertex belongs, the triangle orientation of the triangle to which the vertex belongs, the drawing instance ID, and the vertex adjacency relationship.

[0105] The vertex interval partitioning rules include: the vertex index range of the kth vertex interval among multiple vertex intervals is [S*k, S*k+W), where k is a non-negative integer, W is the number of vertices processed in parallel in a single operation in the shader or an integer multiple of the number of vertices processed in parallel in a single operation, and S is the step size determined according to the type of the strip topology, and S is a positive integer less than W.

[0106] Optionally, S equals W minus C; where C is the number of shared vertices determined according to the type of strip topology, and adjacent vertex intervals in multiple vertex intervals share C consecutive vertices.

[0107] In some embodiments, the type of strip topology includes one or more of the following: line strip, triangular strip, line strip with adjacent points, and triangular strip with adjacent points.

[0108] In some embodiments, when the strip topology is a triangular strip, the vertex index range is [S*k, S*k+W), where S equals W minus C, and C is the range of two adjacent vertex intervals sharing two consecutive vertices.

[0109] In some embodiments, when the strip topology is a line strip, the vertex index range is [S*k, S*k+W), where S equals W minus C, C is 1, and adjacent vertex intervals share one consecutive vertex.

[0110] In some embodiments, when the strip topology is a line strip with adjacent points, the vertex index range is [S*k, S*k+W), where S equals W minus C, and C is 3. Adjacent vertex intervals share 3 consecutive vertices.

[0111] In some embodiments, when the strip topology is a triangular strip with adjacent vertices, the vertex index range is [S*k, S*k+W), where S equals W minus C, and C is 7, and adjacent vertex intervals share 7 consecutive vertices.

[0112] Alternatively, the type of strip topology also includes triangular fans.

[0113] In some embodiments, the vertex interval division rule of the triangle sector includes: the vertex index range is {0, [S*k+1, S*k+W)}, where k is a non-negative integer; where S is W minus 2, adjacent vertex intervals in multiple vertex intervals share 2 consecutive non-center vertices, and the center vertex is the vertex with index 0.

[0114] Where W is the number of vertices processed in a single parallel operation by the shader component or an integer multiple thereof, and k is a non-negative integer.

[0115] Optionally, in the case of a non-strip topology, a second splitting strategy is adopted to split the vertices. First, the vertex flow is split according to the primitives to which it belongs. Then, a vertex cache hit test is performed on the split vertices. The vertex cache hit test is used to check whether the vertex already exists in the vertex cache. Finally, the second vertex shading task is assembled based on the vertices already cached in the vertex cache to avoid duplicate processing.

[0116] Optionally, primitive splitting involves breaking down a non-strip topology-associated vertex flow into independent basic primitives that the GPU can directly render. This is part of the second splitting strategy, which is computationally more demanding and has more complex execution steps. Vertex cache hit testing checks whether a vertex already exists in the vertex cache to avoid duplicate processing; this is also a sub-process of the second splitting strategy, consuming additional GPU computing resources and processing time. In contrast, the first splitting strategy for strip topology does not require at least one of the primitive splitting operation and vertex cache hit testing. Compared to the second splitting strategy, it significantly reduces computational load, simplifies the process, and greatly improves overall processing efficiency. It can quickly complete the shading task of the strip topology vertex flow, effectively reducing performance loss during the GPU geometry processing stage.

[0117] Optionally, a vertex cache hit test is used to check whether a vertex already exists in the vertex cache. The vertex cache hit test sends a query request to the vertex cache for each primitive's vertex index, and the vertex cache searches in parallel using the label array.

[0118] In some embodiments, a hit means the index exists in the label array, marking the vertex as processed and eliminating the need for subsequent shading tasks. A miss means the index does not exist in the label array, marking the vertex as pending processing, writing the vertex index into the hit list, and writing the vertex cache into the operation.

[0119] Optionally, shader 130 and / or shader 230 are used for parallel vertex shading processing. Shader 130 receives vertex shading tasks sent by the task assembly unit.

[0120] Optionally, shader 130 and / or shader 230 are SIMD / SIMT structures that perform SIMD / SIMT parallel processing.

[0121] Optionally, after the geometry task assembly unit completes its task in shader 130 and / or shader 230, it sends additional vertex information to primitive processing unit 140 and / or primitive processing unit 240. This additional information is primitive-related information required by the primitive processing unit for primitive processing, and includes one or more of the following: the primitive ID of the primitive to which the vertex belongs, the triangle orientation of the triangle to which the vertex belongs, the drawing instance ID, and the vertex adjacency relationship.

[0122] Optionally, primitive processing unit 140 and / or primitive processing unit 240 are used to read the vertex processing results based on additional information, perform rasterization, primitive shading and other subsequent operations, and finally output pixel data to the downstream pixel processing pipeline.

[0123] The geometry processing pipeline provided in this application embodiment realizes rapid task assembly of strip topologies. Specifically, when the input primitive topology belongs to a strip topology, including one or more of line strips, triangle strips, line strips with adjacent vertices, triangle strips with adjacent vertices, and triangle fans, a first splitting strategy is used to generate shading tasks. That is, in the geometry processing stage, at least one of primitive splitting operation and vertex cache hit test can be eliminated. The vertex flow is directly split according to the vertex index range determined by the number of threads in the shader wave and the strip topology type. Adjacent vertex intervals reduce redundant processing by sharing continuous vertices. However, when the input primitive topology does not belong to a strip topology, a second splitting strategy is used to generate shading tasks. Primitive splitting and vertex cache hit test must be performed first before assembling the tasks.

[0124] In summary, since the first splitting strategy is more efficient than the second splitting strategy, requires less computation, and has a more streamlined process, this differentiated task assembly design for topology adaptation greatly simplifies the shading task generation process of the vertex flow of strip topology. This effectively improves the processing efficiency of the graphics processor in the geometry processing stage for strip topology and solves the low performance problem caused by redundant sub-processes in traditional processing methods for strip topology.

[0125] The following is an example illustrating a single execution of a shader, such as... Figures 3 to 5 As shown.

[0126] Shaders typically employ a SIMD / SIMT architecture, allowing multiple threads to be scheduled in parallel during a single run. A single shader run is referred to as a wave, and / or warp, and / or wavefront.

[0127] For a wave, each individual thread is called a lane.

[0128] In some embodiments, the number of threads contained in a wave is determined by the GPU design, and this number is typically 16 or 32, but can also be other numbers, such as 128.

[0129] like Figure 3 The diagram shows a waveform with 16 threads starting up at once.

[0130] Optionally, Figure 3 Corresponding to Figure 4 The diagram shows a triangular strip. The 16 threads run the vertex coloring of vertex A, the second thread runs the vertex coloring of vertex B, and so on, until the last two threads run the vertex coloring of vertices O and P respectively. A, B, C, D and O, P correspond as follows: Figure 4 The triangular band shown.

[0131] According to the method proposed in this application, the next wave might be as follows: Figure 5 As shown. The first thread in this wave performs vertex shading for vertex O, the second thread performs vertex shading for vertex P, and so on.

[0132] The following is an example illustrating the splitting of vertices in the first vertex coloring task of a strip topology using the first splitting strategy.

[0133] 1. The strip topology type is line strip topology.

[0134] Optionally, the strip topology type is a line strip, whose structure satisfies the rule that the nth line segment and the (n-1)th line segment share one endpoint vertex, where n is a positive integer greater than 1.

[0135] In some embodiments, such as Figure 6 As shown, the first line segment of the strip topology type is composed of vertices V0 and V1, the second line segment is composed of vertices V1 and V2, and the third line segment is composed of vertices V2 and V3, thus forming a continuous line segment chain structure.

[0136] Optionally, the strip topology type of the line strip describes a large number of continuous line segments with a small number of vertices, reducing the amount of data in the vertex flow.

[0137] Optionally, the vertex attributes of the line strip need to transition smoothly along the line segment direction, and the processing results of the shader for shared vertices need to be reused by adjacent line segments. The geometry task assembly unit must retain the processing results of shared vertices when splitting the vertex shading task to avoid duplicate calculations or data inconsistencies.

[0138] Optionally, the vertex attributes of the line strip include at least one of color and texture coordinates.

[0139] For line strip topology, the geometric task assembly unit uses the left-closed right-open interval formula [(W-1)*k, (W-1)*k+W) to split the vertices, where W is the number of vertices processed in a single parallel process or an integer multiple of the number of vertices processed in a single parallel process.

[0140] Optionally, a line segment requires two vertices to form a line segment, and adjacent line segments share one vertex. Therefore, the vertex processing range of a single wave is set to W-1 to ensure that the line segments processed by adjacent waves can be connected by sharing vertices.

[0141] The task index k is a non-negative integer, and each k corresponds to one independent wave task. All vertices of the line are traversed in order.

[0142] In some embodiments, W is 16, and the number of threads is 16.

[0143] Optionally, when a single wave of the shader is configured with 16 threads, the vertex processing intervals and wave scheduling corresponding to different k values ​​are as follows: In some embodiments, when k is 0, the vertex processing range is [0, 16), corresponding to vertex indices 0 to 15.

[0144] Optionally, the geometry task assembly unit extracts 16 vertices of the interval from the input vertex stream and assigns them to threads 0 through 15.

[0145] Thread 0 processes vertex V0, performing at least one of the following first shading tasks: coordinate transformation and texture sampling. Thread 1 processes vertex V1, executing the same instructions synchronously with thread 0, but with the input data being the attributes of V1. This process continues until thread 15 processes vertex V15.

[0146] This wave can handle 15 line segments, all of which share adjacent vertices, ensuring a smooth transition of properties at the junctions of the line segments.

[0147] In some embodiments, when k is 1, the vertex processing interval is [15, 31), corresponding to vertex indices 15 to 30. It shares vertex index 15 with the interval [0, 16) where k is 0.

[0148] In some embodiments, thread 0 processes vertex V15, reuses the processing result of thread 15 when k is 0, thread 1 processes vertex V16, and so on, with thread 15 processing vertex V30.

[0149] Optionally, this wave can process 15 line segments, and is connected to the last line segment processed by the wave with k=0 via V15.

[0150] In some embodiments, when k is 2, the vertex processing interval is [30, 46), corresponding to vertex indices 30 to 45, which shares vertex index 30 with the interval [15, 31) where k is 1, ensuring the continuity of the strip.

[0151] In some embodiments, W is an extension of an integer multiple of the number of threads; for example, W is 32 and the number of threads is 16.

[0152] In some embodiments, if it is necessary to improve the batch processing efficiency of the strip, W can be set to an integer multiple of the number of threads. If the number of threads is 16, W is 32, and each split interval corresponds to 2 consecutive waves.

[0153] When k is 0, the vertex processing range is [0, 32), corresponding to vertex indices 0 to 31. The first wave processes vertices 0 to 15, and the second wave processes vertices 16 to 31. The two waves share vertices 15 to 16. Within a group, 31 line segments can be processed at once, and scheduling between groups is independent.

[0154] Optionally, primitive processing of the line strip depends on additional information about the vertices. After sending the vertex shading task to the shader, the geometry task assembly unit will compute and send one or more of the following information in parallel: line segment ID, line segment length, and drawing instance ID.

[0155] Optionally, the calculation of additional information is performed in parallel with the vertex shading process of the shader. After the shader completes the first vertex shading task, the additional information is sent to the primitive processing unit synchronously without additional time consumption, thereby improving the system throughput.

[0156] 2. The strip topology type is triangular strip topology.

[0157] Optionally, the strip topology type is a triangle strip whose structure satisfies the rule that the nth triangle and the (n-1th)th triangle share two consecutive vertices, where n is a positive integer greater than 1.

[0158] In some embodiments, such as Figure 7 As shown, the first triangle is composed of vertices V0, V1, and V2; the second triangle is composed of vertices V1, V2, and V3; and the third triangle is composed of vertices V2, V3, and V4, thus forming a continuous triangle chain structure.

[0159] This triangular strip topology describes a large number of consecutive triangles with a small number of vertices, reducing the amount of data in the vertex stream. However, it is necessary to ensure the consistency of the processing of shared vertices of adjacent triangles. If shared vertices are not processed synchronously, it will cause orientation reversal or rendering errors at the triangle junctions.

[0160] Optionally, the vertex attributes of the triangle strip need to transition smoothly along the direction of the triangle strip, and the processing results of the shader for shared vertices need to be reused by adjacent triangles. The geometry task assembly unit must retain the processing results of shared vertices when splitting the vertex shading task to avoid duplicate calculations or data inconsistencies.

[0161] Optionally, vertex attributes include at least one of normal and color.

[0162] For the triangular topology, the geometry task assembly unit uses the left-closed, right-open interval formula [(k(W-2), k(W-2)+W)] to split the vertices, where W is the number of vertices processed in a single parallel operation or an integer multiple of the number of vertices processed in a single parallel operation.

[0163] A triangle requires 3 vertices to form a triangle, and adjacent triangles share 2 vertices. Therefore, the vertex processing range of a single wave is W-2, and triangles processed by adjacent waves can be connected by sharing vertices.

[0164] Optionally, the task index k is a non-negative integer, and each k corresponds to one independent wave task, which traverses all vertices of the triangle strip in order.

[0165] In some embodiments, W is 32, and the number of threads is 32.

[0166] Optionally, when a single wave of the shader is configured with 32 threads, the vertex processing intervals and wave scheduling logic corresponding to different k values ​​are as follows: In some embodiments, when k is 0, the vertex processing range is [0, 32), corresponding to vertex indices 0 to 31.

[0167] Optionally, the geometry task assembly unit extracts 32 vertices of the interval from the input vertex stream and assigns them to threads 0 through 31.

[0168] In some embodiments, threads 0 to 2 process vertices V0, V1, and V2 to form the first triangle and perform at least one of the first shading tasks: normal calculation and lighting calculation. Threads 1 to 3 process vertices V1, V2, and V3 to form the second triangle, executing the same instructions synchronously with threads 0 to 2, except that the input data is the attributes of the corresponding vertex. And so on, threads 29 to 31 process vertices V29, V30, and V31 to form the 30th triangle.

[0169] Optionally, the wave can handle 30 triangles, all with the same orientation.

[0170] In some embodiments, when k is 1, the vertex processing interval is [30, 62), corresponding to vertex indices 30 to 61. It shares vertex indices 30 to 31 with the interval [0, 32) where k is 0. The specific scheduling logic is as follows: In some embodiments, threads 0 to 1 process vertices V30 to V31, reusing the processing results of threads 30 to 31 when k is 0, and threads 2 to 31 process vertices V32 to V61. The first triangle formed is V30, V31, and V32, which is seamlessly connected to the last triangle when k is 0 through V30 and V31.

[0171] Optionally, this wave can process 29 triangles, with the triangles facing the same direction as the wave with k=0.

[0172] In some embodiments, when k is 2, the vertex processing interval is [60, 92), corresponding to vertex indices 60 to 91, which shares vertex indices 60 to 61 with the interval [30, 62) where k is 1, ensuring the continuity of the triangle band.

[0173] In some embodiments, W is an extension of an integer multiple of the number of threads; for example, W is 64 and the number of threads is 32.

[0174] In some embodiments, to improve the batch processing efficiency of the triangle strip, W can be set to an integer multiple of the number of threads.

[0175] In some embodiments, the number of threads is 32 and W is 64, in which case each split interval corresponds to 2 consecutive waves.

[0176] When k is 0, the vertex processing range is [0, 64), corresponding to vertex indices 0 to 63; the first wave processes vertices 0 to 31, and the second wave processes vertices 32 to 63; the two waves share vertices 30 to 31, and can process 62 triangles at once, with independent scheduling between groups.

[0177] Optionally, primitive processing of triangles depends on additional information about the vertices. After sending the vertex shading task to the shader, the geometry task assembly unit will compute and send one or more of the following information in parallel: triangle orientation, triangle ID, and number of adjacent triangles to the vertex.

[0178] Optionally, the calculation of additional information is performed in parallel with the vertex shading process of the shader. After the shader completes the first vertex shading task, the additional information is sent to the primitive processing unit synchronously without additional time consumption, thereby improving the system throughput.

[0179] 3. The strip topology type is a line strip topology with adjacent nodes.

[0180] Optionally, the strip topology type is a line strip with adjacent points whose structure satisfies the rule that the nth line segment and the (n-1)th line segment share one endpoint vertex, and each vertex is additionally associated with one or more non-adjacent line segment vertices as adjacent points, where n is a positive integer greater than 1.

[0181] In some embodiments, such as Figure 8 As shown, the first line segment is composed of vertices V0 and V1, where V0 is adjacent to V3. The second line segment is composed of vertices V1 and V2, where V1 is adjacent to V4. The third line segment is composed of vertices V2 and V3, where V2 is adjacent to V5, thus forming a chain structure of line segments with branches or curves.

[0182] Optionally, the vertex attributes of the line strip with adjacent points need to transition smoothly along the line segment and adjacent branch direction. The shader's processing results for shared vertices and adjacent points need to be reused by the associated line segments. The geometry task assembly unit is required to retain the processing results of shared vertices and adjacent points when splitting the vertex shading task to avoid duplicate calculations or data inconsistencies. Vertex attributes include at least one of texture coordinates and normal vectors.

[0183] For line topologies with adjacent points, the geometric task assembly unit uses the left-closed, right-open interval formula [(W-3)*k, (W-3)*k+W) for vertex splitting.

[0184] In some embodiments, W is an integer multiple of the number of vertices processed in a single parallel operation. Each vertex in a line strip with adjacency points needs to be associated with one adjacency point, and adjacent line segments share one vertex. Therefore, the vertex processing interval step size of a single wave is set to W-3 to ensure that the adjacency relationship is continuous across waves.

[0185] In some embodiments, the task index k is a non-negative integer, and each k corresponds to one independent wave task, which traverses a portion of the vertices of the line strip with adjacent points in sequence.

[0186] In some embodiments, W is an extension that is an integer multiple of the number of threads.

[0187] Optionally, primitive processing of line strips with adjacent points requires additional information about the vertices. After sending the vertex shading task to the shader, the geometry task assembly unit will compute and send one or more of the following information in parallel: the adjacency association table, curvature, and branch type identifier.

[0188] Optionally, the calculation of additional information is performed in parallel with the vertex shading process of the shader. After the shader completes the first vertex shading task, the additional information is sent to the primitive processing unit synchronously without additional time consumption, thereby improving the system throughput.

[0189] 4. The strip topology type is a triangular strip topology with adjacent nodes.

[0190] Optionally, the strip topology type is a triangle strip with adjacent points whose structure satisfies the rule that the nth triangle and the (n-1th)th triangle share two consecutive vertices, and each vertex is additionally associated with two or more vertices of non-adjacent triangles as adjacent points, where n is a positive integer greater than 1.

[0191] In some embodiments, such as Figure 9 As shown, when the six vertices with indices 0, 1, 2, 3, 4, and 5 are obtained, it is impossible to determine whether the vertex connection relationship of the current triangle with adjacent vertices is 0-(1)-2-(5)-4-(3) or 0-(1)-2-(6)-4-(3). Only after the vertices with indices 6 and 7 are obtained can the vertex connection relationship of the first triangle with adjacent vertices be determined, specifically 0-(1)-2-(6)-4-(3).

[0192] In some embodiments, if only vertex number 6 is subsequently obtained, or if vertex data is truncated, the vertex connection relationship of the first primitive is 0-(1)-2-(5)-4-(3).

[0193] like Figure 9 As shown, the first triangle is composed of vertices V0, V2, and V4; the second triangle is composed of vertices V2, V4, and V6; and the third triangle is composed of vertices V4, V6, and V8, thus forming a triangular chain structure with grid subdivision or multi-region connection.

[0194] Optionally, the triangular strip topology with adjacent points enables mesh subdivision or smooth region transition through adjacent points.

[0195] Optionally, the vertex attributes of the triangle strip with adjacent points need to be smoothly transitioned along the direction of the triangle strip and the adjacent region. The processing results of the shader for shared vertices and adjacent points need to be reused by the associated triangles. When splitting the vertex shading task, the geometry task assembly unit retains the processing results of shared vertices and adjacent points to avoid duplicate calculations or data inconsistencies.

[0196] For triangular topologies with adjacent points, the geometric task assembly unit uses the left-closed, right-open interval formula [(W-7)*k, (W-7)*k+W) to split the vertices.

[0197] In some embodiments, W is the number of vertices processed in a single parallel operation or an integer multiple thereof. Each vertex in a triangle strip with adjacent points needs to be associated with two adjacent points, and adjacent triangles share two vertices. Therefore, the vertex processing interval step size for a single wave is set to W-7 to ensure that the adjacency relationship is continuous across waves. The task index k is a non-negative integer, and each k corresponds to an independent wave task. The partial vertices of the triangle strip with adjacent points are traversed in order.

[0198] In some embodiments, W represents the number of threads.

[0199] In some embodiments, W is an extension that is an integer multiple of the number of threads.

[0200] Alternatively, primitive processing of triangle strips with adjacent vertices requires additional information about the vertices.

[0201] Optionally, the calculation of additional information is performed in parallel with the vertex shading process of the shader. After the shader completes the first vertex shading task, the additional information is sent to the primitive processing unit synchronously without additional time consumption, thereby improving the system throughput.

[0202] 5. The strip topology type is triangular fan topology.

[0203] Optionally, the strip topology type is a triangular fan, whose structure satisfies the rule that all triangles share the same central vertex, and the nth triangle is composed of the central vertex, the (n-1)th non-central vertex, and the nth non-central vertex, where n is a positive integer greater than 1.

[0204] In some embodiments, such as Figure 10 As shown, the central vertex is V0. The first triangle is composed of V0, V1, and V2; the second triangle is composed of V0, V2, and V3; and the third triangle is composed of V0, V3, and V4, thus forming a sector-shaped triangle structure centered on V0.

[0205] Optionally, this triangular fan-strip topology reduces the amount of data in the vertex stream by describing a large number of concentric triangles through a shared central vertex.

[0206] Optionally, the non-central vertices of the triangle fan need to be arranged in clockwise or counterclockwise order; otherwise, the triangle orientation will be disordered. This requires the geometry task assembly unit to ensure the order of non-central vertices when splitting the vertex coloring task, while efficiently reusing the processing results of the central vertices.

[0207] For triangular fan topology, the geometric task assembly unit uses the interval {0, [(W-2)*k+1, (W-2)*k+W]} for vertex splitting.

[0208] In some embodiments, the center vertex of the triangular sector is fixed at index 0, and all waves reuse the processing result of V0 without repeated splitting.

[0209] In some embodiments, [(W-2)*k+1, (W-2)*k+W) is a left-closed, right-open interval containing W-1 non-central vertices. A triangular sector requires 3 vertices to form a triangle, and adjacent triangles share 1 non-central vertex. Therefore, the interval step size of the non-central vertex is set to W-2 to ensure that triangles processed by adjacent waves can maintain consistent order by sharing a non-central vertex.

[0210] The task index k is a non-negative integer, and each k corresponds to one wave task, which processes some non-center vertices. The center vertex V0 is always reused.

[0211] In some embodiments, W is 16, and the number of threads is 16.

[0212] Optionally, when a single wave of the shader is configured with 16 threads, the vertex processing intervals and wave scheduling corresponding to different k values ​​are as follows: In some embodiments, when k is 0, the vertex processing interval is {0, [1, 16]}, corresponding to vertex index 0 and vertex indices 1 to 16.

[0213] Optionally, the geometry task assembly unit assigns vertices to threads 0 through 15. Thread 0 specifically processes the central vertex V0, and the processing result is stored in the central vertex cache. Threads 1 through 15 process the non-central vertices V1 through V16 respectively, executing the same instructions synchronously with thread 0, only the input data is the attributes of the non-central vertices.

[0214] This wave can handle 15 triangles, all of which share V0 and are oriented clockwise, with no orientation reversal issues.

[0215] In some embodiments, when k is 1, the vertex processing interval is {0, [15, 30]}, corresponding to vertex indices 0, 15 to 30, where index 0 is the center vertex.

[0216] Optionally, thread 0 does not reprocess V0, but directly reads the result from the central vertex cache; threads 1 to 2 process non-central vertices V15 to V16, reusing the processing results of threads 15 to 16 when k is 0; and threads 3 to 15 process non-central vertices V17 to V30.

[0217] This wave can process 15 triangles, completely overlapping with the last triangle processed by the wave with k=0, ensuring the continuity of the triangle sector without gaps.

[0218] In some embodiments, when k is 2, the vertex processing interval is {0, [29, 44]}, corresponding to vertex indices 0, 29 to 44. It shares vertex indices 29 to 30 with the interval {0, [15, 30]} where k is 1, ensuring the continuity of the triangle sector.

[0219] In some embodiments, W is an extension of an integer multiple of the number of threads; for example, W is 64 and the number of threads is 32.

[0220] Optionally, primitive processing of the triangle fan depends on additional information about the vertices. After sending the vertex shading task to the shader, the geometry task assembly unit will calculate and send one or more of the following information in parallel: the angle between the triangle and the center vertex, the center region identifier, and the fan radius.

[0221] Optionally, the calculation of additional information is performed in parallel with the vertex shading process of the shader. After the shader completes the first vertex shading task, the additional information is sent to the primitive processing unit synchronously without additional time consumption, thereby improving the system throughput.

[0222] The geometry processing pipeline provided in this application embodiment enables rapid task assembly and differentiated processing of strip topologies, specifically as follows: When the input primitive topology belongs to the strip topology, the first splitting strategy is used to split the vertices. There is no need to perform the primitive splitting operation with large computational load and cumbersome steps in the second splitting strategy, and the vertex cache hit test that consumes additional computing resources. Instead, the matching vertex index range is determined directly according to the number of threads W in the shader wave and the corresponding strip topology type, and the first vertex shading task is generated. During the shader processing, parallel computing and sending additional vertex information are possible.

[0223] When the input primitive topology is a non-strip topology, the second splitting strategy is adopted. After primitive splitting and vertex cache hit testing, the second vertex shading task is assembled.

[0224] In summary, the first splitting strategy significantly improves the generation and processing efficiency of shading tasks for strip topology vertex streams by simplifying the process and reducing computational load and resource consumption. At the same time, it reduces system power consumption and increases overall throughput, effectively solving the low performance problem of the graphics processor when processing strip topology in the geometry processing stage. Meanwhile, retaining the traditional second splitting strategy also makes the system more flexible and able to cope with diverse shading tasks.

[0225] When starting a vertex processing task for geometry processing pipeline 100, there are two scenarios.

[0226] Case 1: The primitive topology of the vertex flow is a strip topology.

[0227] Scenario 2: The primitive topology of the vertex flow is a non-strip topology.

[0228] The following sections will introduce two scenarios for vertex processing tasks. It should be noted that the order of introduction does not indicate the superiority or inferiority of vertex processing methods.

[0229] Case 1: The primitive topology of the vertex flow is a strip topology.

[0230] When the primitive topology of the vertex flow is a strip topology, the geometry processing pipeline 100 provided in this application embodiment realizes fast task assembly of strip topology, and the specific technical solution is as follows: Optionally, after receiving the vertex stream or vertex stream fragment sent by the input parsing unit, the geometry task assembly unit in the geometry processing pipeline 100 first reads its primitive topology identification information. If it is determined to be a strip topology, it directly skips the primitive splitting operation and the vertex cache hit test operation (that is, the first splitting strategy skips the primitive splitting operation and the vertex cache hit test operation) and uses the fast task assembly algorithm proposed in this application to execute the subsequent process.

[0231] Optionally, the geometry task assembly unit splits the input vertex stream into corresponding continuous vertex intervals based on the type of strip topology. The geometry task assembly unit assembles the split vertex intervals into the first vertex shading task and sends it to the shader component; simultaneously, it computes and sends additional vertex information in parallel.

[0232] Optionally, the shader component executes vertex shader instructions synchronously, in waves, according to the mapping relationship between line program number and vertex index, to complete the processing of vertex attributes.

[0233] Optionally, since the vertex interval splitting of the strip topology ensures the continuity of shared vertices, the processing results of the shader on shared vertices can be reused by adjacent tasks without the need for additional cache hit verification, which greatly improves processing efficiency.

[0234] In summary, the geometry processing stage eliminates the need for redundant primitive splitting and vertex cache hit testing. By rapidly assembling and building tasks, the processing efficiency of vertex flows in strip topologies is significantly improved. At the same time, the rapid task assembly of strip primitive topologies reduces system power consumption, increases system throughput, solves the low performance problem of the graphics processor in processing strip topologies during the geometry processing stage, and effectively enhances the overall graphics processing performance of the system.

[0235] Scenario 2: The primitive topology of the vertex flow is a non-strip topology.

[0236] When the primitive topology of the vertex flow is a non-strip topology, the geometry processing pipeline 100 adopts the following vertex processing flow.

[0237] In some embodiments, the geometry task assembly unit receives a vertex stream sent by the input parsing unit, reads its primitive topology information, and determines that the current processing type is a non-strip topology. The geometry task assembly unit needs to perform a primitive splitting operation, traversing the vertex stream sequentially according to the primitive composition rules of non-strip topology, and splitting continuous vertices into independent primitives.

[0238] After primitive decomposition, the geometry task assembly unit performs a vertex cache hit test on each primitive's vertices. If a hit occurs, the cached vertex shading result is reused; otherwise, it is marked as a vertex to be processed.

[0239] In some embodiments, the geometry task assembly unit assembles the vertices that missed the hit test into a second vertex shading task based on the number of threads within the wave, and sends it to the shader component. During the execution of the vertex shading task by the shader, the geometry task assembly unit computes and sends additional primitive information in parallel.

[0240] After the shader completes vertex shading, it sends the processing results to the primitive processing unit. At the same time, the geometry task assembly unit sends additional information to the primitive processing unit to complete vertex processing for non-strip topology.

[0241] In summary, this approach ensures the compatibility of the geometry processing pipeline with various non-strip topologies. Although the processing time is increased due to primitive splitting and hit testing, it complements the fast processing flow of strip topologies, together forming a complete vertex processing solution and ensuring the versatility of the geometry processing pipeline.

[0242] It should be noted that Situations 1 and 2 above can be implemented independently or in combination.

[0243] For example, taking scenario one as an example, the workflow flowchart of the geometry task assembly unit is as follows: Figure 11 As shown in the diagram, this flowchart illustrates the topology determination and task assembly process of the geometry task assembly unit for the input vertex flow, comprising six core steps, as follows: Step 1: Detect the topology of the input primitives The geometry task assembly unit receives the vertex stream or vertex stream fragment from the input parsing unit, reads its primitive topology information, and determines the primitive organization form of the current vertex stream to be processed.

[0244] Step 2: Is it a supported strip topology? The geometry task assembly unit compares the detected primitive topology with a preset list of supported strip topologies to determine whether it belongs to a supported strip topology type.

[0245] If the result is yes, proceed to step 5; if the result is no, proceed to step 3.

[0246] Step 3: Process the input vertex stream sequentially and split the primitives. If the current primitive topology does not belong to the supported strip topology, the geometry task assembly unit will follow the traditional process, traversing the input vertex stream in sequence and splitting it into independent primitives.

[0247] Step 4: Vertex cache hit test For each vertex of the split primitive, the geometry task assembly unit sends a hit test request to the vertex cache to check if the vertex already exists in the cache. If a hit occurs, the cached vertex coloring result is reused; if a hit occurs, the vertex is marked as a vertex to be processed.

[0248] Step 5: Quickly split the input vertex stream If the current primitive topology belongs to a supported strip topology, the geometry task assembly unit adopts the method proposed in this application to quickly split the input vertex stream into continuous vertex intervals, skipping redundant primitive splitting and vertex cache hit test steps.

[0249] Step 6: Assemble and send the vertex shader task If it is a strip topology branch: the geometry task assembly unit assembles the continuous vertices into the first vertex shading task according to the first splitting strategy based on the rapidly split vertex interval, and sends it to the task receiving buffer of the shader component. At the same time, additional information of the vertices can be calculated and sent in parallel.

[0250] For non-strip topology branches: the geometry task assembly unit assembles the vertices that did not hit into the second vertex shading task based on the vertex cache hit test results, and sends the task to the shader component. The vertices that hit the test results directly reuse the cache results without repeated processing.

[0251] Figure 12 A schematic diagram of the graphics processing core provided in an embodiment of this application is shown.

[0252] The graphics processing core 10 includes a geometry processing pipeline 100, which is the geometry processing pipeline mentioned above, including a geometry task assembly unit, shaders, and primitive processing units, which will not be described in detail here.

[0253] Optionally, the graphics processing core 10 also includes an input parsing unit 110, a geometry task assembly unit 120, a shader 130, and a primitive processing unit 140. The input parsing unit 110 receives split vertex streams and initial split state information, and is used to receive drawing instructions issued by the user through the driver, splitting or directly forwarding the vertex stream according to the number of downstream geometry processing sub-pipelines. The geometry task assembly unit 120 is connected to the input parsing unit 110 and is used to select the corresponding task splitting method according to the primitive topology type, assembling vertex shading tasks and other possible shading tasks. The shader 130 is connected to the geometry task assembly unit 120, adopts a SIMD / SIMT structure, and runs multiple threads to process vertex shading tasks in waves. The primitive processing unit 140 is connected to the shader 130 and is used to receive additional vertex information and perform subsequent primitive processing operations.

[0254] Optionally, the graphics processing core 10 also includes an input parsing unit 110. One end of the input parsing unit 110 is connected to the vertex buffer unit 170, and the other end of the input parsing unit 110 is connected to the primitive assembly pipeline 150. The input parsing unit 110 is used to split at least one vertex index into multiple vertex indices and send the multiple vertex indices to the vertex buffer unit 170 and the primitive assembly pipeline 150.

[0255] For example, the input parsing unit receives drawing instructions specified by the application or driver, and then retrieves the vertex indices required by the drawing instructions from the storage unit, or the storage unit generates the vertex indices itself. The input parsing unit splits these vertex indices into vertex segments with the same number of vertex indices according to the splitting method specified by the drawing instructions, driver, or system configuration module, i.e., the multiple vertex indices mentioned above.

[0256] Optionally, the graphics processing core 10 further includes: a memory access arbitrator 210 and a pixel processing pipeline 220; a first end of the memory access arbitrator 210 is connected to the output of the primitive processing pipeline 160, and a second end of the memory access arbitrator 210 is connected to the pixel processing pipeline 220; a third end of the memory access arbitrator 210 is used to connect to a system bus, and the system bus is connected to memory units; the memory access arbitrator 210 is used to arbitrate access to a memory unit by one of the primitive processing pipeline 160 and the pixel processing pipeline 220.

[0257] In summary, the graphics processing core provided in this application enables rapid task assembly of strip topologies. Specifically, when the input primitive topology belongs to a strip topology, such as line strips, triangle strips, line strips with adjacent vertices, triangle strips with adjacent vertices, or triangle fans, the geometry processing stage can directly perform the shading task without primitive splitting operations and vertex cache hit tests. This rapid task assembly improves processing efficiency. Simultaneously, the rapid task assembly of strip primitive topologies also reduces system power consumption, increases system throughput, and improves overall system performance. It solves the low-performance problem of the graphics processor's geometry processing stage when handling strip topologies.

[0258] Figure 13 A schematic diagram of a graphics processor provided in an exemplary embodiment of this application is shown.

[0259] In some embodiments, the graphics processor includes: N graphics processing cores 10, a system configuration unit 20, a system bus 30, and a storage unit 40, where N is a positive integer; the N graphics processing cores 10 are respectively connected to the system bus 30, and the system bus 30 is connected to the storage unit 40; the system configuration unit 20 is respectively connected to each of the N graphics processing cores 10; wherein each graphics processing core 10 includes the aforementioned geometry processing pipeline 100.

[0260] Optionally, each graphics processing core 10 can independently receive drawing commands, topology type information, and a portion of vertex streams, and execute geometric processing tasks in parallel; the system configuration unit 20 can issue configuration parameters (such as the number of lanes in a wave, task priority, etc.) to each graphics processing core 10 to coordinate the workload of N cores and achieve load balancing.

[0261] Optionally, the N graphics processing cores 10 are homogeneous, meaning that the performance of the graphics processor can be adjusted by simply increasing or decreasing the number of graphics processing cores 10 to meet the throughput, performance, and power consumption requirements of the graphics processor in different application scenarios, thereby reducing the complexity of design and verification.

[0262] In summary, the graphics processor provided in this application implements fast task assembly for strip topologies. Specifically, when the input primitive topology belongs to a strip topology, such as line strips, triangle strips, line strips with adjacent vertices, triangle strips with adjacent vertices, or triangle fans, the geometry processing stage can directly perform the shading task without primitive splitting operations and vertex cache hit tests. The fast assembly task proposed in this application improves processing efficiency. Simultaneously, the fast task assembly of strip primitive topologies also reduces system power consumption, increases system throughput, and improves overall system performance. This solves the low-performance problem of the graphics processor's geometry processing stage when handling strip topologies.

[0263] Figure 14 A flowchart of a vertex processing method provided in an exemplary embodiment of this application is shown. This method is executed by the geometry processing pipeline 100 shown above. The geometry processing pipeline 100 includes: geometry task assembly; the method includes: Step 510: If the primitive topology of the input vertex stream is a strip topology, the vertex stream is split into a first vertex coloring task using the first splitting strategy.

[0264] In some embodiments, a vertex stream can be a sequence of vertex data that defines attributes such as position, normals, and texture coordinates of the geometry to be rendered (e.g., primitives). Primitive topology can be a set of rules used to define how vertices in the vertex stream are connected to form basic geometry and / or primitives. Common primitive topologies include one or more of the following: point lists, line lists, line strips, triangle lists, and triangle strips.

[0265] Among them, strip topology is a special type of primitive topology, characterized by adjacent primitives sharing vertices.

[0266] For example, in the triangle strip, the nth triangle shares two vertices with the (n+1)th triangle. A shader is a program that runs on a graphics processor and processes graphics data.

[0267] Optionally, the shader in this embodiment can be a vertex shader, which performs a series of transformations on each input vertex and outputs the transformed vertex data.

[0268] Optionally, there is an input processing unit 110, which is used to receive drawing instructions issued by the user through the driver, the drawing instructions carrying a vertex stream.

[0269] Optionally, if the primitive topology of the vertex flow is a strip topology, the vertex flow is split into one or more vertex flow segments depending on the number of geometric task pipelines.

[0270] Primitive topology defines the connection rules between vertices in a vertex flow, instructing the GPU how to combine discrete vertices into basic geometric shapes. These basic geometric shapes, or primitives, include at least one of points, lines, and triangles. Common primitive topologies include one or more of the following: a list of points, where each vertex is a separate point primitive; a list of lines, where every two vertices form an independent line segment; a line band, where adjacent vertices are connected sequentially to form continuous line segments, with each subsequent line segment sharing a vertex; a list of triangles, where every three vertices form an independent triangle; and a triangle band, where adjacent triangles share two vertices.

[0271] Strip topology is a special type of primitive topology with vertex reuse characteristics. Its features include one or more of the following: adjacent primitives share some vertices, eliminating the need to repeatedly store or process shared vertex data, thereby reducing data volume and computational load. Common primitive topologies include one or more of the following: triangular strips, line strips, line strips with adjacent vertices, triangular strips with adjacent vertices, and triangular fans.

[0272] Alternatively, if there is only one geometry processing pipeline, then the input parsing unit does not need to split the specified vertex stream; it can directly send the vertex stream to the single geometry processing pipeline.

[0273] Optionally, the geometry task assembly unit 120 is used to receive vertex stream fragments sent from the input parsing unit, process these vertex stream fragments, assemble vertex shading tasks, as well as other possible shading tasks, and send the assembled vertex shading tasks to the shader 130 to execute the corresponding shader 130 program.

[0274] In some embodiments, other possible shading tasks include, but are not limited to, geometry shading, shell shading, and domain shading.

[0275] The geometry task assembly unit 120 is used to split the vertex flow into a first vertex coloring task by employing a first splitting strategy when the primitive topology of the input vertex flow is a strip topology.

[0276] Optionally, the first splitting strategy includes: dividing the vertex flow into multiple vertex intervals corresponding to the type of the strip topology according to the vertex interval partitioning rules, and splitting the vertices in the multiple vertex intervals into a first vertex coloring task.

[0277] In some embodiments, the first splitting strategy refers to a task splitting strategy applicable to strip topologies. Its design leverages the vertex reuse rules of strip topologies to simplify the splitting logic and reduce computational overhead. Since adjacent primitives in a strip topology share vertices, there is no need to perform complex operations such as primitive assembly and vertex cache hit testing; task assembly can be completed simply by dividing intervals according to fixed rules.

[0278] The vertex interval partitioning rules include: the vertex index range of the kth vertex interval among multiple vertex intervals is [S*k, S*k+W), where k is a non-negative integer, W is the number of vertices processed in parallel in a single operation or an integer multiple of the number of vertices processed in parallel in a single operation, and S is the step size determined according to the type of the strip topology, and S is a positive integer less than W.

[0279] A vertex interval refers to a range of vertex indices divided from a continuous vertex stream according to specific rules. This range serves as an independent processing unit, corresponding to a vertex shading task. Each vertex interval contains multiple consecutive vertices, which are processed synchronously and in parallel by the shader. For example, if the vertex stream index is 0 to 100, the divided vertex intervals may include one or more of the following: [0, 7], [6, 13], [12, 19], with each interval corresponding to a first vertex shading task. The vertex index range is used to define the boundaries of the vertex interval and is represented in the form of a start index and an end index range, i.e., [S*k, S*k+W), where: • The starting index is S*k: representing the index position of the first vertex in the vertex flow of the k-th interval; • The ending index is S*k+W: This represents the index position of the next vertex after the end vertex of the k-th interval. It should be noted that the vertex corresponding to this index does not belong to the current interval. In some embodiments, when k=0, S=1, W=8, the vertex index range is [0, 8), corresponding to 8 vertices with indices 0 to 7; when k=1, the index range is [1, 9), corresponding to 8 vertices with indices 1 to 8.

[0280] Optionally, S equals W minus C; where C is the number of shared vertices determined according to the type of strip topology, and adjacent vertex intervals in multiple vertex intervals share C consecutive vertices.

[0281] The number of shared vertices, C, refers to the number of vertices that overlap between two adjacent vertex intervals. This value is determined by the type of strip topology and directly corresponds to the vertex reuse rules of strip topology. Since adjacent primitives in strip topology share C vertices, adjacent vertex intervals must also maintain an overlap of C vertices to ensure that the colored data can be correctly pieced together into a complete primitive.

[0282] Optionally, the types of strip topology include one or more of the following: triangular strip, line strip, line strip with adjacent points, and triangular strip with adjacent points.

[0283] When the strip topology is triangular strip, C is 2; when the strip topology is linear strip, C is 1; when the strip topology is linear strip with adjacent points, C is 3. In the case of a strip topology of triangular strip with adjacent points, C is 4.

[0284] For example, in a strip topology, the nth line segment and the (n-1th line segment share an endpoint vertex, where n is a positive integer greater than 1.

[0285] For example, in a strip topology, the nth triangle in a triangle strip shares two consecutive vertices with the (n-1)th triangle, where n is a positive integer greater than 1.

[0286] For example, in a strip topology with adjacent points, each vertex is associated with at least one vertex of a non-adjacent line segment as an adjacent point, based on the vertex connection of the strip.

[0287] For example, in a strip topology with adjacent triangles, each vertex is associated with at least one vertex of a non-adjacent triangle as an adjacent vertex.

[0288] For example, in a triangular sector of a strip topology, all triangles share the same central vertex. The nth triangle is composed of the central vertex, the (n-1)th non-central vertex, and the nth non-central vertex, where n is a positive integer greater than 1.

[0289] Where W is the number of vertices processed in a single parallel operation by the shader component or an integer multiple thereof, and k is a non-negative integer.

[0290] Optionally, multiple vertex indices arranged in sequence refer to multiple vertex indices arranged according to the order in which multiple vertices are arranged in the primitive. For example, the vertex indices corresponding to multiple vertices in each primitive are consecutive, and the vertex indices corresponding to multiple vertices in each primitive are arranged in clockwise or counterclockwise order in the primitive.

[0291] Step 520: If the primitive topology of the input vertex stream is not a strip topology, the vertex stream is split into a second vertex coloring task using the second splitting strategy. The computational cost of the first splitting strategy is less than that of the second splitting strategy.

[0292] In some embodiments, computational complexity is used to characterize the computational complexity of the geometry task assembly unit in processes such as splitting vertex flows and organizing tasks, including but not limited to the number and scale of operations such as comparisons, judgments, address calculations, and memory accesses that need to be performed. Lower computational complexity means lower processing overhead and potentially lower pipeline startup latency.

[0293] Because strip topology has a regular vertex reuse pattern, the first splitting strategy generally refers to various strategies that can utilize the aforementioned patterns of strip topology. That is, the first splitting strategy is a splitting strategy applicable to strip topology.

[0294] In some embodiments, the vertex flow can be divided into a set of non-overlapping, continuous vertex intervals according to the indexing rules of the strip topology, with each interval corresponding to an independent vertex shading task.

[0295] The second splitting strategy is applicable to non-strip topologies. For non-strip topologies, since there is no fixed reuse pattern between vertices, and each primitive's vertices are relatively independent, primitive splitting and vertex cache hit testing must be performed first, followed by the assembly task based on the deduplicated vertices. Therefore, the second splitting strategy is a more general but relatively complex method.

[0296] In some embodiments, primitive assembly can be performed based on an index buffer, identifying the vertices referenced by each primitive, and then a shading task can be created based on the set of vertex indices.

[0297] Optionally, the geometry task assembly unit 120 is used to split the vertex flow into a second vertex coloring task using a second splitting strategy if the primitive topology of the input vertex flow is not a strip topology.

[0298] Optionally, the second splitting strategy includes: performing primitive splitting operations and vertex cache hit tests on vertices in the vertex flow that do not belong to the strip topology, and assembling a second vertex shading task based on the vertices already cached in the vertex cache.

[0299] Optionally, the primitive splitting operation is the operation of splitting a non-strip topologically associated vertex flow into independent basic primitives that can be directly drawn by the GPU; the vertex cache hit test is a test to check whether a vertex already exists in the vertex cache to avoid duplicate processing.

[0300] Optionally, a vertex cache hit means that the vertex index of the vertex is already stored in the vertex index cache; a vertex cache miss means that the vertex index of the vertex does not exist in the vertex index cache.

[0301] Step 530: The shader processes the first vertex shading task and / or the second vertex shading task.

[0302] In some embodiments, shaders employ SIMD and / or SIMT structures, and multiple threads can run at once.

[0303] Optionally, a shader run can be a wave and / or a warp and / or a wavefront. The number of threads within a wave in a shader is determined by the image processing core design. Each thread handles the computation task for one vertex, and multiple threads execute the same shader program instructions synchronously.

[0304] In some embodiments, the primitive processing unit is configured to receive additional information about vertices in a first vertex shading task. Exemplarily, the additional information about a vertex includes one or more of the following: the primitive ID of the primitive to which the vertex belongs, the triangle orientation of the triangle to which the vertex belongs, the drawing instance ID, and the vertex adjacency relationship.

[0305] Optionally, primitive processing refers to performing primitive-related processing on the first primitive. Primitive processing includes, but is not limited to: rasterization; primitive shading; and surface subdivision. Surface subdivision is a method for further subdividing a primitive to obtain a smooth surface.

[0306] In summary, the method of this application embodiment achieves fast task assembly of strip topologies. Specifically, when the input primitive topology belongs to a strip topology, such as one or more of line strips, triangle strips, line strips with adjacent vertices, triangle strips with adjacent vertices, and triangle fans, the geometry processing stage can directly perform the shading task without primitive splitting operations and vertex cache hit tests. The fast assembly and construction task proposed in this application improves processing efficiency. Simultaneously, the fast task assembly of strip primitive topologies also reduces system power consumption, increases system throughput, and improves overall system performance. It solves the low performance problem of the graphics processor's geometry processing stage when handling strip topologies.

[0307] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0308] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A geometry processing pipeline, comprising: The geometry processing pipeline comprises a geometry task assembling unit and a shader; The geometry task assembling unit is configured to, in a case where a primitive topology of an input vertex stream is a strip topology, split the vertex stream into a first vertex shading task by using a first splitting strategy; and in a case where the primitive topology of the input vertex stream is not the strip topology, split the vertex stream into a second vertex shading task by using a second splitting strategy, a calculation amount of the first splitting strategy being less than a calculation amount of the second splitting strategy; The shader is configured to process the first vertex shading task and / or the second vertex shading task.

2. The geometry processing pipeline of claim 1, wherein, The first splitting strategy comprises: dividing the vertex stream into a plurality of vertex intervals corresponding to a type of the strip topology according to a vertex interval division rule, and splitting vertices in the plurality of vertex intervals into the first vertex shading task; The vertex interval division rule comprises: a vertex index range of a kth vertex interval in the plurality of vertex intervals is [S*k, S*k+W), k is a non-negative integer, W is a number of vertices processed in a single parallel process or an integer multiple of the number of vertices processed in a single parallel process in the shader, and S is a step length determined according to the type of the strip topology, and the S is a positive integer less than W.

3. The geometry processing pipeline of claim 2, wherein, The S is equal to the W minus C; wherein the C is a number of shared vertices determined according to the type of the strip topology, and adjacent vertex intervals in the plurality of vertex intervals share C consecutive vertices.

4. The geometry processing pipeline of claim 3, wherein, The type of the strip topology comprises one or more of the following: a line strip, a triangle strip, a line strip with adjacent points, and a triangle strip with adjacent points. In a case where the type of the strip topology is the line strip, the C is 1. In a case where the type of the strip topology is the triangle strip, the C is 2. In a case where the type of the strip topology is the line strip with adjacent points, the C is 3. In a case where the type of the strip topology is the triangle strip with adjacent points, the C is 4.

5. The geometry processing pipeline of any one of claims 2 to 4, wherein, The type of the strip topology further comprises a triangle fan. The vertex interval division rule of the triangle fan comprises: the vertex index range is {0, [S*k+1, S*k+W)}, k is a non-negative integer; wherein the S is W minus 2, adjacent vertex intervals in the plurality of vertex intervals share 2 consecutive non-central vertices, and the central vertex is a vertex with an index of 0.

6. The geometry processing pipeline of any one of claims 1 to 5, wherein, The geometry processing pipeline further comprises a primitive processing unit. The geometry task assembling unit is further configured to send additional information of vertices in the first vertex shading task to the primitive processing unit, the additional information being primitive-related information required for the primitive processing unit to perform primitive processing, and the additional information comprising one or more of the following: a primitive ID of a primitive to which the vertex belongs, a triangle orientation of a triangle to which the vertex belongs, a draw instance ID, and a vertex adjacency relationship.

7. A graphics processing core, comprising: The graphics processing core comprises the geometry processing pipeline of any one of claims 1 to 6, and an input parsing unit.

8. A graphics processor, comprising: The graphics processing core comprises: N graphics processing cores, a system configuration unit, a system bus, and a storage unit, N being a positive integer. The N graphics processing cores are connected with the system bus respectively, and the system bus is connected with the storage unit; the system configuration unit is connected with each of the graphics processing cores respectively; Each of the graphics processing cores comprises the geometry processing pipeline according to any one of claims 1 to 6.

9. A vertex processing method, characterized by, The method comprises: In a case where a primitive topology of an input vertex stream is a strip topology, a first splitting strategy is adopted to split the vertex stream into a first vertex shading task; in a case where the primitive topology of the input vertex stream is not the strip topology, a second splitting strategy is adopted to split the vertex stream into a second vertex shading task, and a calculation amount of the first splitting strategy is less than a calculation amount of the second splitting strategy; The first vertex shading task and / or the second vertex shading task are processed.

10. The vertex processing method of claim 9, wherein, The first splitting strategy comprises: According to a vertex interval division rule, the vertex stream is divided into a plurality of vertex intervals corresponding to a type of the strip topology, and vertices in the plurality of vertex intervals are split into the first vertex shading task; The vertex interval division rule comprises: a vertex index range of a kth vertex interval in the plurality of vertex intervals is [S*k, S*k+W), k is a non-negative integer, W is a thread number of a single wave in the shader or an integer multiple of the thread number of the single wave, S is a step length determined according to the type of the strip topology, and the S is a positive integer less than the W.

11. The vertex processing method of claim 10, wherein, The S is equal to the W minus C; wherein the C is a shared vertex number determined according to the type of the strip topology, and adjacent vertex intervals in the plurality of vertex intervals share C continuous vertices.

12. The vertex processing method of claim 11, wherein, The type of the strip topology comprises one or more of the following: a line strip, a triangle strip, a line strip with adjacent points, a triangle strip with adjacent points; In a case where the type of the strip topology is the line strip, the C is 1; In a case where the type of the strip topology is the triangle strip, the C is 2; In a case where the type of the strip topology is the line strip with adjacent points, the C is 3; In a case where the type of the strip topology is the triangle strip with adjacent points, the C is 4.

13. The vertex processing method of any one of claims 10 to 12, wherein, The type of the strip topology further comprises a triangle fan; A vertex interval division rule of the triangle fan comprises: the vertex index range is {0, [S*k+1, S*k+W)}, k is a non-negative integer; wherein the S is W minus 2, adjacent vertex intervals in the plurality of vertex intervals share 2 continuous non-central vertices, and the central vertex is a vertex with an index of 0.

14. The vertex processing method of any one of claims 9 to 13, wherein, The method further comprises: Additional information of a vertex in the first vertex shading task is sent to the primitive processing unit, the additional information being primitive-related information required for the primitive processing unit to perform primitive processing, and the additional information comprising one or more of the following: a primitive ID of a primitive to which the vertex belongs, a triangle orientation of a triangle to which the vertex belongs, a drawing instance ID, and a vertex adjacency relationship.

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