Display device and display control method
By pre-charging during the blanking cycle of the TFT-LCD display panel, the problem of horizontal dark lines caused by insufficient charging time is solved, achieving a higher quality display effect.
Patent Information
- Application Number
- CN202610034220.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-12
- Publication Date
- 2026-03-17
AI Technical Summary
Traditional TFT-LCD display panels have difficulty charging the first pixel row to the expected grayscale voltage within a limited charging time, resulting in horizontal dark lines at the top or bottom of the display panel, which affects the display effect.
By outputting the target grayscale voltage to the data line during the blanking cycle and the grayscale voltage of the scan line cycle during the scan line cycle, the blanking cycle is used for pre-charging to ensure that the data line has a high initial voltage when the scan line cycle is started, thus compensating for insufficient charging caused by RC delay.
Without altering the physical structure of the panel, the charging time of the pixel capacitors was effectively increased, ensuring that the pixel rows were charged to the expected grayscale voltage, eliminating horizontal dark lines, and improving the overall display quality of the display panel.
Smart Images
Figure CN121686967A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of display, in particular to a display device and a display control method. BACKGROUND
[0002] Thin Film Transistor (TFT) Liquid Crystal Display (LCD) panel has been widely applied in various consumer electronics and industrial display fields due to its advantages of mature technology, low cost and wide application.
[0003] However, in the related art, when the traditional TFT-LCD display panel displays, the first pixel row (usually located at the top or bottom of the display panel according to the scanning order) in a display frame is difficult to be charged to the expected gray scale voltage within the limited charging time, resulting in that the brightness of the first pixel row cannot reach the expected brightness. In the overall vision, a horizontal dark line will appear at the top or bottom of the display panel, which affects the overall display effect of the display panel. Therefore, how to charge the first pixel row in a display frame to the expected gray scale voltage within the limited charging time, so as to eliminate the horizontal dark line at the top or bottom of the display panel, is a technical problem to be solved in the field. SUMMARY
[0004] The present application provides a display device and a display control method to solve the above technical problems.
[0005] In a first aspect, a display device is provided, comprising: a display panel, a source driver and a timing controller, one display frame of the display panel comprising a display period and a blanking period, the display period comprising a plurality of scanning row periods, and the blanking period comprising a plurality of blank row periods; the source driver being connected to each pixel column in a pixel array of the display panel through a plurality of data lines; The timing controller is configured to obtain an output gray scale of a target scanning row period and a first target output gray scale, and output the output gray scale and the first target output gray scale to the source driver, the target scanning row period being adjacent to a target blank row period in a blanking period of a current display frame in time sequence, and the target blank row period being located before the target scanning row period in time sequence in the blanking period of the current display frame; The source driver is configured to output a gray scale voltage corresponding to the first target output gray scale to each data line in the target blank row period in the blanking period of the current display frame, and output a gray scale voltage corresponding to the output gray scale of the target scanning row period to each data line in the target scanning row period.
[0006] Optionally, the display period in the display frame is located in time sequence before the blanking period; and the target scan line period is a first scan line period in time sequence in a display period of a next display frame to be displayed of the current display frame.
[0007] Optionally, the display period in the display frame is located in time sequence after the blanking period; and the target scan line period is a first scan line period in time sequence in the display period of the current display frame.
[0008] Optionally, the timing controller is further configured to obtain an output gray scale of a first scan line period in a display period of a first display frame after the display panel is powered on and a second target output gray scale, and output the output gray scale and the second target output gray scale to the source driver. The source driver is further configured to output a gray scale voltage corresponding to the second target output gray scale to each of the data lines within a preset time period before the first scan line period in the display period of the first display frame, and output a gray scale voltage corresponding to the output gray scale of the first scan line period in the display period of the first display frame to each of the data lines within the first scan line period in the display period of the first display frame, the preset time period being equal in time length to the target blank line period.
[0009] Optionally, the timing controller is specifically configured to determine the output gray scale of the target scan line period as the first target output gray scale, or calculate another output gray scale based on the output gray scale of the target scan line period as the first target output gray scale.
[0010] Optionally, the timing controller is specifically configured to obtain the first target output gray scale based on an output gray scale of a last scan line period in the display period of the current display frame.
[0011] Optionally, the timing controller is specifically configured to obtain the first target output gray scale based on an output gray scale of a last scan line period in a display period of a last display frame of the current display frame.
[0012] Optionally, the target blank line period in the blanking period is a last target number of blank line periods in time sequence in the blanking period; and the target number is any one of 1, 2 or 3.
[0013] Optionally, the target blank line period in the blanking period is a last blank line period in time sequence in the blanking period.
[0014] In a second aspect, the embodiments of the present application further provide a display control method applied to a display device, the method comprising: acquire an output gray scale of a target scan line period and a first target output gray scale, the target scan line period being adjacent to a target blank line period in a blanking period of a current display frame in time sequence, and the target blank line period being located before the target scan line period in time sequence in the blanking period of the current display frame; output a gray scale voltage corresponding to the first target output gray scale to each data line in the target blank line period in the blanking period of the current display frame, and output a gray scale voltage corresponding to the output gray scale of the target scan line period to each data line in the target scan line period.
[0015] In the display device in the present application, the first scan line period in time sequence in a display period of a current display frame, or the first scan line period in time sequence in a display period of a next display frame to be displayed of the current display frame is determined as a target scan line period, and a target blank line period in the display period of the current display frame adjacent to the target scan line period and located before the target scan line period in time sequence is taken as a pre-charge stage of the target scan line period. After acquiring the output gray scale of the target scan line period and the first target output gray scale by a time sequence controller, the source driver outputs a gray scale voltage corresponding to the first target output gray scale to each data line in the target blank line period in the display period of the current display frame, and then outputs a gray scale voltage corresponding to the output gray scale of the target scan line period to each data line in the target scan line period. The target scan line period corresponding pixel row can be pre-charged by the blanking period, so that when the target scan line period is turned on, each data line has a higher or expected initial voltage, effectively increasing the effective charging time of the pixel capacitance in the target scan line period, compensating for the insufficient charging caused by the RC delay due to the small data line width or large channel length of the thin film transistor in the display panel. The pixel row corresponding to the target scan line period can be charged to the expected gray scale voltage in the limited charging time of the target scan line period without changing the physical structure of the display panel, thereby eliminating the horizontal dark line problem caused by the insufficient brightness of the first pixel row scanned in the display frame, and significantly improving the overall display quality of the display panel. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.
[0017] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.
[0018] Figure 1 Figure 1 is a driving timing diagram of a conventional display panel.
[0019] Figure 2 Figure 2 is another driving timing diagram of a conventional display panel.
[0020] Figure 3 Figure 3 is a structural schematic diagram of a display device according to an exemplary embodiment of the present disclosure.
[0021] Figure 4 Figure 4 is a timing structural schematic diagram of one display frame according to an exemplary embodiment of the present disclosure.
[0022] Figure 5 Figure 5 is another timing structural schematic diagram of one display frame according to an exemplary embodiment of the present disclosure.
[0023] Figure 6 Figure 6 is a driving timing diagram of a display panel according to an exemplary embodiment of the present disclosure.
[0024] Figure 7 Figure 7 is a flow schematic diagram of a display control method according to an exemplary embodiment of the present disclosure.
[0025] Reference signs: 100: display device; 11: display panel; 12: timing controller; 13: gate controller; 14: source driver. DETAILED DESCRIPTION
[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.
[0027] In the embodiments of the present application, at least one means one or more; and multiple means two or more than two. In the description of the present application, the terms "first", "second", "third" and the like are only used to distinguish the described purposes, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.
[0028] In the present specification, the reference "one embodiment" or "some embodiments" and the like means that the specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the present application. Therefore, the terms "include", "contain", "have" and their variants in the present specification mean "include but not limited to", unless otherwise specifically emphasized.
[0029] It should be noted that in the embodiments of the present application, the association relationship of the associated objects described by "and / or" represents that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / ", if not specially stated, generally represents that the associated objects before and after the character " / " are in an "or" relationship.
[0030] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A is connected to B, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.
[0031] It should be noted that when the TFT-LCD display panel displays, each frame of display image displayed by the TFT-LCD display panel is refreshed by means of line-by-line scanning.
[0032] Specifically, the gate driver is connected to each pixel row in the display panel through a plurality of gate lines, and the source driver is connected to each pixel column in the display panel through a plurality of data lines.
[0033] When the TFT-LCD display panel displays the current display frame, the timing controller controls the gate driver to turn on each pixel row through the gate line in turn. When a certain pixel row is turned on, the driving transistor (driving TFT) of all pixels in the pixel row is turned on, and the timing controller controls the source driver to load the gray scale voltage corresponding to the pixel row on the data line. The gray scale voltage corresponding to the pixel row on the data line charges the pixel capacitance of each pixel in the pixel row through the driving TFT of each pixel. After the scanning period corresponding to the pixel row ends, the timing controller controls the gate driver to turn off the pixel row through the gate line. The driving TFT of the pixel row is turned off, and the voltage on the pixel capacitance of each pixel in the pixel row is maintained until the current display frame ends.
[0034] With the continuous development of the consumer electronics market, users have higher and higher requirements for display devices, and high resolution, high refresh rate and narrow frame design have become important indicators of high-end TFT-LCD display panels. In order to meet the requirements of high resolution, high refresh rate and narrow frame design of TFT-LCD display panel, the width of data line is continuously compressed in related technologies.
[0035] Meanwhile, in order to improve the stability of TFTs in the display panel, reduce the leakage current, ensure the gray scale retention capability and take into account the process yield, the TFTs in the display panel are usually designed with a relatively large channel length.
[0036] Figure 1 is a driving timing diagram of a conventional display panel in the related art. Please refer to Figure 1 In the above driving mode, after the first pixel row (usually located at the top or bottom of the display panel according to the scanning order, hereinafter referred to as the “first pixel row”) in a display frame is scanned first and turned on, the pixel capacitance of each pixel in the first pixel row needs to be charged from 0V to the expected gray scale voltage (14V) within a limited charging time.
[0037] However, due to the RC delay caused by the small width of the data line and / or the large channel length of the TFT, the first pixel row scanned first is difficult to be charged to the expected gray scale voltage within the limited charging time, resulting in insufficient deflection angle of the liquid crystal molecules, and thus the brightness of the first pixel row cannot reach the expected brightness.
[0038] Figure 2 is another driving timing diagram of a conventional display panel in the related art. Please refer to Figure 1 and Figure 2 In contrast, in the above driving mode, after the first pixel row scanned first, the second pixel row is scanned. Since the voltage on the pixel capacitance of each pixel in the previous pixel row is maintained after the previous pixel row is turned off, a certain pre-charge can be formed for the next pixel row, so that each pixel row after the second pixel row does not have to be charged from 0V after being turned on, but from a higher initial voltage (8V), and thus can be charged to the expected gray scale voltage within the limited charging time, so that the deflection angle of the liquid crystal molecules is sufficient, and the brightness of each pixel row can reach the expected brightness.
[0039] In the case where the brightness of the first pixel row cannot reach the expected brightness, but the brightness of each pixel row after the second pixel row scanned after the first pixel row scanned first can reach the expected brightness, a horizontal dark line will appear at the top or bottom of the display panel in the overall vision, affecting the overall display effect of the display panel.
[0040] Based on the above problems, as shown in Figure 3 Figure 3 This is a schematic diagram of the structure of a display device provided in an exemplary embodiment of the present disclosure. In this embodiment, the display device 100 includes: a display panel 11, a source driver 14, and a timing controller 12. A display frame of the display panel 11 includes a display period and a blanking period. The display period includes multiple scan line periods, and the blanking period includes multiple blank line periods. The source driver 14 is connected to each pixel column in the pixel array of the display panel 11 through multiple data lines.
[0041] The timing controller 12 is used to acquire the output grayscale of the target scan line cycle and the first target output grayscale, and output them to the source driver 14. The target scan line cycle is adjacent to the target blank line cycle in the blanking cycle of the current display frame in timing, and the target blank line cycle in the blanking cycle of the current display frame is located before the target scan line cycle in timing.
[0042] The source driver 14 is used to output the gray level voltage corresponding to the first target output gray level to each data line during the target blank line period in the blanking period of the current display frame, and to output the gray level voltage corresponding to the output gray level of the target scan line period to each data line during the target scan line period.
[0043] Specifically, in this embodiment, the display panel 11 is a thin-film transistor liquid crystal display panel 11. The display area of the display panel 11 is provided with a pixel array including multiple pixels. The pixel array includes multiple pixel rows and multiple pixel columns, and each pixel row and each pixel column includes multiple pixel units. The pixels are the basic units constituting the displayed image; in this embodiment, the pixels may include red pixels, green pixels, or blue pixels.
[0044] The display panel 11 includes multiple data lines. The source driver 14 is connected to each pixel column in the pixel array via the multiple data lines. The display device 100 also includes a gate driver, which is connected to each pixel row in the pixel array via multiple gate lines.
[0045] In this embodiment, a display frame of the display panel 11 includes a display period also called the active display area (Vactive area) and a blanking period also called the blank area (Vblank area).
[0046] Figure 4 This is one of the timing structure diagrams of a display frame in an exemplary embodiment of this disclosure. Figure 5 This is a second schematic diagram of the timing structure of a display frame in an exemplary embodiment of this disclosure. Please refer to... Figure 4 and Figure 5The display cycle refers to the time period during which the display panel 11 displays effective image data. The display cycle includes multiple scan line cycles, and each scan line cycle corresponds to the scanning start time of one pixel line in the pixel array.
[0047] The blanking period refers to the time interval in a display frame that is located before or after the display period during which no actual display occurs. During the blanking period, the effective pixel rows are not refreshed. It is usually used to send control commands or perform reset operations. The blanking period includes multiple blank row cycles.
[0048] For example, in an FHD (Full High Definition) standard timing, the total number of line cycles (Vtotal) of a display frame can be 1125, where the display cycle includes 1080 scan line cycles (corresponding to 1080 pixel rows) and the blanking cycle includes 45 blank line cycles.
[0049] During any scan line cycle in the display cycle of the current display frame, the gate driver selects the pixel row corresponding to the scan line cycle, and the source driver 14 outputs the gray level voltage corresponding to the output gray level of each scan line cycle to each data line during the scan line cycle, thereby charging the pixel capacitor of each pixel in the pixel row corresponding to the scan line cycle.
[0050] It should be noted that the target scan line cycle in this embodiment refers to the scan cycle corresponding to the pixel line in the pixel array that is prone to display abnormalities due to insufficient charging when the display panel 11 is displaying an image.
[0051] It is understood that the target scan line period in this embodiment can be the first scan line period in the timing sequence of the display period of the current display frame, or it can be the first scan line period in the timing sequence of the display period of the next frame to be displayed.
[0052] It is understood that, depending on the scanning order required for different scenarios, the pixel row corresponding to the first scanning row cycle in the display frame display cycle in this embodiment can be either the first pixel row in the pixel array of the display panel 11 from top to bottom or the first pixel row in the pixel array of the display panel 11 from bottom to top.
[0053] It should be noted that the target blank line cycle refers to the blank line cycle that is sequentially adjacent to and precedes the aforementioned target scan line cycle.
[0054] In some embodiments, the target blank line period in the blanking cycle is the last target number of blank line periods in the timing of the blanking cycle; the target number can be any one of 1, 2 or 3.
[0055] Specifically, since a blanking cycle of a display frame typically includes dozens of blank line cycles, in order to ensure the pre-filling effect of the target scan line cycle without occupying too many blank line cycles in the blanking cycle, the last one, the last two, or the last three blank line cycles in the timing sequence of the blanking cycle can be determined as the target blank line cycle in the blanking cycle of the display frame.
[0056] It should be noted that when the load on the display panel 11 is large or the RC delay is severe, the last two or three blank line cycles in the timing of the blanking cycle of the display frame can be used to determine the target blank line cycle in the blanking cycle of the display frame, so as to further extend the precharge time of the target scan line cycle.
[0057] The display device in this embodiment flexibly selects the last 1, 2, or 3 blank line cycles in the blanking cycle as the target blank line cycle, providing an adjustable precharge duration scheme. Under conditions of high display panel load or severe RC delay, multiple blank line cycles can be used to further extend the voltage establishment time, ensuring that the data line voltage is completely stable before the pixel row corresponding to the target scan line cycle is opened, thereby adapting to the driving requirements of different panel specifications.
[0058] In some embodiments, the target blank row period in the blanking cycle is the last blank row period in the timing sequence of the blanking cycle.
[0059] Specifically, in order to maximize the resource efficiency of the blanking cycle of the display frame and solve the problem of insufficient charging within the target scan line cycle, this embodiment determines the last blank line cycle in the timing of the blanking cycle of the display frame as the target blank line cycle in the blanking cycle.
[0060] For example, if the blanking period of a display frame contains 45 blank line cycles, then the 1st to 44th blank line cycles are used to transmit regular control commands or are in a high-impedance state. Only the 45th blank line cycle is defined as the target blank line cycle in the blanking period of the display frame, and is used by the source driver 14 to output the grayscale voltage corresponding to the first target output grayscale to each data line. This approach requires minimal modification to the existing timing architecture and is sufficient to meet the precharge requirements in most scenarios.
[0061] The display device in this embodiment uses only the last blank line cycle in the timing of the blanking cycle for pre-charging. This effectively solves the problem of insufficient charging of the first pixel line while maximizing the utilization efficiency of blanking cycle resources. It also minimizes the impact on the transmission of other control commands or reset operations in the blanking cycle, achieving a balance between improved display effect and resource consumption.
[0062] In this embodiment, the timing controller 12 can acquire the output grayscale of the target scan line cycle and the first target output grayscale before the target blank line cycle in the blanking period of the current display frame. The first target output grayscale serves as the basis for the source driver 14 to output grayscale voltage to each data line during the blanking period of the current display frame.
[0063] The timing controller 12 can acquire the output grayscale of the target scan line cycle based on the grayscale data sent by the central processing unit (CPU) or graphics processing unit (GPU).
[0064] The timing controller 12 can obtain the first target output grayscale through data query, numerical calculation, or mathematical statistics. In this embodiment, the specific method by which the timing controller 12 obtains the first target output grayscale is not limited.
[0065] As an optional embodiment, the timing controller 12 is specifically used to determine the output grayscale of the target scan line cycle as the first target output grayscale, or to calculate another output grayscale based on the output grayscale of the target scan line cycle as the first target output grayscale.
[0066] Optionally, to minimize the problem of insufficient pixel capacitor charging during the target scan line cycle, the timing controller 12 in this embodiment can copy the output grayscale of the target scan line cycle as a first target output grayscale. This first target output grayscale is used by the source driver 14 to output the corresponding grayscale voltage to each data line during the target blank line cycle in the blanking period of the current display frame. For example, if the grayscale voltage corresponding to the output grayscale of the target scan line cycle is 14V, then the source driver 14 will also output a 14V grayscale voltage to each data line during the target blank line cycle in the blanking period of the current display frame. In this way, when the target scan line cycle is actually started, the voltage of each data line is already 14V. The pixel row corresponding to the target scan line cycle only needs to maintain this voltage, without having to go through the process of boosting from 0V or 8V to 14V, which greatly compensates for the charging loss of the pixel row corresponding to the target scan line cycle due to RC delay.
[0067] Optionally, in this embodiment, an overdrive approach can also be used to calculate the first target output gray level based on the output gray level of the target scan line cycle. For example, if the gray level voltage corresponding to the output gray level of the target scan line cycle is 14V, an overdrive approach can be used to calculate the first target output gray level, resulting in a gray level voltage slightly higher than 14V (e.g., 14.5V), to further accelerate the charging process of the target scan line cycle.
[0068] Optionally, the timing controller 12 can also be used to determine a preset output grayscale as the first target output grayscale. The preset output grayscale can be predefined based on prior knowledge and / or actual conditions. In this embodiment, the specific value of the preset output grayscale is not limited.
[0069] In this embodiment, the display device directly copies the output grayscale of the target scan line cycle as the first target output grayscale, which minimizes the voltage difference between each data line and the pixel electrode at the moment the pixel row corresponding to the target scan line cycle is turned on, thereby significantly improving charging efficiency. The first target output grayscale is calculated based on the output grayscale of the target scan line cycle, which can further accelerate the charging speed of the pixel row corresponding to the target scan line cycle by providing a higher pre-charge voltage, thus meeting the needs of display panels with larger loads or more severe RC delays.
[0070] After acquiring the output grayscale of the target scan line cycle and the first target output grayscale, the timing controller 12 can output the output grayscale of the target scan line cycle and the first target output grayscale to the source driver 14.
[0071] Figure 6 This is a timing diagram of the drive for the display panel in an exemplary embodiment of this disclosure. Please refer to... Figure 6 Within the target blank line period of the current display frame, the source driver 14 can output the gray level voltage corresponding to the first target output gray level to each data line based on the first target output gray level, thereby pre-charging the pixel row corresponding to the target scan line period before the target scan line period, and then outputting the gray level voltage corresponding to the output gray level of the target scan line period to each data line within the target scan line period after the target blank line period of the current display frame.
[0072] in, Figure 6 In V 0 indicates the gray level voltage corresponding to the first target output gray level; Figure 6 In V 1 represents the gray level voltage corresponding to the output gray level of the target scan line cycle.
[0073] In this embodiment, the display device determines the first scan line cycle in the display period of the current display frame, or the first scan line cycle in the display period of the next frame to be displayed, as the target scan line cycle. It also uses the target blank line cycle in the display period of the current display frame, which is adjacent to and precedes the target scan line cycle, as the pre-charge phase of the target scan line cycle. After obtaining the output grayscale of the target scan line cycle and the first target output grayscale through the timing controller, the source driver outputs the grayscale voltage corresponding to the first target output grayscale to each data line within the target blank line cycle of the current display frame's display period. Furthermore, it outputs the grayscale voltage corresponding to the output grayscale of the target scan line cycle to each data line within the target scan line cycle. Gray-scale voltage can precharge the pixel rows corresponding to the target scan line cycle using the blanking cycle, so that each data line already has a high or desired initial voltage when the target scan line cycle starts. This effectively increases the effective charging time of the pixel capacitor within the target scan line cycle, and compensates for insufficient charging caused by RC delay due to the small width of the data lines or the large channel length of the thin-film transistor in the display panel. Without changing the physical structure of the display panel, it can charge the pixel rows corresponding to the target scan line cycle to the expected gray-scale voltage within the limited charging time of the target scan line cycle, thereby eliminating the problem of horizontal dark lines caused by insufficient brightness of the first pixel row scanned in the display frame, and significantly improving the overall display quality of the display panel.
[0074] Please refer to this again. Figure 4 In one implementation, the display period in the display frame is located before the blanking period in terms of timing; the target scan line period is the first scan line period in terms of timing in the display period of the next frame to be displayed in the current display frame.
[0075] Specifically, in this embodiment, a complete display frame includes a display period and a blanking period in sequence.
[0076] Accordingly, the blanking period of the current display frame is located after the end of the display period of the current display frame in terms of timing, and the display period of the next frame to be displayed is located after the end of the blanking period of the current display frame in terms of timing.
[0077] Therefore, in order to solve the problem of insufficient charging in the first scan line cycle of the display cycle of the next frame to be displayed in the current display frame, in this embodiment, the first scan line cycle of the display cycle of the next frame to be displayed can be determined as the target scan line cycle.
[0078] Accordingly, since the display period of the next frame to be displayed is located after the end of the blanking period of the current display frame in terms of timing, in this embodiment, the last or last few blank line periods in the blanking period of the current display frame can be determined as the target blank line period in the blanking period of the current display frame.
[0079] In this embodiment, the timing controller 12 can acquire the output grayscale of the first scan line cycle and the first target output grayscale in the timing of the display cycle of the next frame to be displayed within the target blank line cycle of the blanking cycle of the current display frame.
[0080] Within the blanking period of the current display frame, the source driver 14 can output the gray level voltage corresponding to the first target output gray level to each data line based on the first target output gray level. This enables pre-charging of the pixel row corresponding to the first scan line cycle in the timing of the next display frame before the first scan line cycle in the timing of the display period of the next display frame. Consequently, within the first scan line cycle in the timing of the next display frame, the source driver 14 outputs the gray level voltage corresponding to the output gray level in the first scan line cycle in the timing of the display period of the next display frame to each data line.
[0081] In this embodiment, when the display period in the display frame is located before the blanking period in the timing sequence, the display device determines the first scan line period of the display period of the next frame to be displayed as the target scan line period setting. It can utilize the last few blank line periods in the blanking period of the current display frame to precharge the first scan line period of the display period of the next frame to be displayed, ensuring that during the continuous switching of display frames, the pixel row corresponding to the first scan line period in each display frame can be charged to the expected grayscale voltage, thus ensuring the uniformity and stability of the display panel during dynamic display.
[0082] In some embodiments, the timing controller 12 is further configured to acquire the output grayscale of the first scan line cycle and the second target output grayscale of the first display frame after the display panel 11 is powered on, and output them to the source driver 14.
[0083] The source driver 14 is also used to output a gray level voltage corresponding to the second target output gray level to each data line within a preset duration before the first scan line cycle in the display cycle of the first display frame, and to output a gray level voltage corresponding to the output gray level of the first scan line cycle in the display cycle of the first display frame to each data line within the first scan line cycle in the display cycle of the first display frame, wherein the preset duration is equal to the duration of the target blank line cycle.
[0084] Specifically, if the blanking period of the current display frame is after the end of the display period of the current display frame in terms of timing, and if the current display frame is the first display frame in the timing after the display panel 11 is powered on, then there is no blanking period of the previous display frame before the current display frame, and it is impossible to precharge the first scan line cycle in the display period of the first display frame.
[0085] Therefore, in order to prevent insufficient charging in the first scan line cycle of the first display frame in the timing sequence after the display panel 11 is powered on, the timing controller 12 in this embodiment can acquire the output grayscale and the second target output grayscale of the first scan line cycle in the display cycle of the first display frame before the first scan line cycle in the display cycle of the first display frame after the display panel 11 is powered on.
[0086] Optionally, in this embodiment, the timing controller 12 may determine the output grayscale of the first scan line cycle in the display period of the first display frame as the second target output grayscale when the output grayscale of the first scan line cycle in the display period of the first display frame is obtained. Alternatively, it may determine another output grayscale calculated based on the output grayscale of the first scan line cycle in the display period of the first display frame as the second target output grayscale.
[0087] After obtaining the output grayscale of the first scan line cycle and the second target output grayscale of the first display frame in the display cycle, the timing controller 12 can send the output grayscale of the first scan line cycle and the second target output grayscale of the first display frame to the source driver 14.
[0088] The source driver 14 can output a grayscale voltage corresponding to the second target output grayscale to each data line within a preset time period before the first scan line cycle in the display cycle of the first display frame, thereby pre-charging the pixel row corresponding to the first scan line cycle in the display cycle of the first display frame before the first scan line cycle in the display cycle of the first display frame, and then outputting a grayscale voltage corresponding to the output grayscale of the first scan line cycle in the display cycle of the first display frame to each data line within the first scan line cycle in the display cycle of the first display frame.
[0089] In this embodiment, the display device sets a preset duration before the first display frame in the timing sequence after the display panel is powered on, and pre-charges the pixel row corresponding to the first scan line cycle in the first display frame. This solves the problem that there is no blanking cycle of the previous display frame when the display panel is powered on, and ensures that the first lit pixel row in the first display frame after the display panel is powered on can also receive sufficient charging. This prevents the display problem of the first dark line appearing at the moment the display panel is powered on, and improves the user's visual experience when booting up.
[0090] As an optional embodiment, the timing controller 12 is specifically used to obtain a first target output grayscale based on the output grayscale of the last scan line cycle in the display cycle of the current display frame.
[0091] It should be noted that when the display cycle in the display frame is located before the blanking cycle in terms of timing, the timing controller 12 can obtain the first target output grayscale based on the output grayscale of the last scan line cycle in the display cycle of the current display frame under certain specific driving scenarios, such as in order to maintain the continuity of voltage in the data line, or in order to match the polarity reversal requirement in certain inversion driving modes.
[0092] Optionally, the timing controller 12 in this embodiment can copy the output grayscale of the last scan line cycle in the display period of the current display frame as the first target output grayscale, which is used by the source driver 14 to output the grayscale voltage corresponding to the first target output grayscale to each data line in the target blank line cycle in the blanking period of the current display frame.
[0093] Alternatively, in this embodiment, an overdrive approach can be used to calculate the first target output grayscale based on the output grayscale of the last scan line cycle in the display cycle of the current display frame.
[0094] In this embodiment, the display device obtains the first target output grayscale based on the output grayscale of the last scan line cycle in the current display frame when the display period is located before the blanking period in the display frame. This can maintain the continuity of the data line voltage during frame switching in a specific driving mode, avoid coupling noise caused by voltage change, and provide a stable initial electrical environment for the display of subsequent target scan line cycles.
[0095] Please refer to Figure 5 In one implementation, the display period in the display frame is located after the blanking period in terms of timing; the target scan line period is the first scan line period in terms of timing in the display period of the current display frame.
[0096] Specifically, in this embodiment, a complete display frame sequentially includes a blanking period and a display period. Accordingly, the display period of the current display frame is located after the end of the blanking period of the current display frame, and the blanking period of the next frame to be displayed is located after the end of the display period of the current display frame.
[0097] Therefore, in order to solve the problem of insufficient charging in the first scan line cycle in the display period of the current display frame, this embodiment can determine the first scan line cycle in the display period of the current display frame as the target scan line cycle.
[0098] Accordingly, since the display period of the current display frame is located after the end of the blanking period of the current display frame in terms of timing, in this embodiment, the last or last few blank line periods in the blanking period of the current display frame in terms of timing can be determined as the target blank line period in the blanking period of the current display frame.
[0099] In this embodiment, the timing controller 12 can acquire the output grayscale of the first scan line cycle and the first target output grayscale in the timing of the display cycle of the current display frame within the blanking period of the previous display frame of the current display frame.
[0100] Within the target blank line period of the blanking period of the current display frame, the source driver 14 can output the gray level voltage corresponding to the first target output gray level to each data line based on the first target output gray level. This enables pre-charging of the pixel row corresponding to the first scan line period in the timing of the current display frame before the first scan line period in the timing of the current display frame, and then outputting the gray level voltage corresponding to the output gray level of the first scan line period in the timing of the current display frame to each data line within the first scan line period in the timing of the current display frame.
[0101] In this embodiment, when the display period in the display frame is located after the blanking period in the timing sequence, the display device determines the first scan line period of the display period of the current display frame as the target scan line period setting. It can utilize the last few blank line periods in the blanking period of the current display frame to pre-charge the first scan line period of the display period of the current display frame, ensuring that when the current display frame starts to display, the pixel row corresponding to the first scan line period in the current display frame can be charged to the expected grayscale voltage, eliminating the problem of horizontal dark lines on the display panel caused by insufficient brightness of the first pixel row scanned first in the display frame.
[0102] As an optional embodiment, the timing controller 12 is specifically used to obtain a first target output grayscale based on the output grayscale of the last scan line cycle in the display cycle of the previous display frame of the current display frame.
[0103] It should be noted that when the display cycle in the display frame is located after the blanking cycle in terms of timing, the timing controller 12 can obtain the first target output grayscale based on the output grayscale of the last scan line cycle in the display cycle of the previous display frame in certain specific driving scenarios, such as in order to maintain the continuity of voltage in the data line, or in order to match the polarity reversal requirement in certain inversion driving modes.
[0104] Optionally, the timing controller 12 in this embodiment can copy the output grayscale of the last scan line cycle in the display period of the previous display frame of the current display frame as the first target output grayscale, which is used by the source driver 14 to output the grayscale voltage corresponding to the first target output grayscale to each data line in the target blank line cycle in the blanking period of the current display frame.
[0105] Alternatively, in this embodiment, an overdrive approach can be used to calculate the first target output grayscale based on the output grayscale of the last scan line cycle in the display cycle of the previous display frame of the current display frame.
[0106] In this embodiment, when the display period in the display frame is located after the blanking period in the timing sequence, the display device obtains the first target output gray level based on the output gray level of the last scan line cycle in the timing sequence of the previous display frame. This can maintain the continuity of the data line voltage during frame switching in a specific driving mode, avoid coupling noise caused by voltage change, and provide a stable initial electrical environment for the display of subsequent target scan line cycles.
[0107] Figure 7 This is a flowchart illustrating a display control method provided in an exemplary embodiment of this disclosure. Please refer to... Figure 7 This embodiment also provides a display control method applied to a display device 100. The method includes: step 701, obtaining the output grayscale of the target scan line cycle and the first target output grayscale, wherein the target scan line cycle is temporally adjacent to the target blank line cycle in the blanking cycle of the current display frame, and the target blank line cycle in the blanking cycle of the current display frame is temporally located before the target scan line cycle.
[0108] Step 702: During the target blank line period in the blanking period of the current display frame, output the gray level voltage corresponding to the first target output gray level to each data line, and during the target scan line period, output the gray level voltage corresponding to the output gray level of the target scan line period to each data line.
[0109] It should be noted that the specific execution steps of the display control method in this embodiment can refer to the content of the above embodiments. They will not be repeated in this embodiment.
[0110] In this embodiment, the first scan line cycle in the display cycle of the current display frame, or the first scan line cycle in the display cycle of the next frame to be displayed, is determined as the target scan line cycle. The target blank line cycle in the display cycle of the current display frame, which is adjacent to and precedes the target scan line cycle, is used as the pre-charge stage of the target scan line cycle. After the timing controller obtains the output grayscale of the target scan line cycle and the first target output grayscale, the source driver outputs the grayscale voltage corresponding to the first target output grayscale to each data line within the target blank line cycle of the current display frame's display cycle. Then, within the target scan line cycle, it outputs the grayscale voltage corresponding to the output grayscale of the target scan line cycle to each data line. The pressure-based pre-charging technology utilizes the blanking cycle to pre-charge the pixel rows corresponding to the target scan line cycle. This ensures that each data line already possesses a high or desired initial voltage when the target scan line cycle begins, effectively increasing the effective charging time of the pixel capacitors within the target scan line cycle. This compensates for insufficient charging caused by RC delay due to the small width of the data lines or the large channel length of the thin-film transistors in the display panel. Without altering the physical structure of the display panel, it can charge the pixel rows corresponding to the target scan line cycle to the expected grayscale voltage within the limited charging time of the target scan line cycle. This eliminates the problem of horizontal dark lines caused by insufficient brightness of the first pixel row scanned in the display frame, significantly improving the overall display quality of the display panel.
[0111] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0112] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A display device comprising: The display panel, the source driver and the timing controller are characterized in that one display frame of the display panel comprises a display period and a blanking period, the display period comprises a plurality of scan line periods, and the blanking period comprises a plurality of blank line periods; the source driver is connected with each pixel column in a pixel array of the display panel through a plurality of data lines; The timing controller is configured to acquire an output gray scale of a target scan line period and a first target output gray scale, the target scan line period is adjacent to a target blank line period in a blanking period of a current display frame in time sequence, and the target blank line period in the blanking period of the current display frame is located before the target scan line period in time sequence; The source driver is configured to output a gray scale voltage corresponding to the first target output gray scale to each data line in the target blank line period in the blanking period of the current display frame, and output a gray scale voltage corresponding to the output gray scale of the target scan line period to each data line in the target scan line period.
2. The display device according to claim 1, wherein The display period in the display frame is located before the blanking period in time sequence; and the target scan line period is a first scan line period in a display period of a next display frame of the current display frame in time sequence.
3. The display device according to claim 1, wherein The display period in the display frame is located after the blanking period in time sequence; and the target scan line period is a first scan line period in the display period of the current display frame in time sequence.
4. The display device according to claim 2, wherein The timing controller is further configured to acquire an output gray scale of a first scan line period in a display period of a first display frame after the display panel is powered on and a second target output gray scale, and output to the source driver; The source driver is further configured to output a gray scale voltage corresponding to the second target output gray scale to each data line within a preset time period before the first scan line period in the display period of the first display frame, and output a gray scale voltage corresponding to the output gray scale of the first scan line period in the display period of the first display frame to each data line within the first scan line period in the display period of the first display frame, the preset time period being equal to a time length of the target blank line period.
5. The display device according to claim 1, wherein The timing controller is specifically configured to determine the output gray scale of the target scan line period as the first target output gray scale, or calculate another output gray scale based on the output gray scale of the target scan line period as the first target output gray scale.
6. The display device according to claim 2, wherein The timing controller is specifically configured to acquire the first target output gray scale based on an output gray scale of a last scan line period in the display period of the current display frame.
7. The display device according to claim 3, wherein The timing controller is specifically configured to acquire the first target output gray scale based on an output gray scale of a last scan line period in a display period of a last display frame of the current display frame.
8. The display device according to any one of claims 1 to 7, wherein The target blank line period in the blanking period is a last target number of blank line periods in time sequence in the blanking period; and the target number is any one of 1, 2 or 3.
9. The display device according to any one of claims 1 to 7, wherein The target blank line period in the blanking period is a last blank line period in time sequence in the blanking period.
10. A display control method characterized by comprising: The method is applied to a display device, and the method comprises: obtaining an output gray scale of a target scanning line period and a first target output gray scale, the target scanning line period being adjacent to a target blank line period in a blanking period of a current display frame in time sequence, and the target blank line period in the blanking period of the current display frame being located before the target scanning line period in time sequence; outputting a gray scale voltage corresponding to the first target output gray scale to each data line in the target blank line period in the blanking period of the current display frame, and outputting a gray scale voltage corresponding to an output gray scale of the target scanning line period to each data line in the target scanning line period.