A frequency distribution system and method based on fractional frequency division phase-locked loop.

Abstract

This invention provides a frequency distribution system and method based on a fractional-frequency-locked loop (FLL). A clock signal is embedded in the data link via a serial transceiver. At the receiving end, a clock data recovery unit accurately extracts the upstream reference clock from the data stream. Subsequently, based on the FLL, a high-precision phase detector obtains the phase difference, and a reconfigurable digital loop filter performs proportional-integral operations and noise filtering to generate a control signal that drives the FLL output to synchronize with the reference clock. This system achieves accurate regeneration and transmission of frequency and phase information across multiple nodes, effectively suppressing accumulated phase drift and reducing transmission jitter. It also avoids the high cost of deploying dedicated optical fibers, significantly improving frequency distribution accuracy and stability, and providing a low-cost, highly flexible synchronization solution for large-scale networking.

Description

Technical Field

[0001] This invention relates to the field of optical network communication technology, and in particular to a frequency distribution system and method based on fractional frequency division phase-locked loop. Background Technology

[0002] With the rapid development of emerging applications such as 5G communication, metaverse, and cloud services, data traffic in optical access networks and data center optical switching networks is growing exponentially, placing higher demands on network bandwidth and throughput. In optical network communication modes based on time-frequency synchronization and time slot distribution, to achieve higher aggregated traffic carrying capacity, it is necessary to continuously refine the time slot granularity, which poses a severe challenge to high-precision time synchronization among nodes in the network. Frequency synchronization, as the foundation of time synchronization, directly affects the collaborative performance of the entire distributed system. If the clock frequencies of each node differ, even if time alignment is achieved at a certain moment, the phase will gradually drift over time due to the accumulation of frequency deviations, ultimately disrupting system synchronization.

[0003] Currently, the main technical solutions for frequency distribution include the following three: First, frequency distribution technology based on ServoClock, which periodically measures clock offset through the PTP protocol and dynamically adjusts the local oscillator frequency using a loop controller. However, its clock error measurement is periodic, and significant phase drift can easily occur due to the accumulation of frequency errors over long measurement intervals, making it difficult to meet the requirements of high-precision frequency distribution. Second, frequency distribution technology based on dedicated fiber optic links, which transmits clock signals through dedicated fiber optics and uses a feedback loop to compensate for transmission delay jitter. Although this solution can achieve good frequency stability, it requires the deployment of high-cost dedicated fiber optics, making it difficult to implement in space-constrained scenarios such as existing data centers, resulting in poor application flexibility. Third, frequency distribution technology based on link-recovered clocks, which recovers clock signals from the data link using the CDR module in the serial transceiver. While this solution can reduce hardware costs, the quality of its recovered clock is heavily dependent on the quality of the link signal, and its performance deteriorates significantly when channel attenuation is large. Furthermore, commonly used binary phase detectors can only provide leading or lagging signals and cannot output linear phase errors, resulting in large clock jitter and limited accuracy.

[0004] Therefore, there is an urgent need in this field for a system solution that can achieve high-precision frequency distribution among large-scale, multi-cascaded nodes under the premise of low cost and flexible networking, so as to overcome the limitations of existing technologies in terms of accuracy, cost and applicable scenarios. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a frequency distribution system and method based on fractional frequency division phase-locked loop (FLL) to eliminate or improve one or more defects in the prior art, and solve the problems that existing frequency synchronization schemes are costly and cannot adapt to the needs of large-scale flexible networking.

[0006] One aspect of the present invention provides a frequency distribution system based on a fractional-frequency-locked loop (FLL). The system includes a master node and multiple levels of sub-nodes. The master node and the sub-nodes are connected tier by tier via serial transceivers. The master node embeds a reference clock signal into a serial data stream and sends it to the first-level sub-node for clock synchronization. Each level of sub-node synchronizes its local clock signal based on the clock signal from the upper level and then embeds the local clock signal into a serial data stream and sends it to the downstream sub-node, thereby realizing frequency distribution of the reference clock signal among any number of tiered sub-nodes.

[0007] The sub-node includes: a serial transceiver receiver, a first phase detector, a first loop filter, a fractional frequency-locked loop, and a serial transceiver transmitter;

[0008] The serial transceiver receiver is used to receive the upstream serial data stream and recover the reference clock signal from the upstream serial data stream through the clock data recovery unit; the first phase detector is used to detect the phase difference measurement value between the local reference clock signal and the local clock signal output by the fractional-frequency-locked loop; the first loop filter is used to filter and adjust the phase difference measurement value based on the proportional-integral controller to obtain a control signal; the fractional-frequency-locked loop is used to receive the control signal and output a local reference clock signal that is frequency-locked and phase-stable with the reference clock signal; the serial transceiver transmitter is used to embed the local reference clock signal into the serial data stream and send it to the downstream child node.

[0009] In some embodiments, the clock data recovery unit extracts the transition pulse synchronized with the bit rate through an edge detector, performs an open-loop scan of the numerically controlled oscillator within a preset frequency range, and outputs the reference clock signal.

[0010] In some embodiments, the first phase detector is an analog phase detector or a binary phase detector;

[0011] Alternatively, the first phase detector includes a delay chain composed of delay units, an array of D flip-flops connected to each node of the delay chain, and a back-end encoder. The reference clock signal is injected into the delay chain as a start signal for propagation, and the local clock signal is used as a stop signal. When the stop signal arrives, the state of each node on the delay chain is latched by the D flip-flop array to obtain a thermometer code consisting of consecutive 1s or 0s. The back-end encoder locks the transition position of the thermometer code to detect the phase difference measurement value.

[0012] In some embodiments, the first loop filter is implemented using a programmable gate array (PGA) to input the phase difference measurement as the current error into a parallel proportional branch and an integral branch, respectively. The proportional branch multiplies the current error by a first coefficient to obtain a fast response component proportional to the instantaneous error. The integral branch adds the current error to the sum of historical errors in an accumulator and then multiplies it by a second coefficient to generate a cumulative correction component for eliminating steady-state errors. The fast response component and the cumulative correction component are added together to form the control signal.

[0013] In some embodiments, the adjustment steps for the first coefficient and the second coefficient include:

[0014] Initialize the loop by setting the second coefficient to 0, and gradually increasing the first coefficient by 50% each time a phase step is applied until the loop response shows an overshoot of 10% to 15%. Then, reduce the current first coefficient by 20% to 30%.

[0015] While maintaining the first coefficient, the second coefficient is gradually increased by applying a frequency step and increasing by 100%. When the amplitude of low-frequency oscillation exceeds 5% of the steady-state value, or the lock-in time is extended by more than 50%, the current second coefficient is reduced by 25% to 40%.

[0016] In some embodiments, the fractional frequency division phase-locked loop includes:

[0017] A fractional frequency divider is used to divide the control signal and the output signal of the fractional frequency-locked loop to obtain a feedback signal.

[0018] The second phase detector is used to measure the phase difference between the local clock signal and the feedback signal;

[0019] A charge pump for generating a control current based on the phase difference;

[0020] The second loop filter is used to filter out high-frequency noise from the control current and convert it into a control voltage;

[0021] A voltage-controlled oscillator is used to linearly adjust the output of the local reference clock signal according to the control voltage.

[0022] In some embodiments, the serial transceiver transmitting end includes a parallel data input end, an encoder, a parallel-to-serial converter, and a transmit driver; the serial transceiver receiving end includes a receive equalizer, a clock data recovery unit, a serial-to-parallel converter, and a decoder.

[0023] In some embodiments, the encoder at the transmitter end of the serial transceiver embeds the clock signal into the serial data stream using 64b / 66b encoding and scrambling.

[0024] In some embodiments, the master node and the child node are connected using a star-ring hybrid topology.

[0025] On the other hand, the present invention also provides a frequency distribution method based on a fractional frequency-locked loop (FLL). The method operates based on the aforementioned frequency distribution system based on a FLL. The master node generates a reference clock signal, embeds it into a serial data stream, and sends it to the first-level sub-node for clock synchronization. After synchronizing their local clock signals based on the upper-level clock signal, each level of the sub-node embeds its local clock signal into a serial data stream and sends it to the downstream sub-node, thereby realizing frequency distribution of the reference clock signal among any number of cascaded sub-nodes.

[0026] The frequency distribution system and method based on fractional-frequency-locked loop (FFL) of this invention embeds a clock signal in the data link through a serial transceiver. At the receiving end, a clock data recovery unit accurately extracts the upstream reference clock. Subsequently, based on the core synchronization mechanism of the FLL, a high-linearity phase detector obtains the accurate phase difference, and a reconfigurable digital loop filter performs proportional-integral operations and noise filtering on the error signal to dynamically generate a control signal. This signal drives the FLL to output a local clock that is frequency-locked and phase-consistent with the reference clock, thereby realizing the regeneration and transmission of phase information at each node. Ultimately, a high-precision distributed frequency synchronization network that can suppress accumulated drift, reduce transmission jitter, and does not rely on dedicated channels is constructed. This system effectively overcomes the phase drift problem caused by the accumulation of periodic measurement errors in traditional schemes, avoids the high-cost deployment limitations of dedicated optical fibers, significantly improves frequency distribution accuracy and phase stability, and achieves low-cost, high-flexibility multi-level frequency synchronization in large-scale networking environments.

[0027] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows, and will also become apparent in part to those skilled in the art upon studying the description, or may be learned by practice of the invention. The objects and other advantages of the invention can be realized and obtained by means of the structures specifically pointed out in the specification and drawings.

[0028] Those skilled in the art will understand that the objectives and advantages achievable with the present invention are not limited to those specifically described above, and that the above and other objectives achievable with the present invention will become clearer from the following detailed description. Attached Figure Description

[0029] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, are not intended to limit the scope of the invention. The components in the drawings are not drawn to scale but are merely illustrative of the principles of the invention. For ease of illustration and description of certain parts of the invention, corresponding portions in the drawings may be enlarged, i.e., may appear larger relative to other components in an exemplary device actually manufactured according to the invention. In the drawings:

[0030] Figure 1 This is a schematic diagram of the frequency distribution system based on fractional frequency division phase-locked loop according to an embodiment of the present invention.

[0031] Figure 2 This is a schematic diagram of frequency synchronization and time synchronization.

[0032] Figure 3 This is a schematic diagram of the frequency distribution logic between master and slave nodes in a frequency distribution system based on fractional frequency division phase-locked loop according to an embodiment of the present invention.

[0033] Figure 4 This is a schematic diagram of the frequency distribution structure between multiple nodes in a frequency distribution system based on fractional frequency division phase-locked loop according to an embodiment of the present invention.

[0034] Figure 5 This is a schematic diagram of the fractional frequency-locked loop (PLL) structure in a frequency distribution system based on a fractional frequency-locked loop according to an embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.

[0036] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.

[0037] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, element, step, or component, but does not exclude the presence or addition of one or more other features, elements, steps, or components.

[0038] It should also be noted that, unless otherwise specified, the term "connection" in this article can refer not only to a direct connection, but also to an indirect connection involving an intermediary.

[0039] In optical networks, achieving high-precision time slot allocation requires accurate time awareness and coordination. With the increasing scale of systems, the prevalence of distributed architectures, and the ever-growing demands for real-time performance, achieving high-precision time synchronization among widely distributed nodes has become a common and increasingly challenging problem. In distributed systems, all nodes need a common reference frequency to achieve time synchronization. For example... Figure 2 As shown, period and frequency are reciprocals, and time = period × number of periods. If the clock frequencies of different nodes are different, then their corresponding periods will be different, and the times of the nodes will differ after the same number of periods. Even if their times are aligned at a certain moment through a time synchronization algorithm, the times between nodes will gradually deviate over time due to frequency differences. Therefore, a frequency distribution system is needed to distribute a high-precision reference clock frequency to each node to ensure that all nodes have the same clock frequency.

[0040] In view of this, such as Figure 1 , Figure 2 and Figure 3 As shown, this invention provides a frequency distribution system based on a fractional-frequency-locked loop (FLL). The system includes a master node and multiple levels of child nodes. The master node and child nodes are connected tier by tier via serial transceivers. The master node embeds a reference clock signal into a serial data stream and sends it to the first-level child node for clock synchronization. Each level of child node synchronizes its local clock signal based on the clock signal from the upper level, and then embeds the local clock signal into a serial data stream and sends it to the downstream child node, thereby achieving frequency distribution of the reference clock signal among any number of tiered child nodes. In some embodiments, the master node and child nodes are connected using a hybrid star-ring topology.

[0041] The frequency distribution system provided by this invention employs a hybrid star-ring topology for networking. A ring connection is constructed between the master node and first-level child nodes to achieve redundancy backup, while a star connection is used between the first-level child nodes and downstream child nodes for expansion. This architecture combines the high reliability of a ring network with the high scalability of a star network: the ring backbone link can maintain synchronization through path switching in the event of a single point of failure, effectively avoiding the cascading failure risk of a chain topology; the star access link significantly reduces the cumulative jitter hop count of lower-level nodes, while facilitating flexible node expansion and centralized management. Through the synergistic effect of this hybrid topology and fractional-frequency-locked loop (FLL), the system achieves highly reliable, low-jitter, and easily scalable frequency distribution in complex network environments, perfectly suited for application scenarios such as data centers and 5G bearer networks that have stringent requirements for synchronization performance and networking flexibility.

[0042] The sub-nodes include: a serial transceiver receiver, a first phase detector, a first loop filter, a fractional frequency division phase-locked loop, and a serial transceiver transmitter.

[0043] The serial transceiver receiver includes a receive equalizer, a clock data recovery unit, a serial-to-parallel converter, and a decoder. The serial transceiver receiver receives the upstream serial data stream and recovers the reference clock signal from it using the clock data recovery unit.

[0044] The serial transceiver receiver performs channel compensation on the attenuated and distorted upstream serial data stream through a receiving equalizer to suppress inter-symbol interference. Subsequently, the clock data recovery unit uses an edge detector to extract the transition pulse sequence synchronized with the bit rate in the data stream, and drives the numerically controlled oscillator to perform open-loop scanning within a frequency window preset based on the system nominal rate and clock tolerance, quickly capturing and generating a reference clock signal that is approximately the same as the upstream transmission clock frequency.

[0045] The first phase detector is used to detect the phase difference between the local reference clock signal and the local clock signal output from the fractional-frequency-locked loop. In some embodiments, the first phase detector is an analog phase detector or a binary phase detector. Analog phase detectors (such as multipliers or mixers) perform analog operations on the two input clock signals and output a voltage signal proportional to the phase difference between them. They have the characteristics of good linearity and high measurement accuracy, but are susceptible to noise interference. Binary phase detectors (such as Bang-Bang PDs) compare the edge order of the two clocks and output only a digital level signal representing the leading or lagging effect. They are simple in structure and fast.

[0046] In other embodiments, the first phase detector includes a delay chain composed of delay units, an array of D flip-flops connected to each node of the delay chain, and a back-end encoder. A reference clock signal is injected into the delay chain as a start signal for propagation, and a local clock signal is used as a stop signal. When the stop signal arrives, the D flip-flop array latches the state of each node on the delay chain, obtaining a thermometer code consisting of consecutive 1s or 0s. The back-end encoder locks the transition position of the thermometer code to detect the phase difference measurement value. This structure is a high-precision phase detector based on a time-to-digital converter. Its core working principle is to convert the measurement of the time interval into the quantization of digital code values. The advantage of this all-digital architecture is that it achieves a measurement resolution far exceeding that of traditional phase detectors (up to picosecond level), provides a completely linear phase error output, fundamentally avoids the nonlinear jitter inherent in binary phase detectors, and its digital output can be directly and seamlessly connected to a digital loop filter, significantly improving the accuracy and stability of the entire frequency synchronization system.

[0047] The first loop filter is used to filter and adjust the phase difference measurement value based on the proportional-integral controller to obtain the control signal. In some embodiments, the first loop filter is implemented using a programmable gate array (PLA), which inputs the phase difference measurement value as the current error into the parallel proportional branch and integral branch respectively. The proportional branch multiplies the current error by a first coefficient to obtain a fast response component proportional to the instantaneous error. The integral branch adds the current error to the sum of historical errors in an accumulator and then multiplies it by a second coefficient to generate a cumulative correction component for eliminating steady-state error. The fast response component and the cumulative correction component are added together to obtain the control signal.

[0048] In some embodiments, the adjustment steps for the first coefficient and the second coefficient include steps S101 and S102:

[0049] Step S101: Initialize the loop, set the second coefficient to 0, apply a phase step and gradually increase the first coefficient by 50% until the loop response shows an overshoot of 10%~15%, and then reduce the current first coefficient by 20%~30%.

[0050] Step S102: Keep the first coefficient, and gradually increase the second coefficient by applying a frequency step and increasing it by 100%. When the amplitude of low-frequency oscillation exceeds 5% of the steady-state value, or the lock time is extended by more than 50%, the current second coefficient is reduced by 25% to 40%.

[0051] Steps S101 and S102 together constitute a systematic and quantifiable parameter tuning method. In S101, the proportional coefficient is determined by setting the integral coefficient to zero and applying a phase step: the first coefficient is increased by 50% increments until an overshoot of 10% to 15% occurs. This critical point indicates that the loop has reached a critical damping state. Subsequently, a 20% to 30% pullback is performed, which essentially adjusts the system damping from critical damping to moderate underdamping, thereby obtaining the optimal response speed while ensuring stability. In S102, the integral action is introduced on the basis of a fixed first coefficient: by applying a frequency step and increasing the second coefficient by 100% increments, the aim is to quickly approach the effective boundary of the integral action. When the system exhibits low-frequency oscillations exceeding 5% of the steady-state value or the lock-in time is extended by 50%, it indicates that the integral action is too strong. At this time, a 25% to 40% pullback can adjust the second coefficient to an optimal range that can effectively eliminate steady-state errors without causing significant oscillations or sluggish response. These two steps, by separating debugging and quantization criteria, effectively solve the problem of mutual coupling between proportional and integral components, and achieve the optimal balance between dynamic response speed and static stability accuracy of the loop.

[0052] A fractional-frequency phase-locked loop (PLL) is used to receive control signals and output a local reference clock signal that is frequency-locked and phase-stable with the reference clock signal.

[0053] In some embodiments, the fractional-frequency-locked loop (PLL) includes: a fractional-frequency divider, a second phase detector, a charge pump, a second loop filter, and a voltage-controlled oscillator (VCO). The fractional-frequency divider divides the control signal and the output signal of the PLL to obtain a feedback signal. The second phase detector measures the phase difference between the local clock signal and the feedback signal. The charge pump generates a control current based on the phase difference. The second loop filter filters out high-frequency noise from the control current and converts it into a control voltage. The VCO linearly adjusts the output local reference clock signal according to the control voltage.

[0054] In this system architecture, the fractional-division phase-locked loop (PLL) serves as the core frequency generation unit of the sub-node, forming a two-layer fine-tuning structure together with the preceding components. It receives control signals from the first digital loop filter, which precisely fine-tunes the output frequency by adjusting the division ratio of the fractional divider. Internally, a traditional analog PLL path composed of a second phase detector, a charge pump, and an analog loop filter performs rapid phase tracking and filtering on the voltage-controlled oscillator (VCO) output. The resulting local reference clock is output as a synchronization result to the serial transceiver transmitter and also fed back to the first phase detector for comparison with the upstream recovered clock. This architecture fully leverages the dual advantages of flexible digital loop configuration and low-noise analog loop output: the fractional division mechanism overcomes the frequency resolution limitations of integer division, enabling the system to accurately generate clocks with arbitrary frequency ratios; while the analog PLL's smoothing of high-frequency phases effectively suppresses quantization noise introduced by digital control, thus achieving excellent phase noise performance and spectral purity while ensuring extremely high frequency accuracy.

[0055] The serial transceiver transmitter is used to embed a local reference clock signal into a serial data stream and transmit it to downstream child nodes. In some embodiments, the serial transceiver transmitter includes a parallel data input, an encoder, a parallel-to-serial converter, and a transmit driver. In some embodiments, the encoder of the serial transceiver transmitter embeds the clock signal into the serial data stream using 64b / 66b encoding and scrambling.

[0056] On the other hand, the present invention also provides a frequency distribution method based on a fractional frequency-locked loop. The method operates based on the above-mentioned frequency distribution system based on a fractional frequency-locked loop. The master node generates a reference clock signal, embeds it into a serial data stream, and sends it to the first-level sub-node for clock synchronization. After synchronizing the local clock signal based on the upper-level clock signal, each sub-node embeds the local clock signal into a serial data stream and sends it to the downstream sub-node, so as to realize the frequency distribution of the reference clock signal among any number of cascaded sub-nodes.

[0057] The present invention will now be described with reference to a specific embodiment:

[0058] This embodiment proposes a high-precision frequency distribution system based on fractional-division PLL, which can realize frequency distribution among large-scale, multi-cascaded nodes. Figure 3 As shown, the master node, based on its internal reference clock, transmits clock signals to the first-level child nodes using a serial transceiver at the transmitting end. The first-level child nodes, at the receiving end, use a serial transceiver to extract the received clock. Internally, each child node uses a phase-locked loop (PLL) based on a fractional-division PLL to determine the frequency difference between the received clock and its local clock. This difference is continuously adjusted by the PLL's internal voltage-controlled oscillator, causing the PLL to lock onto and track the received clock, generating a reference clock based on the received clock's frequency and phase. This enables frequency distribution from the master node to the first-level child nodes. Figure 4 As shown, the N-level child node can use a serial transceiver at the transmitting end to transmit the clock signal to the N+1-level child node based on the reference clock, thus completing the frequency distribution from the N-level child node to the N+1-level child node. Based on the above mode, frequency distribution from any N-level child node to the N+1-level child node can be completed, and a high-precision frequency distribution network between multiple cascaded nodes can be constructed.

[0059] In the frequency distribution system proposed in this embodiment, the key to achieving high-precision frequency distribution between each level of cascaded nodes lies in ensuring that the frequency phase information distributed by the N-level node to the N+1-level node is consistent with the frequency phase information received by the N-level node from the N-1-level node. After the downstream node receives the clock signal distributed by the upstream node, the core of the entire frequency distribution system is how to generate a local clock signal that is frequency-locked and has high phase stability with the clock signal distributed by the upstream node. This embodiment uses a phase-locked loop based on a fractional-division PLL to achieve this core step of generating a local clock signal with high frequency lock and phase stability. Figure 5As shown, the fractional-frequency divider PLL generates a precise local clock signal through a closed-loop feedback process. FREF is the clock signal sent from the upstream, and the output signal FO is the locally generated clock signal. The feedback signal, obtained by comparing the input signal FREF with the output signal FO through a feedback divider (where the division factor N can be a non-integer fraction), is detected. The phase difference accumulated between the two clock signals is then detected, and the charge pump (CP) generates a control current based on this phase difference. The control current is filtered by a loop filter to remove high-frequency noise and converted into a control voltage. The voltage-controlled oscillator (VCO) linearly adjusts the frequency of the output signal FO according to the control voltage. After continuous adjustment of the output signal FO, when the frequency and phase of the output signal FO after N-fold division are aligned with those of the input signal FREF, the system achieves lockout. At this point, the N-level child node generates a local clock signal that is frequency-locked and has high phase stability with the clock signal distributed by the upstream N-1-level child node, ensuring high accuracy of frequency distribution; this local clock signal can be used for frequency distribution to the next level node, realizing frequency distribution between multiple cascaded nodes.

[0060] More specifically, such as Figure 1 As shown in the design scheme of this embodiment, each node uses a core closed-loop link consisting of a serial transceiver receiver, a phase detector, a digital loop filter, a fractional-division PLL, and a serial transceiver transmitter. The entire closed-loop link enables downstream nodes to obtain clock signals that are synchronized with upstream nodes and can continue to distribute frequencies to the child nodes of downstream nodes, realizing high-precision frequency distribution among large-scale, multi-cascaded nodes.

[0061] At the upstream node's transmitting end, a high-precision clock is generated using a fractional-division PLL based on the local clock for data transmission. The data to be transmitted is encoded (e.g., 8b / 10b encoding) and scrambled by a serial transceiver to ensure sufficiently frequent level transitions and DC balance in the data stream. The precise timing of these transitions represents the accurate frequency information of the transmitting clock, thus embedding the clock signal into the data link for transmission.

[0062] At the receiving end of the downstream node, the serial transceiver extracts the clock signal from the input serial data stream, extracts the bit rate-synchronized transition pulse from the input data stream through the edge detector, drives the numerically controlled oscillator to perform open-loop scanning within a preset frequency range, and outputs a reference clock that is approximately the same as the transmission clock frequency of the upstream node.

[0063] The phase detector performs phase detection on the output clock signal generated by the fractional-divided PLL and the reference clock to be locked received by the serial transceiver module. Using a direct sampling phase detector, the clock signal under test is directly sampled in the digital circuit. An additional clock signal independent of the sampled clock signal is used during sampling. Statistical analysis and post-processing are performed on the sampled values ​​to calculate an accurate phase measurement. This is used to detect whether the clock frequency generated by the fractional-divided PLL has reached a state of lock with the reference clock, and feedback is generated by measuring the error (i.e., the phase difference between clocks) in the unlocked state.

[0064] The phase detector's output then enters a loop filter for processing. This loop filter is a PI (Proportional-Integral) controller, which uses digital signal processing to process the phase detector's output. The PI controller's control loop includes proportional and integral branches. The proportional term improves the system's transient response to errors, allowing the controlled variable to reach its target value faster, while the integral component reduces steady-state error. By changing the first coefficient KP and the second coefficient KI of these proportional and integral components, their combinations can balance the speed and accuracy of the tracking loop, meeting the application requirements of fast locking and zero steady-state error. Furthermore, the PI filter also has low-pass characteristics, enabling it to filter high-frequency components in the phase detector's phase output, thereby removing noise and phase jitter from the clock signal. After passing through the loop filter, the fractional N value generated by the fractional divider PLL is more stable, allowing for a more stable frequency and improving the clock quality in the frequency distribution link.

[0065] Downstream nodes perform frequency locking and phase compensation on the clock signal recovered and extracted from the serial transceiver through a phase-locked loop composed of a phase detector, loop filter, and fractional-division PLL. This generates a transmit clock based on the upstream node and a clock signal that can be flexibly configured in the downstream node, thus realizing high-precision frequency distribution among large-scale, multi-cascaded nodes.

[0066] Compared to existing frequency distribution technologies, the method proposed in this embodiment does not require the deployment of high-cost dedicated fiber optic links to achieve accurate frequency distribution. It also avoids the clock performance degradation caused by accumulated phase drift in ServoClock-based frequency distribution technology and the output clock jitter caused by link-based clock recovery frequency distribution technology. This embodiment designs a phase-locked loop (PLL) based on a fractional-division PLL. This PLL can lock onto any clock signal, enabling the switch to distribute frequencies received from upstream. Compared to traditional PLLs, key modules such as the phase detector and loop filter in this loop can be implemented using reconfigurable digital logic resources. This feature gives it good reconfigurability; the filtering algorithm and corresponding parameters in the PLL can be flexibly reconfigured, reducing output clock jitter and achieving high precision in a low-cost frequency distribution system.

[0067] In summary, the frequency distribution system and method based on fractional-frequency-locked loop (FFL) of this invention embeds a clock signal in the data link through a serial transceiver. At the receiving end, a clock data recovery unit accurately extracts the upstream reference clock. Subsequently, based on the core synchronization mechanism of the FLL, a high-linearity phase detector obtains the precise phase difference, and a reconfigurable digital loop filter performs proportional-integral operations and noise filtering on the error signal to dynamically generate a control signal. This signal drives the FLL to output a local clock that is frequency-locked and phase-consistent with the reference clock, thereby realizing the regeneration and transmission of phase information at each node. Ultimately, a high-precision distributed frequency synchronization network that can suppress accumulated drift, reduce transmission jitter, and does not rely on dedicated channels is constructed. This system effectively overcomes the phase drift problem caused by the accumulation of periodic measurement errors in traditional schemes, avoids the high-cost deployment limitations of dedicated optical fibers, significantly improves frequency distribution accuracy and phase stability, and achieves low-cost, high-flexibility multi-level frequency synchronization in large-scale networking environments.

[0068] Those skilled in the art will understand that the exemplary components, systems, and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software, or a combination of both. Whether implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention. When implemented in hardware, it can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this invention are programs or code segments used to perform the desired tasks. The programs or code segments can be stored in a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried in a carrier wave.

[0069] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention.

[0070] In this invention, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or in place of features of other embodiments.

[0071] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations of the embodiments of the present invention are possible. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A frequency distribution system based on a fractional frequency division phase-locked loop, characterized in that, The system includes a master node and multiple levels of child nodes. The master node and the child nodes are connected in stages via serial transceivers. The master node embeds a reference clock signal into a serial data stream and sends it to the first-level child node for clock synchronization. Each level of child node synchronizes its local clock signal based on the clock signal of the upper level, and then embeds the local clock signal into a serial data stream and sends it to the downstream child node to realize the frequency distribution of the reference clock signal among any number of cascaded child nodes. The sub-node includes: a serial transceiver receiver, a first phase detector, a first loop filter, a fractional frequency-locked loop, and a serial transceiver transmitter; The serial transceiver receiver is used to receive the upstream serial data stream and recover the reference clock signal from the upstream serial data stream through the clock data recovery unit; the first phase detector is used to detect the phase difference measurement value between the local reference clock signal and the local clock signal output by the fractional-frequency-locked loop; the first loop filter is used to filter and adjust the phase difference measurement value based on the proportional-integral controller to obtain a control signal; the fractional-frequency-locked loop is used to receive the control signal and output a local reference clock signal that is frequency-locked and phase-stable with the reference clock signal; the serial transceiver transmitter is used to embed the local reference clock signal into the serial data stream and send it to the downstream child node.

2. The frequency distribution system based on fractional frequency division phase-locked loop according to claim 1, characterized in that, The clock data recovery unit extracts the transition pulse synchronized with the bit rate through an edge detector, performs open-loop scanning of the numerically controlled oscillator within a preset frequency range based on the driving of the oscillator, and outputs the reference clock signal.

3. The frequency distribution system based on fractional frequency division phase-locked loop according to claim 1, characterized in that, The first phase detector is either an analog phase detector or a binary phase detector; Alternatively, the first phase detector includes a delay chain composed of delay units, an array of D flip-flops connected to each node of the delay chain, and a back-end encoder. The reference clock signal is injected into the delay chain as a start signal for propagation, and the local clock signal is used as a stop signal. When the stop signal arrives, the state of each node on the delay chain is latched by the D flip-flop array to obtain a thermometer code consisting of consecutive 1s or 0s. The back-end encoder locks the transition position of the thermometer code to detect the phase difference measurement value.

4. The frequency distribution system based on fractional frequency division phase-locked loop according to claim 1, characterized in that, The first loop filter is implemented using a programmable gate array (PGA) to input the phase difference measurement value as the current error into a parallel proportional branch and an integral branch. The proportional branch multiplies the current error by a first coefficient to obtain a fast response component that is proportional to the instantaneous error. The integral branch adds the current error to the sum of historical errors in an accumulator and then multiplies it by a second coefficient to generate a cumulative correction component for eliminating steady-state errors. The fast response component and the cumulative correction component are added together to form the control signal.

5. The frequency distribution system based on fractional-frequency-locked loop according to claim 4, characterized in that, The adjustment steps for the first coefficient and the second coefficient include: Initialize the loop by setting the second coefficient to 0, and gradually increasing the first coefficient by 50% each time a phase step is applied until the loop response shows an overshoot of 10% to 15%. Then, reduce the current first coefficient by 20% to 30%. While maintaining the first coefficient, the second coefficient is gradually increased by applying a frequency step and increasing by 100%. When the amplitude of low-frequency oscillation exceeds 5% of the steady-state value, or the lock-in time is extended by more than 50%, the current second coefficient is reduced by 25% to 40%.

6. The frequency distribution system based on fractional frequency division phase-locked loop according to claim 1, characterized in that, The fractional frequency-locked loop includes: A fractional frequency divider is used to divide the control signal and the output signal of the fractional frequency-locked loop to obtain a feedback signal. The second phase detector is used to measure the phase difference between the local clock signal and the feedback signal; A charge pump for generating a control current based on the phase difference; The second loop filter is used to filter out high-frequency noise from the control current and convert it into a control voltage; A voltage-controlled oscillator is used to linearly adjust the output of the local reference clock signal according to the control voltage.

7. The frequency distribution system based on fractional frequency division phase-locked loop according to claim 1, characterized in that, The serial transceiver transmitter includes a parallel data input terminal, an encoder, a parallel-to-serial converter, and a transmit driver; the serial transceiver receiver includes a receive equalizer, a clock data recovery unit, a serial-to-parallel converter, and a decoder.

8. The frequency distribution system based on fractional frequency division phase-locked loop according to claim 7, characterized in that, The encoder at the transmitting end of the serial transceiver embeds the clock signal into the serial data stream using 64b / 66b encoding and scrambling.

9. The frequency distribution system based on fractional frequency division phase-locked loop according to claim 1, characterized in that, The master node and the child node are connected using a star-ring hybrid topology.

10. A frequency distribution method based on a fractional frequency division phase-locked loop, characterized in that, The method operates based on the frequency distribution system based on fractional frequency division phase-locked loop as described in any one of claims 1 to 9. The master node generates a reference clock signal, embeds it into a serial data stream, and sends it to the first-level sub-node for clock synchronization. After synchronizing the local clock signal based on the upper-level clock signal, each level of the sub-node embeds the local clock signal into a serial data stream and sends it to the downstream sub-node, so as to realize the frequency distribution of the reference clock signal among any number of cascaded sub-nodes.

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