Comparator noise estimation method for successive approximation analog-to-digital converter
By utilizing an on-chip estimation method with capacitor arrays and comparators in successive approximation analog-to-digital converters, the problem of discrepancies between simulation results and actual results is solved, accurate comparator noise estimation is achieved, and the reliability and cost-effectiveness of engineering applications are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI QIMINGXIN SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2026-02-10
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies for estimating comparator noise in successive approximation analog-to-digital converters (SAR ADCs) result in simulations that deviate significantly from actual chips, making it difficult to accurately reflect the effects of process variations and environmental interference. Furthermore, direct analysis methods cannot accurately estimate comparator noise.
By utilizing an on-chip estimation method with capacitor arrays and comparators in a successive approximation analog-to-digital converter, the normal distribution probability value and standard deviation of the comparator noise are calculated through multiple charge-discharge and comparison operations, thus avoiding simulation bias.
This enables accurate on-chip estimation of comparator noise, improving the engineering applicability of the estimation, reducing costs, and increasing the accuracy of the estimation.
Smart Images
Figure CN121690204B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a comparator noise estimation method for a successive approximation analog-to-digital converter. Background Technology
[0002] In digital signal processing and electronic systems, it is often necessary to convert analog signals into digital signals for processing and storage by digital circuits. Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) are widely used due to their moderate performance, low power consumption, and relatively simple structure. The main noise sources of SAR ADCs are sampling switch noise, comparator noise, and quantization noise. The comparator plays a crucial decision-making role in each conversion of the SAR ADC. The higher the resolution of the SAR ADC, the higher the accuracy requirement of the comparator; the accuracy of its output directly determines the correctness of the SAR ADC conversion result.
[0003] To investigate the impact of comparator noise on SAR ADC performance, it is often necessary to estimate the magnitude of the comparator noise. Current methods for estimating comparator noise utilize specialized Electronic Design Automation (EDA) software to simulate the comparator circuit. Random variations in device parameters are introduced into the simulation, and the simulation is run multiple times to obtain the statistical distribution of the noise, thereby yielding noise analysis and statistical results. Existing solutions require simulation to determine the magnitude of the comparator noise voltage; however, actual manufactured chips are affected by factors such as temperature and process variations, meaning simulation data may not be applicable to every chip. Therefore, the engineering application of existing technologies is somewhat limited.
[0004] Another approach involves shorting the ADC input to a zero-level signal. The noise level of the SAR ADC can then be obtained by directly using a histogram to statistically analyze the SAR ADC output. Alternatively, the differential input of the SAR ADC can be shorted to a common-mode voltage, and then the SAR ADC can be sampled and quantized. Each quantization output of the SAR ADC represents a sample, and multiple samples are collected. Since there is no actual signal input, any variation can be attributed to internal noise, including comparator noise. The noise level can be estimated by statistically analyzing the distribution of these samples. However, this approach yields noise that includes not only comparator noise but also ADC quantization noise, and implementing the statistical analysis on-chip is extremely costly, hindering cost reduction.
[0005] Because simulation tools cannot cover all process deviations in actual chip manufacturing, the estimation of noise performance is incomplete. Factors such as electromagnetic interference and temperature variations in the actual working environment are difficult to accurately simulate, and these can affect the comparator's noise performance. Direct noise analysis of the ADC cannot accurately reflect the comparator's noise level, and its calculation process is difficult to integrate on-chip. Therefore, to improve engineering usability, this invention proposes an on-chip automatic estimation method for comparator noise voltage.
[0006] This section is intended to provide background or context for understanding the implementation of this application and is for reference only. It should not be construed as an admission by the applicant that this section pertains to prior art that was disclosed before the filing date of this application. Summary of the Invention
[0007] The purpose of this application is to provide a comparator noise estimation method for successive approximation analog-to-digital converters, which realizes on-chip automatic estimation of comparator noise voltage, can estimate the actual comparator noise, and avoids the deviation between the simulated comparator noise and the actual situation.
[0008] This application discloses a comparator noise estimation method for a successive approximation analog-to-digital converter (ADC). The successive approximation ADC includes a first capacitor array, a second capacitor array, a comparator, and a logic control circuit. The top plate of each capacitor in the first capacitor array is connected to the negative input terminal of the comparator and connected to a common-mode voltage via a sampling switch. The top plate of each capacitor in the second capacitor array is connected to the positive input terminal of the comparator and connected to a common-mode voltage via a sampling switch. The output terminal of the comparator is coupled to the logic control circuit. The logic control circuit determines a digital codeword based on the output of the comparator to control the bottom plate of each capacitor in the first and second capacitor arrays to be connected to either a positive or negative reference voltage. The method includes the following steps:
[0009] The sampling switch is turned on, and the first capacitor array and the second capacitor array are charged through the common mode level. The bottom plate of each capacitor in the first capacitor array is connected to the positive reference voltage, and the bottom plate of each capacitor in the second capacitor array is connected to the negative reference voltage.
[0010] Disconnect the sampling switch, connect the bottom plate of the least significant capacitor in the first capacitor array to the negative reference voltage, and connect the bottom plate of the least significant capacitor in the second capacitor array to the positive reference voltage. The logic control circuit controls the comparator to perform multiple comparisons and output the comparison results, and calculates the first codeword based on the comparison results.
[0011] The sampling switch is turned on, and the first capacitor array and the second capacitor array are charged through the common mode level. The bottom plate of each capacitor in the first capacitor array is connected to the negative reference voltage, and the bottom plate of each capacitor in the second capacitor array is connected to the positive reference voltage.
[0012] Disconnect the sampling switch, connect the bottom plate of the least significant capacitor in the first capacitor array to the positive reference voltage, and connect the bottom plate of the least significant capacitor in the second capacitor array to the negative reference voltage. The logic control circuit controls the comparator to perform multiple comparisons and outputs the comparison results, and calculates the second codeword based on the comparison results; and
[0013] Subtracting the first codeword from the second codeword and dividing by 2 yields the probability value of the normal distribution of the comparator noise, and the standard deviation of the normal distribution of the comparator noise is determined based on the probability value.
[0014] In a preferred embodiment, the successive approximation analog-to-digital converter further includes an estimation circuit, which includes a flip-flop, a first adder, a divider, a counter, a second adder, and a lookup table circuit.
[0015] The counter records the number of comparisons by the comparator, the trigger receives the comparison result of each comparison by the comparator, the first adder accumulates the multiple comparison results of the comparator to obtain an accumulated result, the divider calculates the first codeword and the second codeword based on the accumulated result and the number of comparisons, the second adder subtracts the first codeword from the second codeword and divides by 2 to obtain the probability value of the comparator noise corresponding to the voltage value generated by the flipping of the first capacitor array and the second capacitor array, and the lookup table circuit obtains the standard deviation of the normal distribution of the comparator noise from the standard normal distribution stored therein based on the probability value and the corresponding voltage value.
[0016] In a preferred embodiment, the logic control circuit includes a clock generation circuit that generates a clock signal to the comparator and the counter, wherein the comparator performs multiple comparisons based on the clock signal, and the counter counts based on the clock signal.
[0017] In a preferred embodiment, the clock generation circuit generates a sampling clock signal, which controls the on / off state of the sampling switch. When the sampling clock signal is high, the sampling switch is on; when the sampling clock signal is low, the sampling switch is off, and the clock generation circuit generates the comparison clock signal.
[0018] In a preferred embodiment, the trigger is an SR latch.
[0019] In a preferred embodiment, the comparator performs comparisons 4 to 8 times.
[0020] In a preferred embodiment, the first capacitor array and the second capacitor array each include a capacitor of multiple bits.
[0021] In a preferred embodiment, the bottom plate of each capacitor in the first capacitor array and the second capacitor array is connected to a positive reference voltage and a negative reference voltage respectively via a single-pole double-throw switch.
[0022] This application also discloses a successive approximation analog-to-digital converter (ADC), which includes a first capacitor array, a second capacitor array, a comparator, and a logic control circuit. The top plate of each capacitor in the first capacitor array is connected to a common-mode voltage and the negative input terminal of the comparator, and is also connected to the common-mode voltage via a sampling switch. Similarly, the top plate of each capacitor in the second capacitor array is connected to the common-mode voltage and the positive input terminal of the comparator, and is also connected to the common-mode voltage via a sampling switch. The output terminal of the comparator is coupled to the logic control circuit. The logic control circuit determines a digital codeword based on the comparator's output to control the bottom plate of each capacitor in the first and second capacitor arrays to be connected to either a positive or negative reference voltage. The successive approximation ADC also includes a noise estimation circuit.
[0023] The logic control circuit controls the sampling switch to charge the first capacitor array and the second capacitor array with the common-mode level, connects the bottom plate of each capacitor in the first capacitor array to the positive reference voltage, connects the bottom plate of each capacitor in the second capacitor array to the negative reference voltage, connects the bottom plate of the least significant capacitor in the first capacitor array to the negative reference voltage, and connects the bottom plate of the least significant capacitor in the second capacitor array to the positive reference voltage. The logic control circuit controls the comparator to perform multiple comparisons and outputs the comparison results. The noise estimation circuit calculates the first codeword based on the comparison results.
[0024] The logic control circuit controls the sampling switch to charge the first capacitor array and the second capacitor array with the common-mode level, connects the bottom plate of each capacitor in the first capacitor array to the negative reference voltage, connects the bottom plate of each capacitor in the second capacitor array to the positive reference voltage, connects the bottom plate of the least significant capacitor in the first capacitor array to the positive reference voltage, and connects the bottom plate of the least significant capacitor in the second capacitor array to the negative reference voltage. The logic control circuit controls the comparator to perform multiple comparisons and outputs the comparison results. The noise estimation circuit calculates the second codeword based on the comparison results.
[0025] The noise estimation circuit subtracts the first codeword from the second codeword and divides by 2 to obtain the probability value of the normal distribution of the comparator noise, and determines the standard deviation of the normal distribution of the comparator noise based on the probability value.
[0026] This application provides a method for estimating comparator noise voltage. After the capacitor array charging phase of the ADC is completed, the voltage of the bottom plate of the least significant bit capacitor is switched and compared multiple times by a comparator. Based on the comparison results, the comparator noise probability value corresponding to the least significant bit (LSB) voltage value is calculated. These two values are then substituted into a standard normal distribution probability table to obtain the normal distribution table of the comparator noise, and thus the standard deviation of the comparator noise is obtained. This application enables on-chip automatic estimation of comparator noise voltage, allowing for the estimation of actual comparator noise while avoiding discrepancies between simulated and actual comparator noise.
[0027] It should be understood that, within the scope of this invention, the above-described technical features of this invention and the technical features specifically described below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be described in detail here. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. It should be understood that the accompanying drawings described below are merely some implementation examples of the present invention, and those skilled in the art can obtain other implementation examples based on these drawings without creative effort.
[0029] Figure 1 This is a flowchart illustrating a comparator noise estimation method for a successive approximation analog-to-digital converter according to one embodiment of this application.
[0030] Figures 2 to 6 The circuit operation states corresponding to each step of the comparator noise estimation method in one embodiment of this application are shown.
[0031] Figure 7 A schematic diagram of the structure of a successive approximation analog-to-digital converter in one embodiment of this application is shown.
[0032] Figure 8 A schematic diagram illustrating the principle of a comparator noise estimation method in one embodiment of this application is shown. Detailed Implementation
[0033] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0034] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0035] The first embodiment of this application relates to a comparator noise estimation method for a successive approximation analog-to-digital converter (SAR ADC), wherein the SAR ADC includes a first capacitor array, a second capacitor array, a comparator, and a logic control circuit. The first and second capacitor arrays are symmetrical structures and each includes a capacitor with multiple bits. The top plate of each capacitor in the first capacitor array is connected to the negative input terminal of the comparator and connected to a common-mode voltage via a sampling switch. The top plate of each capacitor in the second capacitor array is connected to the positive input terminal of the comparator and connected to the common-mode voltage via another sampling switch. The output terminal of the comparator is coupled to the logic control circuit, which determines a digital codeword based on the comparator's output to control the bottom plate of each capacitor in the first and second capacitor arrays to be connected to either a positive or negative reference voltage. The bottom plate of each capacitor in the first and second capacitor arrays is connected to the positive and negative reference voltages via a single-pole double-throw switch.
[0036] The flow of the comparator noise estimation method in this embodiment is as follows: Figure 1 As shown. The method includes the following steps, Figures 2 to 6 The circuit operation process and state corresponding to each step are shown. In this embodiment, a differential circuit is used as an example for explanation.
[0037] Step 101: The sampling switch (not shown in the figure) connected to the first capacitor array C1 and the second capacitor array C2 is turned on through the logic control circuit (SAR logic), and the first and second capacitor arrays are charged through the common-mode level VCM. Furthermore, the bottom plate of each capacitor in the first capacitor array is connected to the positive reference voltage VREFP, and the bottom plate of each capacitor in the second capacitor array is connected to the negative reference voltage VREFN. Specifically, the connection of the capacitor to the positive reference voltage VREFP or the negative reference voltage VREFN can be controlled by the single-pole double-throw switch (not shown in the figure) controlled by the logic control circuit. This step 101 is the charging stage, and its corresponding circuit operation process is as follows: Figure 2 As shown.
[0038] Step 102: After the charging phase ends, the sampling switch connected to the first and second capacitor arrays is disconnected via the logic control circuit. The bottom plate of the least significant capacitor in the first capacitor array is connected to the negative reference voltage VREFN, and the bottom plate of the least significant capacitor in the second capacitor array is connected to the positive reference voltage VREFP. Then, the logic control circuit controls the comparator (CMP) to perform multiple comparisons and outputs the comparison results, calculating the first codeword based on the comparison results. The circuit operation process corresponding to this step is as follows: Figure 3 As shown.
[0039] The charging process of the capacitors is controlled by the sampling clock signal of the ADC. When the sampling clock signal is high, the top plates of the first and second capacitor arrays are connected to the common-mode level VCM via the sampling switch. When the sampling clock signal is low, the sampling switch is open, and the bottom plate of the least significant capacitor in the first capacitor array is connected to the negative reference voltage VREFN, and the bottom plate of the least significant capacitor in the second capacitor array is connected to the positive reference voltage VREFP. The specific implementation scheme for controlling the capacitor plates to connect to the positive and negative reference voltages VREFN is as follows: only the least significant capacitors need to be operated, so the bottom plate of the least significant capacitor is connected to the positive reference voltage VREFP and the negative reference voltage VREFN respectively through PMOS and NMOS transistor switches. During operation, the sampling clock of the analog-to-digital converter is directly connected to the gates of the PMOS and NMOS transistors, thereby controlling the capacitor plates to connect to the positive or negative reference voltage VREFP or VREFN. During this process, the reference voltage of the least significant capacitor is flipped, and by pulling up the output voltage of the capacitor array, a DC voltage is supplied to the comparator, which yields the voltage value generated by flipping 1 LSB.
[0040] Step 103: The sampling switch connected to the first capacitor array and the second capacitor array is turned on through the logic control circuit, and the first and second capacitor arrays are charged through the common-mode level VCM. Furthermore, the bottom plate of each capacitor in the first capacitor array is connected to the negative reference voltage VREFN, and the bottom plate of each capacitor in the second capacitor array is connected to the positive reference voltage VREFP. This process in step 103 is also a charging stage, the difference from step 101 being that the reference voltages connected to the bottom plates of each capacitor in the first and second capacitor arrays are opposite. The corresponding circuit operation process is as follows: Figure 4 As shown.
[0041] Step 104: After the charging phase ends, the sampling switch connected to the first and second capacitor arrays is disconnected via the logic control circuit. Furthermore, the bottom plate of the least significant capacitor in the first capacitor array is connected to the positive reference voltage VREFP, and the bottom plate of the least significant capacitor in the second capacitor array is connected to the negative reference voltage VREFN. Then, the logic control circuit controls the comparator to perform multiple comparisons and outputs the comparison results, calculating the second codeword based on the comparison results. During this process, the reference voltage of the least significant capacitor is flipped. By pulling the output voltage of the capacitor array in the other direction, a DC voltage opposite to that in step 102 is applied to the comparator, resulting in the voltage value generated by flipping 1 LSB in the other direction. The circuit operation process corresponding to this step is as follows: Figure 5 As shown.
[0042] Step 105: Subtract the first codeword from the second codeword and divide by 2 to obtain the probability value of the normal distribution of the comparator noise, and determine the standard deviation of the normal distribution of the comparator noise based on the probability value. Subtracting the first codeword from the second codeword and dividing by 2 eliminates the comparator offset. The circuit operation for this step is as follows: Figure 6 As shown.
[0043] The successive approximation analog-to-digital converter also includes an estimation circuit 10, which comprises a flip-flop 11, a first adder 12, a divider 13, a counter 14, a second adder 15, and a lookup table (LUT) circuit 16. The flip-flop 11, first adder 12, divider 13, second adder 15, and lookup table circuit 16 are connected sequentially, and the counter 14 is connected to the divider 13. The flip-flop 11 is, for example, an SR latch. The counter 14 records the number of comparisons by the comparator, the flip-flop 11 receives the comparison result of each comparison by the comparator, and the first adder 12 accumulates the multiple comparison results of the comparator to obtain the accumulated result. Specifically, the logic control circuit includes a clock generation circuit, which generates a sampling clock signal to the sampling switch and a comparison clock signal to the comparator and counter 14. The sampling clock signal controls the on / off state of the sampling switch. When the sampling clock signal is high, the sampling switch is on, entering the charging stage. When the sampling clock signal is low, the sampling switch is off, and the clock generation circuit generates a comparison clock signal, entering the comparison stage. The comparator performs multiple comparisons based on the comparison clock signal, and the counter 14 counts according to the comparison clock signal. The number of comparisons performed by the comparator can be, for example, 4 to 8. After each comparison, the first adder 12 increments the comparison result, and the counter 14 increments its count by 1. Then, the divider 13 calculates the first codeword and the second codeword based on the accumulated result and the number of comparisons. The second adder subtracts the first codeword from the second codeword and divides by 2 to obtain the probability value of the comparator noise corresponding to the voltage values generated by the switching of the first and second capacitor arrays. The lookup table circuit 16 obtains the standard deviation of the normal distribution of the comparator noise from the standard normal distribution stored therein, based on the probability value and the corresponding voltage value. .
[0044] This invention maps the ADC's unit codeword to the standard deviation of the comparator noise through the ADC's built-in front-end process, avoiding discrepancies between the simulated comparator noise and the actual noise. This invention can estimate actual comparator noise and has significant applications in testing engineering and process correction.
[0045] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.
[0046] The successive approximation analog-to-digital converter (SAR ADC) described in this embodiment includes at least: a sampling switch, a capacitor array, a comparator, and a logic control circuit. This embodiment uses a single-ended circuit as an example, and its structure is as follows: Figure 7As shown in the diagram, the top plates of the capacitors in the capacitor array are connected to both the output of a sampling switch (not shown) and the positive input of the comparator CMP. The comparator's output is used to determine the digital codeword for the output of the logic control circuit (SAR logic) and to control the bottom plate of the capacitor array, bringing the differential voltage of the top plate of the capacitor array closer to zero. This process is repeated until the logic control circuit has determined all the output digital codewords.
[0047] This embodiment provides a method for estimating comparator noise in a successive approximation analog-to-digital converter, comprising at least steps a to d, as described above. Figure 7 and Figure 8 As shown.
[0048] Step a: The ADC samples the preset common-mode voltage. After sampling, one or more capacitors in the capacitor array are switched from ground (e.g., AVSS) to the reference voltage (VREF). The comparator then performs N comparisons, sums the output results, and divides by N. The purpose of this step is to bias the CDAC output voltage to provide a DC voltage to the comparator and obtain the probability value of this voltage in the comparator noise normal distribution.
[0049] In step b, the ADC samples the preset common-mode voltage again. After sampling, one or more capacitors in the capacitor array switch from being connected to the reference voltage to ground. The comparator then performs N comparisons, sums the output results, and divides by N. The purpose of this step is to bias the CDAC output voltage in another direction, thereby providing the comparator with a DC voltage opposite to that in the previous step.
[0050] Step c involves subtracting the two calculation results from each other and then dividing by 2. The purpose of this step is to eliminate the comparator's offset.
[0051] Step d, since the comparator noise follows a normal distribution And the noise mean If the value is 0, then the standard deviation of the comparator noise can be determined based on the probability obtained from the above steps. .
[0052] The specific implementation method for comparator noise estimation includes the following steps:
[0053] Step 1: First, the capacitor array of the ADC is charged, meaning the input voltage of the ADC is the common-mode voltage. After charging is complete, the bottom plate of the lowest capacitor is connected to the reference voltage. According to the law of charge conservation, the voltage of the top plate of the capacitor array will rise by one unit voltage.
[0054] Step 2: Have the comparator compare the voltage obtained in Step 1 N times consecutively, and calculate the average value of its output codeword.
[0055] Step 3: Recharge the ADC's capacitor array, i.e., the input voltage is the common-mode voltage. After charging is complete, the bottom plate of the lowest capacitor is connected to ground. According to the law of charge conservation, the voltage of the top plate of the capacitor array will drop by one unit voltage.
[0056] Step 4: Have the comparator compare the voltage obtained in step 3 N times consecutively, and calculate the average value of its output codeword.
[0057] Step 5: Subtract the average value obtained in Step 4 from the average value obtained in Step 2 and divide by 2. The purpose of this step is to provide a DC voltage to the comparator by biasing the output voltage of the CDAC and obtain the probability value of this voltage value in the normal distribution of the comparator noise.
[0058] Step 6: Since the comparator noise follows a normal distribution And the noise mean If the value is 0, then the normal distribution of the comparator noise can be determined based on the probability obtained in step 5, thus yielding the standard deviation of the comparator noise. .
[0059] The second embodiment of this application relates to a successive approximation analog-to-digital converter (ADC). The successive approximation ADC includes a first capacitor array, a second capacitor array, a comparator, and a logic control circuit. The top plate of each capacitor in the first capacitor array is connected to a common-mode voltage and the negative input terminal of the comparator, and is connected to the common-mode voltage via a sampling switch. The top plate of each capacitor in the second capacitor array is connected to a common-mode voltage and the positive input terminal of the comparator, and is connected to the common-mode voltage via a sampling switch. The output terminal of the comparator is coupled to the logic control circuit. The logic control circuit determines a digital codeword based on the output of the comparator to control the bottom plate of each capacitor in the first and second capacitor arrays to be connected to either a positive reference voltage VREFP or a negative reference voltage VREFN. The successive approximation ADC also includes a noise estimation circuit.
[0060] The logic control circuit controls the sampling switch to charge the first capacitor array and the second capacitor array with a common-mode level. The bottom plate of each capacitor in the first capacitor array is connected to the positive reference voltage VREFP, and the bottom plate of each capacitor in the second capacitor array is connected to the negative reference voltage VREFN. Then, the bottom plate of the least significant capacitor in the first capacitor array is connected to the negative reference voltage VREFN, and the bottom plate of the least significant capacitor in the second capacitor array is connected to the positive reference voltage VREFP. The logic control circuit controls the comparator to perform multiple comparisons and outputs the comparison results. The noise estimation circuit calculates the first codeword based on the comparison results.
[0061] The logic control circuit controls the sampling switch to charge the first and second capacitor arrays with common-mode voltage. The bottom plate of each capacitor in the first capacitor array is connected to the negative reference voltage VREFN, and the bottom plate of each capacitor in the second capacitor array is connected to the positive reference voltage VREFP. Then, the bottom plate of the least significant capacitor in the first capacitor array is connected to the positive reference voltage VREFP, and the bottom plate of the least significant capacitor in the second capacitor array is connected to the negative reference voltage VREFN. The logic control circuit controls the comparator to perform multiple comparisons and outputs the comparison results. The noise estimation circuit calculates the second codeword based on the comparison results.
[0062] The noise estimation circuit subtracts the first codeword from the second codeword and divides by 2 to obtain the probability value of the normal distribution of the comparator noise, and determines the standard deviation of the normal distribution of the comparator noise based on the probability value.
[0063] The first embodiment is a method embodiment corresponding to this embodiment. The technical details in the first embodiment can be applied to this embodiment, and the technical details in this embodiment can also be applied to the first embodiment.
[0064] Accordingly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the various method embodiments of this application. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device. As defined herein, computer-readable storage media do not include transient computer-readable media, such as modulated data signals and carrier waves.
[0065] Furthermore, embodiments of this application also provide a comparator noise estimation system for a successive approximation analog-to-digital converter, including a memory for storing computer-executable instructions and a processor; the processor is used to implement the steps in the above-described method embodiments when executing the computer-executable instructions in the memory. The processor may be a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Microcontroller Unit (MCU), Neural Processing Unit (NPU), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices. The aforementioned memory may be read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or solid-state drive, etc. The steps of the methods disclosed in the embodiments of this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
[0066] Furthermore, embodiments of this application also provide a computer program product, including computer-executable instructions that, when executed by a processor, implement the steps in the above-described method embodiments.
[0067] The various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as having been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; it is impossible to use both simultaneously. Feature E can be technically combined with feature C. Therefore, the solution A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution A+B+C+E should be considered as having been recorded.
[0068] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.
[0069] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Claims
1. A method for estimating comparator noise in a successive approximation analog-to-digital converter, characterized in that, The successive approximation analog-to-digital converter includes a first capacitor array, a second capacitor array, a comparator, and a logic control circuit. The top plate of each capacitor in the first capacitor array is connected to the negative input terminal of the comparator and connected to a common-mode voltage via a sampling switch. The top plate of each capacitor in the second capacitor array is connected to the positive input terminal of the comparator and connected to a common-mode voltage via a sampling switch. The output terminal of the comparator is coupled to the logic control circuit. The logic control circuit determines a digital codeword based on the output of the comparator to control the bottom plate of each capacitor in the first and second capacitor arrays to be connected to either a positive or negative reference voltage. The method includes the following steps: The sampling switch is turned on, and the first capacitor array and the second capacitor array are charged through the common mode level. The bottom plate of each capacitor in the first capacitor array is connected to the positive reference voltage, and the bottom plate of each capacitor in the second capacitor array is connected to the negative reference voltage. Disconnect the sampling switch, connect the bottom plate of the least significant capacitor in the first capacitor array to the negative reference voltage, and connect the bottom plate of the least significant capacitor in the second capacitor array to the positive reference voltage. The logic control circuit controls the comparator to perform multiple comparisons and output the comparison results, and calculates the first codeword based on the comparison results. The sampling switch is turned on, and the first capacitor array and the second capacitor array are charged through the common mode level. The bottom plate of each capacitor in the first capacitor array is connected to the negative reference voltage, and the bottom plate of each capacitor in the second capacitor array is connected to the positive reference voltage. Disconnect the sampling switch, connect the bottom plate of the least significant capacitor in the first capacitor array to the positive reference voltage, and connect the bottom plate of the least significant capacitor in the second capacitor array to the negative reference voltage. The logic control circuit controls the comparator to perform multiple comparisons and output the comparison results, and calculates the second codeword based on the comparison results. as well as Subtracting the first codeword from the second codeword and dividing by 2 yields the probability value of the normal distribution of the comparator noise corresponding to the unit voltage of the capacitor array, and the standard deviation of the normal distribution of the comparator noise is determined based on the probability value.
2. The comparator noise estimation method for a successive approximation analog-to-digital converter as described in claim 1, characterized in that, The successive approximation analog-to-digital converter further includes an estimation circuit, which includes a flip-flop, a first adder, a divider, a counter, a second adder, and a lookup table circuit. The counter records the number of comparisons by the comparator, the trigger receives the comparison result of each comparison by the comparator, the first adder accumulates the multiple comparison results of the comparator to obtain an accumulated result, the divider calculates the first codeword and the second codeword based on the accumulated result and the number of comparisons, the second adder subtracts the first codeword from the second codeword and divides by 2 to obtain the probability value of the comparator noise corresponding to the voltage value generated by the flipping of the first capacitor array and the second capacitor array, and the lookup table circuit obtains the standard deviation of the normal distribution of the comparator noise from the standard normal distribution stored therein based on the probability value and the corresponding voltage value.
3. The comparator noise estimation method for a successive approximation analog-to-digital converter as described in claim 2, characterized in that, The logic control circuit includes a clock generation circuit that generates a comparison clock signal to the comparator and the counter. The comparator performs multiple comparisons based on the comparison clock signal, and the counter counts based on the comparison clock signal.
4. The comparator noise estimation method for a successive approximation analog-to-digital converter as described in claim 3, characterized in that, The clock generation circuit generates a sampling clock signal, which controls the on / off state of the sampling switch. When the sampling clock signal is high, the sampling switch is turned on. When the sampling clock signal is low, the sampling switch is turned off, and the clock generation circuit generates the comparison clock signal.
5. The comparator noise estimation method for a successive approximation analog-to-digital converter as described in claim 2, characterized in that, The trigger is an SR latch.
6. The comparator noise estimation method for a successive approximation analog-to-digital converter as described in claim 1, characterized in that, The comparator performs comparisons 4 to 8 times.
7. The comparator noise estimation method for a successive approximation analog-to-digital converter as described in claim 1, characterized in that, The first capacitor array and the second capacitor array each include a capacitor of multiple bits.
8. The comparator noise estimation method for a successive approximation analog-to-digital converter as described in claim 1, characterized in that, In the first capacitor array and the second capacitor array, the bottom plate of each capacitor is connected to a positive reference voltage and a negative reference voltage respectively through a single-pole double-throw switch.
9. A successive approximation analog-to-digital converter, characterized in that, The successive approximation analog-to-digital converter includes a first capacitor array, a second capacitor array, a comparator, and a logic control circuit. The top plate of each capacitor in the first capacitor array is connected to a common-mode voltage and the negative input terminal of the comparator, and is also connected to the common-mode voltage via a sampling switch. Similarly, the top plate of each capacitor in the second capacitor array is connected to a common-mode voltage and the positive input terminal of the comparator, and is also connected to the common-mode voltage via a sampling switch. The output terminal of the comparator is coupled to the logic control circuit. The logic control circuit determines a digital codeword based on the comparator's output to control the bottom plate of each capacitor in the first and second capacitor arrays to connect to either a positive or negative reference voltage. The successive approximation analog-to-digital converter also includes a noise estimation circuit. The logic control circuit controls the sampling switch to charge the first capacitor array and the second capacitor array with the common-mode level, connects the bottom plate of each capacitor in the first capacitor array to the positive reference voltage, connects the bottom plate of each capacitor in the second capacitor array to the negative reference voltage, connects the bottom plate of the least significant capacitor in the first capacitor array to the negative reference voltage, and connects the bottom plate of the least significant capacitor in the second capacitor array to the positive reference voltage. The logic control circuit controls the comparator to perform multiple comparisons and outputs the comparison results. The noise estimation circuit calculates the first codeword based on the comparison results. The logic control circuit controls the sampling switch to charge the first capacitor array and the second capacitor array with the common-mode level, connects the bottom plate of each capacitor in the first capacitor array to the negative reference voltage, connects the bottom plate of each capacitor in the second capacitor array to the positive reference voltage, connects the bottom plate of the least significant capacitor in the first capacitor array to the positive reference voltage, and connects the bottom plate of the least significant capacitor in the second capacitor array to the negative reference voltage. The logic control circuit controls the comparator to perform multiple comparisons and outputs the comparison results. The noise estimation circuit calculates the second codeword based on the comparison results. The noise estimation circuit subtracts the first codeword from the second codeword and divides by 2 to obtain the probability value of the normal distribution of the comparator noise corresponding to the unit voltage of the capacitor array, and determines the standard deviation of the normal distribution of the comparator noise based on the probability value.