Method for obtaining check matrix and communication device

Abstract

The invention provides a method for obtaining a check matrix and a communication device. In the method, a communication device can obtain a check matrix based on a first basis matrix. Compared with the base graph, patch elements are added to the first base matrix, and the patch elements can correspond to the cyclic shift sub-matrixes in the check matrix, so that the number of non-zero elements in the check matrix can be increased, the existence of light columns and heavy columns in the check matrix is reduced, the decoding performance of the flat layer area is improved, and the reliability is improved. Moreover, according to the scheme, the position of the patch element is further determined according to the target code rate, so that the adding of the patch element can obtain greater benefits.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of wireless communication, and in particular to a method for obtaining a check matrix and a communication device. BACKGROUND

[0002] Low density parity check (LDPC) code is a kind of linear block code with sparse check matrix. LDPC code not only has good performance of approaching Shannon limit, but also has low decoding complexity and flexible structure. Therefore, LDPC code has been well applied in some communication systems.

[0003] At present, when LDPC encoding is performed by using a base graph (BG) 1 and a BG 2 defined in a new radio (NR) protocol, in a lower signal noise ratio (SNR) interval, a block error rate (BLER) significantly decreases with an increase of the SNR; and in a higher SNR interval, a trend of the BLER decreasing with the increase of the SNR slows down, and an error floor is obviously present, which may result in low decoding performance, and especially for some scenarios with high reliability requirements, there is a potential risk.

[0004] Therefore, how to improve the decoding performance of the error floor and improve the reliability has become a technical problem to be solved. SUMMARY

[0005] The present application provides a method for obtaining a check matrix and a communication device, so as to improve the decoding performance of the error floor and improve the reliability.

[0006] In a first aspect, a method for obtaining a check matrix is provided. The communication device can be a communication device such as a network device or a terminal device, can be a component configured in the communication device such as a circuit or a chip (such as a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or a system in package (SIP) chip containing a modem core, etc.) in the communication device, can be a logic module or software capable of realizing part or all functions of the communication device, etc., and the present application does not limit the same.

[0007] Exemplarily, the method comprises: obtaining a first base matrix; the first base matrix comprises Q patch elements, each patch element in the Q patch elements has a first value, and the positions of the Q patch elements in the first base matrix coincide with the positions of Q elements having a second value in a second base matrix, Q being a positive integer; and obtaining a check matrix from the first base matrix, the check matrix being used for LDPC encoding or LDPC decoding, the first value corresponding to a cyclic shift square matrix in the check matrix, and the second value corresponding to an all-zero square matrix in the check matrix.

[0008] It can be understood that the cyclic shift square matrix can also be referred to as a cyclic shift submatrix, and the all-zero square matrix can also be referred to as an all-zero submatrix.

[0009] Further, the method further comprises: performing LDPC encoding or LDPC decoding by using the check matrix.

[0010] Based on the above scheme, the communication apparatus can perform LDPC encoding or LDPC decoding based on the check matrix obtained based on the first base matrix. Since the first base matrix has more elements having the first value than the second base matrix, that is, there are more cyclic shift square matrices in the check matrix. This is conducive to increasing the number of non-zero elements in the check matrix, reducing the existence of light columns in the check matrix, improving the decoding performance of the flat area, and improving the reliability. Thus, it can be applied to some scenarios with high reliability requirements, reducing the risk.

[0011] In combination with the first aspect, in some possible implementation manners of the first aspect, the first value is 1, and the second value is 0; or the first value is greater than or equal to 0, and the second value is -1. The present application does not limit the specific values of the first value and the second value.

[0012] In combination with the first aspect, in some possible implementation manners of the first aspect, the first base matrix is obtained according to the second base matrix.

[0013] It should be understood that the second base matrix can be in the form of a base matrix defined in the current new radio (NR), or a base matrix obtained based on the base matrix. In one possible scenario, the second base matrix is pre-stored in the communication apparatus, and the communication apparatus can first obtain the second base matrix, and then obtain the first base matrix according to the second base matrix, thereby reducing the storage overhead caused by pre-storing the first base matrix.

[0014] In combination with the first aspect, in some possible implementation manners of the first aspect, the Q patch elements are located in the first m b rows of the first base matrix, m b satisfying: R is a target code rate, which can be a code rate indicated by a modulation coding scheme (MCS), k b is a number of columns of information bits in the first base matrix, d b is a number of columns of punctured bits in the first base matrix, represents rounding up.

[0015] Since in the LDPC code, the fewer the number of rows actually participating in encoding in the check matrix, the higher the code rate; the more the number of rows actually participating in encoding in the check matrix, the lower the code rate. If the cyclic shift sub-matrix is added in the first m b ' rows of the check matrix, the decoding performance can be affected. Since each non-zero element in the first base matrix is a Z×Z sub-matrix, the first m b ' rows of the check matrix can correspond to the first m b ' rows of the first base matrix, the Q patch elements can be controlled in the first m b ' rows of the first base matrix. Therefore, the range of the rows in which the Q patch elements are located in the first base matrix can be determined according to the target code rate.

[0016] Therefore, the range of the rows in which the Q patch elements are located in the first base matrix is determined according to the target code rate, which is beneficial to increasing the number of elements 1 in the rows actually participating in encoding in the check matrix, so that the addition of the patch elements can obtain greater benefits.

[0017] In combination with the first aspect, in some possible implementation manners of the first aspect, the position information of the patch elements corresponding to the plurality of code rates includes same G column indexes, and G is a positive integer.

[0018] That is, the columns in which the patch elements are located do not change with the change of the code rate. The position information of the patch elements can be pre-stored in the communication device, and if the position information of the patch elements corresponding to the plurality of code rates includes same column indexes, excessive storage overhead can be avoided.

[0019] Optionally, the G columns indicated by the G column indexes satisfy that in G' columns of the second base matrix, the first G columns are arranged in descending order of statistical values of error bit numbers corresponding to the columns; the statistical value of the error bit number corresponding to the i-th column in the G' columns is a function of error bit numbers corresponding to the i-th column in a plurality of sub-matrices of the second base matrix; any one of the plurality of sub-matrices includes the first m b ' rows of the G' columns of the second base matrix, and the m bThe value of ' corresponds to the code rate corresponding to any of the submatrices. The G' columns can be one or more predefined columns, and G' is a positive integer greater than or equal to G.

[0020] Optionally, any one of the plurality of submatrices of the second basis matrix includes the first m from the top left corner of the second basis matrix. b 'The first S columns of the row, and the m corresponding to different sized submatrices. b The values ​​of ' and S differ, and different sizes of submatrices correspond to different code rates; that is, the m values ​​of multiple submatrices... b The value of ' can correspond one-to-one with multiple code rates. For example, in BG 2 of the NR protocol, its complete base matrix (as an example of the second base matrix above) is 42×52. With 2 columns punched, the submatrix corresponding to a code rate of 0.67 is the matrix formed by the first 7 rows and first 17 columns of this base matrix (i.e., m). b '=7,S=17); the submatrix corresponding to a code rate of 0.5 is the matrix formed by the first 12 rows and first 22 columns of the base matrix (i.e., m b '=12,S=22). Where, m b The value of ' can also be called the number of rows in the submatrix, that is, the number of rows included in the submatrix. The value of S is a positive integer.

[0021] The column index of the patch element is determined based on the number of error bits in each column. In other words, patch elements are added to columns with a large number of error bits to improve decoding performance.

[0022] Optionally, the G columns indicated by the G column indices satisfy the following: among the G' columns of the second base matrix, they are ranked in ascending order of the statistical value of the number of target elements contained in each column; wherein, the statistical value of the number of target elements contained in the i-th column of the G' columns is a function of the number of target elements contained in the i-th column of each of the plurality of submatrices of the second base matrix; any one of the plurality of submatrices includes the first m columns of the G' columns of the second base matrix. b 'Okay, the m b The value of ' corresponds to the bitrate of any of the sub-matrices. The G' columns are one or more predefined columns, and G' is a positive integer greater than or equal to G. The target element is the element whose value is the first value. Optionally, the G' columns are the first G' columns, such as the first G' columns starting from the left vertex, or the first G' columns from the top left corner. In this case, the multiple sub-matrices come from the G' columns.

[0023] For information on the number of rows in a submatrix, and the correspondence between the number of rows in multiple submatrixes and multiple bitrates, please refer to the above text, which will not be repeated here.

[0024] Optionally, the above function can be used to take a weighted average, take the maximum value, etc., which is not limited here.

[0025] Since the first value corresponds to the cyclic shift submatrix in the parity check matrix, the column index of the patch element is determined based on the number of target elements contained in each column. This is equivalent to determining the column index of the patch element based on the column weight of each column in the parity check matrix. Therefore, patch elements can be added to columns with lighter column weights to improve decoding performance.

[0026] In conjunction with the first aspect, in some possible implementations of the first aspect, the position information of the patch element corresponding to each of the plurality of bitrates includes one or more column indices, and the position information of the patch element corresponding to at least two of the plurality of bitrates includes at least one different column index.

[0027] In other words, the column where the patch element is located can also change with the bitrate. That is, determining the column index of the patch element based on the bitrate allows for more precise and flexible determination of the patch element's position.

[0028] Optionally, the Q patch elements are located in G columns of the first base matrix, and the G columns satisfy the following condition: in a submatrix of the second base matrix, the columns are ranked in descending order of the number of error bits corresponding to each column; wherein, the submatrix of the second base matrix includes the first m columns of the G' columns of the second base matrix. b 'Okay, the m b The value of ' has a corresponding relationship with the target bit rate. The G' columns are one or more predefined columns, and G' is greater than or equal to G. G' and G are positive integers.

[0029] The column index of the patch element is determined based on the number of error bits in each column. In other words, patch elements are added to columns with a large number of error bits to improve decoding performance.

[0030] Optionally, the Q patch elements are located in the G columns of the first base matrix, and the G columns satisfy the following condition: in the submatrix of the second base matrix, they are ranked in ascending order of the number of target elements contained in each column; wherein, the submatrix of the second base matrix includes the first m columns of the G' columns of the second base matrix. b 'Okay, the m b The value of ' has a corresponding relationship with the target bitrate. The G' columns are one or more predefined columns, and G' is greater than or equal to G. G' and G are positive integers. The target element is an element whose value is the first value.

[0031] Since the first value corresponds to the cyclic shift submatrix in the parity check matrix, the column index of the patch element is determined based on the number of target elements contained in each column. This is equivalent to determining the column index of the patch element based on the column weight of each column in the parity check matrix. Therefore, patch elements can be added to columns with lighter column weights to improve decoding performance.

[0032] In conjunction with the first aspect, in some possible implementations of the first aspect, the method further includes: determining the use of the first basis matrix.

[0033] The communication device can determine whether to use the first basis matrix to obtain the parity check matrix based on actual needs. This allows for more flexible selection of different schemes to address different scenarios and achieve greater benefits in various situations.

[0034] Optionally, determining to use the first basis matrix includes: determining to use the first basis matrix if a first condition is met.

[0035] The communication device can determine whether to use the first basis matrix. For example, this first condition is related to the channel environment, the capabilities of the communication device, and the service scenario. Therefore, the communication device can flexibly choose different solutions to cope with different scenarios and obtain greater benefits in different scenarios.

[0036] Furthermore, the method further includes: sending first indication information, the first indication information being used to indicate the use of the first base matrix or to indicate the first base matrix.

[0037] The communication device indicates whether to use the first base matrix through the first indication information, so that another communication device communicating with it can also obtain the parity matrix based on the same base matrix, thereby avoiding decoding errors and improving decoding performance.

[0038] Optionally, the method further includes: receiving second indication information, the second indication information being used to indicate the use of the first basis matrix, or indicating the first basis matrix; the determination to use the first basis matrix includes: determining to use the first basis matrix based on the second indication information.

[0039] The communication device can also determine which basis matrix to use to obtain the parity matrix based on the instructions of another communication device with which it communicates, thereby avoiding decoding errors and improving decoding performance.

[0040] Secondly, a communication device is provided. This communication device may include modules corresponding to the methods / operations / steps / actions described in the first aspect, or may include modules corresponding to the methods / operations / steps / actions described in the first aspect. These modules may be hardware circuits, software, or a combination of hardware circuits and software.

[0041] In one design, the communication device may include a processing module and a communication module. The communication module is used to perform the sending and receiving actions performed by the communication device in the method described in the first aspect above, while the processing module is used to perform processing-related actions performed by the communication device in the method described in the first aspect above.

[0042] In one design, the device can be a terminal, or a device, module, circuit, or chip configured in the terminal, or a device that can be used in conjunction with the terminal.

[0043] In one design, the device can be a network device, or a device, module, circuit, or chip configured in the network device, or a device that can be used in conjunction with the network device.

[0044] Thirdly, a communication device is provided, including a processor and a storage medium storing instructions that, when executed by the processor, cause a method as described in the first aspect or any possible implementation thereof to be implemented.

[0045] Fourthly, an apparatus is provided, including processing circuitry for processing data and / or information such that the methods described in the first aspect or any possible implementation thereof are implemented.

[0046] The processing circuit may include one or more processors, or all or part of the circuitry in one or more processors used for processing functions.

[0047] Optionally, the apparatus may further include a memory for storing programs or instructions, and the processor for running the programs or instructions to implement the methods as described in the first aspect or any possible implementation thereof.

[0048] Optionally, the device may also include the transceiver circuit, or an input / output interface.

[0049] Fifthly, a chip is provided, including processing circuitry for running programs or instructions to implement methods as described in the first aspect or any possible implementation thereof.

[0050] Optionally, the chip may further include a memory for storing programs or instructions.

[0051] Optionally, the chip may also include transceiver circuitry, or input / output interfaces.

[0052] A sixth aspect provides a computer-readable storage medium comprising instructions that, when executed by a processor, cause the method as described in the first aspect or any possible implementation thereof to be implemented.

[0053] In a seventh aspect, a computer program product is provided, the computer program product including computer program code or instructions, which, when executed, cause the methods of the first aspect and any possible implementation thereof to be implemented.

[0054] Eighthly, a communication system is provided, the communication system including communication means performing the first aspect and any possible implementation thereof.

[0055] It should be understood that the second to eighth aspects of this application correspond to the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of a communication system applicable to the methods provided in the embodiments of this application;

[0057] Figure 2 These are schematic diagrams illustrating several different communication scenarios applicable to the methods provided in the embodiments of this application;

[0058] Figure 3 This is a schematic diagram of the signal processing process of the physical layer provided in the embodiments of this application;

[0059] Figure 4 This is a schematic block diagram of a device used to implement physical layer processing;

[0060] Figure 5 This is an example of a Tanner diagram provided in an embodiment of this application;

[0061] Figure 6 This is a schematic diagram of the structure of the verification matrix provided in the embodiments of this application;

[0062] Figure 7 These are two different dimensions of Raptor-like structures provided in the embodiments of this application;

[0063] Figure 8 This is a schematic diagram illustrating the relationship between base graph (BG) selection and transport block size (TBS) and rate provided in the embodiments of this application.

[0064] Figure 9 These are performance simulation diagrams provided in the embodiments of this application;

[0065] Figure 10 This is a graph showing the correspondence between the columns of BG 2 obtained from the statistics provided in the embodiments of this application and the number of error bits;

[0066] Figure 11 This is a schematic flowchart of the method for obtaining a verification matrix provided in an embodiment of this application;

[0067] Figure 12 This is a schematic diagram of the first basis matrix provided in an embodiment of this application;

[0068] Figure 13 This is another schematic diagram of the first basis matrix provided in the embodiments of this application;

[0069] Figure 14 These are performance simulation diagrams provided in the embodiments of this application;

[0070] Figure 15 This is a schematic block diagram of the communication device provided in the embodiments of this application;

[0071] Figure 16 This is another schematic block diagram of the communication device provided in the embodiments of this application. Detailed Implementation

[0072] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0073] Before introducing the scheme of this application, the following points should be noted.

[0074] First, in this application, the indication includes explicit indication (also known as direct indication) and implicit indication (also known as indirect indication). Explicit indication information A means including information A; implicit indication information A means indicating information A through the correspondence between information A and information B, and direct indication information B. The correspondence between information A and information B can be predefined, pre-stored, pre-burned, or pre-configured; or it can refer to indicating information A through information B and preset rules.

[0075] Second, in this application, information C is used to determine information D, which includes both determining information D based solely on information C and determining it based on information C and other information. Furthermore, information C can also be used to determine information D indirectly, for example, in the case where information D is determined based on information E, and information E is determined based on information C.

[0076] Third, in this application, "at least one" means one or more, and "more than one" means two or more. The expression " / " is used to indicate that the objects before and after are in an "or" relationship; for example, A / B can mean: A or B. The expression "and / or" is used to indicate that the objects before and after are in a relationship of either "and" or "or", for example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects before and after are in an "or" relationship, but it does not exclude the possibility that the objects before and after are in a relationship of "and". The specific meaning can be understood in conjunction with the context. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c; a and b; a and c; b and c; or a and b and c. Where a, b, and c can be single or multiple.

[0077] Fourth, the use of prefixes such as "first" and "second" in this application is solely for the purpose of distinguishing different things belonging to the same name category, and does not constrain the order, size, or quantity of things. For example, "first instruction information" and "second instruction information" are simply different instruction information, and there is no temporal sequence, size, or priority relationship between them; similarly, "first basis matrix" and "second basis matrix" are simply different basis matrices, and there is no temporal sequence, size, or priority relationship between them. It should be understood that such described objects can be interchanged where appropriate, so as to describe solutions other than those in the embodiments of this application.

[0078] Fifth, in this application, "send" and "receive" indicate the direction of signal transmission. For example, "send information to XX" can be understood as the destination of the information being XX, which can include direct transmission via the air interface or indirect transmission by other units or modules via the air interface. "Receive information from YY" can be understood as the source of the information being YY, which can include direct reception from YY via the air interface or indirect reception from YY by other units or modules via the air interface. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface. In other words, sending and receiving can occur between devices, such as between a terminal device and a computing node, or within a device, such as between components, modules, chips, software modules, or hardware modules within the device via a bus, wiring, or interface.

[0079] Sixth, in the embodiments of this application, "when," "if," and "if" all refer to the device making corresponding processing under certain objective circumstances, and are not limited to a time, nor do they require the device to make a judgment action when it is implemented, nor do they mean that there are other limitations.

[0080] Seventh, in this application, the words "example," "exemplarily," "for example," or "such as" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "example," "exemplarily," "for example," or "such as" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "example," "exemplarily," "for example," or "such as" is intended to present the relevant concepts in a specific manner.

[0081] Eighth, to facilitate understanding of the method provided in this application, specific examples are used in many places in the following description. In the examples shown below, the row index, column index, etc., are numbered starting with 0, but this should not constitute any limitation on this application. For example, these numbers can also start with 1, or with other preset values. Therefore, this application does not limit the range of values ​​for the row index, column index, etc.

[0082] The technical solutions provided in this application can be applied to various communication systems, such as: 5th generation (5G) or new radio (NR) systems, long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, wireless local area network (WLAN) systems, satellite communication systems, future communication systems, or integrated systems of multiple systems. The technical solutions provided in this application can also be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems or other communication systems.

[0083] In a communication system, a device can send signals to or receive signals from another device. These signals can include information, signaling, or data. The device can also be replaced by an entity, network entity, communication equipment, communication module, node, communication node, etc.; this application uses a device as an example. For instance, a communication system can include at least one terminal device and at least one network device. The network device can send downlink signals to the terminal device, and / or the terminal device can send uplink signals to the network device. It is understood that the terminal device in this application can be replaced by a first communication device, and the network device can be replaced by a second communication device, both performing the corresponding communication methods described in this application.

[0084] The radio access network (RAN) device in this application is a device with wireless transceiver capabilities. The RAN device can provide wireless communication services, enabling terminal devices to access the wireless network. The RAN can also be called an access network device or a network device. In the embodiments of this application, the network device can refer to a radio access network (RAN) node (or device) used in a cellular network (or mobile network) to connect terminal devices to the wireless network. It can also be a Zigbee base station, a Bluetooth master (BTmaster), a Bluetooth Low Energy (BLE) master, a long-range radio (Lora) base station, or a Wi-Fi access point.

[0085] Network equipment can be a base station. The term "base station" can broadly encompass, or be interchangeable with, various names including: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or similar entities, or combinations thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device that performs base station functions in D2D, V2X, and M2M communications, or a device that performs base station functions in future communication systems. A base station can support networks with the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technology or equipment form used in the network equipment. In some deployments, the network equipment mentioned in the embodiments of this application can be a device including a CU, or a DU, or a device including both CU and DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network equipment can include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0086] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0087] RAN nodes can support one or more types of fronthaul interfaces, each corresponding to a DU and RU with different functions. If the fronthaul interface between the DU and RU is a common public radio interface (CPRI), the DU is configured to implement one or more baseband functions, and the RU is configured to implement one or more radio frequency functions. If the fronthaul interface between the DU and RU is another type of interface, relative to CPRI, some downlink and / or uplink baseband functions, such as, for downlink, one or more of precoding, beamforming (BF), or inverse fast Fourier transform (IFFT) / adding a cyclic prefix (CP), are moved from the DU to the RU; and for uplink, one or more of beamforming (BF), or fast Fourier transform (FFT) / removing CP, are moved from the DU to the RU. In one possible implementation, the interface can be an enhanced common public radio interface (eCPRI). Under the eCPRI architecture, the segmentation between DU and RU differs, corresponding to different categories (Cat) of eCPRI, such as eCPRI Cat A, B, C, D, E, and F.

[0088] Taking eCPRI Cat A as an example, for downlink transmission, layer mapping is used as the dividing line. The DU is configured to implement one or more functions preceding layer mapping (i.e., coding, rate matching, scrambling, modulation, and layer mapping itself), while other functions following layer mapping (e.g., resource element (RE) mapping, digital BF, or IFFT / CP addition) are implemented in the RU. For uplink transmission, de-RE mapping is used as the dividing line. The DU is configured to implement one or more functions preceding de-mapping (i.e., decoding, rate matching de-matching, descrambling, demodulation, inverse discrete Fourier transform (IDFT), channel equalization, and de-RE mapping itself), while other functions following de-mapping (e.g., digital BF or FFT / CP removal) are implemented in the RU. It is understood that descriptions of the functions of the DU and RU corresponding to various types of eCPRI can be found in the eCPRI protocol and will not be elaborated upon here.

[0089] In one possible design, the processing unit in the BBU used to implement baseband functions is called the baseband high (BBH) unit, and the processing unit in the RRU / AAU / RRH used to implement baseband functions is called the baseband low (BBL) unit.

[0090] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open-RAN (O-RAN or ORAN) system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules. The network device in this application can be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. Among them, general-purpose hardware can be a server, such as a cloud server.

[0091] In this embodiment, the apparatus for implementing the functions of a network device can be a network device itself; it can also be an apparatus capable of supporting the network device in implementing those functions, such as a chip system, hardware circuit, software module, or a hardware circuit plus a software module. This apparatus can be installed in the network device or used in conjunction with the network device. In this embodiment, the example of a network device being used to implement the functions of a network device is provided only and does not constitute a limitation on the solutions described in this embodiment.

[0092] The terminal equipment in this application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device.

[0093] Terminal devices can be devices that provide voice / data, such as handheld devices with wireless connectivity, in-vehicle devices, etc. Currently, examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, wearable devices, terminal devices in 5G networks, or future public land mobile communication networks. Terminal devices in a network (PLMN), devices in a Zigbee network, devices in a LoRa network, Bluetooth slaves, Bluetooth Low Energy slaves, Wi-Fi stations (STAs), etc. This application does not limit the scope of the embodiments.

[0094] Terminal devices can also be terminal devices in an IoT system, also known as IoT nodes. IoT is an important component of future information technology development. Its main technical characteristic is connecting objects to networks through communication technologies, thereby realizing an intelligent network that enables human-machine interconnection and machine-to-machine interconnection. Connectivity can be achieved through broadband or narrowband technologies. IoT technology, for example, can achieve massive connectivity, deep coverage, and low terminal power consumption through narrowband (NB) technology. IoT technologies include reflective communication technology, spread spectrum technology, and ultra-wideband (UWB), which will not be elaborated further.

[0095] In addition, terminal devices may also include sensors such as smart printers, train detectors, and gas stations. Their main functions include collecting data (for some terminal devices), receiving control information and downlink data from network devices, and sending electromagnetic waves to transmit uplink data to network devices.

[0096] By way of example and not limitation, in this embodiment, the terminal device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0097] In this embodiment, the device for implementing the functions of the terminal device can be the terminal device itself, or it can be any device capable of supporting the terminal device in implementing those functions, such as a chip system. This device can be installed in or used in conjunction with the terminal device. In this embodiment, the chip system can be composed of chips or may include chips and other discrete components. This embodiment only uses the terminal device as an example to illustrate the device for implementing the functions of the terminal device, and does not constitute a limitation on the solution of this embodiment.

[0098] The terminal device in this application can be a hardware device, a software function running on dedicated hardware, or a software function running on general-purpose hardware. It can also be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. Among them, the general-purpose hardware can be a server, such as a cloud server.

[0099] Network devices and / or terminal devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and satellites. This application does not limit the scenario in which the network devices and terminal devices are located.

[0100] Figure 1 This is a schematic diagram of the architecture of the communication system 10 used in the embodiments of this application. Figure 1 A schematic diagram of a possible, non-limiting system architecture is shown. (e.g.) Figure 1As shown, the communication system 10 includes a radio access network (RAN) 100 and a core network 200. Optionally, the communication system 10 also includes an Internet 300. The RAN 100 may include at least one RAN node (e.g., Figure 1 110a and 110b in the above), may also include at least one terminal device (such as Figure 1 (120a-120j in the RAN 100). Terminal devices can connect to radio access network (RAN) devices wirelessly. Terminal devices can connect to each other, and RAN devices can connect to each other via wired or wireless means. RAN nodes 110a or 110b connect to the core network 200 wirelessly or via wired means. The core network devices in the core network 200 and RAN nodes 110a or 110b in the RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and RAN access network logical functions.

[0101] Figure 1 This is just an illustration; the communication system 10 may also include other network devices, such as wireless repeaters and wireless backhaul devices. Figure 1 It is not shown in the middle.

[0102] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be ORAN, cloud radio access network (CRAN), Zigbee network systems, or wireless fidelity (Wi-Fi) systems. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0103] The RAN node can be an airborne base station, such as satellite base station 110a; or an indoor base station, such as a micro base station or indoor station 110b. It should be understood that this application does not limit the specific technology or device form used in the wireless access network equipment. For ease of description, the following description uses a base station as an example of a wireless access network device.

[0104] The terminal device can be a terminal device deployed in the air, such as... Figure 1 The 120i can be a helicopter or drone; it can also be a terminal device deployed on the ground, such as... Figure 1Among them are mobile phones 120a, 120e, 120f and 120j, vehicles 120b, computers 120g, printers 120h, gas stations 120c, smart home devices 120d, etc.

[0105] Alternatively, the terminal device can also be used as a RAN node. For example, the UE can act as a scheduling entity, providing sidelink signaling between terminal devices in vehicle-to-everything (V2X), device-to-device (D2D), or peer-to-peer (P2P) scenarios.

[0106] RAN nodes and terminal devices can be fixed or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; on water; or in the air on aircraft, balloons, and satellites. The embodiments of this application do not limit the application scenarios of the RAN nodes and terminal devices.

[0107] The roles of RAN nodes and terminal devices can be relative, for example, Figure 1 The helicopter or drone 120i can be configured as a RAN node. For terminal devices 120j that access RAN 100 via 120i, terminal device 120i is a RAN node; however, for RAN node 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Alternatively, 110a and 120i can also communicate via an interface protocol between RAN nodes; in this case, 120i is also a RAN node relative to 110a. Therefore, both RAN nodes and terminal devices can be collectively referred to as communication devices. Figure 1 110a, 110b, and 120a-120j can be referred to as communication devices with their respective corresponding functions, such as communication devices with RAN node functions or communication devices with terminal functions.

[0108] In the embodiments of this application, the functions of the RAN node can be executed by modules (such as chips) within the RAN node, or by a control subsystem that includes RAN node functions. This control subsystem, including RAN node functions, can be a control center in the aforementioned terminal application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. The functions of the terminal device can also be executed by modules (such as chips) within the terminal device, or by a device that includes terminal device functions. This application does not limit the scope of these limitations.

[0109] Figure 2These are schematic diagrams illustrating several different communication scenarios applicable to the communication methods provided in the embodiments of this application. For example, point-to-point transmission between RAN nodes and terminals or between terminals (such as...). Figure 2 (a) in the text refers to point-to-point transmission between RAN nodes and terminals, and multi-hop transmission between RAN nodes and terminals (e.g., ...). Figure 2 (b) Figure 2 (c) Transmission, dual connectivity (DC) of multiple RAN nodes and terminals (e.g.) Figure 2 (d) or multiple connections, etc. It should be noted that the specific communication application scenarios mentioned above are merely examples and do not constitute limitations. In particular, from a business perspective, the embodiments of this application are applicable to many business scenarios, such as data encoding scenarios and high-capacity uplink scenarios in extended reality (XR) services. Furthermore, Figure 2 This application does not impose any restrictions on the network architecture applicable to this application, and it does not restrict uplink, downlink, access link, backhaul link, sidelink (SL) and other transmissions.

[0110] Figure 3 This is a schematic diagram of the signal processing process of the physical layer applicable to embodiments of this application. The signal processing of the physical layer can be divided into downlink processing and uplink processing.

[0111] Downlink processing is the process of processing information data from higher layers using the physical layer before transmitting it. For example, downlink processing includes: performing channel coding (or simply coding) on ​​the layer 2 (L2) information data, modulation, layer mapping, precoding, framing, IFFT, and frequency conversion using radio frequency (RF) or intermediate radio frequency (IRF) to convert it into an air interface signal to be transmitted.

[0112] More specifically, the data transmitter can divide the data from Layer 2 into multiple TBs based on the system's supported transport block (TBS) size (TBS), and add a cyclic redundancy check (CRC) code to each TB. If the size of the TB after adding the CRC code exceeds the maximum code block length, the TB can be segmented to obtain multiple code blocks (CBs). Each segmented CB can be further coded with a CRC code to obtain the input to be encoded corresponding to each CB. This input to be encoded is a sequence of bits to be encoded, specifically including the information bits and check bits (i.e., the CRC code) in its corresponding CB. The transmitter can perform channel coding on this input to be encoded, such as LDPC coding, to obtain the corresponding coded code blocks. Rate matching is performed on the coded code blocks, and the rate-matched coded code blocks are concatenated to form codewords (CWs). The transmitter can scramble the codewords to generate scrambled bits. The scrambled bits are modulated to obtain modulation symbols. After being mapped by resource elements (REs), the modulation symbols are mapped onto multiple REs, thus obtaining the value carried on each RE. Based on the values ​​carried on these REs, the transmitter can generate a baseband signal. The baseband signal can then be processed by RF or IRF and transmitted by the antenna.

[0113] Uplink processing is the process of physical layer processing of signals received through the air interface. For example, uplink processing includes: performing IRF processing on the received signal to obtain the baseband signal, and then completing physical layer signal processing through FFT, deframing, demodulation, and decoding, and then handing the obtained information data to layer 2.

[0114] More specifically, the signal receiver performs RF or IRF processing on the signal received from the antenna to obtain the baseband signal. Subsequently, the receiver's physical layer can sequentially perform RE mapping, demodulation, descrambling, rate matching de-matching, and channel decoding on the signal to obtain the bit sequence before encoding, which may specifically include information bits and parity bits.

[0115] Optionally, after completing RE mapping and before demodulation, the receiver can perform channel equalization. Channel equalization is based on the channel estimated by the channel, and the influence of the channel is removed by using an equalization algorithm, thereby ensuring correct signal demodulation.

[0116] Optionally, after modulation but before RE mapping, the transmitting end can perform layer mapping and precoding. For example, the transmitting end can map the modulation symbols to multiple layers, and the layer-mapped modulation symbols are then precoded to obtain a precoded signal. The precoded signal is then mapped to multiple REs via RE mapping. Correspondingly, after performing de-layer mapping, the receiving end performs channel equalization and then demodulation; or, the receiving end can perform de-layer mapping and then demodulation after completing channel equalization; or it can perform de-layer mapping and then channel equalization after completing deframe.

[0117] because Figure 3 The specific implementation methods for each step can be achieved using existing technologies or future solutions; see the Third Generation Partnership Program (3). rd The relevant sections of the Generation Partnership Project (3GPP) technical specification (TS) 38.211 are not detailed here.

[0118] The apparatus for implementing the above-described physical layer processing can be a communication device, such as a network device or terminal, or a mobile communication chip, such as a baseband chip; this application does not limit this. Based on different functions, the apparatus can be divided into multiple units (or modules). For example, Figure 4 This is a schematic block diagram of a device used to implement physical layer processing. Figure 4 (a) and (b) show apparatus 400A and apparatus 400B, respectively. Apparatus 400A can be used to implement uplink processing, and apparatus 400B can be used to implement downlink processing.

[0119] like Figure 4 As shown in (a) and (b), devices 400A and 400B respectively include a computing unit, a control unit, and a storage unit. The computing unit is responsible for processing the logical operations of the device, specifically including encoding and / or decoding logical operations. The storage unit is responsible for storing data during the computing process, and can also be used to store information related to encoding and decoding, such as base maps. The control unit is responsible for scheduling and controlling the computing unit and storage resources.

[0120] For example, such as Figure 4 As shown in (a), the computing unit of device 400A can be used to perform operations such as TB CRC calculation, BG selection, code block segmentation, CB CRC calculation, LDPC encoding, and code block concatenation. The BG selection can be made from the BGs stored in the storage unit.

[0121] For example, such asFigure 4 As shown in (b), the computing unit of device 400B can be used to perform operations such as rate matching, hybrid automatic repeat request (HARQ) merging, LDPC decoding, CB CRC check, and TBCRC check.

[0122] In another possible implementation, the module in device 400A used for LDPC encoding is an encoder. In yet another possible implementation, the encoder can not only implement LDPC encoding but also perform LDPC encoding preprocessing and / or post-processing. LDPC encoding preprocessing includes, for example, one or more of the following: TB CRC calculation, BG selection, code block segmentation, or CB CRC calculation. LDPC encoding post-processing includes, for example, code block concatenation. For example, device 400A is an encoder. Of course, the encoder can also implement other functions besides LDPC encoding and its preprocessing and post-processing listed above, and this application does not limit this.

[0123] In one possible implementation, the module in device 400B used for LDPC decoding is a decoder. In another possible implementation, the decoder can not only perform LDPC decoding, but also perform LDPC decoding preprocessing and / or post-processing. LDPC decoding preprocessing includes, for example, one or more of the following: rate matching or HARQ merging. LDPC post-processing includes, for example, one or more of the following: CB CRC or TB CRC. For example, device 400B is a decoder. Of course, the decoder can also perform other functions besides LDPC decoding and its preprocessing and post-processing listed above, and this application does not limit this.

[0124] To facilitate understanding of the embodiments of this application, the following is a brief explanation of several terms used in this document.

[0125] Channel coding: Encoding information transmitted through unreliable channels in digital communication to improve the reliability of information transmission. In channel coding, the transmitting end can adopt a certain coding type to convert the original information (such as information bits) into encoded data of a certain format and transmit it through the channel; the receiving end needs to decode the received data and restore the original information. The most critical part of channel coding is forward error correcting coding (FEC). The purpose of error correcting coding is to ensure that the receiving end can automatically correct errors that occur in data transmission with the least possible redundancy overhead. At the same bit error rate, the smaller the overhead required, the higher the coding efficiency. Traditional channel coding types generally include linear block codes (LBCs) (such as Hamming codes, Gray codes, BCH codes (Bose-Chaudhuri-Hocquenghem codes), RS codes (Reed-Solomon codes), etc.), convolutional codes, and concatenated codes. These codes have their own different characteristics and performance, and are suitable for different scenarios.

[0126] Code rate: The proportion of useful information to total information in the encoded data stream. In this paper, useful information is denoted as information bits, and the encoded data stream is denoted as encoded bits. Encoded bits include information bits and parity bits (or redundancy bits). For example, if there are K information bits and N encoded bits after channel coding, then the coding code rate is K / N. The number of encoded bits after channel coding can also be called the code length. It can be understood that high redundancy results in a low coding code rate and strong anti-interference capability, but low transmission efficiency; conversely, low redundancy results in a high coding code rate and weak anti-interference capability, but high transmission efficiency.

[0127] LDPC code: A type of linear block code. Because the parity-check matrix of this linear block code has a sparse property, with elements having a value of 1 accounting for a very small proportion, it is also called an LDPC code. For an LDPC code with K information bits and N code length, its parity-check matrix has a dimension of (N-K)×N, and the corresponding codeword c can be defined by the parity-check matrix H:

[0128]

[0129] Where c represents K information bits; w represents (N+D-K) check bits; [cw] T This represents a column vector of length (N+D) consisting of K information bits and (N+D-K) check bits; D represents the number of puncture bits, where D is a positive integer, for example, D is 2^Z. c Z cZ represents the minimum value of Z, which is the lifting size. The value of Z can be predefined and is an integer greater than or equal to 1.

[0130] The process of LDPC encoding based on the parity-check matrix H is to obtain the encoded output [cw] given the parity-check matrix H and the input c to be encoded. T The process; the process of LDPC decoding based on the parity-check matrix H, that is, given the parity-check matrix H and the input to be decoded [cw] T The process of recovering the input c to be encoded.

[0131] Parity-check matrix: Used for LDPC encoding or decoding. In this application, the parity-check matrix is ​​denoted as a matrix H of dimension M×N. Here, M is the number of parity bits, which satisfies: M = N - K. Therefore, the dimension of the parity-check matrix can also be denoted as (N - K)×N.

[0132] In this parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and (N-K) parity-check equations correspond to (N-K) parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and N symbols correspond to N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... m,n This indicates that the m-th check node and the n-th variable node are connected, where m can be an integer greater than or equal to 0 and less than or equal to (M-1), and n can be an integer greater than or equal to 0 and less than or equal to (N-1). The number of non-zero elements in each row of the check matrix H represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, and all variable nodes also have the same degree, the corresponding LDPC code is a regular code; otherwise, it is an irregular code.

[0133] For example, the parity-check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 is as follows:

[0134]

[0135] In this verification matrix H, each row includes 10 variable nodes and each column includes 5 verification nodes. If we use c0, c1, ..., c9 to represent variable nodes and p0, p1, ..., p4 to represent verification nodes, the verification matrix H can be represented by a graphical model, such as a Tanner graph, a factor graph, or a tree graph.

[0136] Figure 5 An example of a Tanner diagram is shown. Figure 5 The Tanner graph shown corresponds to the parity check matrix H listed above, and the degree of a node is equal to the number of edges connected to that node in the Tanner graph. For example, h in the parity check matrix H above...0,0 If the value is 1, then the variable node c0 and the check node p0 in the Tanner graph are connected; similarly, h in the check matrix... 1,1 If the value is 0, then the variable node c1 and the check node p1 in the Tanner graph are not connected; and so on, without further enumeration.

[0137] In a Tanner graph, a closed path consisting of edges that start from a vertex, follow the edges between vertices, pass through different vertices, and return to the same vertex can be called a "cycle". The number of edges traversed is called the length of the cycle (or simply, the cycle length). Figure 5 For example, starting from variable node c0, the edge between variable node c0 and check node p0 leads to check node p0. Then, the edge between check node p0 and variable node c6 leads to variable node c6. Next, the edge between variable node c6 and check node p1 leads to check node p1. Finally, the edge between check node p1 and variable node c0 leads back to variable node c0. This forms a cycle of length 4 (e.g., ...). Figure 5 (As shown by the thick black line).

[0138] In LDPC codes, iterative probabilistic decoding involves the exchange and transmission of information between nodes. Rings inevitably affect the decoding results. Information originating from a node in the ring is continuously transmitted along the ring's nodes and returns to that node itself, causing the information within that node to accumulate and increasing the probability of decoding failure. The shorter the ring, the shorter the path required for information to return, the faster errors propagate during iteration, and the higher the probability of decoding failure. In other words, short rings severely impact decoding performance.

[0139] It's easy to see that a ring requires at least 4 nodes to form a ring of length 4. In other words, the minimum ring length is 4. Next are rings of 6, rings of 8, and so on, without further listing.

[0140] It should be noted that the above example of a loop is for ease of understanding and explanation, using a Tanner diagram as an example. In fact, loops are not limited to being marked in the Tanner diagram; they can also be marked in the base diagram, as shown later. Figure 10 The diagram also illustrates a ring using a base diagram as an example; see [link / reference] for details. Figure 10 As shown by the dashed line.

[0141] Quasi-cyclic low-density parity-check (QC-LDPC) codes: a subclass of LDPC. The parity check matrix of a QC-LDPC has quasi-cyclic properties, and its representation can be simplified based on the quasi-cyclic structure. For example, for an (N, K) QC-LDPC code, its parity check matrix H can be represented as:

[0142]

[0143] Where M = m b ×Z, N=n b ×Z, P i,j A cyclic shift matrix represents a Z×Z cyclic shift matrix (also called a cyclic shift square matrix or a cyclic shift submatrix) or a Z×Z all-zero matrix (also called an all-zero submatrix or an all-zero square matrix). A cyclic shift matrix can be represented by its corresponding cyclic shift coefficient V. i,j To simplify the representation, for example, the cyclic shift matrix can be defined as a cyclic right shift matrix of an identity matrix, where each element "1" in the identity matrix can be based on the cyclic shift coefficient V. i,j Perform a circular shift to the right. Where V i,j When P = -1, i,j V is a Z×Z matrix containing all zeros; i,j When P = 0, i,j V is a Z×Z identity matrix, which is obtained by cyclically shifting each "1" in the identity matrix to the right by 0 bits (or, in other words, without shifting); i,j ∈[-1, Z max When P = -1], i,j Circularly shift each element "1" in a Z×Z identity matrix to the right by V. i,j The matrix obtained by Z max It is the maximum value of Z, Z≤Z max .

[0144] The element P in the verification matrix H i,j The process of converting a matrix into a cyclic shift matrix or an all-zero matrix can be achieved using the conversion function g(V). i,j Z) represents the following:

[0145]

[0146] Where % represents the modulo operation; V i,jThe value can be predefined, for example, through a protocol, such as in Tables 5.3.2-2 and 5.3.2-3 of the 3rd Generation Partnership Project (3GPP) technical specification (TS) 38.212.

[0147] With Z=4, Z max For example, if the value is 8, the element P in the check matrix... i,j The correspondence between these matrices and cyclic shift matrices or all-zero matrices is as follows:

[0148] The matrix corresponding to the element "-1" That is, an all-zero matrix; elements "0" to "7" correspond to a cyclic shift matrix, where elements "0" and "4" correspond to a matrix The matrix corresponding to elements "1" and "5" The matrix corresponding to elements "2" and "6" The matrix corresponding to elements "3" and "7"

[0149] Base graph and base matrix: In some implementations, the base graph can be simplified as a table, array, or sequence indicating the row and column positions of non-zero elements. In other implementations, the base graph can be identified by a base matrix.

[0150] A base graph can be represented as a graph of dimension m. b ×n b The basis matrix is ​​m. The basis matrix can be used to construct the parity-check matrix of a QC-LDPC code. b ×n b The corresponding check matrix has a dimension of (m) b ×Z)×(n b As can be seen, each element in the basis matrix can be replaced with a matrix of dimension Z×Z, which can be called a submatrix of dimension Z×Z in the parity matrix.

[0151] It should be noted that the terms "Z×Z matrix" and "Z×Z submatrix" mentioned above refer to different objects. A single element in the base matrix can replace a Z×Z matrix, which is only a part of the parity check matrix and can therefore be called a submatrix of the parity check matrix.

[0152] A basis matrix can include zero elements and non-zero elements. Zero elements in a basis matrix can be replaced with a Z×Z matrix of all zeros; non-zero elements in a basis matrix can be a Z×Z cyclic parity check matrix P. i,jLet i and j represent the row and column positions of the non-zero elements in the basis matrix, respectively, and P i,j The specific cyclic shift matrix to be replaced can be determined by the transformation function g(V) mentioned above. i,j The determination is made by Z, which will not be elaborated here.

[0153] In the basis matrix, zero elements can be represented by 0, and non-zero elements can be represented by 1. The number of bits for cyclic shift can be determined according to the conversion function g(V) mentioned above. i,j The value can be determined by (Z); or, zero elements can be represented by -1, non-zero elements by 0, and the number of bits for the circular shift can be determined by the conversion function g(V) mentioned above. i,j The value can be determined by (Z); or, a zero element can be represented by -1, a non-zero element can be represented by a value greater than or equal to 0, and the number of digits in a cycle can be indicated by the value of the non-zero element. This application does not limit this.

[0154] For ease of distinction and explanation, the values ​​of the non-zero elements of the basis matrix are denoted as the first value, and the values ​​of the zero elements are denoted as the second value. For example, the first value can be 1 and the second value can be 0; or, the first value can be 0 and the second value can be -1; or, the first value can be greater than or equal to 0 and the second value can be -1. The first value corresponds to the cyclic shifted square matrix in the parity check matrix, and the second value corresponds to the all-zero square matrix in the parity check matrix.

[0155] Currently, the NR protocol defines two base maps: BG 1 and BG 2. BG 1 defines a base matrix with a dimension of 46×68 and a core matrix with a dimension of 4×26, and is mainly used for scenarios with high throughput requirements, high bit rate, and long code length. BG 2 defines a base matrix with a dimension of 42×52 and a core matrix with a dimension of 4×14, and is mainly used for scenarios with low throughput requirements, low bit rate, and short code length.

[0156] Figure 6 This is a schematic diagram of the structure of the verification matrix provided in the embodiments of this application. Figure 6 The structure of the verification matrix shown is a Raptor-like structure, which is quite common in 5G. For example... Figure 6 As shown, the parity check matrix of the Raptor-like LDPC structure includes the following five parts:

[0157] Part A: Information bits of the core array;

[0158] Part B: The parity bit portion of the core array, which has a double diagonal structure.

[0159] Part C: All-zero matrix;

[0160] Part D: The information bit portion of the extended array;

[0161] Part E: The parity bit portion of the extended matrix, which has a single diagonal structure.

[0162] It should be understood that the descriptions of the core matrix, all-zero matrix, and extended matrix mentioned above are all relative to their respective parts. In the parity check matrix, the core matrix can be called the core submatrix, the all-zero matrix can be called the all-zero submatrix (or simply, the all-zero submatrix), and the extended matrix can be called the extended submatrix.

[0163] The verification matrix includes the core matrix H core and extended array H ext Among them, the core array H core include Figure 6 Parts A and B (shown in thick black boxes in the diagram) constitute a high-bitrate parity-check matrix, which can be represented as [AB]. Its dimension is M. core ×N core M core ≤M, N core ≤N, and also satisfies: N core =M core +K. Based on the core array H core Scalable generation of extended matrix H ext , can correspond to Figure 6 The D and E parts. Extended array H ext Each additional row adds one column to the parity check matrix H. It should be understood that the names of the various parts above are for ease of distinction only and should not constitute any limitation on this application. For example, part A can also be called the high-bitrate information column region, part B can also be called the high-bitrate core parity check region, and parts D and E can also be called incremental redundancy regions.

[0164] It should be noted that since the parity-check matrix can be generated based on the basis matrix, and each element in the basis matrix can be converted into a Z×Z matrix, the dimension M of the core matrix is... core ×N core It can also correspond to a basis matrix with dimension (M) core / Z)×(N core The parity-check matrix is ​​a submatrix of ( / Z). Since part C of the parity-check matrix is ​​an all-zero submatrix and part E is a diagonal submatrix, both having relatively regular structures, the description of the parity-check matrix or basis matrix can primarily focus on parts A, B, and D. For ease of explanation and understanding, parts C and E will not be described in detail later, but those skilled in the art will understand that once the core matrix and extended matrix are determined, the other parts can be obtained based on the aforementioned structure, thus yielding the complete parity-check matrix.

[0165] It should also be noted that in some implementations, the core matrix may include rows and / or columns other than parts A and B. For example, the number of rows in the core matrix is ​​the number of rows in matrix [AB] + 1, and the number of columns in the core matrix is ​​the number of columns in matrix [AB] + 1. The core matrix is ​​defined exemplarily for the convenience of understanding the embodiments of this application and should not constitute any limitation on this application. This application does not limit the dimensions of the core matrix. Unless otherwise specified, the core matrix will still be understood as [AB] below.

[0166] For example, Figure 7 These are two different dimensions of Raptor-like structures provided in the embodiments of this application. The 5G protocol defines two different BGs: BG 1 and BG 2, as follows: Figure 7 As shown in (a) and (b) in the figure. Figure 7 In the structure shown in (a), BG 1 has a size of 46×68, and the core array H core Its size is 4×26, and it is mainly used in scenarios with high throughput requirements, high bit rate, and long bit length. Figure 7 In the structure shown in (b), BG 2 has a size of 42×52, and the core array H core The size is 4×14, and it is mainly used in scenarios with low throughput requirements, low bit rate, and short bit length.

[0167] In practical applications, the choice of which block gauge (BG) to use to generate the parity check matrix for LDPC encoding and decoding can be determined based on the bit gauge block (TBS) and the code rate (R). Figure 8 An example illustrating the relationship between BG selection, TBS, and bitrate is shown. As illustrated, if A ≤ 292; or A ≤ 3824 and R ≤ 0.67; or R ≤ 0.25, BG 2 is selected; otherwise, BG 1 is selected. Here, the message block length A is the TBS excluding CRC, and R can be the bitrate indicated by the MCS index, which can be understood as the desired bitrate, referred to as the target bitrate, rather than the actual bitrate.

[0168] Currently, when using parity-check matrices generated by BG 1 and BG 2 for LDPC encoding and decoding, in the lower symbol signal-to-noise ratio (SNR) range, the BLER decreases significantly with increasing SNR; this range can be called the waterfall region. However, in the higher SNR range, the decreasing trend of BLER with increasing SNR slows down, resulting in a more pronounced error leveling; this range can be called the leveling region. This may lead to low decoding performance in the leveling region, posing potential risks and impacts, especially in scenarios with high reliability requirements.

[0169] Figure 9 This is a performance simulation diagram provided in the embodiments of this application. Figure 9The results are obtained by generating the parity check matrix using NR BG 2 and performing BLER performance simulations with quadrature phase shift keying (QPSK) modulation on a channel with additive white Gaussian noise (AWGN) for a code rate (i.e., the aforementioned target code rate) of 0.67 and different information bit lengths K. Figure 9 The horizontal axis represents the symbol signal-to-noise ratio (Es / N0), which is the ratio of the energy (Es) of each symbol to the noise power spectral density (N0). The vertical axis represents BLER. Es / N0 is directly proportional to SNR, and their conversion relationship is as follows:

[0170] For complex signals: Es / N0(dB) = 10log 10 (T sym / T samp )+SNR(dB);

[0171] For a real signal: Es / N0(dB) = 10log 10 (0.5T sym / T samp )+SNR(dB);

[0172] The units are all in decibels (dB), T sym T represents the symbol period. samp Indicates the sampling interval.

[0173] This shows that the larger Es / N0 is, the larger the SNR is; the smaller Es / N0 is, the smaller the SNR is. Therefore, the relationship between Es / N0 and BLER reveals the relationship between signal-to-noise ratio and BLER.

[0174] As can be seen from the figure, for a fixed information bit length K, the BLER curve drops steeply in the lower symbol signal-to-noise ratio range, indicating good decoding performance; however, as the symbol signal-to-noise ratio increases, the descent slope of the BLER curve gradually slows down, and a more obvious error flattening occurs.

[0175] Researchers further collected the number of error bits in each column appearing in the flat region when using BG 2, which yielded... Figure 10 The result in the middle. Figure 10 This is a graph showing the correspondence between the columns of BG 2 obtained from the statistics provided in this application embodiment and the number of error bits.

[0176] Figure 10Each square in the matrix represents an element in a basis matrix. Squares with filled patterns represent elements in the basis matrix with the first value, which corresponds to a cyclic shift submatrix in the parity check matrix. Blank squares represent elements in the basis matrix with the second value, which corresponds to a zero submatrix in the parity check matrix.

[0177] from Figure 10 As can be seen, the number of errors varies across different columns. Some columns have a relatively high number of error bits. These columns generally have a lighter column weight. In this case, once the elements in these columns participate in the formation of rings in the basis matrix (as shown by the black dashed lines in the figure), they participate in fewer check equations, thus having less external information input, and are therefore more prone to errors.

[0178] In view of this, this application provides a method in which a communication device can obtain a parity check matrix based on a first basis matrix. This first basis matrix, relative to the base map, has patch elements added, such that elements in the base map with values ​​of a second value are replaced with patch elements with values ​​of a first value. Since the first value can correspond to a cyclic shift submatrix in the parity check matrix, and the second value can correspond to an all-zero submatrix in the parity check matrix, by adding patch elements, the all-zero submatrix in the parity check matrix is ​​partially replaced with a cyclic shift submatrix. This increases the number of non-zero elements in the parity check matrix, thereby reducing the presence of light-column overlap in the parity check matrix, improving the decoding performance of the flat-layer region, and enhancing reliability.

[0179] Figure 11 This is a schematic flowchart of the method for obtaining a verification matrix provided in the embodiments of this application. Figure 11 The method shown can be executed by a communication device, which can be a communication equipment, such as a network device or a terminal device, or a component configured in the communication equipment, such as a circuit or chip inside the communication equipment (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, etc.), or a logic module or software that can implement some or all of the functions of the communication device, etc. This application does not limit it in this regard.

[0180] It should be understood that the parity-check matrix obtained based on this method can be used for both LDPC encoding and LDPC decoding. Therefore, Figure 11 The method shown can be applied to the encoding end, for example, it can be used by... Figure 4 The device shown, 400A, performs this action; it can also be applied to a decoding end, for example, it can be executed by... Figure 4 The device 400B shown is used to perform this action.

[0181] Figure 11The method 1100 for generating the parity check matrix shown may include steps 1110 to 1120. Optionally, the method 1100 may also include one or more of steps 1130 or 1140. The following describes... Figure 11 The steps in method 1100 shown are described in detail.

[0182] In step 1110, a first basis matrix is ​​obtained, which includes Q patch elements.

[0183] In this application, a patch element refers to an element with a first value. The positions of these Q patch elements in the first basis matrix coincide with the positions of the Q elements with second values ​​in the second basis matrix. Here, the second basis matrix can be understood as the matrix form of the basis graph, or a basis matrix obtained based on the basis graph. The difference between the first and second basis matrices lies in the different values ​​of the Q elements. In the second basis matrix, the values ​​of these Q elements are the second values, corresponding to the all-zero submatrix in the parity check matrix, while in the first basis matrix, the values ​​of these Q elements are the first values, corresponding to the cyclic shift submatrix in the parity check matrix.

[0184] One possible implementation of step 1110 is that the first basis matrix is ​​obtained based on the second basis matrix. Accordingly, step 1110 specifically includes: obtaining the first basis matrix based on the second basis matrix. That is, the communication device can first obtain the second basis matrix, and then, based on the second basis matrix, replace Q elements with second values ​​with Q elements with first values ​​(i.e., Q patch elements) to obtain the first basis matrix.

[0185] In this implementation, the Q patch elements can be used to replace the Q elements in the second base matrix that have the second value. The first base matrix is ​​essentially obtained by patching the second base matrix with these Q elements, or by adding Q elements with the first value to the second base matrix. This document uses the term "patch element" for ease of distinction and understanding, but this should not be construed as limiting the scope of this application. Patch elements can also be called elements, replacement elements, correction elements, etc., without limitation.

[0186] It should be understood that the terms "patch," "replace," and "add" mentioned above are merely descriptions for ease of understanding. In actual implementation, it is not necessarily necessary to perform actions such as "patching," "replacing," and "adding."

[0187] It should be noted that the inclusion of Q patch elements in the first basis matrix does not mean that the first basis matrix only contains Q elements with the first value. The first basis matrix may also contain more elements with the first value and / or one or more elements with the second value. Similarly, the second basis matrix may not necessarily contain only Q elements with the second value. The second basis matrix may also contain more elements with the second value and / or one or more elements with the first value. Since the difference between the first and second basis matrices lies in the aforementioned Q elements, this explanation will primarily focus on these Q elements.

[0188] Optionally, before obtaining the first basis matrix based on the second basis matrix, the method further includes obtaining the second basis matrix.

[0189] As mentioned earlier, the second basis matrix can be in matrix form of the basis graph, or a basis matrix obtained based on the basis graph. In one implementation, the first basis matrix can be obtained based on the target bit rate and TBS. The NR protocol defines two basis graphs, BG1 and BG2, and in conjunction with the preceding text... Figure 8 The relationship between BG selection, TBS, and code rate is illustrated. Therefore, the communication device can select one of BG 1 and BG 2 based on the target code rate and TBS. The target code rate can be determined by the MCS index.

[0190] The second basis matrix can be a matrix pre-existing in the communication device. Figure 4 Taking (a) or (b) as examples, the second basis matrix can be a matrix pre-existing in a storage unit. The computation unit can read the second basis matrix from this storage unit based on the TBS and the target code rate when there is a need for encoding / decoding.

[0191] Another possible implementation of step 1110 is to read the first basis matrix from a pre-stored basis matrix. For example, the communication device can pre-generate multiple optional basis matrices for different base maps and for different base maps, predefined numbers and positions of patch elements. Therefore, these multiple optional basis matrices are basis matrices corresponding to the base map and with patch elements added. When there is a need for encoding / decoding, the communication device can select the corresponding basis matrix as the first basis matrix based on the current target bitrate and TBS, using the aforementioned method of selecting the base map.

[0192] In step 1120, the parity check matrix is ​​obtained based on the first basis matrix.

[0193] The process of obtaining the parity-check matrix from the basis matrix has been explained in detail in the terminology introduction above, combining the parity-check matrix and the basis matrix, and will not be repeated here.

[0194] For ease of distinction and explanation, this paper refers to the parity-check matrix obtained based on the first basis matrix as the first parity-check matrix, and the parity-check matrix obtained based on the second basis matrix but not the first basis matrix as the second parity-check matrix. Since the first basis matrix contains more elements with the value 1 than the second basis matrix, the first parity-check matrix contains more cyclic shift submatrices than the second parity-check matrix. In other words, the first parity-check matrix contains more elements with the value 1 than the second parity-check matrix. As a result, the number of elements with the value 1 in some columns of the first parity-check matrix increases, thus increasing the column weight.

[0195] Therefore, the parity-check matrix obtained based on the first basis matrix proposed in this application has a reduced number of zero submatrices and an increased number of cyclic shift submatrices compared to the parity-check matrix obtained based on the second basis matrix. This is beneficial for increasing the number of non-zero elements in the parity-check matrix, reducing the presence of light columns with heavy elements, improving the decoding performance of the flat layer region, and enhancing reliability. Thus, it can be applied to scenarios with high reliability requirements, reducing risks.

[0196] Optionally, the method further includes step 1130: performing LDPC encoding or LDPC decoding based on the parity check matrix.

[0197] As mentioned earlier, this parity check matrix can be used for LDPC encoding or LDPC decoding. If the communication device needs to send data, it can perform LDPC encoding based on this parity check matrix; if the communication device receives data, it can perform LDPC decoding based on this parity check matrix. The process will be briefly described below using LDPC encoding and LDPC decoding as examples.

[0198] LDPC encoding:

[0199] If a communication device needs to send data, it can encode the data before sending it. For example, the communication device can preprocess data obtained from a higher layer to obtain information bits to be encoded, and then perform LDPC encoding on the information bits based on a parity check matrix.

[0200] As mentioned earlier, the parity check matrix H satisfies:

[0201]

[0202] Where c represents the information bits to be encoded, including K information bits, for example denoted as c0, ..., c K－1 w represents (N+D-K) parity bits, for example, denoted as c K c N+D－K－1 .

[0203] The process of LDPC encoding based on the parity-check matrix H is as follows: K information bits c0, ..., cK－1 As input, given the parity check matrix H, the (N+D-K) parity bits c can be calculated. K c N+D－K－1 Therefore, the output can be obtained, which consists of (N+D) encoded bits: c0, ..., c K－1 c K c N+D－K－1 .

[0204] The encoded bits obtained can be transmitted after undergoing operations such as modulation, layer mapping, precoding, framing, IFFT, and IRF.

[0205] For a more detailed explanation of the steps before and after encoding, please refer to the preceding text. Figure 3 The relevant descriptions will not be repeated here.

[0206] LDPC decoding:

[0207] If the communication device receives data, it can decode the data and then send it to a higher layer. For example, the communication device can preprocess the signal received from the air interface, such as IRF, FFT, deframing, de-mapping, channel equalization, demodulation, etc., to obtain the encoded bits to be decoded, and then perform LDPC decoding on the encoded bits to be decoded based on the parity check matrix.

[0208] For example, the communication device can use the sum-product algorithm (SPA) and its simplified min-sum algorithm for decoding. For ease of distinction and explanation, the log-likelihood ratio (LLR) of the (N+D) coded bits obtained after demodulation of the signal received by the communication device is denoted as: q0,…,q N+D-1 These are also the initial values ​​of the posterior information for each variable node. The SPA algorithm uses the connection relationships between the variable nodes and check nodes in the check matrix H to iteratively update the posterior information q0,…,q for each variable node (corresponding to the received bit). N+D-1 Finally, the decision result for each variable node (i.e., the received encoded bits) is obtained based on the posterior information. For a more detailed explanation of the steps before and after decoding, please refer to the preceding text. Figure 3 The relevant descriptions will not be repeated here.

[0209] For ease of understanding, the data transmission process will be described here using the data interaction between this communication device and another communication device as an example. In the following text, for ease of distinction and explanation, this communication device will be referred to as communication device #1, and the other communication device with which it communicates will be referred to as communication device #2.

[0210] Communication device #1 preprocesses the information data received from higher layers to obtain a bit sequence to be encoded. Based on a parity-check matrix, it performs LDPC encoding on this bit sequence. The encoded bits are then transmitted after operations such as modulation, layer mapping, precoding, framing, IFFT, and IRF. Communication device #2 receives a signal over the air interface and performs preprocessing on the received signal, including IRF, FFT, deframing, de-layer mapping, channel equalization, and demodulation, to obtain encoded bits to be decoded. It then performs LDPC decoding on these encoded bits and transmits them to higher layers. Both the parity-check matrix used for LDPC encoding and the parity-check matrix used for LDPC decoding can be parity-check matrices obtained using the methods described above; that is, parity-check matrices obtained based on the first base matrix.

[0211] It is understandable that communication device #1 and communication device #2 mentioned above can be interchanged; that is, communication device #2 sends data and performs LDPC encoding, while communication device #1 receives data and performs LDPC decoding. For the sake of brevity, further details will not be provided.

[0212] In this embodiment of the application, whether the communication device uses the first base matrix can be pre-configured.

[0213] For ease of distinction and explanation, the scheme provided in this application that obtains the parity check matrix (i.e., the first parity check matrix mentioned above) based on the first base matrix and then performs LDPC encoding and decoding based on the parity check matrix will be referred to as Scheme 1. The scheme that obtains the parity check matrix (i.e., the second parity check matrix mentioned above) based on the BG (or, based on the second base matrix) instead of the first base matrix, and then performs LDPC encoding and decoding based on the parity check matrix, according to the definition of the current protocol, will be referred to as Scheme 2.

[0214] If the communication device is pre-configured to execute Scheme 1 but not Scheme 2, for example, if a computer program for executing Scheme 1 is installed but a computer program for executing Scheme 2 is not installed, or if it has circuitry for executing Scheme 1 but not for executing Scheme 2, then when there is a need for encoding / decoding, the communication device can directly perform LDPC encoding or decoding based on the aforementioned process (as shown in steps 1110 to 1130). If the communication device is pre-configured to execute Scheme 2 but not Scheme 1, for example, if a computer program for executing Scheme 2 is installed but a computer program for executing Scheme 1 is not installed, or if it has circuitry for executing Scheme 2 but not for executing Scheme 1, then when there is a need for encoding / decoding, the communication device can directly obtain the parity check matrix based on the second base matrix without needing to obtain the first base matrix, and then perform LDPC encoding or decoding based on the parity check matrix.

[0215] The communication device may also be configured to perform both Scheme 1 and Scheme 2, for example, by having computer programs installed that can perform Scheme 1 and Scheme 2, or by having circuitry that can perform Scheme 1 and Scheme 2. In this case, the communication device can determine whether to use the first base matrix before step 1110, and if it is determined that the first base matrix should be used, perform the aforementioned process.

[0216] Optionally, the method further includes step 1140: determining whether to use the first basis matrix.

[0217] Accordingly, step 1110 includes: if it is determined that a first basis matrix is ​​to be used, obtaining the first basis matrix.

[0218] Since the first base matrix is ​​a base matrix that includes patch elements, determining whether to use the first base matrix can also be replaced by determining whether to use patch elements, or determining whether to enable patch elements, or determining whether to add patch elements, and so on.

[0219] Since the parity check matrix obtained based on the first basis matrix is ​​denoted as the first parity check matrix and the parity check matrix obtained based on the second basis matrix is ​​denoted as the second parity check matrix, determining whether to use the first basis matrix can also be replaced by determining whether to use the first parity check matrix or determining whether to enable the second parity check matrix.

[0220] The communication device can determine whether to use the first base matrix on its own, or it can determine whether to use the first base matrix based on an instruction from another communication device with which it is communicating. For ease of distinction and explanation, the communication device will be referred to as communication device #1, and the other communication device with which it is communicating will be referred to as communication device #2.

[0221] In one possible implementation, step 1140 specifically includes: determining the use of the first basis matrix if the first condition is met.

[0222] In other words, the communication device #1 can determine whether to use the first basis matrix, or in other words, whether to execute scheme 1 or scheme 2, based on the first condition. For example, the first condition may be related to the channel environment, the capabilities of the communication device #1, the service scenario, etc.

[0223] As an example, this first condition is related to the business scenario. For example, the first condition could be that the first basis matrix is ​​used in ultra-reliable low-latency communication (URLLC) scenarios; otherwise, the first basis matrix is ​​not used.

[0224] In this embodiment of the application, it is assumed that the communication device #1 is applied to a URLLC scenario, so it can be determined that the first base matrix is ​​used.

[0225] In another example, the first condition is related to the channel environment. This first condition could be, for example, using the first basis matrix when the signal-to-noise ratio (SNR) is greater than or equal to a certain threshold, and not using the first basis matrix when the SNR is lower than that threshold. The channel environment can be determined through channel state information (CSI), etc.

[0226] In the embodiments of this application, it is assumed that the channel environment meets the first condition, so the first basis matrix can be determined to be used.

[0227] In another example, the first condition relates to the capabilities of the communication device. This first condition could be, for example, that the communication device is configured to execute scheme 1 without executing scheme 2, or, if configured to execute both scheme 1 and scheme 2, then the first basis matrix is ​​determined to be used.

[0228] Optionally, the method further includes: sending first indication information, the first indication information being used to indicate the use of a first base matrix, or the first indication information being used to indicate a first base matrix.

[0229] After determining to use the first base matrix, communication device #1 can also notify communication device #2, with which it is communicating, whether to use the first base matrix, or directly indicate the first base matrix to be used to communication device #2. This allows both the transmitting and receiving ends to obtain the parity check matrix based on the same base matrix, and then perform LDPC encoding and decoding. This improves decoding performance.

[0230] In one example, communication device #1 is a base station, and communication device #2 is a terminal. The base station can indicate to the terminal whether to use a first base matrix via first indication information. For example, the first indication information can be an indication bit in downlink control information (DCI), where a value of 1 indicates the use of the first base matrix, and a value of 0 indicates the use of a second base matrix instead of the first base matrix.

[0231] In another example, communication device #1 is a terminal, and communication device #2 is a base station. The terminal can indicate to the base station whether to use the first base matrix via first indication information. For example, the first indication information can be an indication bit in uplink control information (UCI), where a value of 1 indicates the use of the first base matrix, and a value of 0 indicates the use of the second base matrix without using the first base matrix.

[0232] In another possible implementation, the method further includes: receiving second indication information, which indicates the use of a first base matrix, or the second indication information indicates the use of a first base matrix; step 1140 specifically includes: determining the use of the first base matrix based on the second indication information.

[0233] In other words, communication device #1 can also perform the corresponding operation according to the instructions of communication device #2, instead of determining whether to use the first base matrix itself.

[0234] Based on the above scheme, the communication device can determine whether to use the first basis matrix to obtain the parity check matrix according to actual needs. This allows for more flexible selection of different schemes to address different scenarios and achieve greater benefits in different scenarios.

[0235] The preceding text, in conjunction with the accompanying drawings, has described in detail the specific process of obtaining the verification matrix provided in the embodiments of this application. The determination of the positions of the Q patch elements will be described in detail below.

[0236] Optionally, the Q patch elements are located in the first m of the first basis matrix. b In each row, m b 'satisfy: R is the target bitrate, k b k is the column number of the information bits in the first basis matrix. b d is a positive integer; b Let d be the column number of the punched positions in the first basis matrix (hereinafter referred to as the punched column). b For less than or equal to k b The non-negative integer can be understood as the punched column D = d in the parity check matrix. b ×Z, d b A value of 0 indicates no punched column, d b A value greater than 0 indicates that one or more punch columns are set; This indicates rounding up. This can be understood because the first basis matrix has m rows. b Therefore, m b 'For less than or equal to m b Positive integers.

[0237] To facilitate understanding, we will first use BG 2 as defined in the NR protocol to illustrate the relationship between the number of rows in the parity check matrix and the bit rate.

[0238] In the NR protocol, the size of BG 2 is 42×52, and the size of the core matrix is ​​4×14. Typically, the submatrix corresponding to the core matrix in the parity-check matrix H (e.g., denoted as submatrix H') can be preferentially used for LDPC encoding. That is, the first (4×Z) rows of the parity-check matrix H correspond to the first 4 rows of the base graph. In other words, the number of rows in the parity-check matrix actually participating in LDPC encoding is (4×Z), corresponding to the first 4 rows of the base graph.

[0239] Since the core array is 4×14 in size, the first 10 columns are the information bit part, which is associated with the first (10×Z) information bits in the input to be encoded; the last 4 columns are the parity bit part, which is associated with (4×Z) parity bits. Assuming the first two columns of the base map are punched columns, then: if the first (4×Z) rows of the parity check matrix H (that is, the first 4 rows in BG 2) are used for LDPC encoding, the code rate R = 10 / (10+4-2) = 0.833; if the first (5×Z) rows of the parity check matrix H (that is, the first 5 rows in BG 2) are used for LDPC encoding, the code rate R = 10 / (10+5-2) = 0.769; if the first (6×Z) rows of the parity check matrix H (that is, the first 6 rows in BG 2) are used for LDPC encoding, the code rate R = 10 / (10+5-2) = 0.714; if the first (7×Z) rows of the parity check matrix (that is, the first 7 rows in BG 2) are used for LDPC encoding, the code rate R = 10 / (10+7-2) = 0.667; and so on, without further enumeration.

[0240] It is easy to see that the fewer rows involved in encoding in the parity check matrix, the higher the bit rate; the more rows involved in encoding in the parity check matrix, the lower the bit rate.

[0241] It should be noted that the above text uses the first (m) of the check matrix H. b (×Z)(For BG 2, m) b ' is a positive integer less than or equal to 52; for BG 1, m b LDPC encoding is performed on rows containing positive integers less than or equal to 68. This does not mean that only rows containing (m) in the parity-check matrix H are used. b Instead of performing LDPC using the first m lines (×Z), it means that during the encoding process, the first m lines are the ones that actually participate in encoding and have a significant impact on decoding performance. b 'Okay. In the specific implementation, only the first (m)th percentiles of the check matrix H can be used.' b LDPC encoding can be performed using the '×Z' rows, or the entire parity check matrix H can be used for LDPC encoding. This application does not limit this approach.

[0242] As can be seen from the relationship between the number of rows in the parity-check matrix and the bit rate described above, if the first (m) rows of the parity-check matrix H are... b Adding a cyclic shift submatrix to the (m×Z) rows can affect decoding performance. b The '×Z) rows can be combined with the first m rows of the first basis matrix. b ' ' rows correspond, therefore the Q patch elements can be controlled within the first m rows of the first base matrix. b In each of the Q rows, the position of the patch element can be determined based on the target bitrate.

[0243] Assuming the first d in the base graph b If the column is set as a punched column, then the bitrate R can be obtained by satisfying:

[0244]

[0245] For an input to be encoded with a known target bit rate, m b 'Can be satisfied:'

[0246] In one possible design, m b The relationship between the value of ' and the bitrate can be indicated by a first mapping relationship. For example, this first mapping relationship can indicate multiple bitrates and m... b The correspondence between multiple values ​​of ', and the m corresponding to each bitrate. b The value of ' is used to determine the range of rows in the first base matrix where the patch element is located.

[0247] Table 1 is an example of this first mapping relationship. It can be understood that the first mapping relationship can include R and m in Table 1. b One or more of the multiple correspondences of '. As shown in Table 1 below, it can also be represented by multiple tables.

[0248] Table 1

[0249]

[0250]

[0251] It should be understood that Table 1 exemplified above is merely one possible form of the first mapping relationship and should not be construed as limiting this application in any way. This application does not limit the specific form of the mapping relationship; for example, it could also be in the form of a formula, an array, or a sequence. It should also be understood that the first mapping relationship can be predefined by the protocol, calculated by the communication device itself, obtained from other devices, or indicated by other devices; this application does not limit this.

[0252] In this embodiment, the range of rows of the Q patch elements in the first base matrix can be determined according to the above... The value can be calculated using the relational formula, or it can be obtained using the first mapping relationship mentioned above. If obtained using the first mapping relationship, this first mapping relationship can be stored in the communication device in advance. When there is a need for encoding and decoding, the corresponding m can be determined according to the target code rate. b The value of '.

[0253] The patch elements identified above are located in the first m steps of the first basis matrix. b 'Row is just a broad range. This application can further provide a method for determining the row and column positions of patch elements in the first base matrix.'

[0254] For example, the positions of the Q patch elements can be described by their row and column indices in the first base matrix. That is, the position information of the Q patch elements includes their row and column indices. The determination of the row and column indices of the patch elements will be explained in detail below.

[0255] Column index:

[0256] The columns of the Q patch elements in the first base matrix can be predefined or determined based on the target bitrate.

[0257] Optionally, the location information of patch elements corresponding to multiple bitrates includes the same G column indices, where G is a positive integer. In other words, the column indices of the patch elements do not change with the bitrate. The G columns indicated by these G column indices can be determined based on the statistical value of the number of error bits in each column under multiple bitrates, or they can be determined based on the statistical value of the number of target elements contained in each column under multiple bitrates.

[0258] For ease of explanation, we assume here that the location information of the patch element includes G column indices; in other words, the patch element is located in G columns. For clarity and explanation, the G columns where the patch element is located are referred to as the G target columns. It should be understood that these G column indices refer to the column indices in the first base matrix of the G target columns (or patch elements), and can also be equivalent to the column indices in the second base matrix.

[0259] In one implementation, m can be targeted for multiple bitrates respectively. b The value of ' is taken from the first m columns of the G' columns of the second basis matrix. b 'By 'rows, we can obtain multiple sub-matrices with different numbers of rows corresponding to multiple code rates. The number of rows in these multiple sub-matrices is m, which corresponds to each of the multiple code rates.' bThe value of ' is used. Here, the number of rows in a submatrix refers to the number of rows it contains; the number of rows in a submatrix varies depending on the bitrate. For example, referring to Table 1, the submatrix corresponding to a bitrate of 0.769 has 5 rows, which includes the first 5 rows of the second base matrix's G' columns; the submatrix corresponding to a bitrate of 0.714 has 6 rows, which includes the first 6 rows of the second base matrix's G' columns; and so on, resulting in 38 submatrixes, each including the first 5 to the first 42 rows of the second base matrix's G' columns, corresponding to 38 bitrates. The G' columns in the second base matrix are one or more predefined columns. They can be the first G' columns of the second base matrix, G' columns predefined by the protocol, or randomly selected G' columns; this application does not limit this. G target columns are determined from the multiple sub-matrices. These G target columns satisfy the following condition: among the G' columns of the second base matrix, they are ranked in descending order of the statistical value of the number of error bits corresponding to each column; wherein, the statistical value of the number of error bits corresponding to the i-th column of the G' columns is a function of the number of error bits corresponding to the i-th column of each of the multiple sub-matrices of the second base matrix. The number of error bits corresponding to the i-th column of each sub-matrix can be obtained through simulation, for example, by selecting a higher value Es / N0 for simulation, that is, simulation in the flat area.

[0260] Optionally, any one of the aforementioned submatrices includes the top m left corners of the aforementioned second basis matrix. b 'The first S columns of the row, and the m corresponding to different sized submatrices. b The values ​​of ' and S differ, and different sizes of submatrices correspond to different code rates; that is, the m values ​​of multiple submatrices... b The value of ' can correspond one-to-one with multiple code rates. For example, in the NR protocol's BG2, its complete base matrix (as an example of the second base matrix above) is 42×52. With 2 columns punched, the submatrix corresponding to a code rate of 0.67 is the matrix formed by the first 7 rows and first 17 columns of this base matrix (i.e., m). b '=7,S=17); the submatrix corresponding to a code rate of 0.5 is the matrix formed by the first 12 rows and first 22 columns of the base matrix (i.e., m b '=12,S=22). Where, m b The value of ' can also be called the number of rows in the submatrix, that is, the number of rows included in the submatrix. The value of S is a positive integer, S = G'. In other words, the G target columns are determined from the G' columns, and are one or more columns with a higher number of error bits.

[0261] For example, referring to Table 1, 38 sub-matrices corresponding one-to-one with the 38 code rates can be obtained. These 38 sub-matrices each include the first 5 to the first 42 rows of the G' columns of the second base matrix. Based on these 38 sub-matrices, 38 parity check matrices with different numbers of rows can be obtained. Using these 38 parity check matrices, the same input to be encoded is encoded, and the encoded bits are decoded. The number of error bits in each of the G' columns is recorded. For the i-th column, the number of 38 error bits corresponding to the 38 parity check matrices can be recorded. Then, based on a predefined function, the number of error bits corresponding to the i-th column can be calculated to obtain the statistical value of the number of error bits. The predefined function can be, for example, averaging, maximizing, weighted averaging, etc., and this application does not limit it.

[0262] By iterating through the G' columns for i, we can obtain the statistical values ​​of the number of G' error bits corresponding to the G' columns. Sort these G' statistical values ​​in descending order, and determine the top G columns as the G target columns, thus obtaining the column indexes of the G target columns.

[0263] It is understandable that the more erroneous bits there are, the fewer correct bits there will be. Therefore, based on the above implementation, the G target columns determined from these multiple sub-matrices can also satisfy the following: among the G' columns of the second base matrix, the top G columns are ranked in ascending order of the statistical value of the number of correct bits corresponding to each column.

[0264] In another implementation, m can be assigned to multiple bitrates respectively. b The value of ' is taken from the first m columns of the G' columns of the second basis matrix. b 'This yields multiple sub-matrices corresponding to multiple bitrates. These multiple sub-matrices are the same as those in the previous implementation, as described above, and will not be repeated here. From these multiple sub-matrices, G target columns are determined. These G target columns satisfy the following: In the G' columns of the second base matrix, they are ranked in ascending order of the statistical value of the number of target elements contained in each column; wherein, the statistical value of the number of target elements contained in the i-th column of the G' columns is a function of the number of target elements contained in the i-th column of the multiple sub-matrices of the second base matrix, where the target element is the element with the first value.'

[0265] For example, referring to Table 1, 38 sub-matrices corresponding one-to-one with the 38 code rates can be obtained. These 38 sub-matrices each include the first 5 to the first 42 rows of the first 5 columns of the second base matrix G'. For each of these 38 sub-matrices, the number of target elements contained in the i-th column is counted to obtain the number of the 38 target elements corresponding to the 38 sub-matrices. Then, based on a predefined function, the number of these 38 target elements is calculated to obtain the statistical value of the number of target elements contained in the i-th column. The predefined function can be, for example, averaging, maximizing, weighted averaging, etc., and this application does not limit it in this regard.

[0266] By iterating through the G' columns for i, we can obtain the statistical value of the number of target elements corresponding to each of the G' columns. Sort the G' statistical values ​​in ascending order, and determine the top G columns as the G target columns, thus obtaining the column index of the G target columns.

[0267] Since the target element is the element with the first value, corresponding to the cyclic shift submatrix in the parity check matrix, the fewer target elements a column contains in the multiple submatrixes, the fewer the cyclic shift submatrices and the more all-zero submatrices there are in the Z columns of the parity check matrix. This results in a lighter column weight in the corresponding Z columns of the parity check matrix. Therefore, adding patch elements to the G target columns can increase the column weight of those G columns in the parity check matrix.

[0268] It is understandable that for a base matrix, the fewer the first value, the more the second value. Therefore, based on the above implementation, the G target columns determined from these multiple sub-matrices can also satisfy the following: among the G' columns of the second base matrix, they are ranked in descending order of the statistical value of the number of target elements contained in each column; wherein, the statistical value of the number of target elements contained in the i-th column of the G' columns is a function of the number of target elements contained in the i-th column of the multiple sub-matrices of the second base matrix, where the target element is the element with the value of the second value.

[0269] Optionally, the columns containing the patch elements for at least two of the multiple bitrates are different. In other words, the position information of the patch elements for at least two of the multiple bitrates includes at least one different column index. That is, the column index of the patch element can change with the bitrate. The column index of the patch element corresponding to a certain bitrate can be determined based on the statistical value of the number of error bits in each column under that bitrate, or it can be determined based on the statistical value of the number of target elements contained in each column under that bitrate.

[0270] For ease of explanation, we assume here that the position information of the Q patch elements corresponding to the target bitrate includes G column indices; in other words, the Q patch elements are located in G columns. For clarity and explanation, the G columns containing the Q patch elements are referred to as the G target columns. It should be understood that the G column indices refer to the column indices of the G target columns (or patch elements) in the first base matrix, and can be considered equivalent to the column indices in the first base matrix.

[0271] In one implementation, the target bitrate can be targeted at m. b The value of ' is taken from the first m columns of the G' columns of the second basis matrix. b A submatrix of the second basis matrix can be obtained by 'rowsing'. The G' columns in the second basis matrix are predefined; they can be the first G' columns of the second basis matrix, G' columns predefined by the protocol, or G' columns randomly selected. This application does not impose any restrictions on this. G target columns are determined from this submatrix. These G target columns must satisfy the following condition: among the G' columns of the second basis matrix, they are ranked in descending order of the number of error bits corresponding to each column. In other words, the G target columns are determined from the G' columns, and are one or more columns with higher error bit counts.

[0272] The number of error bits in the i-th column of the G' columns is obtained through simulation, such as simulation in a flat area. Traversing i through the G' columns yields G' error bits corresponding to each column. These G' error bits are then sorted in descending order, and the top G columns are identified as the G target columns, thus yielding the column indices of the G target columns. It should be understood that these column indices refer to the column indices of the G target columns in the second base matrix, that is, in the first base matrix.

[0273] In another implementation, the target bitrate can be targeted at m. b The value of ' is taken from the first m columns of the G' columns of the second basis matrix. b Rows can be used to obtain a submatrix of the second basis matrix. From this submatrix, G target columns are determined, which satisfy the following: In the G' columns of the second basis matrix, the columns are ranked in ascending order of the number of target elements they contain; where the target element is the element with the first value. Alternatively, these G target elements can satisfy the following: In the G' columns of the second basis matrix, the columns are ranked in descending order of the number of target elements they contain; where the target element is the element with the second value.

[0274] In another implementation, multiple bitrates can be divided into multiple groups, with each group corresponding to a range of bitrates. Each group can include multiple bitrates. For each range, the G column indices corresponding to the multiple bitrates within that range can be determined using the implementation method described above. For example, taking the 38 bitrates shown in Table 1 as an example, these 38 bitrates can be divided into 4 groups, with the corresponding ranges as follows: (0, 0.4], (0.4, 0.5], (0.5, 0.6], (0.6, 1). The G column indices corresponding to the bitrates within each group can be determined using the method described above, for example, based on the statistical value of the number of error bits in each column of the multiple sub-matrices corresponding to the multiple bitrates within each group, or based on the statistical value of the number of target elements contained in each column of the multiple sub-matrices corresponding to the multiple bitrates within each group. This will not be elaborated further here.

[0275] It should be understood that the above-described implementations of column indexes for determining patch elements are merely some possible implementations and should not constitute any limitation on this application.

[0276] In one possible design, the relationship between column indices and bitrates can be indicated by a third mapping. For example, this third mapping can indicate the correspondence between multiple bitrates and one or more column indices, where the column index corresponding to each bitrate is used to determine the column in which the patch element is located in the first base matrix. For instance, under the multiple bitrates exemplified in Table 1, if numbered starting from 0, the G column indices could be 2, 12, 13, etc. Since this third mapping is shown in Table 2 below, it will not be elaborated further here.

[0277] The third mapping relationship can indicate the correspondence between multiple code rates and the same G column indices, or it can indicate the correspondence between multiple code rates and one or more different column indices. This application does not limit this.

[0278] It should be understood that the third mapping relationship can be predefined by the protocol or calculated by the communication device itself, and this application does not limit it.

[0279] In this embodiment, the column indices of the Q patch elements can be determined by calculation, such as using the implementation method provided above, or by obtaining them based on the aforementioned third mapping relationship. If obtained based on the third mapping relationship, this third mapping relationship can be pre-stored in the communication device to determine the column indices of the Q patch elements when there is a need for encoding / decoding.

[0280] Row index:

[0281] Optionally, the row index of the Q patch elements in the first base matrix is ​​determined according to the target bit rate.

[0282] After determining the column indices of the Q patch elements, the communication device can further determine the row indices of these Q patch elements. For example, assume that the Q patch elements are located in G target columns. The communication device can determine one or more rows in the corresponding columns of the second base matrix based on the column indices of the G target columns, such that after adding patch elements at the positions corresponding to the determined row and column indices, the resulting matrix satisfies a predefined objective function. For ease of distinction and explanation, the rows containing the patch elements are referred to as target rows, assumed to be J rows, where J is a positive integer. As previously mentioned, the Q patch elements can be located in the first m rows of the first base matrix. b Therefore, J can be less than or equal to m in the ' rows'. b A positive integer.

[0283] For example, in the first m of the second basis matrix b In a set of G target columns and 1 row, the row index is determined at the column level. For each of the G target columns, m... b The values ​​of the elements in J rows of m rows are set to the first value, and then calculated using a predefined function. This can be understood as... b There are multiple combinations of J rows. By traversing these combinations, different function values ​​can be obtained. Then, the combination corresponding to the top-ranking function values ​​is selected. This determines the J target rows.

[0284] Taking a second value of 0 as an example, the row index of the J target rows in the i-th column can satisfy:

[0285]

[0286] in, Let f(r) represent the row indices of the J target rows; f() represents a predefined function; argmin f() represents finding the minimum value of the predefined function; B represents the second basis matrix; B(r) 0,i ~r J-1,i (i) = 0 indicates that the column index is i and the row index is r0 to r1 in the second basis matrix. J-1 J elements, where each of the J row indices can be from 0 to (m). b By iterating through the values ​​in '-1), we can obtain various combinations with the J row indices. This can be understood as the row indices of the J target rows. It is one of the many combinations; G patch This represents the set of column indexes consisting of the above G column indexes; B|B(r 0,i ~r J-1,i ,i)=0 means that the r0th to rth elements in the second basis matrix B are... J-1The element in the row and i-th column is assigned the second value (e.g., 0 in this example). Note that during the assignment process, elements in the second base matrix whose values ​​are already the second value can be avoided.

[0287] It should be understood that during the assignment process, values ​​can be assigned column by column from r0 to r1. J-1 Assigning values ​​to elements in a row can also simultaneously assign values ​​to elements r0 to r1 in multiple columns. J-1 This application does not impose restrictions on the assignment of values ​​to the elements of a row. When assigning values ​​to the r0th to rth elements of multiple columns simultaneously... J-1 When assigning values ​​to the elements of a row, the formula above can be simplified to:

[0288] For example, if the predefined function above is a protograph-based extrinsic information transfer (PEXIT) function, then the row indices of the J target rows can satisfy:

[0289]

[0290] The PEXIT function can be used to calculate the PEXIT threshold; the smaller the threshold, the better the matrix performance.

[0291] In one possible design, the relationship between row indices and bitrates can be indicated by a second mapping. For example, this second mapping can indicate a correspondence between multiple bitrates and multiple row indices, each bitrate corresponding to one or more row indices used to determine the row in which the patch element is located within the first base matrix.

[0292] It should be understood that the second mapping relationship can be predefined by the protocol or calculated by the communication device itself, and this application does not limit it.

[0293] For example, assuming J is 1 and the column indices of the G target columns are 2, 12, and 13, using the PEXIT function described above, the row indices of the target rows at different bitrates can include one or more of the correspondences between multiple bitrates R and the row indices of one or more columns shown in Table 2. These one or more columns can include one or more of the following: column 2, column 12, and column 13. It is understood that Table 2 can also be split into multiple tables, which is not limited here. Furthermore, the correspondence between the multiple bitrates R and the row indices of one or more columns can also be represented in other forms, such as formulas, arrays, or sequences, which are not limited here.

[0294] Table 2

[0295]

[0296]

[0297] It should be understood that Table 2 is merely an example of the second mapping relationship, showing the correspondence between multiple bitrates and multiple row indices. It can be seen that the row indices of patch elements are not necessarily the same at different bitrates; in other words, the row index of a patch element is related to the bitrate.

[0298] In fact, Table 2 also shows the same column indices at multiple bitrates; that is, the column indices of the patch elements are the same at different bitrates, namely 2, 12, and 13. Therefore, Table 2 can also be considered as showing an example of a third mapping relationship.

[0299] In this embodiment, the row indices of the Q patch elements can be determined by calculation, such as using the implementation method provided above, or by obtaining them according to the second mapping relationship described above. If obtained according to the second mapping relationship, the second mapping relationship can be stored in the communication device in advance, and the row indices of the Q patch elements can be determined when there is a need for encoding / decoding.

[0300] It should also be understood that Tables 1 and 2 in the examples above are shown for ease of understanding only and do not constitute any limitation on the values ​​in the tables (or the first and second mapping relationships). Furthermore, Tables 1 and 2 can be combined into one table, or split into more tables, for example, for different bitrates. Each table could indicate a bitrate and its corresponding one or more of the following: m b The value of ' can be either the row index of the patch element or the column index of the patch element.

[0301] Based on the above discussion of m b The value of ', the row index of the patch element, or the column index of the patch element are specified so that the communication device can determine the position of the Q patch elements in the first base matrix according to the target code rate.

[0302] Figure 12 and Figure 13 These are two schematic diagrams of the first base matrix provided in the embodiments of this application. Since the positions of the patch elements proposed in this application correspond to parts A, B, and D of the parity-check matrix, therefore... Figure 12 and Figure 13 The first basis matrix is ​​primarily displayed by focusing on the elements corresponding to these three parts within it. Figure 12 and Figure 13 In this matrix, each square represents an element in a base matrix. Squares with filled patterns represent elements in the first base matrix whose value is the first value, which corresponds to a cyclic shift submatrix in the parity check matrix. To make them easier to distinguish, patched elements are identified with different filled patterns from other elements whose value is the first value. Blank squares represent elements in the first base matrix whose value is the second value, which corresponds to a zero submatrix in the parity check matrix.

[0303] Figure 12 In the first base matrix shown, patch elements corresponding to multiple bitrates are located in the same three columns, and patch elements at the same bitrate are located in the same row. Specifically, when R is 0.67, the patch elements are located in columns 2, 12, and 13, and row 6; when R is 0.5, the patch elements are located in columns 2, 12, and 13, and row 9. This corresponds to the relationship between bitrate and column and row indices shown in Table 2 above (shown in bold in the table).

[0304] Figure 13 In the first basis matrix shown, the columns of the patch elements corresponding to different bitrates are not exactly the same, and the rows of the patch elements under the same bitrate are not exactly the same. Specifically, when R is 0.67, the patch elements are located in (column 2, row 6), (column 3, row 4), and (column 12, row 5); when R is 0.5, the patch elements are located in (column 2, row 9), (column 4, row 10), and (column 11, row 11).

[0305] To achieve better decoding performance, this application also provides a possible design for the offset value of the cyclic shift submatrix corresponding to the patch element in the parity check matrix.

[0306] In this embodiment, the offset value refers to the number of bits that element 1 in the cyclic shift submatrix is ​​shifted. For example, an offset value of 0 means no shift, an offset value of 1 means shifting by 1 bit, and so on, without further enumeration. The direction of the shift can be predefined, either as a left shift or a right shift; this application does not limit this. Since the dimension of each cyclic shift submatrix in the parity check matrix is ​​Z×Z, the number of bits for cyclic shifting does not exceed Z, that is, the offset value can take values ​​from 0 to (Z-1).

[0307] As mentioned earlier, in LDPC codes, the shorter the ring length, the higher the probability of decoding failure; therefore, short rings severely impact decoding performance. Thus, the number of short rings can be reduced as much as possible through offset design. One possible method is to lengthen the original short rings by shifting the "1"s in the cyclic shift submatrix. The definition of a short ring can be determined by its ring length. For example, a short ring is a ring whose length does not exceed a preset threshold. For instance, if the preset threshold is 4, short rings can include rings with a length of 4; or, if the preset threshold is 6, short rings can include rings with lengths of 4 and 6. This application does not limit the definition of short rings or the specific value of the preset threshold.

[0308] Based on the scheme provided above, after determining the positions of the Q patch elements in the first base matrix, the corresponding ring length can be determined by setting different offset values ​​for each patch element. The offset values ​​of each patch element are determined when the number of short rings is minimized, thereby controlling the number of short rings to a minimum.

[0309] For example, assuming Q is 1, the cyclic shift submatrix corresponding to the patch element in the parity check matrix can be shifted by offsets from 0 to (Z-1), and short cycles can be searched at different offset values ​​to count the number of short cycles at different offset values, thereby obtaining the offset value with the minimum number of short cycles. This offset value can be used to control the number of bits shifted for element 1 in the cyclic shift submatrix corresponding to the patch element in the parity check matrix.

[0310] For example, assuming Q is 3, the cyclic shift submatrices corresponding to the three patch elements in the check matrix can be shifted by offsets from 0 to (Z-1). It can be understood that the three patch elements can have multiple combinations of offset values, which can be represented by an array, denoted as (a1, a2, a3), where a... q This represents the offset of the q-th patch element, where q can be an integer from 1 to Q, and a q It can be an integer from 0 to (Z-1). Short cycles are searched based on the offset values ​​under different combinations, and the number of short cycles corresponding to different combinations is counted to obtain the combination with the smallest number of short cycles. The offset values ​​in this combination can be used to control the number of bits shifted by element 1 in the cyclic shift submatrix corresponding to each patch element in the check matrix.

[0311] The determination of the offset value has been explained in detail above, taking into account both cases where there is one patch element and cases where there are multiple patch elements. It should be understood that the implementation method provided above is only an example and should not constitute any limitation on this application.

[0312] Based on the above scheme, by designing the offset value, the number of short loops in the parity check matrix can be reduced, thereby further improving the decoding performance.

[0313] Figure 14 This is a performance simulation diagram provided in the embodiments of this application. Figure 14 The simulation results show a performance comparison in the leveled area under two different schemes. These two schemes are Scheme 1 and Scheme 2 mentioned above. It is observed that under different simulation parameters, BLER = 10 -7 The time symbol signal-to-noise ratio (Es / N0) is improved by 0.5 to 1 dB.

[0314] The methods provided in the embodiments of this application have been described in detail above with reference to several accompanying drawings. The apparatus provided in the embodiments of this application will now be described with reference to the accompanying drawings.

[0315] As an example, Figure 15 and Figure 16 These are schematic block diagrams illustrating possible apparatuses provided in embodiments of this application. These apparatuses can be used to implement the functions of the communication apparatus in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0316] Figure 15 A schematic block diagram of a communication device provided in an embodiment of this application. Figure 15 The device 1500 shown may include a processing module 1510 and a communication module 1520.

[0317] In one possible design, device 1500 can be used to implement Figure 11 The communication method implemented by the communication device in the illustrated embodiment. For example, the processing module 1510 is used to implement the processing-related steps such as acquisition and encoding / decoding performed by the communication device in steps 1110 to 1140 of method 1100, and the communication module 1520 can be used to implement the sending and / or receiving steps performed by the communication device in method 1100.

[0318] For example, the processing module 1510 can be used to: obtain a first base matrix; obtain a parity check matrix based on the first base matrix; and perform LDPC encoding or LDPC decoding based on the parity check matrix.

[0319] Optionally, the processing module 1510 can also be used to determine the use of the first basis matrix.

[0320] Optionally, the communication module 1520 can be used to send a first instruction message or receive a second instruction message.

[0321] For a more detailed description of the processing module 1510 and the communication module 1520 mentioned above, please refer to [link / reference needed]. Figure 11 The relevant descriptions in the method embodiments shown are directly obtained and will not be repeated here.

[0322] It should be noted that the communication module can also be called a transceiver module, transceiver unit, transceiver, transceiver device, or transceiver apparatus, etc. The processing module can also be called a processor, processing board, processing unit, or processing apparatus, etc. Optionally, the communication module is used to execute the sending and receiving operations of the first or second communication device in the above method. The device in the communication module that implements the receiving function can be considered as the receiving module, and the device in the communication module that implements the sending function can be considered as the sending module; that is, the communication module can include both a receiving module and a sending module.

[0323] It should also be noted that, in one possible design, the aforementioned processing module and / or communication module can be implemented through virtual modules. For example, the processing module can be implemented through software functional units or virtual devices, and the communication module can be implemented through software functions or virtual devices. In another possible design, the processing module or communication module can also be implemented through physical devices. For example, if the device is implemented using a chip / chip circuit, the communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module can be an integrated processor, a microprocessor, or an integrated circuit.

[0324] The module division in this embodiment is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. Furthermore, the functional modules in the various examples of this embodiment can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0325] Figure 16 This is a schematic diagram of the structure of a communication device provided in yet another embodiment of this application. (See attached diagram.) Figure 16 As shown, the device 1600 includes a processing circuit 1610 and a communication circuit 1620. The processing circuit 1610 and the communication circuit 1620 are coupled to each other.

[0326] It can be understood that the processing circuit 1610 can be one or more processors, or it can be all or part of the processing functions of one or more processors.

[0327] Understandably, the communication circuit 1620 can be a transceiver or an input / output interface.

[0328] Optionally, the device 1600 may further include a memory 1630 for storing instructions executed by the processing circuit 1610, or storing input data required for the running instructions of the processing circuit 1610, or storing data generated after the running instructions of the processing circuit 1610.

[0329] It is understood that the memory 1630 may be located outside the processing circuit 1610, or inside the processing circuit 1610.

[0330] As an example, the processing circuit 1610 is used to implement the functions of the processing module 1510, and the communication circuit 1620 is used to implement the functions of the communication module 1520.

[0331] As an example, device 1600 can be a communication device or a chip used in a communication device.

[0332] When device 1600 is a communication device, the communication circuit can be a transceiver; when device 1600 is a chip, the communication circuit can be an input / output circuit, a bus, pins, or other types of communication interfaces. The input circuit in the input / output circuit can be used for receiving, and the output interface can be used for transmitting.

[0333] In some embodiments of this application, a computer program product is also provided, which, when run on a processor, can implement the method for obtaining a verification matrix implemented by a communication device in the above method embodiments.

[0334] In some embodiments of this application, a computer-readable storage medium is also provided, which contains computer instructions that, when executed on a processor, can implement the method for obtaining a parity check matrix implemented by a communication device in the above-described method embodiments.

[0335] In some embodiments of this application, a communication system is also provided, including the aforementioned communication device, which can be used to implement the method for obtaining a parity check matrix implemented by the communication device in the above method embodiments.

[0336] It is understood that the processor in the embodiments of this application may be any of the following devices or all or part of the circuitry used for processing functions: a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor may be a microprocessor or any conventional processor.

[0337] The terms “unit”, “module”, etc., used in this specification may be used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution.

[0338] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0339] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0340] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0341] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0342] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0343] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. This computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0344] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0345] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for obtaining a parity check matrix, characterized in that, include: Obtain the first base matrix; the first base matrix includes Q patch elements, each of the Q patch elements has a first value, and the positions of the Q patch elements in the first base matrix coincide with the positions of the Q elements with second values ​​in the second base matrix, where Q is a positive integer; Based on the first base matrix, a parity check matrix is ​​obtained. The parity check matrix is ​​used for low-density parity check (LDPC) encoding or LDPC decoding. The first value corresponds to a cyclic shift matrix in the parity check matrix, and the second value corresponds to an all-zero matrix in the parity check matrix.

2. The method as described in claim 1, characterized in that, The first value is 1, and the second value is 0; or, the first value is greater than or equal to 0, and the second value is -1.

3. The method as described in claim 1 or 2, characterized in that, The process of obtaining the first basis matrix includes: The first basis matrix is ​​obtained based on the second basis matrix.

4. The method according to any one of claims 1 to 3, characterized in that, The Q patch elements are located in the first m of the first base matrix. b In each row, m b 'satisfy: R represents the target code rate, which is the code rate indicated by the modulation and coding scheme (MCS), and k b Let d be the column number of the information bits in the first basis matrix. b Let be the column number of the punched positions in the first base matrix. This indicates rounding up to the nearest integer.

5. The method as described in claim 4, characterized in that, The m b The relationship between the value of ' and the target bitrate is determined according to a first mapping relationship, which indicates multiple bitrates and the relationship between m b The correspondence between multiple values ​​of ', the value corresponding to each bitrate is used to determine the range of the row where the patch element is located in the first base matrix, and the multiple bitrates include the target bitrate.

6. The method as described in claim 4 or 5, characterized in that, The positions of the Q patch elements in the first base matrix are determined according to a second mapping relationship, which indicates the position information of the patch elements corresponding to multiple bitrates, including the target bitrate.

7. The method as described in claim 6, characterized in that, The location information of the patch elements corresponding to the multiple bitrates includes G column indices that are the same, where G is a positive integer.

8. The method as described in claim 7, characterized in that, The G columns indicated by the G column indices satisfy the following: among the G' columns of the second base matrix, the columns are ranked in descending order of the statistical value of the number of error bits corresponding to each column; wherein, the statistical value of the number of error bits corresponding to the i-th column among the G' columns is a function of the number of error bits corresponding to the i-th column of each of the plurality of submatrices of the second base matrix; any one of the plurality of submatrices includes the first m columns of the G' columns of the second base matrix. b 'Okay, the m b The value of ' corresponds to the code rate corresponding to any of the submatrices; the G' columns are one or more predefined columns, and G' is a positive integer greater than or equal to G.

9. The method as described in claim 7, characterized in that, The G columns indicated by the G column indices satisfy the following: In the G' columns of the second base matrix, the columns are ranked in ascending order of the statistical value of the number of target elements contained in each column; wherein, the statistical value of the number of target elements contained in the i-th column of the G' columns is a function of the number of target elements contained in the i-th column of each of the plurality of submatrices of the second base matrix; any one of the plurality of submatrices includes the first m columns of the G' columns of the second base matrix. b 'Okay, the m b The value of ' corresponds to the code rate corresponding to any of the submatrices; the G' columns are one or more predefined columns, and G' is a positive integer greater than or equal to G; the target element is an element whose value is the first value.

10. The method as described in claim 6, characterized in that, The location information of the patch element corresponding to each of the multiple bitrates includes one or more column indices, and the location information of the patch element corresponding to at least two of the multiple bitrates includes at least one different column index.

11. The method according to any one of claims 1 to 6, or 10, characterized in that, The Q patch elements are located in G columns of the first base matrix, and the G columns satisfy the following condition: in a submatrix of the second base matrix, the columns are ranked in descending order of the number of error bits corresponding to each column; wherein, the submatrix of the second base matrix includes the first m columns of the G' columns of the second base matrix. b 'Okay, the m b The value of ' has a corresponding relationship with the target bit rate; the G' columns are one or more predefined columns, and G' is greater than or equal to G, where G' and G are positive integers.

12. The method according to any one of claims 1 to 6, or 10, characterized in that, The Q patch elements are located in the G columns of the first base matrix, and the G columns satisfy the following condition: in the submatrix of the second base matrix, they are ranked in ascending order of the number of target elements contained in each column; wherein, the submatrix of the second base matrix includes the first m columns of the G' columns of the second base matrix. b 'Okay, the m b The value of ' has a corresponding relationship with the target bitrate; the G' columns are one or more predefined columns, and G' is greater than or equal to G, where G' and G are positive integers; the target element is the element whose value is the first value.

13. The method according to any one of claims 1 to 12, characterized in that, The method further includes: The first base matrix is ​​determined to be used.

14. The method as described in claim 13, characterized in that, The determination of using the first basis matrix includes: If the first condition is met, the first basis matrix is ​​determined to be used.

15. The method as described in claim 13 or 14, characterized in that, The method further includes: Send a first indication message, which is used to indicate the use of the first base matrix.

16. The method as described in claim 13, characterized in that, The method further includes: Receive a second indication message, the second indication message being used to indicate the use of the first base matrix; The determination of using the first basis matrix includes: Based on the second instruction information, it is determined that the first base matrix will be used.

17. A communication device, characterized in that, Includes functional modules for implementing the method as described in any one of claims 1 to 16.

18. A communication device, characterized in that, include: One or more processors and communication circuitry, the communication circuitry being used by the communication device to perform at least one of signal input or output; the one or more processors being used to implement the method as described in any one of claims 1 to 16.

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