Wafer semiconductor manufacturing method and system based on machine vision

Abstract

The application discloses a wafer semiconductor manufacturing method and system based on machine vision, and the method comprises the following steps: selecting specific illumination parameters for exposure according to wafer area glue thickness difference data, and dynamically adjusting the baking parameters of the residual glue situation corresponding to the development results of the difference area; after analyzing the photoresist pattern of the wafer area after baking, the etching profile is predicted, the mixed gas is in the form of a line format, the safe gas parameters are obtained after the etching simulation is realized, the deformation area is graded and the etching effect is evaluated, and the etching operation parameters are real-time regulated; the wafer area is controlled by spraying thin film deposition, the reaction of multiple ions and lattices is obtained after single ion-lattice collision simulation, and the by-products are detected and analyzed, and the ion implantation parameters are regulated to ensure the safe reaction of the lattice, and the application has the characteristics of improving accuracy and efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a wafer semiconductor manufacturing method and system based on machine vision. Background Technology

[0002] In the semiconductor manufacturing industry, process precision and yield are core competitive advantages. The wafer fabrication process is extremely complex, involving multiple key steps, and advanced processes place increasingly stringent requirements on process control.

[0003] Current manufacturing technologies only provide engraving machines for photoresist etching at fixed wafer positions, failing to fully consider the potentially large variations in resist thickness across different areas of the wafer surface. This results in significant shadows during subsequent light exposure, severely impacting the accurate transfer of photolithographic patterns. In critical etching processes, existing methods fail to effectively address pattern alignment deviations arising from increasingly three-dimensional and multi-layered chip structures, and also pay little attention to the microscopic electrical characteristics of pre-installed resistors, capacitors, and other components within the wafer. Using fixed direction and rate parameters during etching easily leads to uneven material wear on complex structures, and can even induce leakage and other deviations affecting chip performance. In thin film deposition and ion implantation processes, there is insufficient control over the precise regulation of implantation dosage and the strict control of the incident angle. This not only exacerbates lattice damage but also hinders the identification of error sources.

[0004] Therefore, it is essential to design a machine vision-based wafer semiconductor manufacturing method and system that can comprehensively improve process safety and significantly enhance semiconductor manufacturing precision. Summary of the Invention

[0005] The purpose of this invention is to provide a wafer semiconductor manufacturing method and system based on machine vision to solve the problems mentioned in the background art.

[0006] To address the aforementioned technical problems, the present invention provides the following technical solution: a wafer semiconductor manufacturing method based on machine vision, the method comprising the following steps:

[0007] Based on the difference in resist thickness in different areas of the wafer, specific lighting parameters are selected for exposure, and baking parameters are dynamically adjusted according to the resist residue in the development results of the different areas.

[0008] After analyzing the photoresist pattern of the baked wafer area, the etching profile is predicted. The mixed gas is simulated by passing it in a line format to obtain the safety gas parameters. The deformed area is classified and the etching effect is evaluated. The etching operation parameters are then adjusted in real time.

[0009] Thin film deposition is controlled by spraying gas onto the wafer region. After constructing a gas flow rate and deposition rate model, the wind speed and spray position are dynamically adjusted. Single-ion-lattice collision simulation is performed to obtain the reaction between multiple ions and the lattice. Byproducts are detected and their impact is analyzed. Ion implantation parameters are adjusted to ensure safe lattice reaction.

[0010] According to the above technical solution, the step of selecting specific illumination parameters for exposure based on the wafer region resist thickness difference data includes:

[0011] During the photoresist coating stage, the photoresist thickness data of the wafer area is monitored and recorded in real time. Based on the differences in the photoresist thickness data distribution, the illumination and projection of specific wavelength light in multiple groups are simulated. Specific locations of photoresist where the light reflection or refraction angle exceeds a preset threshold are grouped and marked as abnormal areas. Based on the threshold of the proportion of the abnormal area to the photoresist area and the shortest edge distance between the abnormal areas, preset corresponding weights are obtained, and the products are summed to obtain the abnormal value. The light parameters of the group with the lowest abnormal value are marked as the exposure standard parameters and exposure is performed.

[0012] According to the above technical solution, the step of dynamically adjusting the baking parameters to reflect the colloid residue in the development results of the differential regions includes:

[0013] The actual exposure area is obtained based on the exposure process results and compared with the expected exposure area. The difference area where the adhesive thickness exceeds the preset threshold is obtained and marked as the development area. The shortest distance between the development area and the point closest to the edge of the exposure area is analyzed. The adhesive properties and adhesive thickness difference corresponding to the distance are recorded. The action area of ​​the developer and the preset corresponding liquid concentration threshold are obtained based on the adhesive thickness difference, and the development work is carried out.

[0014] Based on the development results, the residual colloid is obtained. The wafer area is divided into several unit grids. The photoresist thickness and positive / negative properties of the colloid within each unit grid are obtained. These are input into a preset standard grid photoresist parameter library to obtain simulated baking parameters for each unit grid. The simulated baking parameters are corrected according to the positional relationship between the unit grids to obtain the optimal baking temperature and baking time. The correction follows the rule that the temperature gradually decreases from the center to the edge of the baking equipment and follows the differential response of positive and negative colloids to the baking temperature.

[0015] According to the above technical solution, the step of analyzing the photoresist pattern in the baked wafer area to predict the etching profile includes:

[0016] The photoresist pattern of the baked wafer area is obtained and its multi-angle visual image is analyzed to generate a predicted etching profile. The wafer area is labeled with layers according to the etching profile. The photoresist thickness difference between adjacent layers and the angle between the line connecting any two points in the wafer area within the same layer and the vertical direction are required to be within a specific threshold.

[0017] The minimum deformation threshold between the photoresist position distribution at each level and the etching profile is obtained. The deformation threshold is positively correlated with the photoresist volume and thickness. Etching simulation is performed in a preset system. Mixed gas flows through the wafer area at a specific flow rate and in the form of several line combinations. The similarity between the actual etching profile and the predicted etching profile at each level is monitored in real time after the lines pass through. Mixed gas parameters whose photoresist sidewall profile sharpness exceeds the preset threshold in a specific level are removed. Mixed gas parameters whose reaction time and similarity are both within the specific threshold are marked as a set of safe gas parameters.

[0018] According to the above technical solution, the step of classifying the deformed area, evaluating the etching effect, and then adjusting the etching operation parameters in real time includes:

[0019] Weights are assigned to the reaction time and the similarity of each layer, and the results are summed to obtain a safety score. The etching operation is performed using the safety gas parameters corresponding to the highest safety score. The volume and thickness of the colloid at each layer are monitored in real time. The etching effect is estimated based on the real-time changes in the length, width, and height of the colloid and the real-time changes in volume. When the etching effect results in colloid deformation exceeding a preset safety threshold, the layer where the deformation area is located is determined. Based on the correlation between the etching effects of this layer and other layers, a specific influence mapping combination corresponding to the differential deformation parameter values ​​is obtained. The etching effect is evaluated based on the combination. The etching effect includes the difference in deformation volume, the photoresist reaction time, and the similarity between the etching profile and the predicted etching profile. Dynamic etching is achieved by using the safety gas parameters corresponding to the group with the best etching effect.

[0020] According to the above technical solution, the operation of controlling thin film deposition in the wafer region using spray-type gas includes:

[0021] A gas-phase chemical reaction is performed in the wafer region. The reaction is uniformly controlled by a spray-type gas. The reaction substrate is heated and the deposition rate and the thickness of the deposited film in the region are monitored in real time. A mathematical model of gas flow rate and deposition rate is constructed. The film thickness at the edge and core of the region is monitored. When the thickness difference exceeds a threshold or the film thickness dispersion in the divided region exceeds a threshold, the location of the abnormal film thickness region is monitored, and the wind speed and spray position are adjusted to control the deposition of the reaction substrate until the film thickness in the region meets the standard requirements.

[0022] According to the above technical solution, the regulation of ion implantation parameters to ensure lattice-safe reactions includes:

[0023] The lattice arrangement structure and position in the wafer region are obtained. Single-ion-lattice collision simulation is performed in the system, and the effects of ion concentration, ion angle, and reaction temperature on the lattice are recorded. Relevant parameters under the condition of lattice damage are eliminated. The collision and reaction of multiple types of ions with the lattice after mixing are obtained according to preset rules. The reaction adjustment coefficients corresponding to the differences between the mixed situation and the single-ion situation are obtained according to the reaction properties of the ions themselves or the differences in the properties between the ions. The reaction adjustment coefficients under all parameters are collected, and the ion mixing parameter with the adjustment coefficient of the lowest lattice damage is marked as the initial mixed ion for implantation.

[0024] During the ion implantation process, the wafer region is irradiated with specific visible light, and the light trajectory is tracked. The location of byproducts is located based on the abnormal reflection of the light trajectory. The estimated impact of the byproducts at this location on the lattice reaction is analyzed. This impact manifests as changes in the type and velocity of ions flowing between the lattice. When the similarity between the estimated impact and the expected lattice reaction is lower than a threshold, the ion implantation amount, implantation angle, and reaction temperature are adjusted to ensure lattice integrity and maintain the normal progress of the ion-lattice reaction. The adjustments are manifested as ion implantation amount compensation based on the threshold of the distribution ratio of various ions within the lattice region, adjustment of the implantation angle based on the migration rate brought about by the initial ion implantation direction, and control of the reaction temperature based on ion activity and lattice reaction intensity.

[0025] A machine vision-based wafer semiconductor manufacturing system, the system comprising:

[0026] The wafer engraving module is used to select specific lighting parameters for exposure based on the difference in resist thickness in different areas of the wafer, and to dynamically adjust the baking parameters according to the residual resist in the developing results of the different areas.

[0027] The wafer etching module is used to analyze the photoresist pattern of the baked wafer area to predict the etching profile, simulate the etching process by passing the mixed gas in a line format to obtain safety gas parameters, classify the deformed area, evaluate the etching effect, and adjust the etching operation parameters in real time.

[0028] The deposition and ion implantation module is used to control the thin film deposition operation on the wafer region using spray gas. After constructing a gas flow rate and deposition rate model, the wind speed and spray position are dynamically adjusted. After performing single-ion-lattice collision simulation, the reaction between multiple ions and the lattice is obtained. Byproducts are detected and their impact is analyzed. Ion implantation parameters are adjusted to ensure safe lattice reaction.

[0029] A third aspect of this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it causes the electronic device to perform the method described in the first aspect of this application.

[0030] A fourth aspect of this application provides a computer-readable storage medium for storing a computer program that, when run on a computer, causes the computer to perform the method described in the first aspect of this application.

[0031] Compared with existing technologies, the beneficial effects achieved by this invention are as follows: In the photolithography stage, this invention predicts the shadow situation based on the photoresist thickness data of the wafer area, especially predicting the shadow of the overlapping area and using indirect data feedback to achieve dynamic parameter engraving, which effectively improves the accuracy of the photolithography engraving process of the wafer; In the etching stage, the photoresist and wafer area are layered and the differences and correlations are monitored, and the optimal etching control parameters are dynamically determined based on the real-time deformation, which significantly improves the accuracy of the etching process and effectively ensures the structural safety and electrical performance of the wafer components; In the ion implantation stage, the implantation dose, angle and other related parameters are dynamically adjusted according to the real-time lattice reaction and following the ion transition law, which maximizes the safety and integrity of the lattice points, thereby improving the overall accuracy of semiconductor manufacturing and the final electrical performance of the chip. Attached Figure Description

[0032] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0033] Figure 1 This is a flowchart of the steps of a machine vision-based wafer semiconductor manufacturing method according to an embodiment of this application.

[0034] Figure 2 This is a schematic diagram of a system module composition for wafer semiconductor manufacturing based on machine vision, according to an embodiment of this application.

[0035] Figure 3 This is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] Please see Figure 1 The present invention provides a technical solution: a wafer semiconductor manufacturing method based on machine vision, comprising:

[0040] Based on the difference in resist thickness in different areas of the wafer, specific lighting parameters are selected for exposure, and baking parameters are dynamically adjusted according to the resist residue in the development results of the different areas.

[0041] After analyzing the photoresist pattern of the baked wafer area, the etching profile is predicted. The mixed gas is simulated by passing it in a line format to obtain the safety gas parameters. The deformed area is classified and the etching effect is evaluated. The etching operation parameters are then adjusted in real time.

[0042] Thin film deposition was controlled by spraying gas onto the wafer region. After constructing a gas flow rate and deposition rate model, the wind speed and spray position were dynamically adjusted. Single-ion-lattice collision simulation was performed to obtain the reaction between multiple ions and the lattice. Byproducts were detected and their impact was analyzed. Ion implantation parameters were adjusted to ensure safe lattice reaction.

[0043] This invention predicts shadow conditions based on the photoresist thickness data of the wafer region during the photolithography stage, especially predicting the shadows in overlapping areas and using indirect data feedback to achieve dynamic parameter engraving, effectively improving the accuracy of the photolithography process. During the etching stage, the photoresist and wafer region are layered and their differences and correlations are monitored. The optimal etching control parameters are dynamically determined based on real-time deformation, significantly improving the accuracy of the etching process and effectively ensuring the structural safety and electrical performance of wafer components. During the ion implantation stage, the implantation dose, angle, and other related parameters are dynamically adjusted based on real-time lattice reactions and following ion transition laws, maximizing the safety and integrity of the lattice points, thereby improving the overall precision of semiconductor manufacturing and the final electrical performance of the chip.

[0044] In some preferred embodiments, specific illumination parameters are selected for exposure based on wafer region resist thickness difference data, further including the following steps:

[0045] During the photoresist coating stage, the photoresist thickness data of the wafer area is monitored and recorded in real time. Based on the differences in the photoresist thickness data distribution, the illumination and projection of specific wavelength light in multiple groups are simulated. Specific locations of photoresist where the light reflection or refraction angle exceeds the preset threshold are grouped and marked as abnormal areas. Based on the threshold of the proportion of abnormal areas to photoresist area and the shortest edge distance between abnormal areas, preset corresponding weights are obtained, and the products are summed to obtain the abnormal value. The light parameters of the group with the lowest abnormal value are marked as the exposure standard parameters and exposure is performed.

[0046] The shortest edge distance is the average value obtained by combining the shortest distances between a single edge point in an abnormal region and any other edge point. The outlier calculation is to obtain the corresponding weights of the proportional threshold and the average distance for each individual abnormal region, multiply them, and then sum them to obtain the anomaly assessment of all abnormal regions within the wafer area.

[0047] In some preferred embodiments, and by dynamically adjusting the baking parameters to reflect the colloid residue in the development results of the differential regions, the method further includes the following steps:

[0048] The actual exposure area is obtained based on the exposure process results and compared with the expected exposure area. The difference area where the adhesive thickness exceeds the preset threshold is obtained and marked as the development area. The shortest distance between the development area and the edge point closest to the exposure area is analyzed. The distance corresponds to the adhesive properties and the adhesive thickness difference. Based on the adhesive thickness difference, the area of ​​action of the developer and the preset corresponding liquid concentration threshold are obtained, and the development work is carried out.

[0049] Based on the development results, the residual colloid is obtained. The wafer area is divided into several unit grids. The photoresist thickness and positive / negative properties of the colloid within each unit grid are obtained. These are input into a preset standard grid photoresist parameter library to obtain simulated baking parameters for each unit grid. The simulated baking parameters are corrected according to the positional relationship between the unit grids to obtain the optimal baking temperature and baking time. The correction follows the rule that the temperature gradually decreases from the center to the edge of the baking equipment, and also follows the difference in reaction between positive and negative colloids to the baking temperature.

[0050] In some preferred embodiments, after analyzing the photoresist pattern of the baked wafer area, the etching profile is predicted, further including the following steps:

[0051] The photoresist pattern of the baked wafer area is obtained and its multi-angle visual image is analyzed to generate a predicted etching profile. The wafer area is labeled with layers according to the etching profile. The photoresist thickness difference between adjacent layers and the angle between the line connecting any two points in the wafer area within the same layer and the vertical direction are required to be within a specific threshold.

[0052] For the problem of defining the angle between the line connecting any two points in a single plane and the vertical direction within a threshold, for example, the photoresist is first divided into layers. For instance, the first layer has a thickness of 3mm, the second layer has a thickness of 4mm, and the difference between the two layers is 1mm. Within a preset specific threshold, for the angle between the line connecting any two points in the photoresist wafer region within the same layer and the vertical direction, in this application, each layer plane is not an absolute plane, but rather has a similarity to an absolute plane within a specific threshold. That is, it has a specific degree of convexity or concavity relative to an absolute plane, but is generally flat. Based on this understanding of "plane", there is an angle between the line connecting any two points in the "one-layer plane" in this application and the vertical direction. For points in different locations and regions within this plane, due to the thickness specification for adjacent layers, the line connecting the points will have a corresponding estimated angle with the vertical direction. Therefore, it can satisfy the requirement that the angle between the line connecting any two points in the "one-layer plane" in this application and the vertical direction is within a specific threshold, and the threshold is a specific range obtained according to a preset angle evaluation method.

[0053] The minimum deformation threshold between the photoresist position distribution at each level and the etching profile is obtained. The deformation threshold is positively correlated with the photoresist volume and thickness. Etching simulation is performed in a preset system. Mixed gas flows through the wafer area at a specific flow rate and in the form of several line combinations. The similarity between the actual etching profile and the predicted etching profile at each level is monitored in real time after the lines pass through. Mixed gas parameters whose photoresist sidewall profile sharpness exceeds the preset threshold in a specific level are removed. Mixed gas parameters whose reaction time and similarity are both within the specific threshold are marked as a set of safe gas parameters.

[0054] In some preferred embodiments, after classifying the deformed areas and evaluating the etching effect, the etching operation parameters are adjusted in real time, further including the following steps:

[0055] Weights are assigned to reaction time and similarity at each level, and the results are summed to obtain a safety score. The etching operation is performed using the safety gas parameters corresponding to the highest safety score. The volume and thickness of the colloid at each level are monitored in real time. The etching effect is estimated based on the real-time difference in the length, width, and height of the colloid and the real-time volume change. When the etching effect results in colloid deformation exceeding the preset safety threshold, the level of the deformation area is determined. Based on the correlation between the etching effects of this level and other levels, a specific influence mapping combination corresponding to the differential deformation parameter values ​​is obtained. The etching effect is evaluated for the combination, which includes the difference in deformation volume, photoresist reaction time, and the similarity between the etching profile and the predicted etching profile. The etching operation is performed using the safety gas parameters corresponding to the group with the best etching effect to achieve dynamic etching.

[0056] For example, the evaluation of etching effect is divided into three dimensions: volume difference, time and contour similarity. After the data of the three dimensions are statistically obtained, joint evaluation or data fusion is performed. The confirmation of the best effect group is not based on the maximum or minimum value of a single dimension, but on the specific data requirements corresponding to the etching object and the etching standard. According to the system's preset calculation rules or data fusion rules, the data comparison results are obtained and the difference between them and the preset standard data is used to select the best etching group parameter.

[0057] In some preferred embodiments, the thin film deposition control operation on the wafer region is performed using a spray gas, further including the following steps:

[0058] A gas-phase chemical reaction operation is performed in the wafer area. A spray-type gas is used to uniformly control the reaction. The reaction substrate is heated and the deposition rate and the thickness of the deposited film in the area are monitored in real time. A mathematical model of gas flow rate and deposition rate is constructed to monitor the film thickness at the edge and core of the area. When the thickness difference exceeds the threshold or the film thickness dispersion in the divided area exceeds the threshold, the location of the abnormal film thickness area is monitored, and the wind speed and spray position are adjusted to control the deposition of the reaction substrate until the film thickness in the area meets the standard requirements.

[0059] In some preferred embodiments, adjusting the ion implantation parameters to ensure a lattice-safe reaction further includes the following steps:

[0060] The system obtains the lattice arrangement structure and position in the wafer region, performs single-ion-lattice collision simulations, and records the effects of ion concentration, ion angle, and reaction temperature on the lattice. Parameters related to lattice damage scenarios are removed. The system obtains the collision and reaction of mixed ions with the lattice according to preset rules. Based on the reaction properties of the ions themselves or the differences in inter-ion properties, the system obtains the reaction adjustment coefficients corresponding to the differences between the mixed scenario and the single-ion scenario. The system aggregates the reaction adjustment coefficients under all parameters and marks the ion mixing parameter with the lowest lattice damage coefficient as the initial mixed ion for implantation.

[0061] During the ion implantation process, specific visible light is used to irradiate the wafer area and track the light trajectory. The location of by-products is located based on the abnormal reflection of the light trajectory. The predicted impact of the by-products at this location on the lattice reaction is analyzed. The impact manifests as changes in the type and velocity of ions flowing between the lattice. When the similarity between the predicted impact and the expected lattice reaction is lower than a threshold, the ion implantation amount, implantation angle, and reaction temperature are adjusted to ensure lattice integrity and maintain the normal progress of the ion-lattice reaction. The adjustments are made by compensating for the ion implantation amount based on the threshold of the distribution ratio of various ions in the lattice region, adjusting the implantation angle based on the migration rate brought about by the initial ion implantation direction, and controlling the reaction temperature based on the ion activity and the intensity of the lattice reaction.

[0062] Please see Figure 2 Similar to the embodiments described above, this application also provides a machine vision-based wafer semiconductor manufacturing system, comprising:

[0063] The wafer engraving module is used to select specific lighting parameters for exposure based on the difference in resist thickness in different areas of the wafer, and to dynamically adjust the baking parameters according to the residual resist in the developing results of the different areas.

[0064] The wafer etching module is used to analyze the photoresist pattern of the baked wafer area to predict the etching profile, simulate the etching process by using mixed gas in a line format to obtain safety gas parameters, classify the deformed area, evaluate the etching effect, and adjust the etching operation parameters in real time.

[0065] The deposition and ion implantation module is used to control the thin film deposition operation on the wafer area using spray gas. After constructing a gas flow rate and deposition rate model, the wind speed and spray position are dynamically adjusted. After performing single-ion-lattice collision simulation, the reaction between multiple ions and the lattice is obtained. Byproducts are detected and their impact is analyzed. Ion implantation parameters are adjusted to ensure safe lattice reaction.

[0066] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0067] Based on the same inventive concept as the above method embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it enables the electronic device to implement the control method described in the above embodiments.

[0068] In one embodiment, the electronic device may be a server, and in this embodiment, the structure of the electronic device may be as follows: Figure 3 As shown, it includes a memory 2001, a communication module 2003, and one or more processors 2002.

[0069] The memory 2001 is used to store computer programs executed by the processor 2002. The memory 2001 may mainly include a program storage area and a data storage area. The program storage area may store the operating system and programs required to run instant messaging functions, etc.; the data storage area may store various instant messaging information and operation instruction sets, etc.

[0070] Memory 2001 may be volatile memory, such as random-access memory (RAM); memory 2001 may also be non-volatile memory, such as read-only memory, flash memory, hard disk drive (HDD), or solid-state drive (SSD); or memory 2001 may be any other medium capable of carrying or storing a desired computer program having the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 2001 may be a combination of the above-mentioned memories.

[0071] Processor 2002 may include one or more central processing units (CPUs) or digital processing units, etc. Processor 2002 is used to implement the above-mentioned audio data processing method when calling computer programs stored in memory 2001.

[0072] The communication module 2003 is used to communicate with terminal devices and other servers.

[0073] This application embodiment does not limit the specific connection medium between the memory 2001, communication module 2003, and processor 2002. This application embodiment... Figure 3 The memory 2001 and the processor 2002 are connected via a bus 2004, which is in... Figure 3 The connections between other components are illustrated with arrows and are for illustrative purposes only, not as limiting information. The Bus 2004 can be divided into address bus, data bus, control bus, etc. For ease of description, Figure 3 The text uses only one arrow to describe it, but does not indicate that there is only one bus or one type of bus.

[0074] Based on the same inventive concept as the above-described method embodiments, embodiments of the present invention also provide a computer-readable storage medium for storing a computer program. When the computer program is run on a computer, it enables the electronic device to implement the control method described in the above embodiments. The computer-readable storage medium can be a readable signal medium or a readable storage medium. A readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0075] Based on the same inventive concept as the above-described method embodiments, embodiments of the present invention also provide a computer program product, which includes a computer program that, when run on an electronic device, causes the electronic device to perform the steps of the control methods described above according to various exemplary embodiments of this application. The program product may take the form of any combination of one or more readable media. These computer program commands can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the commands executed by the processor of the computer or other programmable data processing device generate a process for implementing... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0076] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0077] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A wafer semiconductor manufacturing method based on machine vision, characterized in that: The method includes the following steps: Based on the difference in resist thickness in different areas of the wafer, specific lighting parameters are selected for exposure, and baking parameters are dynamically adjusted according to the resist residue in the development results of the different areas. After analyzing the photoresist pattern of the baked wafer area, the etching profile is predicted. The mixed gas is simulated by passing it in a line format to obtain the safety gas parameters. The deformed area is classified and the etching effect is evaluated. The etching operation parameters are then adjusted in real time. Thin film deposition is controlled by spraying gas onto the wafer region. After constructing a gas flow rate and deposition rate model, the wind speed and spray position are dynamically adjusted. After single-ion-lattice collision simulation, the reaction between multiple ions and the lattice is obtained. Byproducts are detected and their impact is analyzed. Ion implantation parameters are adjusted to ensure safe lattice reaction.

2. The machine vision-based wafer semiconductor manufacturing method of claim 1, wherein: The step of selecting specific illumination parameters for exposure based on wafer region resist thickness difference data includes: During the photoresist coating stage, the photoresist thickness data of the wafer area is monitored and recorded in real time. Based on the differences in the photoresist thickness data distribution, the illumination and projection of specific wavelength light in multiple groups are simulated. Specific locations of photoresist where the light reflection or refraction angle exceeds a preset threshold are grouped and marked as abnormal areas. Based on the threshold of the proportion of the abnormal area to the photoresist area and the shortest edge distance between the abnormal areas, preset corresponding weights are obtained, and the products are summed to obtain the abnormal value. The light parameters of the group with the lowest abnormal value are marked as the exposure standard parameters and exposure is performed.

3. The machine vision-based wafer semiconductor manufacturing method of claim 2, wherein: The process of dynamically adjusting baking parameters based on the colloid residue levels corresponding to the development results in the differential regions includes: The actual exposure area is obtained based on the exposure process results and compared with the expected exposure area. The difference area where the adhesive thickness exceeds the preset threshold is obtained and marked as the development area. The shortest distance between the development area and the point closest to the edge of the exposure area is analyzed. The adhesive properties and adhesive thickness difference corresponding to the distance are recorded. The action area of ​​the developer and the preset corresponding liquid concentration threshold are obtained based on the adhesive thickness difference, and the development work is carried out. Based on the development results, the residual colloid is obtained. The wafer area is divided into several unit grids. The photoresist thickness and positive / negative properties of the colloid within each unit grid are obtained. These are input into a preset standard grid photoresist parameter library to obtain unit grid simulated baking parameters. The simulated baking parameters are corrected according to the positional relationship between the unit grids to obtain the optimal baking temperature and baking time. The correction follows the rule that the temperature gradually decreases from the center to the edge of the baking equipment and follows the differential response of positive and negative colloids to the baking temperature.

4. The machine vision-based wafer semiconductor manufacturing method of claim 3, wherein: The step of analyzing the photoresist pattern in the baked wafer area to predict the etching profile includes: The photoresist pattern of the baked wafer area is obtained and its multi-angle visual image is analyzed to generate a predicted etching profile. The wafer area is labeled with layers according to the etching profile. The photoresist thickness difference between adjacent layers and the angle between the line connecting any two points in the wafer area within the same layer and the vertical direction are required to be within a specific threshold. The minimum deformation threshold between the photoresist position distribution at each level and the etching profile is obtained. The deformation threshold is positively correlated with the photoresist volume and thickness. Etching simulation is performed in a preset system. Mixed gas flows through the wafer area at a specific flow rate and in the form of several line combinations. The similarity between the actual etching profile and the predicted etching profile at each level is monitored in real time after the lines pass through. Mixed gas parameters whose photoresist sidewall profile sharpness exceeds the preset threshold in a specific level are removed. Mixed gas parameters whose reaction time and similarity are both within the specific threshold are marked as a set of safe gas parameters.

5. The machine vision-based wafer semiconductor manufacturing method of claim 4, wherein: The process of grading the deformed area, evaluating the etching effect, and then adjusting the etching operation parameters in real time includes: Weights are assigned to the reaction time and the similarity of each layer, and the results are summed to obtain a safety score. The etching operation is performed using the safety gas parameters corresponding to the highest safety score. The volume and thickness of the colloid at each layer are monitored in real time. The etching effect is estimated based on the real-time changes in the length, width, and height of the colloid and the real-time changes in volume. When the etching effect results in colloid deformation exceeding a preset safety threshold, the layer where the deformation area is located is determined. Based on the correlation between the etching effects of this layer and other layers, a specific influence mapping combination corresponding to the differential deformation parameter values ​​is obtained. The etching effect is evaluated based on the combination. The etching effect includes the difference in deformation volume, the photoresist reaction time, and the similarity between the etching profile and the predicted etching profile. Dynamic etching is achieved by using the safety gas parameters corresponding to the group with the best etching effect.

6. The machine vision-based wafer semiconductor manufacturing method of claim 5, wherein: The operation of controlling thin film deposition in the wafer region using spray-type gas includes: A gas-phase chemical reaction is performed in the wafer region. The reaction is uniformly controlled by a spray-type gas. The reaction substrate is heated and the deposition rate and the thickness of the deposited film in the region are monitored in real time. A mathematical model of gas flow rate and deposition rate is constructed. The film thickness at the edge and core of the region is monitored. When the thickness difference exceeds a threshold or the film thickness dispersion in the divided region exceeds a threshold, the location of the abnormal film thickness region is monitored, and the wind speed and spray position are adjusted to control the deposition of the reaction substrate until the film thickness in the region meets the standard requirements.

7. The machine vision-based wafer semiconductor manufacturing method of claim 6, wherein: The regulation of ion implantation parameters to ensure lattice-safe reactions includes: The lattice arrangement structure and position in the wafer region are obtained. Single-ion-lattice collision simulation is performed in the system, and the effects of ion concentration, ion angle, and reaction temperature on the lattice are recorded. Relevant parameters under the condition of lattice damage are eliminated. The collision and reaction of multiple types of ions with the lattice after mixing are obtained according to preset rules. The reaction adjustment coefficients corresponding to the differences between the mixed situation and the single-ion situation are obtained according to the reaction properties of the ions themselves or the differences in the properties between the ions. The reaction adjustment coefficients under all parameters are collected, and the ion mixing parameter with the adjustment coefficient of the lowest lattice damage is marked as the initial mixed ion for implantation. During the ion implantation process, the wafer region is irradiated with specific visible light, and the light trajectory is tracked. The location of byproducts is located based on the abnormal reflection of the light trajectory. The estimated impact of the byproducts at this location on the lattice reaction is analyzed. This impact manifests as changes in the type and velocity of ions flowing between the lattice. When the similarity between the estimated impact and the expected lattice reaction is lower than a threshold, the ion implantation amount, implantation angle, and reaction temperature are adjusted to ensure lattice integrity and maintain the normal progress of the ion-lattice reaction. The adjustments are manifested as ion implantation amount compensation based on the threshold of the distribution ratio of various ions within the lattice region, adjustment of the implantation angle based on the migration rate brought about by the initial ion implantation direction, and control of the reaction temperature based on ion activity and lattice reaction intensity.

8. A machine vision-based wafer semiconductor manufacturing system, characterized in that: The system includes: The wafer engraving module is used to select specific lighting parameters for exposure based on the difference in resist thickness in different areas of the wafer, and to dynamically adjust the baking parameters according to the residual resist in the developing results of the different areas. The wafer etching module is used to analyze the photoresist pattern of the baked wafer area to predict the etching profile, simulate the etching process by passing the mixed gas in a line format to obtain safety gas parameters, classify the deformed area, evaluate the etching effect, and adjust the etching operation parameters in real time. The deposition and ion implantation module is used to control the thin film deposition operation on the wafer region using spray gas. After constructing a gas flow rate and deposition rate model, the wind speed and spray position are dynamically adjusted. After performing single-ion-lattice collision simulation, the reaction between multiple ions and the lattice is obtained. Byproducts are detected and their impact is analyzed. Ion implantation parameters are adjusted to ensure safe lattice reaction.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it causes the electronic device to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program that, when run on a computer, causes the computer to perform the method as described in any one of claims 1 to 7.

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