Architecture for optimizing a boot-up process of an integrated
By introducing concurrent chiplet boot sequences and verification mechanisms into the SoC, the interdependence problem in the chiplet boot process is solved, resulting in faster boot times and higher reliability, ensuring that the SoC's performance and functionality meet expectations.
CN121693722APending Publication Date: 2026-03-17QUALCOMM INC
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Patent Information
- Application Number
- CN202480049698.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-04
- Filing Date
- 2024-06-07
- Publication Date
- 2026-03-17
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Figure CN121693722A_ABST
Abstract
An integrated circuit device includes a plurality of chiplets. The first chiplet is configured to execute a first boot sequence to prepare the first chiplet for operation and output a trigger signal. The second chiplet is configured to perform a second boot sequence in response to the trigger signal to prepare the second chiplet for operation. The first boot sequence at least partially overlaps the second boot sequence in time. An example of an integrated circuit device is a system-on-chip (SoC) that may include various subsystems distributed in a plurality of chiplets or dies. The boot sequences of the subsystems are ranked to increase concurrency between the boot sequences. The concurrency of startup sequences among the chiplets is increased, and the overall startup time of the SoC is reduced.
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