Test case generation method, device, medium, and product

Abstract

The application relates to the chip technical field and provides a test case generation method, equipment, medium and product.The method comprises the following steps: a first layer excitation generation module is used to generate a constraint sequence; the constraint sequence is transmitted to a second layer excitation generation module, and a control identifier used for indicating that the constraint sequence is preferentially used is configured in the second layer excitation generation module; in the case that the control identifier is in an effective state, target constraint data is obtained from the constraint sequence, the target constraint data is taken as a basic constraint condition of a target input, and a residual signal of the target input is solved according to the basic constraint condition; the basic constraint condition and the residual signal are assembled, and a test case of the target input is generated. Since the second layer excitation generation module inherits complex dependent constraints as the basic constraint condition when generating each target input, only a low-complexity solution is needed for the residual signal, so that constraint solving complexity, which originally increases exponentially with the number of inputs, is reduced to linear or constant level.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a test case generation method, device, medium, and product. Background Technology

[0002] In chip verification, constrained random verification techniques are typically used to generate test stimuli. Current verification methods, when dealing with strongly correlated input signals, such as address correlations in cache testing, usually employ a scheme that solves all constraints simultaneously. However, the computational complexity of this scheme increases exponentially with the number of inputs. When the number of signals or inputs is large, the constraint solving time becomes excessively long, and may even cause the simulation to freeze. Summary of the Invention

[0003] This invention provides a test case generation method, device, medium, and product to address the deficiencies in related technologies.

[0004] This invention provides a test case generation method, comprising the following steps: A constraint sequence is generated using the first-layer stimulus generation module. The constraint sequence includes target constraint data for generating target inputs. The target constraint data has a dependency relationship with the constraint data of other inputs in the verification scenario. The constraint sequence is passed to the second-level stimulus generation module, and a control identifier is configured in the second-level stimulus generation module to indicate the priority use of the constraint sequence; When the control flag is in an active state, the target constraint data is obtained from the constraint sequence, the target constraint data is used as the basic constraint condition of the target input, and the remaining signal of the target input is solved according to the basic constraint condition; Assemble the basic constraints and the remaining signals to generate test cases for the target input.

[0005] According to a test case generation method provided by the present invention, configuring a control identifier in the second-layer stimulus generation module to indicate the preferential use of the constraint sequence includes: Based on the structural characteristics of the target input, a data container for storing the constraint sequence is configured in the second-layer excitation generation module; Configure the control identifier and establish a mapping relationship between the target field in the target input and the data in the data container. The control identifier is used to indicate that the value of the target field is preferentially taken from the data container.

[0006] According to a test case generation method provided by the present invention, the step of obtaining the target constraint data from the constraint sequence and using the target constraint data as the basic constraint condition for the target input includes: Lock the value of the target field to the target constraint data from the data container; In the process of solving the target input, the randomization generation step of the target field is skipped, and the locked target constraint data is used as the basic constraint condition.

[0007] According to a test case generation method provided by the present invention, locking the value of the target field to the target constraint data from the data container includes: Read the target constraint data from the data container; The target constraint data is assigned to the target field, and the target constraint data is removed from the data container.

[0008] According to a test case generation method provided by the present invention, the step of solving for the residual signal of the target input based on the basic constraints includes: If any remaining signal in the target input has a dependency relationship with the basic constraint, logical operations are performed according to the basic constraint to generate the constraint value of any remaining signal. If any remaining signal in the target input has no dependency on the basic constraints, the remaining signal is solved independently according to the preset design specifications.

[0009] According to a test case generation method provided by the present invention, the step of generating a constraint sequence using a first-layer stimulus generation module includes: Based on the preset input dependency rules in the verification scenario, a sequence of data containing the target constraint data is generated, and the sequence of data is used as the constraint sequence. The sequence data contains data items that correspond to multiple inputs, including the target input, and the data items in the sequence data satisfy the input dependency rules.

[0010] According to a test case generation method provided by the present invention, the verification scenario includes, but is not limited to, a cache verification scenario; in the scenario of verifying the same group of index fields in the cache, the target constraint data is address information with the same group of index fields, and the other input constraint data is address information with the same group of index fields as the target constraint data.

[0011] The present invention also provides a test case generation device, comprising the following modules: The first generation module is used to generate a constraint sequence using the first-layer excitation generation module. The constraint sequence includes target constraint data for generating target inputs. The target constraint data has a dependency relationship with the constraint data of other inputs in the verification scenario. A sequence transmission module is used to transmit the constraint sequence to the second-level stimulus generation module, and to configure a control identifier in the second-level stimulus generation module to indicate the priority use of the constraint sequence; The data acquisition module is used to acquire the target constraint data from the constraint sequence when the control identifier is in a valid state, use the target constraint data as the basic constraint condition of the target input, and solve the remaining signal of the target input based on the basic constraint condition; The second generation module is used to assemble the basic constraints and the remaining signals to generate test cases for the target input.

[0012] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the test case generation method as described above.

[0013] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the test case generation method as described above.

[0014] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the test case generation method as described above.

[0015] The test case generation method, device, medium, and product provided by this invention utilize a first-layer stimulus generation module to focus on processing constraint sequences with strong correlations between different inputs, and forcibly injects the pre-generated constraint sequences into the local solution process of the second-layer stimulus generation module through a control identification mechanism. Since the second-layer stimulus generation module directly inherits the complex dependency constraints as basic constraints when generating each target input, it only needs to solve the remaining signals with low complexity, thereby reducing the constraint solution complexity, which originally increased exponentially with the number of inputs, to linear or constant level. This not only greatly shortens the constraint solution time and improves simulation efficiency, but also effectively solves the technical problem that traditional single-step solution schemes struggle to handle strong correlations between inputs, achieving a dual improvement in verification efficiency and verification quality. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the test case generation method provided by the present invention.

[0018] Figure 2 This is a schematic diagram of the test case generation device provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the structure of the electronic device provided by the present invention.

[0020] Figure label: 210: First generation module; 220: Sequence transmission module; 230: Data acquisition module; 240: Second generation module; 310: Processor; 320: Communication interface; 330: Memory; 340: Communication bus. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0022] As the scale of integrated circuit design continues to expand, the complexity of chip front-end verification is increasing. To improve verification coverage, restricted random verification techniques are typically used to automatically generate a large number of test stimuli.

[0023] In relevant verification techniques, two main approaches are used for constraint solving of test stimuli. The first approach solves all constraints simultaneously, where the solver attempts to satisfy all constraints between all input signals at once. While this approach ensures overall consistency among inputs, the computational complexity increases exponentially when the number of inputs or signals is large, resulting in lengthy constraint solving times that severely slow down simulation progress or even prevent the solution from being completed. The second approach solves the constraints of one input at a time, performing constraint solving independently for each input signal. While this approach is faster per-input calculation, the fragmented generation of inputs makes it difficult to handle strong correlations between inputs, hindering the generation of complex verification scenarios with tight temporal or logical dependencies.

[0024] To address this, the present invention provides a test case generation method. This method utilizes a first-layer stimulus generation module to pre-generate a constraint sequence containing dependencies, which is then passed to a second-layer stimulus generation module. By configuring control flags, the second layer can preferentially inherit the target constraint data from the first layer as basic constraints when generating target inputs. This allows for the solution of remaining signals and the assembly of test cases. This decouples complex global dependency constraints from local single-input solution processes. While ensuring accurate generation of test cases with strong correlation characteristics, it significantly reduces constraint solution time and avoids exponential growth in computational complexity.

[0025] in, Figure 1 This is a flowchart illustrating the test case generation method provided by the present invention, as shown below. Figure 1 As shown, the method includes steps 110, 120, 130 and 140.

[0026] Step 110: Generate a constraint sequence using the first-layer stimulus generation module. The constraint sequence contains target constraint data used to generate target inputs. There is a dependency between the target constraint data and the constraint data of other inputs in the verification scenario.

[0027] Here, the first-layer stimulus generation module can be understood as the module in the verification environment architecture responsible for macro-level control and generating data with global or cross-input dependencies. In general verification methodologies, it can be implemented, but is not limited to, through virtual sequences or upper-layer test cases. The main responsibility of the first-layer stimulus generation module is not to generate a specific, complete input package, but to plan the relationships between different inputs.

[0028] A constraint sequence is a set of ordered or unordered data. This data is not just independent numerical values, but also a carrier of the rules governing the dependencies between inputs. For example, in a verification scenario, it may be necessary to generate a series of continuous inputs, or a set of inputs with specific logical relationships. The constraint sequence contains the specific data set required to realize these logical relationships, such as a specific list of address values, a set of control parameters with a specific step size, or a specific sequence of state flags.

[0029] The target input refers to a specific verification stimulus that needs to be generated. In chip verification, an input typically consists of multiple sets of signals, such as address signals, data signals, read / write control signals, burst transfer type signals, atomic operation attribute signals, and transfer identifier signals.

[0030] Target constraint data refers to certain key parameters or conditions that must be followed when generating the target input. Other inputs refer to other input objects that belong to the same verification scenario as the target input, but differ in temporal or logical order.

[0031] A dependency refers to a specific constraint that must be satisfied between different inputs on certain signal domains. For example, in a test cache eviction mechanism, the verification scenario typically requires generating several sets of inputs with the same set index field address to trigger cache replacement. In this case, the set field in the addresses of different inputs is the same, which is a typical dependency.

[0032] In this step, the first-level stimulus generation module does not directly generate complete inputs, but focuses on generating signal domain segments or constraints that are strongly correlated between different inputs. For example, it generates a sequence containing N identical Set addresses. Each of these addresses, when assigned to a specific input, constitutes the target constraint data for that corresponding input.

[0033] As an optional implementation, the first-layer stimulus generation module can generate the constraint sequence by calling a randomization function or by directly assigning values. Since only key dependency data is generated at this stage, rather than the complete complex input, the computational cost is very small.

[0034] Step 120: Pass the constraint sequence to the second-level stimulus generation module, and configure a control identifier in the second-level stimulus generation module to indicate the priority use of the constraint sequence.

[0035] Specifically, the second-layer stimulus generation module can be understood as the module in the verification environment architecture responsible for the specific execution and generation of a single complete input object. In general verification methodologies, it can correspond to a functional module at the sequence or driver level.

[0036] There are various ways to pass the constraint sequence to the second-level stimulus generation module. As an alternative embodiment, the constraint sequence can be passed to the second-level stimulus generation module through parameter passing, global variables, or specific data structures (such as queues, arrays, mailboxes, etc.).

[0037] The control flag can be understood as a switch, used to establish a priority mechanism in the second-level stimulus generation module. The control flag tells the second-level stimulus generation module that for certain inputs, it should not generate them using the default random method, but should instead prioritize data passed down from the first-level stimulus generation module.

[0038] The process of configuring the control flag is essentially the process of establishing a connection between the first-level constraints and the second-level execution logic. For example, when the first-level stimulus generation module generates a specific address sequence for testing the Cache Evict, and the control flag is in a valid state, it instructs the second-level stimulus generation module that the address field should use the address sequence pre-generated by the first-level stimulus generation module when generating inputs subsequently.

[0039] Step 130: When the control flag is in an active state, obtain the target constraint data from the constraint sequence, use the target constraint data as the basic constraint condition for the target input, and solve the remaining signal of the target input based on the basic constraint condition.

[0040] Specifically, if the control flag is in a valid state, it indicates that there is currently a mandatory constraint from the upper layer. At this time, the second-layer excitation generation module extracts the data belonging to the target input from the received constraint sequence, i.e., the target constraint data.

[0041] Next, this target constraint data is used as the basic constraint condition. This means that the target constraint data is treated as a fixed value during the generation of the target input and no longer participates in the randomization solution, or serves as a hard constraint condition to restrict the subsequent solution process.

[0042] Subsequently, based on this fundamental constraint, the residual signals are solved. The residual signals refer to all signals in the target input other than those corresponding to the target constraint data.

[0043] As an implementation scenario, if the remaining signals have a dependency on the basic constraints, they are generated according to that dependency. For example, in a bus protocol, burst type and atomic operation attributes may depend on the address. If the address has been determined as the basic constraint in the first-level stimulus generation module, then the remaining signals, such as burst type, can be directly derived according to the protocol rules or randomly generated within a limited range.

[0044] As another implementation scenario, if the remaining signals are not dependent on the basic constraints, they are generated independently according to the design specifications. For example, the data payload may be address-independent and can be generated independently and randomly.

[0045] This step removes the target constraint data from the complex global dependency solution and directly inherits it as the known conditions for a single solution. This allows each loop to solve only the remaining part of the input, greatly reducing the complexity of a single solution.

[0046] Step 140: Assemble the basic constraints and remaining signals to generate test cases for the target input.

[0047] Specifically, after obtaining the basic constraints from the first-layer stimulus generation module and the residual signals obtained from the local solution of the second-layer stimulus generation module, these two sets of data are combined and packaged to form a complete test case that can be used to drive the design under test. This embodiment ensures that the generated test cases meet the global verification scenario requirements by directly reusing the basic constraints, and also gives the test cases rich local random characteristics through independent randomization of the residual signals.

[0048] As an optional implementation, the basic constraints can be assigned to the corresponding fields of the target input, and the calculated remaining signals can be assigned to the remaining fields of the target input. Finally, the standard packaging function of the verification environment can be called to generate test cases for the target input.

[0049] The test case generation method provided in this embodiment utilizes a first-layer stimulus generation module that focuses on processing constraint sequences with strong correlations between different inputs. A control identification mechanism then forces the pre-generated constraint sequences into the local solution process of the second-layer stimulus generation module. Since the second-layer stimulus generation module directly inherits complex dependency constraints as basic constraints when generating each target input, it only needs to solve the remaining signals with low complexity. This reduces the constraint solution complexity, which originally increased exponentially with the number of inputs, to linear or constant level. This not only significantly shortens the constraint solution time and improves simulation efficiency but also effectively solves the technical problem of traditional single-step solution schemes struggling to handle strong correlations between inputs, achieving a dual improvement in verification efficiency and verification quality.

[0050] Considering that in actual verification projects, the verification environment needs to be able to flexibly adapt to different types of input objects and different forms of constraint data, and at the same time, a clear and efficient mechanism is needed to associate the upper-level constraint sequence with the lower-level specific signals, this embodiment further refines the "configuration of a control identifier in the second-level excitation generation module to indicate the priority use of the constraint sequence".

[0051] Specifically, the second-level stimulus generation module is configured with a control identifier to indicate the priority use of constraint sequences, including: Based on the structural characteristics of the target input, a data container for storing the constraint sequence is configured in the second-layer excitation generation module; Configure control identifiers and establish a mapping relationship between the target field in the target input and the data in the data container. The control identifiers are used to indicate that the value of the target field is preferentially taken from the data container.

[0052] Specifically, the structural characteristics of the target input refer to information such as signal type, bit width, and protocol segment definition contained in the target input. A data container is a storage structure used to temporarily store data received from the first-layer stimulus generation module; its specific form can be adapted according to the data type of the constraint sequence, including but not limited to queues, dynamic arrays, or associative arrays.

[0053] For example, if the structural characteristics of the target input indicate that it contains a 32-bit address field and the constraint sequence is a set of 32-bit unsigned integers, then a queue of type bit[31:0] can be configured in the second-layer stimulus generation module as a data container to receive these address data in sequence. This configuration method based on structural characteristics ensures that the data container can accurately carry the information transmitted from the upper layer, avoiding the problem of data type mismatch.

[0054] Considering that without establishing a clear mapping, the verification environment will be unable to identify which signal the constraint data stored in the data container is intended for, nor will it be able to determine when to enable this data to override the default generation logic, thus preventing the data in the data container from being used correctly, this embodiment configures a control flag and establishes a mapping relationship between the target field in the target input and the data in the data container. This allows the status of the control flag to clearly indicate when the data is used, and the mapping relationship to lock in the specific path of data injection. This ensures that when the control flag is valid, the value of the target field can be accurately and preferentially taken from the specified data container, achieving targeted and forced injection of constraint data.

[0055] Here, the target field refers to the signal or domain segment in the target input that needs to be subject to specific constraints. It can be determined by analyzing key test points in the verification plan or by the data attributes corresponding to the constraint sequence generated by the first-level stimulus generation module. The mapping relationship refers to the operation path or logical binding set in the verification code logic that assigns specific data elements from the data container to specific target fields in the target input. This mapping relationship ensures that when the control flag is valid, the program can automatically and accurately find the corresponding data source to populate the target field without manual intervention.

[0056] This embodiment configures an adapted data container based on the structural characteristics of the target input and establishes a clear mapping relationship between the target field and the data container through control identifiers. This realizes a standardized and configurable constraint injection interface, which not only ensures the accurate transmission and storage of different types of constraint data, but also enables the global constraints generated by the first-layer stimulus generation module to be accurately applied to specific fields of the target input of the second-layer stimulus generation module. This ensures that the strategy of prioritizing the use of constraint sequences has high execution accuracy and maintainability in complex automated verification processes.

[0057] Considering that during the constraint solving process, if only the target constraint data is simply obtained without mandatory intervention in the generation mechanism, the default randomization engine of the verification environment may overwrite these externally injected data or cause constraint conflicts. To ensure that the constraint data passed down from the first layer is absolutely effective, this embodiment provides specific logical constraints for "obtaining target constraint data from the constraint sequence and using the target constraint data as the basic constraint condition for the target input".

[0058] Specifically, the target constraint data is obtained from the constraint sequence, and the target constraint data is used as the basic constraint conditions for the target input, including: Lock the value of the target field to the target constraint data from the data container; In the process of solving for the target input, the randomization generation step of the target field is skipped, and the locked target constraint data is used as the basic constraint condition.

[0059] Considering that if the locking operation is not performed, the data in the data container will only remain at the storage level and will not actually be used for the target input, and will not be recognized and utilized by the subsequent solution logic, this embodiment locks the value of the target field to the target constraint data from the data container.

[0060] Specifically, when the control flag is detected to be valid, the target constraint data is read from the data container and directly assigned to the target field in the target input, ensuring that the target field has the expected exact value before entering the solver.

[0061] Considering that if the randomization generation step is not skipped, the solver in the verification environment will still attempt to reassign or calculate the target field, which not only wastes computational resources but may also cause the target field to be assigned a new random value due to the solver's random algorithm, thereby overwriting the correct data locked in the previous step and causing the constraint to fail. Based on this, this embodiment skips the randomization generation step of the target field during the solution process for the target input and uses the locked target constraint data as the basic constraint conditions.

[0062] As an alternative implementation, the random property of the target field can be turned off by setting the random mode of the target field. Thus, when the solver starts, the target field can be ignored and treated as a known constant, and other residual signals can be calculated based on this constant.

[0063] This embodiment fundamentally changes the generation path of verification stimuli by explicitly locking the value of the target field and disabling its randomization generation step. This transforms the target field from a variable to be solved into a known constant, which not only ensures the absolute priority of the upper-level constraints and avoids randomization conflicts, but more importantly, it greatly reduces the search space of the solver, thereby significantly improving the speed and efficiency of constraint solving.

[0064] Considering that in actual verification scenarios, the constraint sequences generated by the first-layer stimulus generation module usually have strict temporal relationships, such as requiring access to address A before accessing address B, and the generated data needs to be consumed sequentially by the second-layer stimulus generation module, this embodiment specifies the data container type and data locking and maintenance mechanisms to ensure that the data access order is consistent with the generated temporal logic and to effectively manage memory resources.

[0065] Specifically, locking the value of the target field to target constraint data from the data container includes: Read the target constraint data from the data container; Assign the target constraint data to the target field and remove the target constraint data from the data container.

[0066] Specifically, the data container can be configured as a First-In-First-Out (FIFO) queue, an array, etc. When the data container is configured as a FIFO queue, the data at the head of the queue is used as the target constraint data. A FIFO queue is a specific data structure where the data stored first is retrieved first. FIFO queues naturally align with the "order-based generation and execution" characteristics of validation stimuli. They do not require additional index pointer maintenance; only the head element needs to be monitored to ensure that the sequence planned by the first-level stimulus generation module is perfectly reproduced in the second-level stimulus generation module, avoiding validation logic errors caused by out-of-order access.

[0067] Furthermore, considering that the head data represents the most urgent and priority constraint to be met within the current generation cycle, and that direct assignment is the most direct way to ensure that the condition takes effect, this embodiment first reads the head data of the first-in-first-out queue as the target constraint data and assigns the target constraint data to the target field, thereby completing the data transfer at the physical level and instantiating the abstract queue data into specific attribute values ​​of the target input.

[0068] After assigning the target constraint data to the target field, considering that the data has been consumed by the target input, if it is not removed in time, the next target input will repeatedly obtain the same data, thereby destroying the continuity and correctness of the sequence. Therefore, in this embodiment, the target constraint data is removed from the first-in-first-out queue, thereby updating the state of the queue so that the head of the queue automatically points to the next data in the sequence, preparing for the next cycle generation.

[0069] This embodiment uses a first-in-first-out (FIFO) queue as the data container and employs an atomic "read-assign-remove" operation process to ensure strict temporal consistency of the constraint sequence. By promptly removing data after each use, the queue state is automatically updated, enabling the second-layer stimulus generation module to accurately process complex sequences of arbitrary length using a simple, efficient, and stateless loop logic, significantly reducing the complexity of the control logic.

[0070] Considering that in the target input, besides the basic constraints forcibly locked by the first layer, there are a large number of residual signals, some of which are closely related to the basic constraints, while others are relatively independent. If all these residual signals are generated in a completely random manner, not only will the computational efficiency be low, but illegal stimuli that violate the protocol specifications may also be generated; if fixed values ​​are used for all of them, the random coverage of the verification will be lost. In order to balance the legality and coverage of the verification, while maximizing the solution efficiency, this embodiment classifies the steps of "solving the residual signals of the target input according to the basic constraints".

[0071] Specifically, solving for the residual signal of the target input based on the basic constraints includes: If any residual signal in the target input has a dependency relationship with the basic constraint, perform logical operations based on the basic constraint to generate the constraint value of any residual signal; If any remaining signal in the target input has no dependency on the basic constraints, the remaining signal is solved independently according to the preset design specifications.

[0072] Specifically, if any residual signal in the target input has a dependency relationship with the basic constraints, it indicates that the range or specific value of the residual signal is logically constrained by the basic constraints. If this constraint relationship is not met, the generated stimulus will be considered an illegal stimulus, which may cause the design under test to enter an error state or the verification result to be invalid. Considering that the value space of the signal has converged significantly at this time, and can even be directly derived, if a general stochastic solver is used for searching, it will not only waste computing resources, but may also lead to solution failure due to improper constraint configuration. Therefore, this embodiment performs logical operations based on the basic constraints to generate the constraint value of any residual signal.

[0073] As an alternative embodiment, code logic can be written that instructs the calculation of constraint values ​​for any remaining signal based on the values ​​of the underlying constraints.

[0074] If any residual signal in the target input has no dependency on the basic constraints, it indicates that the residual signal can vary freely within the design-allowed range, and its value does not affect the validity of the basic constraints. Considering that in order to improve the completeness of the verification, it is necessary to traverse all possible values ​​of the signal as much as possible to cover various boundary cases, this embodiment solves for any residual signal independently according to the preset design specifications. Here, the preset design specifications can be understood as the bit width limit defined by the interface protocol, the value range specified in the datasheet, or the specific distribution weight set in the verification plan.

[0075] As an alternative embodiment, a randomization function combined with local constraint blocks can be used to solve for any remaining signal independently.

[0076] Considering that in complex system-level verification, simply generating discrete, unrelated random inputs often fails to uncover deep-seated design flaws, many critical functional verifications heavily rely on a set of input sequences that are closely related in time or logic. To systematically construct such complex verification scenarios and lay the foundation for efficient subsequent solutions, this embodiment elaborates on the step of "generating constraint sequences using the first-layer stimulus generation module."

[0077] Specifically, the constraint sequence is generated using the first-level excitation generation module, including: Based on the preset input dependency rules in the verification scenario, generate sequence data containing target constraint data, and use the sequence data as the constraint sequence; The sequence data contains data items that correspond to multiple inputs, including the target input, and the data items in the sequence data satisfy the input dependency rules.

[0078] Considering that the core of verification scenarios often lies in the rules—that is, different inputs need to follow certain mathematical or logical relationships, such as address increment, identical IDs, or continuous data content—if these rules are not planned in advance, the subsequently generated stimuli may not trigger the core logic of the design under test. Therefore, this embodiment first clarifies that data is generated based on the dependency rules between inputs.

[0079] Here, the input dependency rule refers to the relational model defined in the validation plan that must be satisfied between multiple inputs. Sequence data refers to a set of data carrying specific numerical values ​​generated according to this rule.

[0080] As an alternative implementation, sequence data can be generated by writing a generation algorithm in the first-level stimulus generation module. For example, if the dependency rule is "generate 10 addresses with the same Set index but different tags", the code can first randomly generate a base Set value, then loop 10 times, keeping the Set unchanged each time while randomly generating a Tag, and finally store these 10 addresses into an array to obtain the sequence data.

[0081] Furthermore, considering that the sequence data generated by the first-layer stimulus generation module serves not only a single target input but also a series of inputs throughout the entire verification scenario, it is necessary to clearly define the correspondence between each data item in the sequence data and each subsequent specific input in order to achieve an efficient strategy of generating once and reusing multiple times. Here, a data item refers to each specific element in the sequence data, such as a specific address. Multiple inputs refer to a series of stimulus objects generated sequentially by the second-layer stimulus generation module during the simulation process, and the target input is precisely the object currently being generated and solved among these multiple inputs.

[0082] As an optional implementation, an index mapping method can be used, which specifies that the data item with index i in the sequence data corresponds to the input generated in the i-th simulation process. In this way, each data item in the sequence data naturally passes the input dependency rules to each input, ensuring that although these inputs are generated one by one, they as a whole satisfy the global dependency requirements.

[0083] This embodiment centrally processes input dependency rules in the first-layer stimulus generation module, enabling the efficient generation of complex sequence data from a global perspective. This avoids the complex cross-object communication and state maintenance required when generating data one by one at the lower level, allowing verifiers to focus on designing high-level dependency scenarios without worrying about the underlying implementation details, thus greatly improving the efficiency and quality of verification scenario development.

[0084] Considering that the test case generation method proposed in the above embodiments has strong versatility, but its effect is particularly significant when dealing with specific types of strongly correlated inputs, in order to more clearly demonstrate the application value of this embodiment in the most typical pain point scenarios in the actual industry, this embodiment specifies the method in the cache verification scenario.

[0085] Specifically, the verification scenarios include, but are not limited to, cache verification scenarios. In the scenario of verifying the same set of index fields in the cache, the target constraint data is the address information with the same set of index fields, and the other input constraint data is the address information with the same set of index fields as the target constraint data.

[0086] In cache design, a set-associative mapping is typically used. When the CPU accesses memory, the physical address is divided into a tag, a set index, and an offset. To verify the cache replacement policy, verifiers must construct a special scenario: multiple consecutive access requests targeting the same set index but with different tags, exceeding the cache's path limit, thus forcing the cache to evict older data. Using a traditional fully random method, the probability of randomly generating two addresses with the same set index is extremely low, making it very difficult to trigger this scenario. Using traditional constraint solving, forcibly constraining N addresses to have the same set index places a huge computational burden on the solver.

[0087] Here, the cache verification scenario refers to a simulation verification environment for the functionality, performance, and consistency of the chip's internal cache module. The set index field segment refers to the portion of the address bus used to locate the cache set.

[0088] For each target input, its corresponding target constraint data can be one of N addresses, while the constraint data for other inputs are the remaining (N-1) addresses.

[0089] This embodiment precisely resolves the contradiction between high coverage and low solution efficiency in cache eviction mechanism verification by applying a general method to a cache verification scenario. By pre-locking group index fields, the verification environment can generate address sequences with deep logical relationships in batches with extremely high efficiency, thereby quickly and effectively verifying the core replacement logic of the cache controller.

[0090] To more intuitively demonstrate the significant advantages of the test case generation method provided by this invention in constraint solving efficiency, the following uses a specific mathematical model example to compare and analyze the "simultaneous solution scheme" in related technologies with the "layered solution scheme" of this invention.

[0091] Suppose that in a certain verification scenario, two strongly correlated target inputs a and b need to be generated. Input a contains two signals a0 and a1, and input b contains two signals b0 and b1. According to the verification requirements, the following constraints exist between inputs a and b, and within each input b: Cross-input dependency constraint: a0=b0 (that is, the 0th bit signal of inputs a and b must be the same); Input internal constraints for 'a': if a0=1, then a1=1; if a0=0, then a1=0. Input b internal constraints: if b0=1, then b1=0; if b0=0, then b1=1.

[0092] In the "simultaneous solution of all constraints" scheme of related technologies, the solver needs to treat all the above input signals as a whole and construct a system of equations containing 4 variables (a0, a1, b0, b1) and 5 logical constraints for one-time solution.

[0093] In this model, as the number of inputs n increases, the dependencies across inputs cause the size of the constraint network to expand dramatically. The computational complexity of the solver is typically between O(n) and O(2^n). n The value fluctuates between n and n, exhibiting an exponential growth trend. When n is large or there are many signals, the constraint solving engine needs to consume an extremely long time for backtracking and searching, and may even fail to obtain a valid solution in a finite time due to the explosion of the state space.

[0094] After adopting the "test case generation method" provided by this invention, the solution process is decoupled into two levels: First layer (global constraint generation): First, process the cross-input dependency constraint a0=b0. The first-layer stimulus generation module directly generates a value randomly and passes it as a constraint sequence to the second-layer stimulus generation module.

[0095] The second layer (locally independent solution): When generating input 'a', the value of the first-layer excitation generation module is directly inherited, i.e., a0=1. At this time, the solver only needs to process the internal constraints of input 'a', that is, it only needs to calculate 2 relevant internal constraints in a single operation.

[0096] When generating input b, the value is inherited from the first-level excitation generation module, i.e., b0=1. The solver only needs to process the internal constraints of input b, and only needs to calculate 2 relevant internal constraints at a time.

[0097] Through this hierarchical processing, regardless of the increase in the number of inputs n, the second-layer stimulus generation module only needs to deal with constant-level local constraints when generating each target input. The originally complex global network is decomposed into a series of independent atomic solution processes. Therefore, the method of this invention successfully reduces the solution complexity from O(2^n) as the number of inputs increases. n The time complexity is reduced to O(1), which is independent of the number of inputs, greatly reducing the constraint solving time and improving the verification efficiency.

[0098] The test case generation apparatus provided by the present invention is described below. The test case generation apparatus described below and the test case generation method described above can be referred to in correspondence.

[0099] Based on any of the above embodiments Figure 2 This is a schematic diagram of the test case generation device provided by the present invention, as shown below. Figure 2 As shown, the device includes: The first generation module 210 is used to generate a constraint sequence using the first-layer excitation generation module. The constraint sequence contains target constraint data for generating target inputs. There is a dependency between the target constraint data and the constraint data of other inputs in the verification scenario. The sequence transmission module 220 is used to transmit the constraint sequence to the second-level excitation generation module, and to configure a control identifier in the second-level excitation generation module to indicate the priority use of the constraint sequence; The data acquisition module 230 is used to acquire target constraint data from the constraint sequence when the control flag is in an effective state, use the target constraint data as the basic constraint conditions of the target input, and solve the remaining signal of the target input based on the basic constraint conditions; The second generation module 240 is used to assemble the basic constraints and residual signals to generate test cases for the target input.

[0100] Figure 3 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 3 As shown, the electronic device may include a processor 310, a communications interface 320, a memory 330, and a communication bus 340. The processor 310, communications interface 320, and memory 330 communicate with each other via the communication bus 340. The processor 310 can call logical instructions in the memory 330 to execute a test case generation method.

[0101] Furthermore, the logical instructions in the aforementioned memory 330 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0102] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the test case generation method provided by the above methods.

[0103] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the test case generation methods provided by the methods described above.

[0104] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0105] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A test case generation method, characterized in that, include: A constraint sequence is generated using the first-layer stimulus generation module. The constraint sequence includes target constraint data for generating target inputs. The target constraint data has a dependency relationship with the constraint data of other inputs in the verification scenario. The constraint sequence is passed to the second-level stimulus generation module, and a control identifier is configured in the second-level stimulus generation module to indicate the priority use of the constraint sequence; When the control flag is in an active state, the target constraint data is obtained from the constraint sequence, the target constraint data is used as the basic constraint condition of the target input, and the remaining signal of the target input is solved according to the basic constraint condition; Assemble the basic constraints and the remaining signals to generate test cases for the target input.

2. The test case generation method according to claim 1, characterized in that, The configuration of a control identifier in the second-layer excitation generation module to indicate the preferential use of the constraint sequence includes: Based on the structural characteristics of the target input, a data container for storing the constraint sequence is configured in the second-layer excitation generation module; Configure the control identifier and establish a mapping relationship between the target field in the target input and the data in the data container. The control identifier is used to indicate that the value of the target field is preferentially taken from the data container.

3. The test case generation method according to claim 2, characterized in that, The step of obtaining the target constraint data from the constraint sequence and using the target constraint data as the basic constraint condition for the target input includes: Lock the value of the target field to the target constraint data from the data container; In the process of solving the target input, the randomization generation step of the target field is skipped, and the locked target constraint data is used as the basic constraint condition.

4. The test case generation method according to claim 3, characterized in that, Locking the value of the target field to the target constraint data from the data container includes: Read the target constraint data from the data container; The target constraint data is assigned to the target field, and the target constraint data is removed from the data container.

5. The test case generation method according to any one of claims 1 to 4, characterized in that, The step of solving for the residual signal of the target input based on the basic constraints includes: If any remaining signal in the target input has a dependency relationship with the basic constraint, logical operations are performed according to the basic constraint to generate the constraint value of any remaining signal. If any remaining signal in the target input has no dependency on the basic constraints, the remaining signal is solved independently according to the preset design specifications.

6. The test case generation method according to any one of claims 1 to 4, characterized in that, The generation of the constraint sequence using the first-layer excitation generation module includes: Based on the preset input dependency rules in the verification scenario, a sequence of data containing the target constraint data is generated, and the sequence of data is used as the constraint sequence. The sequence data contains data items that correspond to multiple inputs, including the target input, and the data items in the sequence data satisfy the input dependency rules.

7. The test case generation method according to any one of claims 1 to 4, characterized in that, The verification scenarios include, but are not limited to, cache verification scenarios; in the scenario of verifying the same set of index fields in the cache, the target constraint data is address information with the same set of index fields, and the other input constraint data is address information with the same set of index fields as the target constraint data.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the test case generation method as described in any one of claims 1 to 7.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the test case generation method as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the test case generation method as described in any one of claims 1 to 7.

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