General electrical equipment control system, method and device based on hardware resource virtualization and software defined logic

Abstract

The invention discloses a universal electrical equipment control system, method and device based on hardware resource virtualization and software defined logic. The system comprises a central controller, a system bus and at least one programmable controlled terminal. The core innovation is as follows: the terminal is universal hardware which is internally arranged or can access a control logic function library and can be remotely defined by a logic mode code issued by the central controller, and the lifelong software reconfiguration of a hardware logic function is realized by calling a preset function or loading a configuration module to dynamically instantiate and solidify. The terminal is integrated with a state monitoring circuit, real-time feedback of the load state is achieved, and the central controller conducts trend analysis on data based on self-adaptive baseline modeling so as to achieve predictive maintenance. The system adopts a daisy chain bus to realize extremely simple deployment, and supports local direct connection control such as radio frequency remote control to realize common interaction. According to the invention, an evolvable, highly reliable, green and energy-saving open type general control platform with intelligent operation and maintenance capability is constructed.

Description

Technical Field

[0001] This invention belongs to the field of Internet of Things and electrical automation control technology, specifically relating to an innovation in electrical control infrastructure. In particular, it relates to a system, method, and apparatus that abstracts general-purpose hardware into functional units whose underlying electrical control logic can be defined by software, and achieves intelligent control and operation and maintenance based on closed-loop state feedback. Background Technology

[0002] Current intelligent control systems for electrical equipment generally follow a design paradigm of "deeply binding the underlying electrical control logic with dedicated hardware," typically manifested as "one function, one hardware" or "one hardware, one logic." That is, specific underlying electrical control functions (such as on / off switching, linear dimming, and timing control) are permanently implemented by specially designed hardware circuits and corresponding firmware. Most improvements in existing technologies are limited to application-layer configuration and management (e.g., setting up device linkage scenarios in a smart home app), without addressing the fundamental architectural limitation of "fixed underlying electrical control logic functionality."

[0003] For example, the programmability of common "programmable smart switches" on the market is essentially limited to changing the mapping relationship between buttons and controlled objects (such as a lamp), while the inherent "instantaneous on / off" electrical logic function of the switch hardware itself cannot be changed. Users cannot redefine the same switch hardware as a dimmer or a timing controller through software configuration.

[0004] This deeply coupled paradigm leads to a series of problems, including poor system flexibility, high costs for function upgrades and changes, and low levels of intelligent operation and maintenance. It also generates a large amount of electronic waste due to frequent hardware replacements. In the industrial sector, while programmable logic controller (PLC) systems are powerful and programmable, their complex architecture, high cost, and large size make them unsuitable for widespread residential and commercial building applications. Furthermore, devices in building bus systems such as KNX remain functionally specific.

[0005] Furthermore, due to the long-standing dominance of the "function-hardware" deep integration paradigm in industry practice, a deeply ingrained technological perception and design constraint has formed in this field: in scenarios with stringent safety and reliability requirements, such as building electrical systems, the underlying electrical control logic must be implemented by dedicated hardware circuits. This is considered the only reliable path to ensure system determinism, real-time performance, and security. Conversely, the technical approach of "dynamically defining or reconstructing the underlying hardware logic through software" is generally believed to introduce unpredictability, compatibility risks, and security vulnerabilities, and is therefore often deliberately avoided in critical applications. This technological bias derived from the traditional paradigm essentially constitutes a fundamental mental constraint hindering the evolution of hardware resource universality and system architecture flexibility.

[0006] Therefore, the industry has long lacked a unified solution that can break through the aforementioned rigid functional paradigms and cognitive limitations at the infrastructure level, achieve lifetime reconfigurability of hardware resources, and combine simplified deployment with intelligent operation and maintenance capabilities. The limitations of existing technologies lie not only in specific engineering defects, but also in their deeply constrained design philosophies. Summary of the Invention

[0007] (a) Technical problems to be solved This invention aims to break through the traditional paradigm of "fixed electrical control logic function at the hardware level" and the resulting limitations in technical understanding, and solve the technical problems caused by this, such as poor flexibility of electrical control systems, high deployment and transformation costs, reliance on manual experience for operation and maintenance, low overall energy efficiency, short life cycle of hardware resources, and insufficient universality of intelligent technology.

[0008] (II) Basic Concepts and Paradigm Shift To fundamentally solve the aforementioned technical problems and overcome inherent technical biases, this invention abandons the traditional "functional rigidity" design paradigm and proposes a new infrastructure that integrates "hardware resource virtualization" and "software-defined logic".

[0009] Its core lies in achieving a fundamental paradigm shift: 1. Deconstructing traditional dedicated hardware: Deconstructing dedicated hardware that performs specific functions into a "general-purpose hardware resource pool" with undefined functions, consisting of general-purpose driver channels, programmable computing units, and standardized state awareness units.

[0010] 2. Reconstruct control logic: Software-encode various underlying electrical control logics into "logic services" that can be stored, dynamically loaded, instantiated, and solidified into the aforementioned resource pool.

[0011] Under this new paradigm, the final functional identity of physical hardware is no longer permanently locked by the circuit design at the factory, but is dynamically assigned and reconfigured through software configuration after deployment and throughout its entire lifecycle. This achieves a fundamental shift from "function determines hardware" to "software defines function, and hardware provides resources," laying the top-level design foundation for subsequent technical solutions.

[0012] (III) Technical Solution To overcome the aforementioned shortcomings, this invention proposes a new infrastructure paradigm of "general-purpose hardware resource virtualization + software-defined logic + closed-loop state awareness". The core of this paradigm lies in abstracting physical control hardware into a unified, programmable resource pool, and software-firing the specific underlying electrical control logic into services that can be dynamically loaded, instantiated, managed, and evolved.

[0013] Terminology definition: To clarify this invention, key terms are first defined: 1. "Underlying electrical control logic function": refers to the basic control algorithm that directly determines the physical form (such as discrete level, continuously changing pulse width), timing relationship and generation rules of the output signal of the electrical interface channel. Its implementation directly depends on the hardware drive circuit and underlying firmware / logic unit.

[0014] 2. "Different Categories" of Underlying Electrical Control Logic: These refer to logic types that differ fundamentally in the physical nature of their output signals and their control dimensions. These differences cannot be converted to each other through simple parameter adjustments. Examples include, but are not limited to: binary switching logic (output is a discrete on / off state), linear modulation logic (output is a continuous or segmented continuously changing analog or high-resolution digital quantity, such as pulse width modulation (PWM) dimming), timing control logic (output changes according to a preset absolute or relative time sequence), and event-response logic (output is triggered by specific events or combinations of conditions, such as linkage or interlocking). Changing the logic category inevitably alters the core algorithm executed by the microprocessor and / or the operating mode of the drive circuit.

[0015] 3. "Control Logic Function Library": refers to a collection of software functions, firmware code, hardware configuration files (such as FPGA bitstreams), or logic description units that can be recognized, loaded, and executed by the microprocessor to implement specific low-level electrical control logic. Its physical carrier is not limited to the terminal's local memory, but also includes remote storage media accessible via the system bus or network.

[0016] 4. “Microprocessor”: In this invention, it is interpreted broadly, and its core feature is that it includes programmable computing units or logic units capable of executing predetermined operation sequences according to instructions or configurations to control peripheral circuits. This includes, but is not limited to: microcontrollers (MCUs), central processing units (CPUs), digital signal processors (DSPs), and field-programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs).

[0017] 5. “Reconfiguration”: In this invention, it specifically refers to the process of fundamentally changing the basic electrical control function implemented by the programmable controlled terminal as a whole by changing the category of the underlying electrical control logic of the general drive channel through software instructions (e.g., changing from implementing a switching function to implementing a dimming function). This process is different from parameter adjustment, function optimization, or communication protocol update that do not change the basic function category.

[0018] In a first aspect, a general electrical equipment control system based on hardware resource virtualization and software-defined logic is provided, characterized in that it includes: Central controller; One system bus; At least one programmable controlled terminal is communicatively connected to the central controller via the system bus; The programmable controlled terminal includes: microprocessor; At least two common drive channels with the same or substantially similar hardware circuit designs are connected to the microprocessor; Non-volatile memory, connected to the microprocessor; A status monitoring circuit, coupled to the general-purpose drive channel and the microprocessor, is used to collect the drive status of the channel and / or the electrical parameters of the load circuit. The central controller is configured to generate function configuration instructions containing logical mode codes and send them to the target programmable controlled terminal via the system bus. The microprocessor of the programmable controlled terminal is configured to: access a control logic function library and, in response to the function configuration instructions, call the corresponding control logic function from the control logic function library or load the corresponding hardware configuration module according to the logic mode code, so as to reconstruct the underlying electrical control logic of the general drive channel at the software or hardware logic level, and solidify the reconstructed logic configuration in the non-volatile memory; and process the output of the status monitoring circuit, generate status feedback data, and send it to the central controller through the system bus. The central controller is also configured to receive and process the status feedback data.

[0019] Furthermore, the condition monitoring circuit includes a load current detection unit; the central controller is further configured to perform trend analysis on the load current timing information in the historical condition feedback data based on adaptive baseline modeling, and generate predictive maintenance information based on the analysis results.

[0020] Furthermore, the system supports operation via at least one local direct-connection control device, which includes an RF remote controller, a physical button panel, or a touch panel; wherein, the RF remote controller is paired with the RF transceiver unit built into the programmable controlled terminal or the central controller, and can send control commands directly to the designated programmable controlled terminal to trigger its fixed logic functions without relying on the centralized scheduling of the central controller.

[0021] Furthermore, the programmable controlled terminal is a modular device, its housing is adapted to be installed on a standard electrical rail, and the housing integrates a lateral electrical connector; multiple programmable controlled terminals are connected in series with the system bus in a daisy-chain topology through the lateral electrical connector.

[0022] Furthermore, the system bus is a multi-core cable configured to simultaneously transmit DC operating power and bidirectional data signals based on a digital communication protocol to all the serially connected programmable controlled terminals.

[0023] Furthermore, the programmable controlled terminal also includes a standardized hardware expansion interface for connecting functional expansion modules; the microprocessor is further configured to be able to identify and drive the connected functional expansion modules through the expansion interface.

[0024] Furthermore, the central controller also includes a multi-protocol adaptation module for communicating with external devices that use a different communication protocol than the system bus; the central controller is capable of uniformly arranging and synchronously executing control instructions for the external devices and control instructions for the programmable controlled terminal.

[0025] Furthermore, the microprocessor is further configured to execute hardware interlock logic when at least two general-purpose drive channels are logically associated, in order to prevent the output of simultaneously valid drive signals to loads that are not allowed to be turned on at the same time.

[0026] Furthermore, the function configuration instructions also include a scene context identifier; the programmable controlled terminal is configured to: load and solidify different combinations of control logic functions for the same set of general drive channels under different scene context identifiers, and activate the corresponding solidified logic according to the received scene switching instructions at runtime.

[0027] Furthermore, the virtual functional devices formed by the reconstruction of the general drive channels after being defined by the functional configuration instructions include, but are not limited to, any one or more of the following: single-channel switch, double-control switch, curtain controller, dimmer, socket controller, speed control device, timed task trigger, sequence controller, or scene trigger.

[0028] Secondly, a method for hardware function reconfiguration and closed-loop state management of the aforementioned system is provided, characterized by comprising the following steps: The central controller generates and issues function configuration instructions containing logic mode codes to programmable underlying electrical control logic of the general drive channel within the controlled terminal using software definition. The target programmable controlled terminal calls the corresponding function from the accessible control logic function library or loads the corresponding hardware configuration module according to the logic mode code to instantiate the logic, and then stores the instantiated logic in a fixed manner. The programmable controlled terminal acquires status information through a status monitoring circuit and reports feedback data containing the status information to the central controller. The central controller performs status display, fault alarm, or trend analysis based on adaptive baseline modeling based on the feedback data.

[0029] Thirdly, a programmable controlled terminal device for the aforementioned system is provided, characterized in that it comprises: case; The microprocessor, non-volatile memory, at least two general-purpose drive channels with the same or substantially similar hardware circuit designs, status monitoring circuit and bus interface circuit are disposed within the housing. The microprocessor is configured to access a control logic function library; The microprocessor is further configured to: receive a function configuration instruction through the bus interface circuit; call a control logic function from the control logic function library or load a hardware configuration module according to the function configuration instruction to reconstruct the control logic of the general drive channel; and generate state feedback data based on the input of the state monitoring circuit and send it through the bus interface circuit.

[0030] Fourthly, a method for manufacturing a programmable controlled terminal device is provided, characterized in that it includes: Provide a housing; The housing contains a microprocessor, non-volatile memory, at least two universal drive channels with identical hardware circuit designs, a status monitoring circuit, and a bus interface circuit. Configure the microprocessor to access a control logic function library containing various categories of low-level electrical control logic functions; The microprocessor is configured to respond to external instructions by calling functions in the function library to reconstruct the logic of the general-purpose driver channel.

[0031] (iv) Beneficial effects Compared with the prior art, the present invention, through the above-mentioned paradigm shift and specific technical solutions, has achieved the following outstanding substantive features and significant progress: 1. It represents a fundamental shift in the infrastructure paradigm, directly overcoming the perception of function rigidity: Addressing the system rigidity problem caused by the deep coupling of traditional "function-hardware," the core architecture combining the "microprocessor whose underlying logic can be reconfigured via software instructions" and the "general-purpose driver channel" as described in claim 1 allows the same physical hardware to be remotely configured to achieve fundamentally different logical functions, from switches to dimmers. This not only achieves lifetime reconfigurability of hardware functions but also practically proves and breaks the technical prejudice that "underlying logic must be hardware-fixed," providing a new paradigm for the sustainable evolution of electrical control systems.

[0032] 2. A highly reliable security system was systematically constructed to address security concerns regarding software-defined systems: Addressing concerns about the uncertainty of software-defined systems in the field, a defense-in-depth system was built through the hardware interlocking logic of claim 8, the closed-loop state monitoring and feedback of claims 1-2, and the multi-layered security mechanisms (hardware interlocking, system self-monitoring, and emergency bypass) described in the specific embodiments. This system ensures the behavioral determinism and failure safety of software-defined systems, empirically demonstrating that it can surpass the comprehensive security level of traditional fixed hardware, thus systematically refuting related technical biases.

[0033] 3. Unexpectedly simplified deployment and significant cost reduction benefits: Addressing the pain points of complex deployment and high costs, based on the "modular terminal daisy-chain serial" topology structure defined in claims 4-5, the traditional point-to-point radial cabling is innovatively transformed into a single serial bus. As quantitatively demonstrated by the topology model in Example 6 of the specification, this structure mathematically and inevitably significantly reduces the amount of cable conduit and construction work, resulting in highly synergistic economic and environmental benefits that are unattainable by traditional system improvements.

[0034] 4. It opens a new data-driven intelligent operation and maintenance paradigm: Relying on the "status monitoring circuit" built into each terminal in claims 1-2 and the system's "closed-loop feedback" channel, combined with the intelligent analysis algorithm of the central controller, the system achieves a leap from real-time fault alarms to predictive maintenance capabilities. This transforms operation and maintenance from a "passive response" relying on human experience to a data-driven "proactive prevention," significantly reducing long-term operation and maintenance costs and technical barriers.

[0035] 5. It embodies the unity of green circular economy and inclusive economic development: by pooling hardware resources, it greatly extends the life cycle of equipment, reducing electronic waste at the source; by combining "minimalist deployment" to reduce initial resource consumption; and by leveraging the minimalist local interaction such as "radio frequency remote control" supported by claim 3, it hides complex technologies in the background. Ultimately, it achieves the social goal of green sustainable development and widespread accessibility of intelligent technologies. Attached Figure Description

[0036] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram comparing the architecture of the system of this invention (daisy chain bus) with that of a traditional system (star radial cabling).

[0038] Figure 2This is a block diagram illustrating the hardware composition principle of the central controller in an embodiment of the present invention.

[0039] Figure 3 This is a block diagram illustrating the hardware composition principle of the programmable controlled terminal in an embodiment of the present invention.

[0040] Figure 4 A schematic diagram illustrating the daisy-chain connection of multiple programmable controlled terminals via a side connector.

[0041] Figure 5 The timing waveform diagram of the hardware interlock logic under the configuration of a dual-control switch.

[0042] Figure 6 This is a flowchart illustrating the integration of external devices into a central controller via a multi-protocol adapter module.

[0043] Figure 7 This is a diagram showing the overall workflow and state transitions of the system of this invention.

[0044] Figure 8 This is a schematic diagram of a specific embodiment of a condition monitoring circuit.

[0045] Figure 9 This is a flowchart illustrating the multi-layered security mechanism and failure mode handling process of the system of the present invention.

[0046] Figure 10 This diagram illustrates a logical comparison of the technical problems and solutions between the "functionally fixed paradigm" and the "software-defined paradigm". Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only some embodiments of this invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0048] 1. System Architecture and New Paradigm Logic (Refer to...) Figure 1 , Figure 10 ) like Figure 10 As shown, under the traditional paradigm of "fixed underlying electrical control logic functions," each control function requires a dedicated hardware component, leading to system rigidity and difficulty in upgrading. The "general-purpose hardware resource pool + software-defined logic" paradigm proposed in this invention abstracts general-purpose hardware into a resource pool, and defines its underlying logic services on demand through software, thereby achieving decoupling between functions and hardware. Figure 1 The invention provides a direct comparison of the significant differences in structural complexity and material consumption between the daisy-chain bus architecture of this invention and the traditional star-shaped radial wiring.

[0049] 2. Overall system workflow and state transitions (refer to...) Figure 7 ) Figure 7 This demonstrates the entire state transition process of the system of the present invention, from power-on initialization to normal operation, logic reconfiguration, and fault handling. The core of the system's workflow is a deterministic state machine, whose key states and transition conditions include: Enter the "Wait for Configuration Mode" from the "Power-On Initialization" screen.

[0050] The conditions for automatically switching from the "Waiting for Configuration Mode" to "Normal Operation" are: if no valid function configuration command is received within a preset time after the system is powered on, the default logical configuration will be automatically loaded from the non-volatile memory.

[0051] The transition condition from "normal operation" to "logic refactoring" is: the central controller issues a new function configuration instruction containing logic mode code.

[0052] The transition condition from "normal operation" to "scene switching" is: the central controller issues a scene switching command containing a scene context identifier.

[0053] The transition condition from "normal operation" to "fault state" is as follows: the status monitoring circuit detects hardware faults such as overcurrent, overvoltage, or short circuit, or the microprocessor self-test fails or the communication heartbeat times out.

[0054] Conditions for recovery from a fault state: The fault is cleared (e.g., by manual reset) and the system self-test passes, or a clear system reset command is received.

[0055] These clearly defined state transition conditions ensure that the system can operate safely, reliably, and deterministically or enter a preset safe state under various expected and unexpected conditions, which is the core design embodiment of the system's robustness and controllability.

[0056] 3. Detailed Description of Specific Implementation Methods The key technologies and implementation methods of the system will be explained in detail below, based on the overall process described above.

[0057] 3.1 Example 1: Core Logic Restructuring Mechanism The microprocessor-accessible control logic function library of the programmable controlled terminal contains pre-compiled machine code function blocks or hardware configuration descriptions such as func_switch(), func_dimmer(), and func_sequential(), each corresponding to a unique logic mode code (e.g., 0x01 corresponds to a single-channel switch, and 0x02 corresponds to dual-control interlock logic).

[0058] When the central controller needs to configure channels 1 and 2 of terminal A as dual-control interlocked switches, it will issue the following instruction: {CMD: DEFINE, TARGET: A, LOGIC_ID: 0x02, BIND_CH: [1,2]}. Upon receiving this instruction, the microprocessor of terminal A executes the following process: (1) Parse logic mode code 0x02; (2) Locate and call the corresponding function func_interlocked_dual_switch() from the accessible control logic function library; (3) Pass the channel parameters [1,2] into the function to create and run the logic instance in memory; (4) Write the key configuration parameters of the instance (such as logical ID, binding channel, interlock relationship) into the local non-volatile memory for solidification.

[0059] Key differentiator: This process alters the underlying electrical control logic of channels 1 and 2 (e.g., introducing interlocks), rather than simply performing application-level device binding. After a reboot, the terminal can independently operate this interlock logic, and its basic dual-control switch function remains unaffected even if system bus communication is interrupted. This fundamentally distinguishes it from any "pseudo-programmable" device that only supports application-level configuration.

[0060] Implementation of hardware interlock logic: When a microprocessor calls an interlocked logic function, it synchronously configures its internal or external output logic circuits, enabling the hardware interlock mechanism. One implementation method is shown in the appendix. Figure 5 As shown, this is implemented using digital logic gates (such as AND gates and OR gates). The logic is as follows: when the drive signal of channel 1 is valid (high level), the drive output enable terminal of channel 2 is directly blocked by the hardware circuit, and vice versa. This physically prevents the output of simultaneously valid drive signals to loads that are not allowed to be turned on at the same time (such as the two paths of a double-control switch), avoiding the risk of short circuit. This interlocking function is automatically integrated during logic instantiation, forming the first layer of safety mechanism.

[0061] 3.2 Example 1-A: Dynamic Reconfiguration of Hardware Logic Based on FPGA In a variant embodiment of the present invention, the core processing unit of the programmable controlled terminal is implemented by a field-programmable gate array (FPGA). In this scheme, the "control logic function library" is embodied as multiple different hardware configuration files (or IP cores) stored in the non-volatile memory outside the FPGA, each file corresponding to a hardware circuit description of a low-level electrical control logic (such as a switching logic circuit or a PWM dimming logic circuit).

[0062] When the central controller issues a function configuration instruction containing specific logic mode codes, the FPGA's configuration logic reads the corresponding hardware configuration file from memory based on these codes and dynamically reconstructs the interconnection relationships of its internal logic units. This process is completed within milliseconds, and the FPGA is reconstructed into a hardware circuit with a specific function (e.g., a dedicated switch controller or a high-precision PWM generator). This reconstructed hardware circuit directly controls the general-purpose drive channel, achieving logic reconstruction at the circuit level rather than just the software level, resulting in higher performance and greater determinism.

[0063] 3.3 Example 2: Closed-Loop State Awareness and Predictive Maintenance Algorithm Status monitoring circuit (see one specific schematic diagram) Figure 8 The system continuously and in real-time collects electrical parameters such as load current from each general-purpose drive channel. The central controller performs in-depth analysis of the operating current of critical loads (such as water pumps and fans) and executes a trend analysis algorithm based on adaptive baseline modeling to achieve predictive maintenance. (1) Data acquisition and feature extraction: Establish historical time series datasets of load current characteristic parameters (such as peak starting current I_peak, steady-state operating current I_steady, start-up time, etc.) for specific load circuits.

[0064] (2) Dynamic baseline modeling: Based on the historical data, dynamically calculate the moving statistical baseline value of the feature parameter (e.g., the moving average value of the peak current of the past 100 starts, MA_peak) and its normal fluctuation range (e.g., based on the moving standard deviation σ_peak).

[0065] (3) Real-time comparison and trend judgment: The latest real-time characteristic parameters collected by the status monitoring circuit are compared with the calculated dynamic baseline and fluctuation range.

[0066] (4) Warning generation: When the real-time parameters continuously and significantly deviate from the dynamic baseline (for example, I_peak is greater than MA_peak + 2σ_peak for 5 consecutive operating cycles), it is determined that the load equipment (such as motor) may have a performance degradation trend such as mechanical wear and bearing aging. The system automatically generates warning information and notifies the operation and maintenance personnel.

[0067] Collaborative Analysis: The predictive maintenance capability revealed in this embodiment is a direct technical product of the deep coupling and synergistic effect of the three major features of this invention: "software-defined architecture," "closed-loop state awareness," and "unified communication bus." The software-defined architecture ensures that the functional semantics of each terminal are clear and unambiguous, enabling accurate classification and analysis of the collected current data; the reliable, real-time bidirectional communication provided by the daisy-chain bus allows high-frequency, continuous time-series data to be stably uploaded to the central controller; and the powerful computing power of the central controller supports complex adaptive trend analysis algorithms. All three are indispensable, together forming a complete technical closed loop from accurate perception to intelligent decision-making.

[0068] 3.4 Example 3: Multi-layered security mechanism design (refer to...) Figure 9 ) To systematically ensure reliability and address traditional concerns about the security of software-defined systems, this system incorporates a three-layer security-in-depth mechanism: (1) Application layer / logic layer security: As described in Example 1, a hardware interlock circuit is used at the driver output stage to prevent logic conflicts and avoid short circuits caused by misoperation.

[0069] (2) System-level self-monitoring: The microprocessor has a built-in hardware watchdog timer and performs self-tests on memory, communication interfaces, etc. on a regular basis. If the self-test fails or the periodic communication heartbeat signal with the central controller times out, the terminal will automatically enter a preset safety state (for example, immediately shut down all drive outputs and enter fault lockout mode).

[0070] (3) Hardware Emergency Layer (Optional Enhancement): The terminal is designed with an independent "emergency pass-through" hard-wired signal input interface. When a high-priority external emergency signal is received from the fire protection system, security system, or other systems, regardless of the terminal's current software logic state, the designated critical channel (such as the emergency lighting circuit) is forcibly activated through physical circuits (such as relays or optocouplers) to ensure the absolute reliability of the emergency function.

[0071] This multi-layered security design demonstrates that, through a systematic security consideration from hardware to software, a software-defined general-purpose hardware system can fully achieve, and even surpass, the determinism and failure security of traditional functionally fixed hardware systems.

[0072] 3.5 Example 4: Simplified Daisy Chain Deployment and Scenario-Based Function Reconstruction like Figure 4 As shown, the programmable controlled terminal is designed as a standard DIN rail module with lateral electrical connectors integrated on both sides of the housing. During deployment, multiple terminals can be connected end-to-end via these connectors in a daisy-chain topology to a single system bus. This bus is typically a multi-core cable that simultaneously transmits DC power and digital communication signals to all connected terminals, greatly simplifying wiring.

[0073] The function configuration instructions may include a Scene Context ID. For example, two logical modes can be configured for a terminal B in a conference room: in a daily office scenario (ID: 0x01), its channel 1 is defined as a regular lighting switch; in a conference presentation scenario (ID: 0x02), the same channel 1 is redefined as a trigger linked to the projector (automatically dimming the lights when the projector is turned on). The central controller only needs to issue a single scene switching instruction to activate the corresponding fixed logic of terminal B, realizing dynamic context switching of device functions.

[0074] 3.6 Example 5: Multi-protocol ecosystem integration and inclusive interaction Multi-protocol adaptation: such as Figure 2 As shown, the central controller integrates a multi-protocol adaptation module, which may include infrared learning / transmitting circuits, Sub-1GHz / 433MHz RF transceiver circuits, Wi-Fi, Bluetooth, and other units. Users can use the learning function to enable the central controller to learn the control codes of traditional non-system devices such as air conditioners, curtain motors, and televisions. In scene orchestration, these heterogeneous devices can be uniformly scheduled.

[0075] Inclusive Interaction: The system natively supports low-cost RF remote controls and other locally connected control devices. Users can bind any button on the remote control to a specific function (or scenario) of any programmable controlled terminal through the central controller's configuration interface. After binding, users do not need smartphones or complex network knowledge; they can achieve reliable control simply by operating the physical remote control, greatly reducing the barrier to entry for smart technology and achieving true technology accessibility.

[0076] 3.7 Example 6: Quantitative Benefit Analysis Model in the Deployment Phase To illustrate the fundamental advantages of this invention during the deployment phase, a simplified topology model is constructed for comparative analysis: Model setup: There is a rectangular area with a power distribution box located at corner point O. There are N load points {P1, P2, ..., Pn} that need to be controlled within the area.

[0077] Traditional star-radial cabling model: Each load point Pi requires a separate set of cables to be laid from point O. The total cabling length L_star ≈ Σ|OPi| (the sum of the lengths of all radial segments).

[0078] This invention presents a daisy-chain bus model: all control terminals are centrally located at point O, and a high-voltage bus connects each load point sequentially. The total wiring length L_chain ≈ the shortest serial path length traversing all Pi points.

[0079] Quantitative Comparison: Geometrically, it can be proven that for any set of points N>2 and not collinearly distributed, L_star is always greater than L_chain. When N is large, L_star is approximately (N / 2) times the size of L_chain. This model mathematically reveals the inherent advantages of the invention's architecture in reducing pipeline materials and construction work.

[0080] Relevance to the claims: This fundamental saving stems directly from the core structural feature described in the claims: "programmable controlled terminals...connected in series in a daisy-chain topology via lateral electrical connectors." This structure transforms N independent "point-to-point" connections into one "serial link," determining a significant difference in material consumption at the topology level and supporting subsequent efficient intelligent operation and maintenance.

[0081] It is understood that the specific deployment and access methods of the "control logic function library" described in this invention (such as fully pre-installed, partially pre-installed combined with remote loading, or completely based on cloud on-demand download, etc.), as well as the specific selection of the "microprocessor" (MCU, FPGA, etc.), can all be implemented in various ways without departing from the core concept of this invention, and should all fall within the protection scope of this invention.

Claims

1. A general-purpose electrical equipment control system based on hardware resource virtualization and software-defined logic, characterized in that, include: Central controller; One system bus; At least one programmable controlled terminal is communicatively connected to the central controller via the system bus; The programmable controlled terminal includes: microprocessor; At least two common drive channels with the same or substantially similar hardware circuit designs are connected to the microprocessor; Non-volatile memory, connected to the microprocessor; A status monitoring circuit, coupled to the general-purpose drive channel and the microprocessor, is used to collect the drive status of the channel and / or the electrical parameters of the load circuit. The central controller is configured to generate function configuration instructions containing logical mode codes and send them to the target programmable controlled terminal via the system bus. The microprocessor of the programmable controlled terminal is configured to: access a control logic function library and, in response to the function configuration instructions, call the corresponding control logic function from the control logic function library or load the corresponding hardware configuration module according to the logic mode code, so as to reconstruct the underlying electrical control logic of the general drive channel at the software or hardware logic level, and solidify the reconstructed logic configuration in the non-volatile memory; and process the output of the status monitoring circuit, generate status feedback data, and send it to the central controller through the system bus. The central controller is also configured to receive and process the status feedback data.

2. The system according to claim 1, characterized in that: The condition monitoring circuit includes a load current detection unit; the central controller is further configured to perform trend analysis on the load current timing information in the historical condition feedback data based on adaptive baseline modeling, and generate predictive maintenance information based on the analysis results.

3. The system according to claim 1, characterized in that: The system supports operation via at least one local direct-connection control device, which includes an RF remote controller, a physical button panel, or a touch panel. The RF remote controller is paired with the RF transceiver unit built into the programmable controlled terminal or the central controller, and can send control commands directly to the designated programmable controlled terminal to trigger its pre-defined logic functions without relying on the centralized scheduling of the central controller.

4. The system according to claim 1, characterized in that: The programmable controlled terminal is a modular device with a housing suitable for installation on a standard electrical rail, and the housing integrates a lateral electrical connector; multiple programmable controlled terminals are connected in series with the system bus in a daisy-chain topology via the lateral electrical connector.

5. The system according to claim 4, characterized in that: The system bus is a multi-core cable configured to simultaneously transmit DC operating power and bidirectional data signals based on a digital communication protocol to all the programmable controlled terminals connected in series.

6. The system according to claim 1, characterized in that: The programmable controlled terminal also includes a standardized hardware expansion interface for connecting functional expansion modules; the microprocessor is further configured to identify and drive the connected functional expansion modules through the expansion interface.

7. The system according to claim 1, characterized in that: The central controller also includes a multi-protocol adaptation module for communicating with external devices that use a different communication protocol than the system bus; the central controller is capable of uniformly arranging and synchronously executing control commands for the external devices and control commands for the programmable controlled terminal.

8. The system according to claim 1 or 7, characterized in that: The microprocessor is further configured to execute hardware interlock logic when at least two general-purpose drive channels are logically associated to prevent the output of simultaneously valid drive signals to loads that are not allowed to be turned on at the same time.

9. The system according to claim 1, characterized in that: The function configuration instructions also include a scene context identifier; the programmable controlled terminal is configured to load and solidify different combinations of control logic functions for the same set of general drive channels under different scene context identifiers, and activate the corresponding solidified logic according to the received scene switching instructions at runtime.

10. The system according to claim 1, characterized in that: The virtual functional devices formed by the reconstruction of the general drive channels after being defined by the function configuration instructions include, but are not limited to, any one or more of the following: single-channel switch, double-control switch, curtain controller, dimmer, socket controller, speed control device, timed task trigger, sequence controller, or scene trigger.

11. A method for hardware function reconfiguration and closed-loop state management of a system as described in any one of claims 1-10, characterized in that, Includes the following steps: The central controller generates and issues function configuration instructions containing logic mode codes to programmable underlying electrical control logic of the general drive channel within the controlled terminal using software definition. The target programmable controlled terminal calls the corresponding function from the accessible control logic function library or loads the corresponding hardware configuration module according to the logic mode code to instantiate the logic, and then stores the instantiated logic in a fixed manner. The programmable controlled terminal acquires status information through a status monitoring circuit and reports feedback data containing the status information to the central controller. The central controller performs status display, fault alarm, or trend analysis based on adaptive baseline modeling based on the feedback data.

12. A programmable controlled terminal device for use in the system as described in any one of claims 1-10, characterized in that, include: case; The microprocessor, non-volatile memory, at least two general-purpose drive channels with the same or substantially similar hardware circuit designs, status monitoring circuit and bus interface circuit are disposed within the housing. The microprocessor is configured to access a control logic function library; The microprocessor is further configured to: receive a function configuration instruction through the bus interface circuit; call a control logic function from the control logic function library or load a hardware configuration module according to the function configuration instruction to reconstruct the control logic of the general drive channel; and generate state feedback data based on the input of the state monitoring circuit and send it through the bus interface circuit.

13. A method for manufacturing a programmable controlled terminal device, characterized in that, include: Provide a housing; The housing contains a microprocessor, non-volatile memory, at least two universal drive channels with identical hardware circuit designs, a status monitoring circuit, and a bus interface circuit. Configure the microprocessor to access a control logic function library containing various categories of low-level electrical control logic functions; The microprocessor is configured to respond to external instructions by calling functions in the function library to reconstruct the logic of the general-purpose driver channel.

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