Efficient resource scheduling method for embedded heterogeneous computing platform

Abstract

The invention belongs to the technical field of electric digital data processing, and particularly relates to an efficient resource scheduling method for an embedded heterogeneous computing platform, which comprises the following steps of: 1, acquiring real-time state information of various computing units in the embedded heterogeneous computing platform, the computing units at least comprising two of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an NPU (Network Processing Unit), a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array); 2, one or more tasks to be scheduled are received, a resource demand descriptor of each task is analyzed, and the resource demand descriptor at least comprises a task type, a calculation intensive level, a data intensive level and expected completion time; and 3, matching a proper calculation unit set for each task to be scheduled. According to the method, the characteristics of any computing task are described in a standardized mode through the resource demand descriptor, and various heterogeneous computing resources including a DSP, an FPGA and the like are managed in a declarative mode; the system is no longer limited to some types of processors or specific tasks.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital data processing, and particularly relates to an efficient resource scheduling method for an embedded heterogeneous computing platform. BACKGROUND

[0002] The embedded heterogeneous computing platform is a special computer system based on the cooperative work of multiple processing units with different architectures, aiming to achieve the optimal balance of performance, power consumption and flexibility by reasonably allocating tasks to various processing cores.

[0003] In the prior art, the scheduling method has obvious speciality and limitation in application scenarios. For example, the publication No. CN120687239A discloses an embedded heterogeneous system speculation decoding dynamic scheduling lightweight method and system. The claim and abstract of the publication clearly indicate that the scheme is designed specifically for the inference efficiency bottleneck problem of large language models under the resource limited condition of embedded devices. The core scheduling logic, including the allocation of speculation decoding tasks to CPU, GPU and NPU, and the model compression of draft models and target models, is closely related to the specific large model inference optimization technology of speculation decoding.

[0004] This highly specialized design results in that the scheduling architecture and strategy cannot be applied to other common computing tasks on the embedded heterogeneous computing platform, such as signal processing, image recognition or automation control. When the task type exceeds the preset large model inference category, the scheduling method will be difficult to take effect due to the lack of general task description and resource abstraction mechanism, thereby greatly limiting its universality and expansibility in diversified embedded application scenarios. SUMMARY

[0005] To solve the above problems in the prior art, the application provides an efficient resource scheduling method for an embedded heterogeneous computing platform, aiming to solve the technical problem that the highly specialized design in the prior art results in that the scheduling architecture and strategy cannot be applied to other common computing tasks on the embedded heterogeneous computing platform.

[0006] To achieve the above purpose, the application provides the following technical scheme: an efficient resource scheduling method for an embedded heterogeneous computing platform, comprising the following steps:

[0007] Step 1: obtaining real-time state information of various computing units in the embedded heterogeneous computing platform, wherein the computing units at least include two of CPU, GPU, NPU, DSP and FPGA;

[0008] Step 2: Receive one or more tasks to be scheduled, and parse the resource requirement descriptor of each task. The resource requirement descriptor includes at least the task type, computational intensity level, data intensity level, and expected completion time.

[0009] Step 3: Based on the real-time status information and the resource requirement descriptor, match a suitable set of computing units for each task to be scheduled;

[0010] Step 4: Based on the matching results, generate resource scheduling instructions and issue them to the corresponding computing units to execute the tasks.

[0011] Furthermore, obtaining the real-time status information of various computing units in the embedded heterogeneous computing platform includes:

[0012] Step 1: Periodically collect the current utilization rate, available memory, power consumption threshold, and current temperature of each computing unit;

[0013] Step 2: Update the collected information to a global resource status table.

[0014] Furthermore, the resource requirement descriptor is defined and parsed through a standardized interface that is independent of the specific computing unit architecture.

[0015] Furthermore, the step of matching a suitable set of computing units for each scheduled task employs a greedy algorithm based on load balancing, prioritizing the allocation of computationally intensive tasks to the GPU or NPU with the lowest current utilization, and allocating data-intensive tasks to DSPs or FPGAs with integrated high-bandwidth memory.

[0016] Furthermore, during the matching process, if multiple computing units meet the resource requirements of the task, the computing unit with the shortest expected task completion time is selected.

[0017] Furthermore, the method also includes:

[0018] Step 1: During task execution, continuously monitor the actual load of each computing unit;

[0019] Step 2: When the actual load of a certain computing unit is detected to be continuously higher than the preset threshold, according to the resource demand descriptor, some of the tasks on it are dynamically migrated to other idle or low-load computing units of the same or different types within the platform.

[0020] Furthermore, the dynamic migration process must ensure that the state of the migrated task is completely saved and restored, and that the migration action is completed within the task's migrateable time window.

[0021] Furthermore, for a task graph consisting of multiple tasks with dependencies, it is first sorted topologically before scheduling, and tasks with tight coupling dependencies are prioritized to be scheduled to homogeneous or heterogeneous computing units with high-speed interconnect channels based on the data flow relationship between tasks.

[0022] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of the method as claimed in any one of claims 1 to 8.

[0023] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method as claimed in any one of claims 1 to 8.

[0024] Compared with the prior art, the beneficial effects of the present invention are:

[0025] 1. In this invention, the characteristics of any computing task are described in a standardized manner using resource requirement descriptors, and various heterogeneous computing resources, including DSPs and FPGAs, are managed declaratively. The system is no longer limited to a few types of processors or specific tasks. When a new computing unit is added to the platform or a new task needs to be run, there is no need to rewrite the scheduling core; integration is achieved simply by defining the corresponding descriptor. Application developers do not need to delve into the complex details of the underlying hardware; they only need to describe the task requirements according to the standard format, and the scheduler will automatically find the best execution resources for it, greatly simplifying the difficulty of parallel programming. This enables complex embedded heterogeneous hardware platforms to quickly adapt to diverse software applications, such as efficiently handling different tasks such as speech recognition, surround-view video processing, and vehicle control simultaneously in a smart cockpit. This design protects hardware investments; when upgrading hardware in the future, existing software can utilize the performance of the new hardware without large-scale modifications.

[0026] 2. In this invention, during task execution, the system continuously senses the system load and can proactively and safely migrate tasks online from one computing unit to another, achieving system-level load balancing and fault avoidance. This effectively prevents localized overheating, performance bottlenecks, or even system crashes caused by continuous high loads on a particular computing unit. When a risk is predicted, the system can proactively migrate tasks to prevent problems before they occur. Through dynamic migration, the peaks and troughs of uneven workloads among different computing units can be smoothed out, enabling all computing units to work collaboratively with high efficiency. This avoids some units being idle while others are overloaded, thus completing more computing tasks with lower overall energy consumption. For scenarios where interruptions are not allowed, such as security monitoring and industrial automation, even if a hardware module experiences performance fluctuations, critical tasks can be seamlessly connected through migration, ensuring business continuity. By balancing the load and avoiding localized hotspots, the pressure on the cooling system can be reduced, fan noise and energy consumption can be decreased, and the long-term reliability of hardware devices can be improved.

[0027] 3. In this invention, data dependencies between tasks are identified before scheduling, and tasks with tight coupling are prioritized for scheduling to physically adjacent or high-speed interconnected computing units based on topology sorting results. Tasks requiring frequent data exchange are grouped together, eliminating the need for lengthy and energy-intensive external bus transmissions, significantly improving data throughput efficiency. This is crucial for processing pipelined video streams or complex sensor fusion algorithms, solving bottlenecks in computation and other data processing. It allows high-performance computing units to operate at full capacity, fully leveraging the inherent parallel computing capabilities of embedded heterogeneous platforms. For latency-sensitive applications such as autonomous driving, reduced communication latency means faster control command generation, directly improving system safety and performance. This ensures the entire processing chain from data input to output is efficient, not just a single fast computing node, ultimately resulting in a smoother overall performance improvement for the user. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0029] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Example 1:

[0032] Please see Figure 1 This embodiment provides the following technical solution, including the following steps: Step 1: Obtain real-time status information of various computing units in the embedded heterogeneous computing platform. The computing units include at least two of the following: CPU, GPU, NPU, DSP, and FPGA; Step 2: Receive one or more tasks to be scheduled and parse the resource requirement descriptor of each task. The resource requirement descriptor includes at least the task type, computational intensity level, data intensity level, and expected completion time; Step 3: Match a suitable set of computing units for each task to be scheduled based on the real-time status information and the resource requirement descriptor; Step 4: Based on the matching results, generate resource scheduling instructions and issue them to the corresponding computing units to execute the tasks.

[0033] Specifically, its core processes include: Resource Status Awareness: Through a monitoring agent deployed at the platform's operating system level, real-time data is collected and aggregated, including but not limited to, CPU core utilization, GPU stream processor utilization and memory usage, NPU computing power utilization, DSP MIPS utilization, FPGA logic unit utilization and remaining reconfigurable area, as well as the shared and dedicated memory reserves, current power consumption, and chip junction temperature of all computing units. Task Requirement Parsing: Upon receiving a task to be scheduled, its accompanying standardized resource requirement descriptor is parsed. This descriptor is a structured data segment that clearly defines the task's attributes, such as: task type, computational intensity level, data intensity level, dependency on specific instruction sets or hardware acceleration units, expected latest completion time, and task data input / output dependencies. Resource Matching Decision: The parsed task requirements are matched against the global resource status table. The matching process first performs resource filtering, excluding units that do not meet the basic hardware requirements of the task, and then filters from the remaining candidate units according to a preset scheduling strategy. Instruction Generation and Execution: Based on the final decision, specific scheduling instructions are generated. This instruction not only includes which computing unit to assign the task to, but may also include the load address of the task binary code, the physical address of the input data in shared memory, the register parameters for configuring a specific accelerator, etc., and is sent to the execution engine of the target computing unit via the system bus or on-chip network.

[0034] By "acquiring real-time status information of various computing units in an embedded heterogeneous computing platform" and "parseing the resource requirement descriptor of each task," and finally "matching a suitable set of computing units for each task to be scheduled," this claim achieves unified management and scheduling of diverse computing resources in an embedded heterogeneous computing platform. Its core advantage lies in greatly improving the versatility and scalability of the scheduling system, enabling it to efficiently handle different types of computing tasks, rather than being limited to a specific algorithm.

[0035] Obtaining real-time status information of various computing units in an embedded heterogeneous computing platform includes: Step 1: Periodically collecting the current utilization rate, available memory, power consumption threshold, and current temperature of each computing unit; Step 2: Updating the collected information to a global resource status table.

[0036] Specifically, the global resource status table is a multidimensional data structure located in kernel space, organized in the form of key-value pairs or relational tables. The monitoring agent updates this table at fixed sampling intervals or through event-triggered updates. The table maintains one record for each physical computing unit, with fields including at least: unit identifier, unit type, timestamp, current average utilization, available memory capacity, current power consumption, instantaneous power consumption, power consumption upper limit threshold, and the current temperature value read from the temperature sensor. This table uses a locking mechanism to ensure data consistency during multi-threaded access.

[0037] By periodically collecting the current utilization rate, available memory, power consumption threshold, and current temperature of each computing unit and updating the collected information to a global resource status table, this claim provides accurate and comprehensive real-time data support for scheduling decisions. Its direct benefit is ensuring that the scheduler can make dynamic and optimized resource allocation decisions based on the latest system status, thereby effectively improving overall resource utilization and energy efficiency.

[0038] Resource requirement descriptors are defined and parsed through a standardized interface that is independent of the specific computing unit architecture.

[0039] Specifically, the standardized interface is a set of predefined application programming interfaces and data structures. Task developers create and populate a `task_desc` structure instance by calling API functions such as `init_task_descriptor()`. This structure uses C language community or extensible markup structures to encapsulate different types of requirement parameters, ensuring that it can clearly express requirements and has the ability to compile and execute across platforms, regardless of whether the underlying architecture is ARM, MIPS, or RISC-V.

[0040] By specifying that "resource requirement descriptors are defined and parsed through a standardized interface, and this interface is independent of the specific computing unit architecture," this claim achieves decoupling between task description and underlying hardware implementation. This significantly reduces the complexity of application development, allowing developers to efficiently utilize heterogeneous resources without needing in-depth knowledge of hardware details, while also enhancing the portability of software across different hardware platforms.

[0041] The step of matching a suitable set of computing units for each scheduled task adopts a greedy algorithm based on load balancing, prioritizing the allocation of computationally intensive tasks to the GPU or NPU with the lowest current utilization, and allocating data-intensive tasks to DSPs or FPGAs with integrated high-bandwidth memory.

[0042] During the matching process, if multiple computing units meet the resource requirements of the task, the computing unit with the shortest expected task completion time is selected.

[0043] Specifically, the greedy algorithm based on load balancing executes as follows: Task Classification: Tasks are initially classified according to the "computation-intensive level" and "data-intensive level" fields in the resource requirement descriptor. For example, a task with a computation-intensive level of "high" and a data-intensive level of "low" is marked as "computation-intensive". Resource Filtering: For "computation-intensive" tasks, all GPUs and NPUs are filtered from the resource status table and sorted from low to high according to their current utilization. For "data-intensive" tasks, DSPs and FPGAs with integrated high-bandwidth memory or efficient DMA engines are filtered. Final Decision: From the set of candidate computing units, a second filtering is performed based on the expected completion time requirement of the task. Specifically, the scheduler estimates the expected execution time of the task on each candidate unit and finally selects the unit that can complete the task earliest. This is the specific implementation of claim 5;

[0044] By employing a greedy algorithm based on load balancing and implementing differentiated allocation strategies for "computation-intensive tasks" and "data-intensive tasks," a reasonable distribution of computing load across available resources was achieved. This avoids bottlenecks imposed by individual computing units and improves the system's concurrent processing capabilities. By selecting the computing unit with the shortest expected task completion time as the final decision criterion, the execution latency of individual tasks is minimized, optimizing the system's real-time response performance.

[0045] The method also includes: Step 1: During task execution, continuously monitor the actual load of each computing unit; Step 2: When it is detected that the actual load of a computing unit is continuously higher than a preset threshold, according to the resource demand descriptor, dynamically migrate some of the tasks on it to other idle or low-load similar or dissimilar computing units within the platform.

[0046] The dynamic migration process must ensure that the state of the migrated task is completely saved and restored, and that the migration action is completed within the task's migrateable time window.

[0047] Specifically, the dynamic migration mechanism is a closed-loop control process: Monitoring and Detection: The background monitoring thread continuously compares the actual load of each computing unit with the preset migration trigger threshold. Migration Decision: Once triggered, the migration manager analyzes all running tasks on the high-load unit, assesses their portability based on their resource requirement descriptors and current system state, and selects one or more tasks with the least impact on overall system performance as migration targets. Safe Migration Execution: Before the migration process begins, necessary resources are reserved on the target computing unit. Then, tasks on the source unit are paused, and the task execution context is completely transferred to the target unit. Afterward, task execution is resumed on the target unit. The entire process must be completed within the "portable time window" defined in the task descriptor. This time window is usually determined based on the task's real-time requirements to ensure that the migration does not cause the task to miss its deadline.

[0048] By continuously monitoring the actual load of each computing unit during task execution and triggering "dynamic migration" when the load is too high, the core advantage of this claim is that it endows the system with the ability to adapt to runtime load fluctuations, thereby ensuring the long-term stability and high reliability of the system under changing loads. By stipulating that the dynamic migration process must "ensure that the state of the migrated task is completely saved and restored" and "complete within the task's migration time window," it ensures the security and seamlessness of task migration operations, avoiding task errors or performance interruptions caused by resource rescheduling.

[0049] For a task graph consisting of multiple tasks with dependencies, it is first sorted topologically before scheduling. Based on the data flow relationship between tasks, tasks with tight coupling dependencies are prioritized for scheduling to homogeneous or heterogeneous computing units with high-speed interconnect channels.

[0050] Specifically, for task graph scheduling: Dependency analysis: Before scheduling, the topology of nodes and edges in the task graph is first analyzed. The Kahn algorithm or depth-first search is used for topology sorting to determine the executable order of all tasks. Cooperative scheduling: For task pairs with direct edge connections after sorting, when allocating computing units, priority is given to placing them on CPU cores within the same chip cluster that communicate via shared cache, or between GPUs directly connected via high-speed interconnects, or on CPU and FPGA hard cores tightly coupled via on-chip buses. The goal is to complete data exchange as much as possible within the chip, avoiding slower and more power-consuming external memory and system buses.

[0051] By "topologically sorting a task graph composed of multiple tasks with dependencies" and "prioritizing the scheduling of tasks with tight coupling dependencies to computing units with high-speed interconnect channels," this claim effectively aggregates communication-intensive tasks onto physically proximate resources. Its direct benefit is a significant reduction in data communication latency and bandwidth consumption between tasks, thereby improving the overall execution efficiency of complex task flows.

[0052] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: when the processor executes the program, it implements the steps of any one of claims 1 to 8.

[0053] A computer-readable storage medium having a computer program stored thereon, characterized in that: when the computer program is executed by a processor, it implements the steps of any one of claims 1 to 8.

[0054] By transforming the method into the form of an "electronic device" and a "computer-readable storage medium," these two claims solidify the innovative advantages of the aforementioned method into concrete physical products and storage carriers. The advantage is that it clarifies that the scope of protection for the invention is not limited to the method itself, but also covers the hardware devices and software products that implement the method, providing more comprehensive legal protection for the exercise of patent rights.

[0055] Example 2:

[0056] Please see Figure 1 In this embodiment, the device disclosed in this invention is specifically implemented in an intelligent driving vehicle computing platform.

[0057] The platform needs to process data from multiple sensors simultaneously and perform key tasks such as environmental perception and planning decisions in real time.

[0058] This embodiment utilizes the NVIDIA Jetson AGX Orin as its core computing platform, integrating ARM architecture CPU and GPU cores, and equipped with the NVIDIA Deep Learning Accelerator (NVDLA). Simultaneously, the system expands via a PCIe interface with a Texas Instruments TDA4VM processor, which includes a Cortex series CPU core, a deep learning matrix multiplication accelerator (MMA), an image signal processor (ISP), and a digital signal processor (DSP). Furthermore, the platform integrates a Xilinx Artix 7 series FPGA for dedicated image preprocessing logic.

[0059] After the system powers on, monitoring agents deployed at the bottom layer of the Ubuntu operating system immediately begin working. These agents collect status information of all computing units at a fixed interval of 10 milliseconds. The monitoring data includes the individual utilization of the twelve CPU cores on the Jetson Orin, the overall utilization of the 512 CUDA cores of the GPU, the computing power utilization of NVDLA, and the real-time usage of the shared 16GB LPDDR5 memory. At the same time, it collects the C66x core utilization of the DSP on the TDA4VM, the throughput of the MMA, and the logic unit utilization and BRAM usage of the FPGA. All data, along with instantaneous power consumption and core temperature read from the chip's built-in sensors, are recorded and updated in the global resource status table.

[0060] A vehicle's front-facing camera captures a 1920x1080 pixel RGB image, which requires processing to identify vehicles and pedestrians. The system first receives a scheduled task called "Object Detection" and parses its resource requirement descriptor. The descriptor indicates that the task is computationally intensive, the task type is deep learning inference, strongly recommends using a neural network accelerator, and requires completion within 30 milliseconds. Based on this descriptor, the scheduler's decision engine immediately lists the TDA4VM's MMA and Jetson Orin's NVDLA as candidate units. A query of the resource status table reveals that the NVDLA is currently performing another perception task with 70% utilization, while the TDA4VM's MMA is currently idle. Based on a load balancing strategy, the scheduler ultimately assigns the detection task for this frame to the TDA4VM's MMA and transfers the image data from the shared memory area to the TDA4VM's dedicated memory via direct memory access.

[0061] Almost simultaneously, a LiDAR point cloud processing task was submitted. Its descriptor identified it as a data-intensive and computationally intensive task. The initial scheduler assigned it to a Jetson Orin GPU. However, during task execution, the monitoring agent detected that GPU utilization was rapidly increasing due to processing complex point cloud data and consistently exceeding the 85% threshold. The system responded immediately, initiating a dynamic migration mechanism. It first reserved computing resources on the TDA4VM's DSP, then paused the point cloud processing task on the GPU, completely transferring its computational context and intermediate state data to the DSP's local memory via the high-speed PCIe bus, and seamlessly resumed task execution on the DSP. The entire migration process was completed within the task's specified 5-millisecond interruptible time window, ensuring real-time performance.

[0062] For tasks with strict dependencies, such as a path planning task that requires the results of object detection and point cloud processing as input, the system will first resolve the task graph dependencies before scheduling. Only after confirming that the detection and point cloud results are ready will the scheduler start the planning task and assign it to the less loaded Jetson Orin CPU core cluster for execution, ensuring that the final control commands can be generated in a timely manner.

[0063] The working principle of this invention is as follows: First, after system initialization, the monitoring agents deployed at the platform's underlying layer are activated. These agents actively collect key status parameters of all computing units at fixed sampling periods or through event triggering.

[0064] The parameters collected include, but are not limited to:

[0065] Computation status: utilization of each CPU core, utilization of GPU stream processors, computing power utilization of NPU / DSP, and utilization of FPGA programmable logic units.

[0066] Memory status: the hit rate and usage of each level of cache, and the remaining capacity of global shared memory and dedicated memory for each unit.

[0067] Physical status: instantaneous power consumption, average power consumption, set upper limit threshold for power consumption of each computing unit, and real-time chip junction temperature read from the temperature sensor.

[0068] All this real-time data is aggregated and updated into a global resource status table located in kernel space. This table, acting as a dynamically updated "resource map," provides the most direct and comprehensive data foundation for scheduling decisions.

[0069] The second step: When a new computing task is submitted to the system, the scheduler does not directly process its binary code, but first parses its accompanying resource requirement descriptor. This is a standardized, structured metadata file, like a task's "resume" or "requirements list," which is predefined by the developers and independent of any specific hardware architecture.

[0070] The key information contained in the descriptor includes:

[0071] Task types: For example, convolution calculation, matrix multiplication, image filtering, fast Fourier transform, etc.

[0072] Resource preference: Identifies whether a task is computationally intensive, data-intensive, or control-intensive.

[0073] Hardware dependency: Whether a specific instruction set or hardware acceleration unit must be used.

[0074] Service quality requirements: The most important is the expected completion time, i.e. the deadline for the task.

[0075] Dependency: Indicates the data input and output dependencies between this task and other tasks, and is used to construct a task relationship graph.

[0076] Through this step, the system abstracts the diverse specific tasks into standardized objects that can be uniformly understood and processed.

[0077] Step 3: The decision engine synchronously reads the global resource status table and the resource requirement descriptor of the current task, and executes a multi-stage matching and decision-making process:

[0078] Resource filtering: First, hard criteria are used for screening. For example, if a task declares that it must use the GPU's double-precision floating-point capabilities, then all computing units that do not have this capability will be immediately excluded.

[0079] Strategy matching: From the remaining candidate resource pool, fine-grained screening is performed according to the system's preset scheduling strategy.

[0080] If a load balancing strategy is adopted, computationally intensive tasks will be preferentially assigned to the GPU or NPU with the lowest current utilization, while data-intensive tasks will be assigned to the DSP or FPGA with high-bandwidth memory.

[0081] If the goal is to achieve optimal performance, the execution time of the task on each candidate unit will be estimated, and the unit that can complete the task earliest will be selected.

[0082] Generate scheduling instructions: After matching is complete, specific, executable scheduling instructions are generated. These instructions not only specify the target computing unit, but may also include the load address of the task code, the physical address of the input data in memory, and the register parameters for configuring the hardware accelerator.

[0083] Step 4: After the task begins execution, the system enters a closed-loop feedback phase. The monitoring system continues to operate, and once a significant change in the system state is detected, it will trigger an adaptive adjustment mechanism.

[0084] Dynamic Task Migration: If the actual load of a computing unit is found to be consistently higher than a preset safety threshold, and it is predicted that a task on that unit may not be able to complete on time, the system will initiate a migration process. It will reserve resources on the target unit, then safely and seamlessly migrate the complete execution state of the task to the new unit and resume execution there. The entire process must be completed within the task's migration window to ensure real-time performance.

[0085] Dependent Task Co-scheduling: For task groups with tight coupling dependencies, the system analyzes their execution order through topological sorting during initial scheduling and prioritizes scheduling task pairs that require frequent communication to physically adjacent or high-speed interconnected computing units, thereby minimizing communication latency.

[0086] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-efficiency resource scheduling method for embedded heterogeneous computing platforms, characterized in that: Includes the following steps: Step 1: Obtain real-time status information of various computing units in the embedded heterogeneous computing platform. The computing units include at least two of the following: CPU, GPU, NPU, DSP, and FPGA. Step 2: Receive one or more tasks to be scheduled, and parse the resource requirement descriptor of each task. The resource requirement descriptor includes at least the task type, computational intensity level, data intensity level, and expected completion time. Step 3: Based on the real-time status information and the resource requirement descriptor, match a suitable set of computing units for each task to be scheduled; Step 4: Based on the matching results, generate resource scheduling instructions and issue them to the corresponding computing units to execute the tasks.

2. The efficient resource scheduling method for embedded heterogeneous computing platforms according to claim 1, characterized in that: The acquisition of real-time status information of various computing units in the embedded heterogeneous computing platform includes: Step 1: Periodically collect the current utilization rate, available memory, power consumption threshold, and current temperature of each computing unit; Step 2: Update the collected information to a global resource status table.

3. The efficient resource scheduling method for embedded heterogeneous computing platforms according to claim 1, characterized in that: The resource requirement descriptor is defined and parsed through a standardized interface that is independent of the specific computing unit architecture.

4. The efficient resource scheduling method for embedded heterogeneous computing platforms according to claim 1, characterized in that: The step of matching a suitable set of computing units for each scheduled task adopts a greedy algorithm based on load balancing, which prioritizes allocating computationally intensive tasks to the GPU or NPU with the lowest current utilization, and allocating data-intensive tasks to DSPs or FPGAs with integrated high-bandwidth memory.

5. The efficient resource scheduling method for embedded heterogeneous computing platforms according to claim 4, characterized in that: During the matching process, if multiple computing units meet the resource requirements of the task, the computing unit with the shortest expected task completion time is selected.

6. The efficient resource scheduling method for embedded heterogeneous computing platforms according to claim 1, characterized in that: The method further includes: Step 1: During task execution, continuously monitor the actual load of each computing unit; Step 2: When the actual load of a certain computing unit is detected to be continuously higher than the preset threshold, according to the resource demand descriptor, some of the tasks on it are dynamically migrated to other idle or low-load computing units of the same or different types within the platform.

7. The efficient resource scheduling method for embedded heterogeneous computing platforms according to claim 6, characterized in that: The dynamic migration process must ensure that the state of the migrated task is completely saved and restored, and that the migration action is completed within the task's migrateable time window.

8. The efficient resource scheduling method for embedded heterogeneous computing platforms according to claim 1, characterized in that: For a task graph consisting of multiple tasks with dependencies, it is first sorted topologically before scheduling. Based on the data flow relationship between tasks, tasks with tight coupling dependencies are prioritized for scheduling to homogeneous or heterogeneous computing units with high-speed interconnect channels.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, it implements the steps of the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 8.

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