Processor power consumption management method and device, equipment and medium

Abstract

The invention discloses a processor power consumption management method and device, equipment and a medium. The method comprises the following steps: acquiring multi-dimensional data of target equipment; determining a scene feature tag according to the multi-dimensional data and a scene recognition model; determining a target regulation and control parameter combination of a processor in the target equipment according to the scene feature tag; and determining a power consumption management strategy of the processor according to the target regulation and control parameter combination. According to the technical scheme, various use scene features are intelligently marked through the scene recognition model, and the core regulation and control parameters of the processor are dynamically adjusted according to the scene, so that intelligent regulation and control of the idle state of the processor are realized, and the purposes of power consumption optimization and performance balance are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a processor power consumption management method, device, equipment and medium. BACKGROUND

[0002] With the popularity of ARM architecture PC, mobile terminal and other devices, users' requirements for device endurance and performance experience are increasing, and CPU power consumption management technology has become a key technology to balance device performance and endurance.

[0003] At present, the CPU idle state management scheme based on CPUIDLE subsystem is one of the current mainstream power consumption management methods, and its core principle is to configure key parameters to decide the CPU core to enter different levels of idle state (C-state), thereby reducing power consumption during the CPU idle period.

[0004] However, the existing CPUIDLE power consumption management scheme gradually exposes significant limitations in actual application process, and it is difficult to meet the performance and power consumption balance requirements in diversified user scenarios. The main limitation is that the existing scheme usually adopts a fixed parameter configuration strategy, and the core parameters are mostly factory defaults or set based on a single hardware load threshold. It cannot realize differentiated idle state management for different scenarios, which is prone to cause high wake-up delay, frame rate stuttering and other problems in high-performance scenarios, and power waste due to the CPU failing to enter deep sleep in time in low-performance scenarios. Therefore, the existing scheme cannot distinguish the performance requirement difference of different scenarios, and can only manage the CPU idle state according to a unified fixed rule, which cannot guarantee the response speed in high-performance scenarios, and misses a lot of energy-saving opportunities in low-performance scenarios, resulting in low overall power consumption management efficiency of the device. SUMMARY

[0005] The present application provides a processor power consumption management method, device, equipment and medium, which intelligently marks various use scenario features through a scene recognition model, and dynamically adjusts processor core control parameters according to the scene, thereby realizing intelligent control of the processor idle state, and achieving the purpose of optimizing power consumption and performance balance.

[0006] According to an aspect of the present application, a processor power consumption management method is provided, comprising: obtaining multi-dimensional data of a target device; determining a scene feature label according to the multi-dimensional data and a scene recognition model; determining a target control parameter combination of a processor in the target device according to the scene feature label; and determining a power consumption management strategy of the processor according to the target control parameter combination.

[0007] Optionally, the multi-dimensional data includes device operation data and user operation data; determining scene feature labels based on the multi-dimensional data and the scene recognition model includes: inputting the device operation data and the user operation data into the scene recognition model, identifying the usage scenario of the target device and marking the corresponding scene feature labels; wherein, the scene feature labels include high-performance scene labels and low-performance scene labels.

[0008] Optionally, determining the target control parameter combination of the processor in the target device based on the scene feature label includes: determining the corresponding state entry time parameter, state exit time parameter, and state dwell time parameter from the parameter mapping table based on the scene feature label; and determining the state entry time parameter, the state exit time parameter, and the state dwell time parameter as the target control parameter combination of the processor in the target device.

[0009] Optionally, it also includes enabling or disabling the processor's target low-power level based on the scene feature label.

[0010] Optionally, determining the power management strategy of the processor based on the target control parameter combination includes: real-time overwriting of the processor's original control parameters based on the target control parameter combination, and determining the low power level corresponding to the processor; and determining the power management strategy of the processor based on the low power level.

[0011] Optionally, after determining the power management strategy of the processor, the method further includes: adjusting the first working mode corresponding to the processor core and the second working mode corresponding to the cluster according to the power management strategy.

[0012] Optionally, the high-performance scene feature tags include at least game scenes, video playback scenes, and download scenes; the low-performance scene feature tags include at least text editing scenes, text browsing scenes, and office scenes.

[0013] According to another aspect of the present invention, a processor power management device is provided, comprising: a data acquisition module for acquiring multi-dimensional data of a target device; a tag determination module for determining scene feature tags based on the multi-dimensional data and a scene recognition model; a parameter determination module for determining a target control parameter combination of the processor in the target device based on the scene feature tags; and a strategy determination module for determining a power management strategy of the processor based on the target control parameter combination.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the processor power management method according to any embodiment of the present invention.

[0015] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to implement the processor power management method according to any embodiment of the present invention when executed.

[0016] The technical solution of this invention involves acquiring multi-dimensional data of a target device; determining scene feature labels based on the multi-dimensional data and a scene recognition model; determining a target control parameter combination for the processor in the target device based on the scene feature labels; and determining a power management strategy for the processor based on the target control parameter combination. This technical solution intelligently labels various usage scenario characteristics through a scene recognition model and dynamically adjusts the processor core control parameters according to the scenario, thereby achieving intelligent control of the processor's idle state to optimize the balance between power consumption and performance.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a processor power management method provided according to Embodiment 1 of the present invention.

[0020] Figure 2 This is a flowchart of a processor power management method provided in Embodiment 2 of the present invention.

[0021] Figure 3 This is a schematic diagram of a processor power management device according to Embodiment 3 of the present invention.

[0022] Figure 4This is a schematic diagram of the structure of an electronic device provided according to Embodiment 4 of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first," "second," "target," and "original," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Example 1

[0026] Figure 1 This is a flowchart of a processor power management method according to Embodiment 1 of the present invention. This embodiment is applicable to intelligent power management of processors in any terminal device based on the ARM architecture. The method can be executed by a processor power management device, which can be implemented in hardware and / or software. This processor power management device can be configured in an electronic device with data processing capabilities. Figure 1 As shown, the method includes:

[0027] S110. Obtain multi-dimensional data of the target device.

[0028] The technical solution in this embodiment can be executed by an adaptive CPU power management system. This system can include a data acquisition module, an AI intelligent decision-making module, a CPUIDLE management module, and a CPU power control module. By integrating AI artificial intelligence recognition technology, it can accurately mark various usage scenarios of the target device and dynamically adjust the CPUIDLE parameters according to the scenario to achieve intelligent control of the CPU's idle state, so as to optimize the balance between power consumption and performance.

[0029] The target device can refer to any computer device or any mobile terminal device based on the ARM architecture. In this embodiment, any computer device based on the ARM architecture can include ARM-based laptops, desktops, industrial PCs, and edge computing nodes. Any mobile terminal device based on the ARM architecture can include, but is not limited to, smartphones, tablets, and smart wearable devices. Multi-dimensional data can refer to the real-time operating data of the target device and the user's operation data on the target device. For example, in this embodiment, multi-dimensional data can include, but is not limited to, operating data such as CPU load and CPU power consumption, as well as user operation frequency.

[0030] In this embodiment, the data acquisition module can be embedded in the device's underlying driver and system core module to collect multi-dimensional data of the target device in real time, thereby obtaining data such as the target device's real-time operating data, memory usage data, and user operation status.

[0031] S120. Determine scene feature labels based on multi-dimensional data and scene recognition models.

[0032] The scene recognition model can be a pre-trained AI scene recognition model used to identify the current usage scenario of the target device. The scene feature label refers to the scene tagging information corresponding to the current usage scenario identified by the scene recognition model. In this embodiment, scene feature labels can be assigned to different usage scenarios. The scene feature labels in this embodiment can be divided into two main categories: high-performance scene labels and low-performance scene labels. It can be understood that the high-performance scene label in this embodiment corresponds to a usage scenario where the target device needs to continuously output high computing power and high resource consumption to meet user needs; this usage scenario can be considered to be in a high-load operating state. The low-performance scene label corresponds to a usage scenario where the target device only needs low computing power and low resource consumption to meet user needs; this usage scenario can be considered to be in a light-load or idle state, prioritizing low power consumption.

[0033] Furthermore, in this embodiment, specific usage scenarios can be included under the high-performance scenario tag and the low-performance scenario tag, respectively. Optionally, the high-performance scenario feature tag can include at least game scenarios, video playback scenarios, and download scenarios; the low-performance scenario feature tag can include at least text editing scenarios, text browsing scenarios, and office scenarios. The text browsing scenario can be a text-based webpage browsing scenario or an e-book reading scenario. The office scenario can be a data entry scenario using office software, such as data entry using Word or Excel. Through this setting, the specific usage scenarios included under the high-performance scenario tag and the low-performance scenario tag can be flexibly labeled according to actual needs.

[0034] In this embodiment, multi-dimensional data collected in real time by the device can be input into a pre-trained AI scene recognition model. The model can output the probability distribution of the current scene, select the scene with the highest probability as the recognition result, and assign the corresponding scene feature label based on the recognition result of the scene recognition model.

[0035] S130. Determine the target control parameter combination of the processor in the target device based on the scene feature labels.

[0036] The target control parameter combination can be a combination of control parameters for the processor CPU to enter or exit a low-power state. In this embodiment, the control parameter combination can also be considered as a CPUIDLE parameter combination. The target control parameter combination in this embodiment can correspond to various scene labels. In this embodiment, various different CPUIDLE parameter combinations can be pre-configured for different scene labels and stored as parameter mapping tables in the scene-policy mapping library. Specifically, the target control parameter combination in this embodiment can include specific values ​​or value ranges of key parameters such as the entry-latency-us delay for entering a low-power state, the exit-latency-us delay for exiting a low-power state, and the min-residency-us time spent in a low-power state. For example, in this embodiment, if it is a high-performance scene label, a larger value can be set for entry-latency-us and exit-latency-us, making it less likely to enter an idle state in a high-performance scene; if it is a low-performance scene label, a smaller value can be set for entry-latency-us and exit-latency-us, making it easier to enter an idle state in a low-performance scene, thereby achieving a significant reduction in power consumption. Understandably, in this embodiment, larger entry-latency-us and exit-latency-us parameters indicate that it is less likely to enter the idle state; conversely, smaller entry-latency-us and exit-latency-us parameters indicate that it is more likely to enter the idle state.

[0037] In this embodiment, before configuring the corresponding target control parameter combination for the scene feature label, specific low-power states (C-states) can be enabled or disabled as needed. Optionally, this embodiment also includes enabling or disabling the processor's target low-power level based on the scene feature label.

[0038] Here, low power level refers to different levels corresponding to the processor in a low power state. In this embodiment, the low power level can be divided into layered idle states, i.e., C-state levels, based on the degree of power reduction and wake-up latency data. In this embodiment, the numerical number of the low power level is positively correlated with energy saving capability and wake-up latency; that is, the larger the low power level number, the lower the power consumption and the longer the wake-up latency. The target low power level can be a specified low power level selected from the different levels corresponding to the low power state. For example, the target low power level can be C1 or C2, or it can be C3 or C6, etc., which can be set according to the corresponding scenario.

[0039] In this embodiment, specific target low-power levels of the processor can be enabled or disabled based on scene feature tags. Specifically, in high-performance scenarios, only low-level low-power states (e.g., C1 / C2) can be enabled, while deeper levels such as C3 / C6 can be disabled. Since deeper levels have high wake-up latency, they can cause stuttering during load fluctuations. Therefore, enabling shallower levels achieves short-term energy saving and rapid wake-up. In low-performance scenarios, higher-level low-power states (e.g., C3 / C6), or even cluster-level power-down states, can be prioritized to ensure that low-performance scenarios have lower response speed requirements, while deeper levels maximize energy saving, and the long dwell time can cover the switching latency cost. Through this setting, specific low-power levels in the processor can be enabled or disabled based on different scene feature tags, thereby achieving a balance between performance response speed and energy-saving benefits.

[0040] For example, in this embodiment, under the high-performance game scene tag, the corresponding target control parameter combination can be entry-latency-us=10us, exit-latency-us=20us and min-residency-us=50us, and only low power state levels C1 or C2 are allowed.

[0041] In this embodiment, the target control parameter combination corresponding to the CPU entering or exiting the low-power state in the target device can be determined from the pre-stored parameter mapping table based on the identified scene feature labels.

[0042] In this embodiment, the CPUIDLE management module is deeply integrated with and enhances the Linux kernel CPUIDLE subsystem. Based on the scene feature labels output by the AI ​​decision module, it determines the corresponding control strategy, i.e., the target control parameter combination, thereby dynamically adjusting key parameters such as entry-latency-us, exit-latency-us, and min-residency-us of each CPU core in real time, or enabling / disabling specific C-state states as needed. This achieves fine-grained management of idle states, adaptive management of different scenarios, and strict compatibility with the original kernel state switching mechanism and stability assurance.

[0043] S140. Determine the processor's power management strategy based on the target control parameter combination.

[0044] In this context, power management strategy refers to a low-power state scheduling and resource control strategy formulated for the processor based on a target combination of control parameters. In this embodiment, the power management strategy refers to corresponding power management measures for the processor cores and clusters within the processor. Specifically, in this embodiment, the power management strategy can configure the corresponding operating modes for each processor core and cluster. This embodiment can determine the corresponding CPUIDLE state based on the target combination of control parameters determined under different scenario feature labels, thereby determining the corresponding low-power level. Then, it can determine the power management strategy for the processor cores (CPU Core) and clusters under this low-power level, and adjust the current operating modes of the processor cores and clusters according to the determined power management strategy.

[0045] The technical solution of this invention involves acquiring multi-dimensional data of the target device; determining scene feature labels based on the multi-dimensional data and a scene recognition model; determining the target control parameter combination of the processor in the target device based on the scene feature labels; and determining the processor's power management strategy based on the target control parameter combination. This technical solution intelligently labels various usage scenario characteristics through a scene recognition model and dynamically adjusts the processor core control parameters according to the scenario, thereby achieving intelligent control of the processor's idle state to optimize the balance between power consumption and performance.

[0046] Example 2

[0047] Figure 2 This is a flowchart of a processor power management method according to Embodiment 2 of the present invention. This embodiment is an optimization based on the above embodiment. Specifically, the optimization involves: determining the target control parameter combination of the processor in the target device based on scene feature tags, including: determining the corresponding state entry time parameter, state exit time parameter, and state dwell time parameter from the parameter mapping table according to the scene feature tags; and determining the state entry time parameter, state exit time parameter, and state dwell time parameter as the target control parameter combination of the processor in the target device. Figure 2 As shown, the method includes:

[0048] S210. Obtain multi-dimensional data of the target device.

[0049] S220. Determine scene feature labels based on multi-dimensional data and scene recognition models.

[0050] In this embodiment, optionally, the multi-dimensional data includes device operation data and user operation data; determining scene feature labels based on multi-dimensional data and scene recognition model includes: inputting device operation data and user operation data into scene recognition model, identifying the usage scenario of the target device and marking the corresponding scene feature labels; wherein, scene feature labels include high-performance scene labels and low-performance scene labels.

[0051] Device operation data can refer to the real-time operating data of the target device. In this embodiment, device operation data may include, but is not limited to, data such as CPU utilization, memory usage, types of running applications, and network connection status. User operation data can refer to user operation behavior data on the target device. In this embodiment, user operation data may include user operation frequency. For example, in this embodiment, the user's operation frequency can be determined by analyzing the number of touchscreen operations and key response frequency per unit time. Furthermore, in this embodiment, user operation data may also include touchscreen click frequency, keyboard input frequency, voice command trigger records, and camera or microphone usage status, etc.

[0052] In this embodiment, device operation data and user operation data can be input into the trained and optimized AI scene recognition model. The model can analyze multi-dimensional data to obtain the characteristics of the currently running application, accurately match the usage scenario of the corresponding target device, and immediately assign a high-performance scene label or a low-performance scene label.

[0053] For example, in this embodiment, the scene recognition model analyzes multi-dimensional data to obtain the characteristics of the currently running application (such as the high frame rate rendering requirements of game applications and the low real-time requirements of document editing software). Combined with data such as the number of touch screen operations and key response frequency of the user per unit time, it identifies that the user is running a shooting game with extremely high image quality requirements and frame rate sensitivity, and quickly marks the scene feature label as a high-performance game scene.

[0054] This embodiment, through such a setting, can analyze the current operating status of the device in real time, accurately match the corresponding scene, and immediately assign scene feature labels, thereby improving the accuracy and timeliness of scene recognition.

[0055] The AI ​​scene recognition model in this embodiment can be integrated into the dedicated hardware accelerator of the target device. For example, the AI ​​scene recognition model can be integrated into the NPU of the target device to efficiently perform inference and training of the scene recognition model. In this embodiment, the AI ​​intelligent decision-making module can analyze the collected data in real time, accurately determine the current user's usage scenario and performance / power consumption requirements, thereby determining the optimal CPUIDLE control strategy and its parameters.

[0056] In this embodiment, the training phase of the AI ​​scene recognition model can utilize massive amounts of historical usage data, covering various typical scenarios (office software usage, online video playback, running large-scale 3D games, and voice calls, etc.), to initially train the model. Specifically, supervised learning algorithms can be used to allow the model to learn data feature patterns under different scenarios. For example, the model can automatically identify key feature combinations of game scenes: continuous high GPU / CPU load, high frame rate requests, dense user input events, and specific graphics API call patterns, and establish a strong mapping relationship between features and scene labels.

[0057] Furthermore, the AI ​​scene recognition model in this embodiment can also support online continuous learning and adaptive optimization. Specifically, during the actual use of the target device, real-time data is continuously collected and fed back to the AI ​​scene recognition model, enabling dynamic updates and optimization of the model. For example, when a user uses a new game for the first time on the target device, its unique resource calling patterns, such as the special algorithm calls of the new game engine and the high-definition texture loading method, can be captured by the model in real time, allowing for timely adjustments to the scene recognition strategy, thereby continuously improving the accuracy and timeliness of scene recognition.

[0058] S230. Determine the corresponding state entry time parameter, state exit time parameter, and state dwell time parameter from the parameter mapping table based on the scene feature labels.

[0059] The parameter mapping table can refer to a pre-defined mapping relationship table between scene feature labels and combinations of control parameters. In this embodiment, the mapping relationships between various scene feature labels and multiple combinations of control parameters can be pre-configured, and the pre-defined mapping relationships can be stored in a database as a data table. In this embodiment, the state entry time parameter is the entry-latency-us parameter, which can refer to the latency time required for the CPU to enter the idle state. The state exit time parameter is the exit-latency-us parameter, which can refer to the latency time required for the CPU to exit the idle state and resume the running state. The state stay time parameter is the min-residency-us parameter, which can refer to the minimum time the CPU is expected to stay in the state, so that the overhead of entering / exiting the state achieves a balance between power saving and cost savings.

[0060] In this embodiment, after obtaining the scene feature labels output by the AI ​​scene recognition model, the parameter adjustment module can quickly retrieve the corresponding state entry time parameters, state exit time parameters, and state dwell time parameters from the parameter mapping table of the mapping database based on the scene feature labels.

[0061] This embodiment pre-sets a rich variety of CPUIDLE parameter combinations, precisely corresponding to various scene labels. For example, taking a high-performance game scene, the parameter mapping table can increase entry-latency-us, exit-latency-us, and min-residency-us. By setting these time parameters for longer periods, it becomes more difficult for the CPU to enter the CPUIDLE state. This ensures that the CPU enters the CPUIDLE state as little as possible in high-performance game scenes, guaranteeing smooth gameplay and performance. For software chat scenes, given that they mainly involve lightweight operations such as text input and occasional image sending, entry-latency-us, exit-latency-us, and min-residency-us are appropriately decreased. By setting these time parameters for shorter periods, the CPU is more likely to enter a deep idle state in software chat scenes, achieving energy saving and power reduction while ensuring basic interactive smoothness.

[0062] S240. The state entry time parameter, state exit time parameter, and state dwell time parameter are determined as the target control parameter combination of the processor in the target device.

[0063] In this embodiment, the state entry time parameter, state exit time parameter, and state dwell time parameter corresponding to the scene feature label retrieved from the parameter mapping table can be determined as the target control parameter combination for the processor in the current target device. It is understood that in this embodiment, control parameters in the target control parameter combination can also be set according to actual needs.

[0064] S250: Determine the processor's power management strategy based on the target control parameter combination.

[0065] In this embodiment, optionally, determining the processor's power management strategy based on the target control parameter combination includes: real-time overlaying the processor's original control parameters based on the target control parameter combination, and determining the processor's corresponding low power level; and determining the processor's power management strategy based on the low power level.

[0066] Here, the original control parameters can refer to the general control parameters in the processor, or they can refer to the various CPUIDLE parameters currently being used by the processor. The low power level can be a low power level determined for the range of each parameter in the currently determined target control parameter combination. In this embodiment, different low power levels can be entered according to different target control parameter combinations, that is, through different target CPUIDLE parameters.

[0067] In this embodiment, after obtaining the scene feature labels output by the AI ​​scene recognition model, the parameter adjustment module quickly retrieves the corresponding control parameters from the mapping database to obtain the corresponding target control parameter combination. The target control parameter combination is then overlaid on the current CPUIDLE parameters of the processor in real time. Based on the data range matching of each CPUIDLE parameter in the target control parameter combination, the range of currently allowed low power consumption levels is locked, thereby determining the low power consumption level of the processor. Based on the different low power consumption levels, the power management strategy for the processor cores and clusters in the processor can be determined.

[0068] In this embodiment, the low power level and the power management strategy of the processor core and cluster can be mutually corresponding, that is, each low power level can correspond to a combination of the respective working modes of the processor core and cluster.

[0069] Furthermore, in this embodiment, different scenarios and CPUIDLE states can be pre-configured for different scenarios and target control parameter combinations determined under different scenario feature labels, and power management strategies for the CPU core and cluster can be configured. For example, in this embodiment, the power management strategy may specifically include configuring the working mode of the CPU core and cluster, which may include Wait For Interrupt (WFI) mode, Retention mode, Power Off mode, etc.

[0070] In this embodiment, the power management strategies of the CPU Core and Cluster can be dynamically adjusted according to the current scenario and CPUIDLE state. For example, in a gaming scenario, to ensure high performance, the CPU Core can be set to WFI mode and the Cluster to Retention mode; in lightweight application scenarios such as software chat, the CPU Core can be set to Retention mode and the Cluster to Power Off mode to achieve maximum energy saving.

[0071] In this embodiment, this setting enables seamless and instantaneous switching of strategies during various usage scenario transitions (such as exiting a game and entering a chat application), ensuring that power management always accurately adapts to the current user activity, eliminating strategy lag, and achieving a dynamic optimal balance between performance and energy efficiency.

[0072] In this embodiment, optionally, after determining the processor's power management strategy, the method further includes: adjusting the first working mode corresponding to the processor core and the second working mode corresponding to the cluster according to the power management strategy.

[0073] The first working mode can be the current working mode corresponding to the processor core. In this embodiment, the first working mode may include working modes such as Wake-up Upon Interrupt (WFI) mode, Retention mode, and Power Off mode. The second working mode can be the current working mode corresponding to the cluster. In this embodiment, the second working mode may include working modes such as Retention mode and Power Off mode.

[0074] In this embodiment, the adjustment of the working mode of the processor core and the cluster can be implemented at the firmware layer. Based on the power management strategy, the underlying power state of the CPU Core and Cluster (such as WFI state, Retention state, Power-Off state, etc.) can be directly configured and adjusted through the hardware abstraction interface, thereby achieving fine-grained and low-latency control of the chip-level power domain.

[0075] In this embodiment, based on the determined power management strategy of the processor, the first working mode corresponding to the processor core and the second working mode corresponding to the cluster are adjusted respectively according to the working mode included in the power management strategy, so that the processor core and the cluster can meet the power state control configured in the current power management strategy.

[0076] The technical solution in this embodiment can adjust CPUIDLE parameters in a targeted manner according to specific scenario characteristics, such as the high frame rate requirements of games and the low load characteristics of chat software, so that CPU idle state management accurately matches the usage scenario; and by leveraging the self-learning capability of the AI ​​model, it can continuously adapt to changes in user habits and new application scenarios. As users explore different types of games and install and use various new applications, the system can adjust the parameter adaptation strategy in real time without manual user intervention or exhaustive search of pre-set scenarios, improving the accuracy of scenario recognition and parameter adaptation. In addition, the technical solution in this embodiment adopts a modular design, with data acquisition, AI processing, and CPUIDLE management units decoupled from each other. When adapting to different Arm PC hardware platforms, only a small amount of driver adaptation adjustment is required for the data acquisition unit, and the AI ​​model and CPUIDLE management logic can be reused; when introducing new AI algorithms or expanding the dimensions of CPUIDLE parameters, only the corresponding modules need to be updated and iterated, without affecting the overall architecture stability.

[0077] The technical solution of this invention involves acquiring multi-dimensional data of the target device; determining scene feature labels based on the multi-dimensional data and a scene recognition model; determining corresponding state entry time parameters, state exit time parameters, and state dwell time parameters from a parameter mapping table based on the scene feature labels; and defining the state entry time parameters, state exit time parameters, and state dwell time parameters as the target control parameter combination for the processor in the target device. A power management strategy for the processor is then determined based on this target control parameter combination. This technical solution intelligently labels various usage scenario characteristics through a scene recognition model and dynamically adjusts the processor core control parameters according to the scenario, thereby achieving intelligent control of the processor's idle state to optimize the balance between power consumption and performance.

[0078] Example 3

[0079] Figure 3 This is a schematic diagram of a processor power management device according to Embodiment 3 of the present invention. Figure 3 As shown, the device includes:

[0080] The data acquisition module 310 is used to acquire multi-dimensional data of the target device.

[0081] The label determination module 320 is used to determine scene feature labels based on multi-dimensional data and scene recognition models.

[0082] The parameter determination module 330 is used to determine the target control parameter combination of the processor in the target device based on the scene feature labels.

[0083] The strategy determination module 340 is used to determine the processor's power management strategy based on the target control parameter combination.

[0084] Optional, multi-dimensional data includes device operation data and user operation data.

[0085] The label determination module 320 is specifically used to: input device operation data and user operation data into the scene recognition model, identify the usage scenario of the target device and mark the corresponding scene feature labels; wherein, the scene feature labels include high-performance scene labels and low-performance scene labels.

[0086] Optionally, the parameter determination module 330 is specifically used to: determine the corresponding state entry time parameter, state exit time parameter, and state dwell time parameter from the parameter mapping table based on the scene feature label; and determine the state entry time parameter, state exit time parameter, and state dwell time parameter as the target control parameter combination of the processor in the target device.

[0087] Optionally, it also includes: a level setting module for enabling or disabling the processor's target low-power level based on scene feature labels.

[0088] Optionally, the strategy determination module 340 is specifically used to: overwrite the processor's original control parameters in real time based on the target control parameter combination, and determine the corresponding low power level of the processor; and determine the processor's power management strategy based on the low power level.

[0089] Optionally, it also includes: a mode adjustment module, used to adjust the first working mode corresponding to the processor core and the second working mode corresponding to the cluster according to the power management strategy after the power management strategy of the processor is determined.

[0090] Optionally, high-performance scene feature tags should include at least game scenes, video playback scenes, and download scenes; low-performance scene feature tags should include at least text editing scenes, text browsing scenes, and office scenes.

[0091] The processor power management device provided in this embodiment of the invention can execute a processor power management method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0092] Example 4

[0093] Figure 4 This is a schematic diagram of an electronic device according to Embodiment 4 of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0094] like Figure 4 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0095] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0096] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as processor power management methods.

[0097] In some embodiments, the processor power management method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the processor power management method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the processor power management method by any other suitable means (e.g., by means of firmware).

[0098] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0099] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0100] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0101] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0102] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0103] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0104] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0105] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A processor power consumption management method, characterized in that, include: Acquire multi-dimensional data of the target device; Determine scene feature labels based on the multi-dimensional data and scene recognition model; The target control parameter combination of the processor in the target device is determined based on the scene feature labels; The power management strategy of the processor is determined based on the target control parameter combination.

2. The method according to claim 1, characterized in that, The multi-dimensional data includes equipment operation data and user operation data; Based on the multi-dimensional data and scene recognition model, scene feature labels are determined, including: The device operation data and the user operation data are input into the scene recognition model to identify the usage scenario of the target device and mark the corresponding scene feature labels; wherein, the scene feature labels include high-performance scene labels and low-performance scene labels.

3. The method according to claim 1, characterized in that, Determining the target control parameter combination of the processor in the target device based on the scene feature labels includes: Based on the scene feature labels, the corresponding state entry time parameter, state exit time parameter, and state dwell time parameter are determined from the parameter mapping table; The state entry time parameter, the state exit time parameter, and the state dwell time parameter are determined as the target control parameter combination for the processor in the target device.

4. The method according to claim 1, characterized in that, Also includes: The target low-power level of the processor is enabled or disabled based on the scene feature tags.

5. The method according to claim 1, characterized in that, The power management strategy of the processor is determined based on the target control parameter combination, including: Based on the target control parameter combination, the original control parameters of the processor are covered in real time, and the low power consumption level corresponding to the processor is determined. The power management strategy of the processor is determined based on the low power level.

6. The method according to claim 5, characterized in that, After determining the power management strategy for the processor, the following is also included: Based on the power management strategy, the first working mode corresponding to the processor core and the second working mode corresponding to the cluster are adjusted respectively.

7. The method according to claim 2, characterized in that, The high-performance scene feature tags include at least game scenes, video playback scenes, and download scenes; the low-performance scene feature tags include at least text editing scenes, text browsing scenes, and office scenes.

8. A processor power management device, characterized in that, include: The data acquisition module is used to acquire multi-dimensional data from the target device; The label determination module is used to determine scene feature labels based on the multi-dimensional data and the scene recognition model; The parameter determination module is used to determine the target control parameter combination of the processor in the target device based on the scene feature labels; The strategy determination module is used to determine the power management strategy of the processor based on the target control parameter combination.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the processor power management method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause the processor to implement the processor power management method according to any one of claims 1-7 when executed.

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