Graphics card performance optimization and promotion method and system based on deep learning

Abstract

The application discloses a graphics card performance optimization and promotion method and system based on deep learning, relates to the technical field of intelligent optimization of graphics cards, and comprises the time sequence data of core computing power utilization rate, video memory bandwidth occupancy rate and core temperature when the graphics card executes a task; the utilization rate and bandwidth data are subjected to pattern recognition and analysis, and a calculation data cooperation mode atlas is generated through space-time alignment and correlation analysis; a pre-trained energy consumption performance decision model is called to deduce the atlas, a candidate scheduling strategy set is generated, and thermal constraint screening is carried out according to a temperature curve, so that an adaptability strategy set is obtained; and a dynamic frequency voltage adjustment instruction sequence is generated according to the set and is executed. The method provides fine-grained basis for optimization by constructing a cooperation atlas, and realizes adaptive dynamic strategy generation by using a deep learning model, so that the overall performance of the graphics card performance and energy efficiency is improved under the premise of meeting the thermal constraint.

Description

Technical Field

[0001] This invention belongs to the field of graphics card intelligent optimization technology, specifically a method and system for optimizing and improving graphics card performance based on deep learning. Background Technology

[0002] Current graphics card performance optimization commonly employs monitoring methods based on single runtime metrics, such as periodically sampling core utilization or memory bandwidth usage. Optimization decisions typically rely on preset static thresholds or simple proportional-integral-derivative control loops. These methods treat computing units and storage control units as independent entities, and their control strategies are essentially reactive rules based on isolated signals, failing to delve into the intrinsic connections and interaction patterns between data processing flows and arithmetic logic flows in computational tasks.

[0003] This technical approach has limitations. Static rules and single-dimensional feedback cannot characterize the complex dependencies between computational load and data throughput over time, resulting in a lack of synergy and predictability in resource scheduling strategies. This often manifests as a difficulty in balancing performance improvement and power consumption control, or an excessive sacrifice of computing power to maintain thermal safety. Furthermore, instantaneous response mechanisms cannot model the long-term effects of sequential scheduling instructions, easily leading to performance fluctuations and energy efficiency imbalances.

[0004] A technology is needed to automatically parse and characterize the "computation-memory access" collaborative behavior pattern from multi-source timing characteristics. A method is needed that, based on this pattern, can autonomously deduce fine-grained scheduling instruction sequences that conform to physical constraints, in order to achieve precise collaborative optimization of graphics card performance and energy efficiency. Summary of the Invention

[0005] This invention aims to solve at least one of the technical problems existing in the prior art;

[0006] To this end, this invention proposes a deep learning-based method for optimizing and improving graphics card performance, including:

[0007] The runtime characteristic data stream of the target graphics card is collected when it performs a specific computing task. The runtime characteristic data stream includes core computing power utilization time-series data, memory bandwidth utilization time-series data, and core temperature change curve.

[0008] The computation intensity pattern is identified by performing computation intensity pattern recognition on the core computing power utilization time series data to obtain multiple computation intensity pattern segments. The data throughput pattern is parsed by performing data throughput pattern analysis on the memory bandwidth utilization time series data to obtain multiple data throughput pattern segments. The computation intensity pattern segments and the data throughput pattern segments are spatiotemporally aligned and pattern correlation analyzed to generate a computation data collaborative pattern map.

[0009] The pre-trained energy consumption performance decision model is invoked to perform resource scheduling strategy deduction on the computing data collaborative pattern map, generating a set of candidate scheduling strategies corresponding to the specific computing task;

[0010] Based on the core temperature change curve, the feasibility of the candidate scheduling strategy set under thermal constraints is screened, and candidate scheduling strategies that violate the preset thermal limit are eliminated to form an adaptive scheduling strategy set.

[0011] A dynamic frequency and voltage adjustment instruction sequence is generated based on the adaptive scheduling strategy set, and the dynamic frequency and voltage adjustment instruction sequence is sent to the driver layer of the target graphics card to perform real-time performance tuning.

[0012] Furthermore, the computational intensity pattern recognition of the core computing power utilization time-series data yields multiple computational intensity pattern segments, including:

[0013] The core computing power utilization time-series data is divided into several equal-length computing power utilization data windows by performing sliding window segmentation.

[0014] Statistical features are extracted for each of the computing power utilization data windows to generate a window statistical feature vector containing mean, variance, and slope;

[0015] A pre-trained computational pattern classifier is invoked to perform pattern discrimination on the statistical feature vector of the window, and a computational intensity pattern label is marked for each computational utilization data window. The computational intensity pattern label includes intensive computational pattern, idle computational pattern, and fluctuating computational pattern.

[0016] The computing power utilization data windows that are continuous and have the same computing intensity mode label are merged to form the computing intensity mode segment.

[0017] Furthermore, the data throughput pattern parsing of the memory bandwidth utilization timing data yields multiple data throughput pattern segments, including:

[0018] Peak and valley detection is performed on the video memory bandwidth utilization time-series data to identify periodic bursts and intervals in data throughput;

[0019] Based on the identified periodic burst points and intermittent points, the original video memory bandwidth utilization time series data is adaptively segmented to form multiple data throughput behavior intervals.

[0020] Within each data throughput behavior interval, the average bandwidth utilization rate, the bandwidth utilization rate rise slope, and the duration of high utilization rate are calculated to form the data throughput behavior feature vector of the data throughput behavior interval.

[0021] The data throughput behavior feature vector is input into a pre-trained throughput pattern clustering model, and a data throughput pattern label is assigned to each data throughput behavior interval. The data throughput pattern label includes a continuous high throughput mode, a burst pulse mode, and a low throughput idle mode.

[0022] Connect the data throughput behavior intervals that have the same data throughput pattern label and are adjacent in time to form the data throughput pattern segment.

[0023] Further, the step of performing spatiotemporal alignment and pattern correlation analysis between the computation intensity pattern fragment and the data throughput pattern fragment to generate a computation data cooperative pattern map includes:

[0024] Establish a unified timeline and map the computation intensity pattern segment and the data throughput pattern segment onto the timeline;

[0025] For each synchronization time point on the time axis, extract the computation intensity mode label and data throughput mode label corresponding to the time point to form a mode pair;

[0026] Statistically analyze the frequency of different pattern pairs at all time points and construct a pattern pair co-occurrence frequency matrix.

[0027] Based on the co-occurrence frequency matrix of the aforementioned patterns, a directed graph network is constructed, where nodes represent different computation intensity patterns or data throughput patterns, and the weights of the edges represent the probability that the two patterns occur consecutively in time.

[0028] The directed graph network and the start and end time information of each pattern segment on the time axis are jointly encapsulated into the computational data collaborative pattern graph.

[0029] Furthermore, the step of invoking a pre-trained energy consumption performance decision model to perform resource scheduling strategy deduction on the computational data collaborative pattern map, generating a set of candidate scheduling strategies corresponding to the specific computational task, including:

[0030] The candidate scheduling strategy set includes suggestions for computing power allocation and memory access for different combinations of computing intensity mode segments and data throughput mode segments;

[0031] The computational data collaborative pattern graph is input into the pattern encoder of the energy consumption performance decision model to transform the node and edge relationships in the graph into high-dimensional feature vectors.

[0032] The high-dimensional feature vector is input into the strategy generation network of the energy consumption performance decision model. The strategy generation network generates a series of potential mode transition paths by simulating the impact of different resource allocations on mode transitions in the collaborative mode map of the computing data.

[0033] For each potential mode transition path, the strategy generation network deduces the sequence of computing power allocation adjustment actions and the sequence of memory access optimization actions required to realize the mode transition path.

[0034] The computing power allocation adjustment action sequence is combined with the memory access optimization action sequence and encapsulated into a complete resource scheduling strategy. The resource scheduling strategies corresponding to all potential mode transition paths constitute the candidate scheduling strategy set.

[0035] Furthermore, the feasibility screening of the candidate scheduling strategy set under thermal constraints based on the core temperature change curve, eliminating candidate scheduling strategies that violate preset thermal limits, and forming an adaptive scheduling strategy set includes:

[0036] Extract the current temperature baseline and the slope of the temperature rise trend from the core temperature change curve;

[0037] For each resource scheduling policy in the candidate scheduling policy set, simulate the execution of the computing power allocation adjustment action sequence suggested by the resource scheduling policy, and estimate the resulting increase in chip power consumption.

[0038] Based on the estimated chip power consumption increment, the current temperature baseline, and the upward trend slope, the core temperature change trajectory after executing the resource scheduling strategy is predicted using a thermal simulation model.

[0039] Determine whether the predicted core temperature change trajectory exceeds the preset hard temperature limit or soft temperature warning line at any point in time;

[0040] All resource scheduling strategies that do not exceed any temperature limit based on predicted temperature trajectories are retained to form the adaptive scheduling strategy set.

[0041] Furthermore, the process of constructing and predicting the thermal simulation model includes:

[0042] A simplified thermal resistance network model of the target graphics card's core, memory, and heat dissipation components is established.

[0043] The estimated chip power consumption increment is used as a heat source input into the simplified thermal resistance network model;

[0044] The current temperature baseline is used as the initial temperature state of the simplified thermal resistance network model;

[0045] The ambient temperature and heat dissipation conditions reflected in the core temperature change curve are used as boundary conditions input.

[0046] The simplified thermal resistance network model is run to calculate the dynamic changes of the core temperature nodes over a future period of time, generating a predicted temperature change trajectory.

[0047] Further, the step of generating a dynamic frequency voltage adjustment command sequence based on the adaptive scheduling strategy set includes:

[0048] From the set of adaptive scheduling strategies, select the resource scheduling strategy with the largest estimated performance improvement within the preset evaluation period as the target execution strategy;

[0049] The sequence of computing power allocation adjustment actions in the target execution strategy is analyzed and converted into specific GPU core frequency adjustment values, voltage adjustment values, and timing points.

[0050] The memory access optimization action sequence in the target execution strategy is analyzed and converted into specific memory controller frequency adjustment values, memory timing adjustment values, and timing points.

[0051] All frequency adjustment values, voltage adjustment values, timing adjustment values, and their corresponding execution timing points are arranged and encoded in chronological order to generate the dynamic frequency and voltage adjustment instruction sequence.

[0052] Furthermore, the step of sending the dynamic frequency voltage adjustment instruction sequence to the driver layer of the target graphics card to perform real-time performance tuning includes:

[0053] The dynamic frequency voltage adjustment instruction sequence is loaded into the policy execution queue of the target graphics card driver layer;

[0054] The monitoring thread in the driver layer compares the current system time with the execution timing points in the dynamic frequency voltage adjustment instruction sequence in real time.

[0055] When the preset execution timing point is reached, the control thread of the driver layer calls the underlying hardware interface and sets the graphics card hardware parameters according to the frequency adjustment value, voltage adjustment value, and timing adjustment value in the instruction;

[0056] During the optimization process, new runtime feature data streams are continuously collected to initiate a new round of optimization cycles.

[0057] Furthermore, the present invention also includes a deep learning-based graphics card performance optimization and improvement system, the system including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the computer program, it implements the steps of the deep learning-based graphics card performance optimization and improvement method described above.

[0058] Compared with the prior art, the beneficial effects of the present invention are:

[0059] By performing computational intensity pattern recognition on time-series data of core computing power utilization and data throughput pattern analysis on time-series data of GPU memory bandwidth utilization, and then performing spatiotemporal alignment and correlation analysis on the identified pattern fragments, a structured map revealing the interaction patterns between "computation and data" within the computing task can be constructed. This process goes beyond isolated monitoring metrics, achieving deep modeling of the task's micro-behavior. It can accurately locate computationally intensive phases, data bottleneck phases, and moments of collaboration or mismatch between the two, providing a fine-grained and semantically rich blueprint of task behavior that is not available in traditional methods for subsequent optimization.

[0060] This approach utilizes a deep learning model pre-trained on a large amount of historical runtime data to perform end-to-end policy deduction on the generated computational data collaborative pattern map. This model implicitly learns the complex, non-linear mapping relationships between performance, power consumption, and multi-dimensional scheduling parameters, thereby directly outputting a set of optimized candidate scheduling strategies based on the feature map of the current task. This method replaces decision-making methods that rely on manual rules and formulas, automatically adapting to the unique patterns of different tasks, achieving a shift from "rule-driven" to "data and model-driven," and generating scheduling schemes that better fit the actual needs of the task and possess a global perspective. Attached Figure Description

[0061] Figure 1 This is a flowchart illustrating the steps of the deep learning-based graphics card performance optimization and improvement method described in this invention.

[0062] Figure 2 A flowchart for calculating intensity pattern recognition;

[0063] Figure 3 A flowchart for generating a computational data collaborative pattern map;

[0064] Figure 4 A dynamic comparison of the chip power consumption increments and stacked area diagrams for each candidate scheduling strategy during the thermal constraint screening phase.

[0065] Figure 5 The heatmap is associated with the data throughput pattern. Detailed Implementation

[0066] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0067] See Figure 1The system collects runtime characteristic data streams of the target graphics card when performing specific computing tasks. These data streams include core computing power utilization time-series data, memory bandwidth utilization time-series data, and core temperature variation curves. It performs computational intensity pattern recognition on the core computing power utilization time-series data to obtain multiple computational intensity pattern segments, and analyzes the data throughput pattern of the memory bandwidth utilization time-series data to obtain multiple data throughput pattern segments. The system then performs spatiotemporal alignment and pattern correlation analysis between the computational intensity pattern segments and the data throughput pattern segments to generate a computational data collaborative pattern map. A pre-trained energy consumption performance decision model is invoked to deduce resource scheduling strategies from the computational data collaborative pattern map, generating a set of candidate scheduling strategies corresponding to specific computing tasks. Based on the core temperature variation curves, the feasibility of the candidate scheduling strategies under thermal constraints is screened, eliminating those that violate preset thermal limits, forming a set of adaptive scheduling strategies. Finally, a dynamic frequency and voltage adjustment instruction sequence is generated based on the adaptive scheduling strategy set and sent to the driver layer of the target graphics card for real-time performance tuning.

[0068] See Figure 2In one embodiment of the present invention, when the target graphics card performs a graphics rendering task, the system collects a continuous time-series data of core computing power utilization. The core computing power utilization time-series data is a percentage sequence that changes over time, representing the workload of the graphics card's computing cores. A sliding window segmentation is performed on the core computing power utilization time-series data, for example, using a fixed-length window of 100 milliseconds, sliding in 10-millisecond steps to obtain a series of overlapping computing power utilization data windows. Statistical feature extraction is performed on each computing power utilization data window. For a given window, the feature extraction calculates the average of all utilization values ​​within it to reflect the overall load level, calculates the variance to characterize the degree of load fluctuation, and calculates the linear regression slope of the utilization to capture the trend of load changes. These three values ​​together constitute the window statistical feature vector of the window. Subsequently, the window statistical feature vector is fed into a pre-trained computing pattern classifier. In a specific implementation, the computing pattern classifier can be a multi-classification model based on support vector machines, whose function is to receive the window statistical feature vector and output a classification result. The computational pattern classifier labels each computational intensity pattern for each computational utilization data window with a computational intensity pattern label based on the numerical characteristics of the window's statistical feature vector. These labels include "intensive computational pattern," "idle computational pattern," and "fluctuating computational pattern." Intensive computational patterns correspond to high mean, low variance, and a gentle slope; idle computational patterns correspond to low mean and low variance; and fluctuating computational patterns correspond to high variance or a large absolute value of the slope. After labeling, the system scans the computational intensity pattern labels for all computational utilization data windows, merging windows that are temporally continuous and have the same label, ultimately forming one or more computational intensity pattern segments. Each segment represents a time interval with stable computational behavior characteristics.

[0069] In practical implementation, the system synchronously collects time-series data on video memory bandwidth utilization within the same time period. This data represents the busy level of data transmission on the video memory interface. Peak and valley detection is performed on the video memory bandwidth utilization time-series data; the algorithm locates all local maxima and minima in the sequence, corresponding to periodic bursts and intervals in data throughput. Based on the identified periodic bursts and intervals, the system segments the original video memory bandwidth utilization time-series data adaptively between adjacent bursts and intervals, forming multiple data throughput behavior intervals with relatively consistent behavior. Within each data throughput behavior interval, the system calculates three key indicators: the arithmetic mean of all bandwidth utilization rates within the interval, yielding the average bandwidth utilization rate; the rate of change of utilization rate from the start of the interval to the first peak point, yielding the bandwidth utilization rate rise slope; and the cumulative time during which the bandwidth utilization rate remains above a set threshold (e.g., 80%), yielding the high utilization rate duration. These three indicators constitute the data throughput behavior feature vector for that data throughput behavior interval. Understandably, data throughput behavior feature vectors are input into a pre-trained throughput pattern clustering model, such as a model based on the K-means algorithm. The throughput pattern clustering model assigns a data throughput pattern label to each data throughput behavior interval based on the spatial distribution of the data throughput behavior feature vectors. Data throughput pattern labels include "sustained high throughput pattern," "burst pulse pattern," and "low throughput idle pattern." Sustained high throughput patterns are characterized by high average occupancy and long high occupancy durations; burst pulse patterns are characterized by high rise slopes and short high occupancy durations; and low throughput idle patterns are characterized by low average occupancy. After label assignment, the system connects temporally adjacent data throughput behavior intervals with the same data throughput pattern label, ultimately forming one or more data throughput pattern segments.

[0070] See Figure 3 In one embodiment of the present invention, after identifying computational intensity mode segments and data throughput mode segments from the runtime feature data stream of a graphics rendering task, the system first establishes a unified high-precision timeline that covers the start and end times of all analyzed segments. In a specific implementation, the computational intensity mode segments and data throughput mode segments are mapped onto the unified timeline. The mapping process involves accurately placing each computational intensity mode segment and data throughput mode segment into the corresponding interval of the timeline based on its actual start and end timestamps. Since the start and end times of the computational intensity mode segments and data throughput mode segments may not be perfectly aligned, after mapping, any point on the timeline is covered by at least one computational intensity mode segment and one data throughput mode segment.

[0071] For each synchronized time point on a unified time axis, for example, traversing the time axis at a fixed sampling interval, the system extracts the computational intensity pattern label carried by the computational intensity pattern segment to which the current time point belongs, and extracts the data throughput pattern label carried by the data throughput pattern segment to which the current time point belongs. These two labels together constitute a pattern pair. For example, at a certain time point, the computational intensity pattern label is "intensive computational mode" and the data throughput pattern label is "sustained high throughput mode," then the recorded pattern pair is (intensive computational mode, sustained high throughput mode). The system traverses all synchronized time points and counts the number of times each different pattern pair appears on the entire time axis. It can be understood that the system constructs a pattern pair co-occurrence frequency matrix based on these statistical data. The row index of the matrix represents different computational intensity pattern labels, the column index of the matrix represents different data throughput pattern labels, and the value in the matrix cell represents the frequency or number of times the corresponding pattern pair appears on the unified time axis. In some embodiments, the frequency can be normalized to the proportion of the total number of sampling points.

[0072] Based on the co-occurrence frequency matrix of pattern pairs, the system further constructs a directed graph network. In a specific implementation, nodes in the directed graph network represent all unique computational intensity pattern labels and data throughput pattern labels that have appeared. Edges in the directed graph network connect two nodes, and the direction indicates the temporal order of the patterns. The weight of an edge is defined as the probability of transitioning from a previous pattern (source node pattern) to a subsequent pattern (target node pattern). The calculation of this probability depends on the continuous co-occurrence relationship of the patterns in the time series. In some embodiments, the transition probability from the composite state consisting of computational intensity pattern A and data throughput pattern B to the composite state consisting of computational intensity pattern C and data throughput pattern D is calculated, but a more general construction approach is to consider the sequential relationship of the computational intensity pattern or the data throughput pattern itself on the time axis. Optionally, the weight for transitioning from any pattern label X (which can be either a computational intensity pattern or a data throughput pattern) to another pattern label Y can be calculated. The formula can be expressed as:

[0073] in: This represents the number of times pattern X appears in a sequence preceding pattern Y within a unified timeline. This represents the total number of times pattern X appears in adjacent time intervals before any other pattern (including itself). In the formula... and Representing different pattern tags, It is a summation index, representing all possible target patterns. The construction of directed graph networks reveals the dynamic evolution of different computation and data access patterns over time.

[0074] Finally, the system encapsulates the completed directed graph network, along with the start and end times of each original computation intensity pattern fragment and data throughput pattern fragment on a unified time axis, into a computation-data co-occurrence pattern graph. This computation-data co-occurrence pattern graph can be understood as a structured data object that contains both the static correlation strength between computation and data patterns (implied through the co-occurrence frequency matrix) and their dynamic transition relationships (represented through the directed graph network), while also preserving the original temporal position information of all pattern fragments.

[0075] In one embodiment of the present invention, the candidate scheduling strategy set includes computing power allocation suggestions and memory access suggestions for combinations of different computing intensity mode segments and data throughput mode segments. The computing power allocation suggestions involve the adjustment planning of the clock frequency and operating voltage of the GPU streaming multiprocessor cluster, and the memory access suggestions involve the adjustment planning of the memory controller frequency and memory access timing parameters. The system inputs the computing data collaborative pattern graph into the pattern encoder of the energy consumption performance decision model. The pattern encoder is a graph neural network structure whose function is to read the node information, edge relationships between nodes, and edge weights in the computing data collaborative pattern graph. Through multi-layer message passing and aggregation operations, it transforms the topological structure and semantic information of the entire graph into a fixed-dimensional high-dimensional feature vector. This high-dimensional feature vector is a dense numerical representation of the graph.

[0076] The policy generation network (PRN) of the energy consumption performance decision model inputs high-dimensional feature vectors. In some embodiments, the PRF can be constructed based on the actor-critic framework in deep reinforcement learning. The PRF generates a series of potential mode transition paths by simulating the impact of different resource allocations on mode transitions in the computational data collaborative mode graph. The simulation process is carried out in a state space derived from the graph, defined by a combination of the current computational intensity mode and data throughput mode. The PRF evaluates the next most likely mode state the system will migrate to after taking different resource allocation actions starting from the current mode state, thus forming multiple possible state sequences starting from the current state and spanning several future time steps. These state sequences are the potential mode transition paths. For each potential mode transition path, the PRF needs to deduce the sequence of computational power allocation adjustment actions and memory access optimization actions required to realize the mode transition. This can be understood as a reverse derivation process. The policy generation network outputs a series of specific and ordered hardware parameter adjustment instructions based on the conditions required for each state transition step in the target mode transition path. These instructions constitute a sequence of computing power allocation adjustment actions and a sequence of memory access optimization actions. For example, one action in the action sequence could be "to increase the core frequency by Δf and the voltage by Δv at time t".

[0077] Optionally, when the policy generation network infers the action sequence, it evaluates the long-term value of each action. In one embodiment, a value function can be used. To assist in decision-making:

[0078]

[0079] in: This represents the current system state, jointly defined by the computational intensity mode and the data throughput mode. Represents the current state The resource allocation actions taken below This represents an immediate reward, i.e., the execution of an action. The estimated immediate performance or energy efficiency gains obtained afterward Represents the execution of actions The next state after transitioning to Represents the state The following actions are available. It is a discount factor between 0 and 1, used to weigh the importance of current rewards against future rewards. Indicates the next state The maximum expected cumulative reward can be obtained from all possible actions. This value assessment process helps the policy generation network select action sequences that not only achieve short-term mode transitions but also lead to better long-term performance states. The action sequences for adjusting computing power allocation and optimizing memory access are combined and encapsulated. Each complete action sequence corresponds to a specific operational plan for achieving a particular mode transition path. These operational plans are encapsulated into complete resource scheduling strategies. All resource scheduling strategies derived from the current state, corresponding to different potential mode transition paths, together constitute a candidate scheduling strategy set.

[0080] In one embodiment of the present invention, the system extracts two key parameters from the real-time monitored core temperature change curve: one is the real-time temperature value of the graphics card core at the current moment, which serves as the current temperature baseline; the other is the rate of change of the core temperature within a recent time window, obtained by linear fitting to determine the slope of the temperature's upward trend. In specific implementation, for each resource scheduling strategy in the candidate scheduling strategy set, the system simulates the execution of the computing power allocation adjustment action sequence suggested by the resource scheduling strategy. The simulation process, based on each adjustment instruction in the action sequence (e.g., increasing core frequency or voltage), queries a preset power lookup table to estimate the chip power consumption increment after executing this series of adjustments, compared to the current baseline power consumption. The chip power consumption increment is a time-varying estimated value sequence.

[0081] Based on the estimated chip power consumption increment, the current temperature baseline, and the slope of the upward trend, the system predicts the core temperature change trajectory after implementing the resource scheduling strategy using a thermal simulation model. The thermal simulation model can be understood as a simplified dynamic thermal model, whose construction process includes establishing a simplified thermal resistance network model of the target graphics card's core, memory, and heat dissipation components. The simplified thermal resistance network model abstracts the main heat-generating components and heat dissipation paths of the graphics card into nodes and thermal resistances. For example, the core is considered as a heat source node, and the heatsink as a heat dissipation node, connected by a thermal resistance. The indirect impact of memory heat generation on the core temperature is also considered. The estimated chip power consumption increment is input to the simplified thermal resistance network model as a heat source, and this power consumption increment is applied to the heat source node representing the core. The current temperature baseline is used as the initial temperature state of the simplified thermal resistance network model, meaning the initial temperature of all nodes is known. The ambient temperature and heat dissipation condition information reflected in the core temperature change curve are used as boundary condition inputs. For example, based on the relationship between the recent core temperature change curve and the ambient temperature sensor, the equivalent heat dissipation coefficient of the cooling fan is derived. The simplified thermal resistance network model is run. Based on the input heat source, initial state and boundary conditions, the model calculates the dynamic changes of the core temperature node over a period of time and generates a predicted temperature change trajectory, which is a time-temperature sequence.

[0082] The system determines whether the predicted core temperature change trajectory exceeds a preset hard temperature limit or soft temperature warning line at any point in time. The hard temperature limit is a safety protection threshold for the graphics card hardware, which cannot be exceeded. The soft temperature warning line is an optimized target temperature set for long-term stability. All resource scheduling strategies whose predicted temperature trajectories do not exceed any temperature limit are retained, forming an adaptive scheduling strategy set. In specific implementations, the prediction calculation of the thermal simulation model is based on a discretized thermal balance equation. In some embodiments, for core temperature nodes, their temperature changes can be iteratively calculated using the following difference equation:

[0083] in: Indicates the first The predicted core temperature at each discrete time step. This represents the predicted core temperature for the next time step. It is the time step of discrete computation. It is the heat capacity parameter from the core to the environment. It is in the The total power consumption input at each time step is the baseline power consumption plus the estimated chip power consumption increment. The ambient temperature is used as a boundary condition. This is the total thermal resistance parameter from the core to the environment. The formula describes how the core temperature changes with power consumption, ambient temperature, and heat dissipation conditions. Refer to Table 1, which shows a simplified example of the thermal constraint screening process. Table 1 compares the key results of three different candidate resource scheduling strategies after being predicted by the thermal simulation model.

[0084] Table 1: Candidate Scheduling Strategy Hot Constraint Screening Table

[0085] Resource scheduling strategy number Estimated performance improvement Predicted peak core temperature Does it exceed the hard temperature limit? Does it exceed the soft temperature warning line? Filtering results (whether to include in the fit set) Strategy A high 82°C no yes no Strategy B middle 78°C no no yes Strategy C Low 85°C yes yes no

[0086] Optional, parameters of the thermal simulation model (such as...) , The temperature can be obtained by performing offline thermal characteristic tests on the graphics card and fitting the data using a system identification method. Running a simplified thermal resistance network model involves iteratively solving the above difference equations, starting from the initial moment and gradually calculating the temperature value at each future time step until the complete cycle of the resource scheduling strategy is covered, thus obtaining a complete predicted temperature change trajectory.

[0087] See Figure 4 The graph, with time steps (minutes) on the horizontal axis and chip power consumption increment (W) on the vertical axis, visually compares the dynamic power consumption performance of strategies A, B, and C: Strategy C consistently exhibits the highest power consumption increment, peaking at over 40W, and shows a significant upward trend in the 0-40 minute range, reflecting the largest adjustment range in computing power allocation and corresponding to a high estimated performance improvement, but also bringing the most severe thermal load risk; Strategy A's power consumption increment curve lies between Strategy C and Strategy B, with a peak of approximately 30W, showing an overall trend of first rising and then fluctuating downwards, reflecting the dynamic adaptability of its computing power adjustment; Strategy B shows the most gradual power consumption increment, peaking at approximately 18W, and exhibiting a continuous downward trend in the later stages, indicating that its resource scheduling strategy is more inclined towards a conservative configuration prioritizing thermal safety.

[0088] In one embodiment of the present invention, the system evaluates the performance gains of each resource scheduling strategy in the adaptive scheduling strategy set, assessing the estimated impact of hardware parameter adjustments suggested by the resource scheduling strategy on the execution efficiency of a specific computing task. From the adaptive scheduling strategy set, the system selects the resource scheduling strategy with the largest estimated performance improvement within a preset evaluation period as the target execution strategy. The preset evaluation period is a fixed time window in the future used to measure the immediate effect of the strategy. In some embodiments, the estimated performance improvement can be achieved through an evaluation function. Perform the calculation:

[0089]

[0090] in: This represents a sequence of differences between the planned GPU core frequency adjustment value and the current base frequency in the resource scheduling strategy. This represents a sequence of differences between the planned adjustment value of the memory controller frequency and the current reference frequency. This indicates that the differences between all adjustments made within the evaluation period are accumulated. This represents the difference between the core voltage adjustment value and the current reference voltage. and These are the weighting coefficients corresponding to the performance impact of core frequency and memory frequency increases, respectively. It is a penalty coefficient that weighs the impact of the additional power consumption caused by the voltage increase on the net performance gain, and is chosen to make the evaluation function... The resource scheduling strategy with the highest value is selected as the target execution strategy.

[0091] The system parses the computational power allocation adjustment action sequence in the target execution strategy. This sequence consists of a series of instructions with timestamps and parameter values. The system converts these instructions into specific GPU core frequency adjustment values, voltage adjustment values, and timing points that can be recognized by the graphics card hardware registers. The timing points indicate the absolute time of each adjustment action or its offset time relative to the start of the optimization cycle. Similarly, the system parses the memory access optimization action sequence in the target execution strategy, converting these actions into specific memory controller frequency adjustment values, memory timing adjustment values, and timing points. All frequency adjustment values, voltage adjustment values, timing adjustment values, and their corresponding execution timing points are arranged and encoded in chronological order. The encoding format must ensure that the driver layer can unambiguously parse the encoded sequence. The resulting sequence is the dynamic frequency and voltage adjustment instruction sequence, which is a structured instruction list.

[0092] The process of sending a dynamic frequency and voltage adjustment instruction sequence to the target graphics card's driver layer for real-time performance tuning involves the system loading the sequence into a policy execution queue maintained in memory by the driver layer via inter-process communication or system calls. The driver layer's monitoring thread runs at a high frequency, comparing the current system time with each execution timing point in the dynamic frequency and voltage adjustment instruction sequence in real time. When the current system time reaches or exceeds a preset execution timing point in the sequence, the driver layer's control thread is triggered. This thread calls the underlying hardware interface to set the graphics card hardware parameters according to the frequency, voltage, and timing adjustment values ​​encoded in the instruction corresponding to the current timing point. During tuning, the system continuously collects new runtime characteristic data streams, including new core computing power utilization timing data, memory bandwidth utilization timing data, and core temperature change curves, to initiate a new optimization cycle. Optionally, the execution of the dynamic frequency and voltage adjustment instruction sequence is atomic; each instruction's setting operation must be completed within the shortest time interval allowed by the graphics card driver to avoid hardware state conflicts.

[0093] See Figure 5 Specifically, the matrix's row dimension represents the three identified computation intensity patterns (intensive computation, idle computation, and fluctuating computation), and the column dimension represents the three analyzed data throughput patterns (sustained high throughput, burst pulse, and low throughput idle). The values ​​within the matrix represent the co-occurrence frequency of the corresponding pattern pairs, and the color band on the right is a visual mapping of the pattern correlation, with colors ranging from dark blue to dark red corresponding to correlations from 0 to 1. From the matrix values, it is clear that: intensive computation has the highest correlation with the sustained high throughput pattern (0.85), indicating a high match between computational power requirements and memory bandwidth requirements in this scenario; idle computation has the highest correlation with the low throughput idle pattern (0.80), reflecting a strong correspondence between low computational load and low data throughput; fluctuating computation has the highest correlation with the burst pulse pattern (0.50), and also shows some correlation with the sustained high throughput pattern (0.40), reflecting the dynamic fluctuation characteristics of its computational power requirements and data throughput. The correlation matrix provides a key basis for the co-occurrence of patterns in the subsequent energy consumption performance decision model for resource scheduling strategy deduction, and can directly support the precise adjustment of hardware parameters for different computing-throughput mode combinations.

[0094] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. A method for optimizing and improving graphics card performance based on deep learning, characterized in that, include: The runtime characteristic data stream of the target graphics card is collected when it performs a specific computing task. The runtime characteristic data stream includes core computing power utilization time-series data, memory bandwidth utilization time-series data, and core temperature change curve. The computation intensity pattern is identified by performing computation intensity pattern recognition on the core computing power utilization time series data to obtain multiple computation intensity pattern segments. The data throughput pattern is parsed by performing data throughput pattern analysis on the memory bandwidth utilization time series data to obtain multiple data throughput pattern segments. The computation intensity pattern segments and the data throughput pattern segments are spatiotemporally aligned and pattern correlation analyzed to generate a computation data collaborative pattern map. The pre-trained energy consumption performance decision model is invoked to perform resource scheduling strategy deduction on the computing data collaborative pattern map, generating a set of candidate scheduling strategies corresponding to the specific computing task; Based on the core temperature change curve, the feasibility of the candidate scheduling strategy set under thermal constraints is screened, and candidate scheduling strategies that violate the preset thermal limit are eliminated to form an adaptive scheduling strategy set. A dynamic frequency and voltage adjustment instruction sequence is generated based on the adaptive scheduling strategy set, and the dynamic frequency and voltage adjustment instruction sequence is sent to the driver layer of the target graphics card to perform real-time performance tuning. The step of performing spatiotemporal alignment and pattern correlation analysis between the computation intensity pattern fragment and the data throughput pattern fragment to generate a computational data collaborative pattern map includes: Establish a unified timeline and map the computation intensity pattern segment and the data throughput pattern segment onto the timeline; For each synchronization time point on the time axis, extract the computation intensity mode label and data throughput mode label corresponding to the time point to form a mode pair; Statistically analyze the frequency of different pattern pairs at all time points and construct a pattern pair co-occurrence frequency matrix. Based on the co-occurrence frequency matrix of the aforementioned patterns, a directed graph network is constructed, where nodes represent different computation intensity patterns or data throughput patterns, and the weights of the edges represent the probability that the two patterns occur consecutively in time. The directed graph network and the start and end time information of each pattern segment on the time axis are jointly encapsulated into the computational data collaborative pattern graph.

2. The method for optimizing and improving graphics card performance based on deep learning according to claim 1, characterized in that, The process of performing computational intensity pattern recognition on the time-series data of the core computing power utilization rate yields multiple computational intensity pattern segments, including: The core computing power utilization time-series data is divided into several equal-length computing power utilization data windows by performing sliding window segmentation. Statistical features are extracted for each of the computing power utilization data windows to generate a window statistical feature vector containing mean, variance, and slope; A pre-trained computational pattern classifier is invoked to perform pattern discrimination on the statistical feature vector of the window, and a computational intensity pattern label is marked for each computational utilization data window. The computational intensity pattern label includes intensive computational pattern, idle computational pattern, and fluctuating computational pattern. The computing power utilization data windows that are continuous and have the same computing intensity mode label are merged to form the computing intensity mode segment.

3. The method for optimizing and improving graphics card performance based on deep learning according to claim 2, characterized in that, The data throughput pattern is parsed from the timing data of the video memory bandwidth utilization rate to obtain multiple data throughput pattern segments, including: Peak and valley detection is performed on the video memory bandwidth utilization time-series data to identify periodic bursts and intervals in data throughput; Based on the identified periodic burst points and intermittent points, the original video memory bandwidth utilization time series data is adaptively segmented to form multiple data throughput behavior intervals. Within each data throughput behavior interval, the average bandwidth utilization rate, the bandwidth utilization rate rise slope, and the duration of high utilization rate are calculated to form the data throughput behavior feature vector of the data throughput behavior interval. The data throughput behavior feature vector is input into a pre-trained throughput pattern clustering model, and a data throughput pattern label is assigned to each data throughput behavior interval. The data throughput pattern label includes a continuous high throughput mode, a burst pulse mode, and a low throughput idle mode. Connect the data throughput behavior intervals that have the same data throughput pattern label and are adjacent in time to form the data throughput pattern segment.

4. The method for optimizing and improving graphics card performance based on deep learning according to claim 3, characterized in that, The process involves invoking a pre-trained energy consumption performance decision model to perform resource scheduling strategy deduction on the computational data collaborative pattern map, generating a set of candidate scheduling strategies corresponding to the specific computational task, including: The candidate scheduling strategy set includes suggestions for computing power allocation and memory access for different combinations of computing intensity mode segments and data throughput mode segments; The computational data collaborative pattern graph is input into the pattern encoder of the energy consumption performance decision model to transform the node and edge relationships in the graph into high-dimensional feature vectors. The high-dimensional feature vector is input into the strategy generation network of the energy consumption performance decision model. The strategy generation network generates a series of potential mode transition paths by simulating the impact of different resource allocations on mode transitions in the collaborative mode map of the computing data. For each potential mode transition path, the strategy generation network deduces the sequence of computing power allocation adjustment actions and the sequence of memory access optimization actions required to realize the mode transition path. The computing power allocation adjustment action sequence is combined with the memory access optimization action sequence and encapsulated into a complete resource scheduling strategy. The resource scheduling strategies corresponding to all potential mode transition paths constitute the candidate scheduling strategy set.

5. The method for optimizing and improving graphics card performance based on deep learning according to claim 4, characterized in that, The feasibility screening of the candidate scheduling strategy set under thermal constraints based on the core temperature change curve is performed, eliminating candidate scheduling strategies that violate preset thermal limits, and forming an adaptive scheduling strategy set, including: Extract the current temperature baseline and the slope of the temperature rise trend from the core temperature change curve; For each resource scheduling policy in the candidate scheduling policy set, simulate the execution of the computing power allocation adjustment action sequence suggested by the resource scheduling policy, and estimate the resulting increase in chip power consumption. Based on the estimated chip power consumption increment, the current temperature baseline, and the upward trend slope, the core temperature change trajectory after executing the resource scheduling strategy is predicted using a thermal simulation model. Determine whether the predicted core temperature change trajectory exceeds the preset hard temperature limit or soft temperature warning line at any point in time; All resource scheduling strategies that do not exceed any temperature limit based on predicted temperature trajectories are retained to form the adaptive scheduling strategy set.

6. The method for optimizing and improving graphics card performance based on deep learning according to claim 5, characterized in that, The process of constructing and predicting the thermal simulation model includes: A simplified thermal resistance network model of the target graphics card's core, memory, and heat dissipation components is established. The estimated chip power consumption increment is used as a heat source input into the simplified thermal resistance network model; The current temperature baseline is used as the initial temperature state of the simplified thermal resistance network model; The ambient temperature and heat dissipation conditions reflected in the core temperature change curve are used as boundary conditions input. The simplified thermal resistance network model is run to calculate the dynamic changes of the core temperature nodes over a future period of time, generating a predicted temperature change trajectory.

7. The method for optimizing and improving graphics card performance based on deep learning according to claim 6, characterized in that, The step of generating a dynamic frequency and voltage adjustment command sequence based on the adaptive scheduling strategy set includes: From the set of adaptive scheduling strategies, select the resource scheduling strategy with the largest estimated performance improvement within the preset evaluation period as the target execution strategy; The sequence of computing power allocation adjustment actions in the target execution strategy is analyzed and converted into specific GPU core frequency adjustment values, voltage adjustment values, and timing points. The memory access optimization action sequence in the target execution strategy is analyzed and converted into specific memory controller frequency adjustment values, memory timing adjustment values, and timing points. All frequency adjustment values, voltage adjustment values, timing adjustment values, and their corresponding execution timing points are arranged and encoded in chronological order to generate the dynamic frequency and voltage adjustment instruction sequence.

8. The method for optimizing and improving graphics card performance based on deep learning according to claim 7, characterized in that, The step of sending the dynamic frequency voltage adjustment instruction sequence to the driver layer of the target graphics card to perform real-time performance tuning includes: The dynamic frequency voltage adjustment instruction sequence is loaded into the policy execution queue of the target graphics card driver layer; The monitoring thread in the driver layer compares the current system time with the execution timing points in the dynamic frequency voltage adjustment instruction sequence in real time. When the preset execution timing point is reached, the control thread of the driver layer calls the underlying hardware interface and sets the graphics card hardware parameters according to the frequency adjustment value, voltage adjustment value, and timing adjustment value in the instruction; During the optimization process, new runtime feature data streams are continuously collected to initiate a new round of optimization cycles.

9. A deep learning-based graphics card performance optimization and improvement system, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the deep learning-based graphics card performance optimization and improvement method as described in any one of claims 1 to 8.

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