On-chip clock controller for design for testability and optimization method thereof

Abstract

The application discloses an on-chip clock controller for testability design and an optimization method thereof, based on the thought that there is no timing relationship between asynchronous logics and timing checking is not needed, a selector inside an OCC circuit is fixed to select a high-speed clock output path, a front-end selector is added in front of each OCC circuit, and a path selection signal of the front-end selector is used to select a high-speed function clock signal or a low-speed test clock signal, so that the low-speed test clock signal enters the OCC circuit and is output through the high-speed clock output path of the internal selector, so that the clocks output by different OCCs maintain an asynchronous clock domain relationship, so that cross-domain timing checking between different clock domains is not triggered, time consumption of timing convergence iteration performed at the back end due to the cross-domain timing checking is saved, and the overall development cycle of the chip is shortened.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit verification design technology, specifically, it relates to an on-chip clock controller for design for testability and its optimization method. Background Technology

[0002] During the manufacturing process, including packaging, chips may develop physical defects, necessitating functional testing of the finished chips. Design for Test (DFT) is a technology specifically introduced to improve chip testability and reduce testing costs. By integrating various test circuits within the chip, such as Scan Chain, Built-In Self-Test (BIST), and Boundary Scan, it can significantly reduce testing costs and time, allowing for more efficient and comprehensive chip testing and quickly identifying chips with manufacturing defects.

[0003] The on-chip clock controller (OCC) is the core circuit in the scan-chain structure used to manage the test clock. Its function is to switch the clock between test mode and functional mode, and to precisely control the test clock to complete stuck-at and at-speed tests, while avoiding the high-speed clock bottleneck of ATE (Automatic Test Equipment). Stuck-at tests are used to test whether the logic function of the gate circuit is abnormal, requiring only slow_clk (a low-speed clock input from outside the chip, usually 10-50MHz). At-speed tests are used to test whether the chip's operating frequency can reach the expected requirements (for example, an abnormal input-to-output delay time of an AND gate causes it to not reach the expected main frequency), requiring the OCC circuit to generate fast_clk (a high-frequency operating clock in functional mode) and slow_clk in a timely manner to drive the circuit.

[0004] In multi-clock domain designs, to increase test coverage for each clock domain, multiple OCC circuits are needed to precisely control each clock. One OCC corresponds to one clock domain, and this is automatically generated by EDA (Electronic Design Automation) tools (such as Synopsys' DFT compiler) using scripts to set parameters. When multiple asynchronous clock domains exist, due to the limited number of available control terminals on the chip, multiple OCC circuits sharing a single control terminal leads to the following drawbacks of the default OCC circuit: Figure 1As shown, the control logic between the two OCCs, OCC_1 and OCC_2, is asynchronous. When the path selection signal Occ_bypass=1, the selectors of both OCC_1 and OCC_2 select the low-speed clock Slow_clk path data, and the output clock_1 and clock_2 are both low-speed ate_clock. However, since Slow_clk in the OCC circuit is synchronously driven, this causes the originally asynchronous logic Domain#1 (clock domain #1) and Domain#2 (clock domain #2) to become synchronous logic. This requires timing checks on the path between the two OCCs and iterative timing convergence in the backend. Timing checks and timing convergence iterations consume a lot of time and extend the project cycle, which also reduces test coverage to some extent. Summary of the Invention

[0005] This invention proposes an on-chip clock controller and its optimization method for design for testability. Based on the idea that there is no timing relationship between asynchronous logic and no need for timing checks, the internal selector of the OCC (Optical Clock Control) is fixed to select the high-speed clock output path. A front-end selector is added to the front end of each OCC, and its path selection signal selects either a high-speed functional clock signal or a low-speed test clock signal. This ensures that the low-speed test clock signal enters the OCC and is output through the high-speed clock output path of its internal selector, thus maintaining asynchronous logic. This avoids timing checks between different modules, saves time on back-end timing convergence, and shortens the project cycle.

[0006] The present invention is implemented using the following technical solutions:

[0007] An on-chip clock controller for design-for-testability is proposed, comprising:

[0008] Multiple standard on-chip clock controllers are provided. Each standard on-chip clock controller includes an internal selector and a clock gating unit. High-speed clock signals and low-speed clock signals are connected to the high-speed clock input and low-speed clock input of the clock gating unit, respectively. The output of the clock gating unit is connected to the input of the internal selector. Each standard on-chip clock controller is configured in multiple asynchronous clock domains.

[0009] The front-end selector is configured at the front end of each standard on-chip clock controller. Its first input receives a high-speed function clock signal, its second input receives a low-speed test clock signal, its selection terminal receives a path selection signal, and its output terminal is connected to the high-speed clock input terminal of the standard on-chip clock controller.

[0010] In this case, the selection terminal of the internal selector of each standard on-chip clock controller is configured to always select the high-speed clock output path.

[0011] In one embodiment of the present invention, the selection terminal of the internal selector of each standard on-chip clock controller is fixedly connected to a logic low level so that it always selects the high-speed clock output path.

[0012] An optimization method for on-chip clock controllers in design-for-testability is proposed, including:

[0013] S1: Using the DFT tool with the gate-level netlist as input, insert at least two asynchronous clock domains into the standard on-chip clock controller to obtain the netlist after the scan chain is inserted;

[0014] S2: Optimize the generated standard on-chip clock controller using a script, including: configuring the selection terminal of the internal selector of the standard on-chip clock controller to always select the high-speed clock output path; and adding a front-end selector to the front end of the standard on-chip clock controller, configuring its high-level terminal to receive the high-speed function clock signal, its low-level terminal to receive the low-speed test clock signal, its selection terminal to receive the path selection signal, and its output terminal to connect to the high-speed clock input terminal of the standard on-chip clock controller.

[0015] S3: Generate a gate-level netlist containing the scan chain and the optimized on-chip clock controller, and perform placement and routing and static timing analysis in conjunction with the timing constraint file to obtain a timing-converged netlist file;

[0016] S4: Use the ATPG tool to generate test vectors from the netlist file, and set up a simulation environment to perform simulation verification of the netlist and test vectors.

[0017] Compared with the prior art, the advantages and positive effects of the present invention are as follows: The on-chip clock controller and its optimization method for design for testability proposed in this invention are based on the idea that there is no timing relationship between asynchronous logic and no need for timing checks. The internal selector of the OCC circuit is fixed to select the high-speed clock output path, and a front-end selector is added at the front end of each OCC circuit. The path selection signal of the front-end selector selects the input high-speed functional clock signal or low-speed test clock signal. After the low-speed test clock signal enters the OCC circuit, it is output through the high-speed clock output path of its internal selector. This maintains the asynchronous clock domain relationship between the clocks output by different OCCs, so as not to trigger cross-domain timing checks between different clock domains. This saves the time consumed by the timing convergence iteration in the back end due to cross-domain timing checks, and shortens the overall chip development cycle.

[0018] Furthermore, the design of this invention only adjusts the configuration of the internal selector of the existing standard OCC, without changing the circuit structure of the standard OCC, and retains the core functions of OCC such as clock gating and pulse control, without affecting the existing testing functions.

[0019] Furthermore, the design scheme of this invention can be implemented on a gate-level netlist using simple EDA tool scripts, without the need to redesign the RTL code, thus having little impact on the overall design process and being easy to integrate into existing DFT design processes.

[0020] Other features and advantages of the present invention will become clearer after reading the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. Attached Figure Description

[0021] Figure 1 The circuit structure of an existing on-chip clock controller;

[0022] Figure 2 The circuit structure of the on-chip clock controller for design-for-testability proposed in this invention is shown below.

[0023] Figure 3 This is a schematic diagram of the on-chip clock controller optimization method for design-for-testability proposed in this invention. Detailed Implementation

[0024] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0025] This invention aims to propose an improved on-chip clock controller (OCC) for multi-asynchronous clock domain design. It ensures that, in at-speed test mode, different asynchronous clock domains maintain asynchronous characteristics regardless of whether a high-speed or low-speed clock signal is selected for output. In other words, the low-speed clock signal is made asynchronous even when it is synchronous, thereby eliminating timing checks between different modules caused by selecting low-speed clock output and improving the efficiency of back-end design.

[0026] Specifically, such as Figure 2 As shown, the improved OCC circuit of this invention includes:

[0027] At least two on-chip standard clock controllers (OCCs) (OCC1 and OCC2 in the diagram) are included. Each standard OCC includes an internal selector MUX and a clock gating unit (including high-speed clock gating and low-speed clock gating). The high-speed clock signal Fast_clk and the low-speed clock signal Slow_clk are connected to the high-speed clock input and the low-speed clock input of the clock gating unit, respectively. The output of the clock gating unit is connected to the input of the internal selector MUX (wherein, the output of the high-speed clock gating is connected to the high-level terminal of the internal selector MUX, and the output of the low-speed clock gating is connected to the low-level terminal of the internal selector MUX). The selection terminal Occ_bypass of the internal selector MUX is configured to always select the high-speed clock output path.

[0028] The front-end selectors (MUX1 and MUX2 in the diagram) are configured at the front end of each standard OCC. Their first input receives the high-speed function clock signal PLL, their second input receives the low-speed test clock signal Ate_clk, their selection end receives the path selection signal OCC_bypass, and their output is connected to the high-speed clock input of the standard OCC.

[0029] Based on the modified OCC circuit of this invention, when the path selection signal OCC_bypass selects the input low-speed test clock signal Ate_clk (OCC_bypass=1 in the figure), the front-end selector outputs the low-speed test clock signal Ate_clk to the low-speed clock input terminal of the corresponding standard OCC. Since the internal selector of the standard OCC is configured to always select the high-speed clock output path (Occ_bypass=0), the low-speed test clock signal Ate_clk is output through the high-speed clock output path of the internal selector MUX. When the path selection signal OCC_bypass selects the input high-speed function clock signal PLL (OCC_bypass=0), the front-end selector outputs the high-speed function clock signal PLL to the high-speed clock input terminal of the corresponding standard OCC. Since the internal selector MUX of the standard OCC is configured to always select the high-speed clock output path (Occ_bypass=0), the high-speed function clock signal PLL is output through the high-speed clock output path of the internal selector MUX.

[0030] The OCC circuit modified by the present invention, by forcing the internal selector of the standard OCC to select the high-speed clock output path, combined with the design of the pre-selector, ensures that regardless of whether the path selection signal OCC_bypass selects the input high-speed function clock signal PLL or the input low-speed test clock signal Ate_ckl, both are output through the high-speed clock output path of the internal selector of the standard OCC. Since the high-speed clock outputs of the standard OCC are asynchronous, the low-speed test clock signal Slow_clk can also become asynchronous, thereby solving the technical problem pointed out by the present invention.

[0031] Under the design of this invention, although the low-speed clock signals output by OCCs in different clock domains are physically from the same source (both originating from the low-speed test clock signal Ate_clk), after passing through their respective independent high-speed clock output paths, they are, for timing analysis tools, "high-speed clock signals" generated by different OCCs, maintaining their original asynchronous clock domain relationship, thus not triggering cross-domain timing checks.

[0032] In this invention, the selection function of the Occ_bypass terminal of the front-end selector is replaced by the selection function of the Occ_bypass terminal of the standard OCC internal selector MUX. The low-speed test clock signal Ate_clk can be directly connected to the low-speed clock input terminal of the standard OCC internal selector MUX without affecting the core logic.

[0033] This invention also proposes a method for optimizing the on-chip clock controller in the Design for Testability (DFT) of integrated circuits, which is described below with specific embodiments.

[0034] This embodiment uses Synopsys' DC synthesis tool, DFT tool, and ATPG (Automatic Test Pattern Generation) tool to complete the full-process DFT design of a SoC, including test vector generation and simulation.

[0035] Specifically, such as Figure 3 As shown, it includes the following steps:

[0036] S1: Using the DFT tool with the gate-level netlist as input, insert the standard on-chip clock controller for at least two clock domains to obtain the netlist after inserting the scan chain.

[0037] During the RTL design phase, a hardware description language is used to complete the entire SoC code design, analyze the clock network of the entire chip, divide the clock domains, and write timing constraint files. The code is manually modified to insert OCC buffers, facilitating the generation of standard OCC circuits at the target locations in the circuit via scripts during the insertion of scan chains after logic synthesis.

[0038] During the logic synthesis phase, the synthesis environment is prepared, such as the target technology library file and the simulation IP file. The timing constraint file is loaded, and then logic synthesis is performed, which involves translation, transformation, and mapping, that is, synthesizing the RTL code into a gate-level netlist.

[0039] During the scan chain insertion stage, the DFT tool takes the obtained gate-level netlist file as input, sets the parameters related to scan insertion through the script, and generates standard OCC circuits. According to the design requirements, multiple standard OCC circuits need to be set and inserted for multiple clock domains, thus obtaining the netlist after the scan chain is inserted.

[0040] S2: Optimize the generated standard on-chip clock controller using a script, including: configuring the selection terminal of the internal selector of the standard on-chip clock controller to always select the high-speed clock output path; and adding a front-end selector to the front end of the standard on-chip clock controller, configuring its high-level terminal to receive the high-speed function clock signal, its low-level terminal to receive the low-speed test clock signal, its selection terminal to receive the path selection signal, and its output terminal to connect to the high-speed clock input terminal of the standard on-chip clock controller.

[0041] S3: Generate a gate-level netlist containing the scan chain and the optimized on-chip clock controller. Combine this with the timing constraint file to perform placement and routing and static timing analysis, and obtain a timing-converged netlist file.

[0042] After S1 completes the scan chain insertion and S2 optimizes the on-chip clock controller, the gate-level netlist, along with the timing constraint file, is submitted to the backend for placement and routing and static timing analysis. Timing convergence is then completed to obtain the final netlist file.

[0043] S4: Use the ATPG tool to generate test vectors from the netlist file, and set up a simulation environment to perform simulation verification of the netlist and test vectors.

[0044] When generating test vectors, calculate the test coverage.

[0045] The present invention addresses a common defect introduced by the standard DFT process through a clever and low-cost circuit structure adjustment, improving the efficiency and quality of the design process. It has significant practical value and wide applicability, and is especially suitable for the design of complex SoC chips with multiple clock domains and high performance.

[0046] It should be noted that the above description is not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. An on-chip clock controller for design-to-testability, comprising: Multiple standard on-chip clock controllers are provided. Each standard on-chip clock controller includes an internal selector and a clock gating unit. High-speed clock signals and low-speed clock signals are connected to the high-speed clock input and low-speed clock input of the clock gating unit, respectively. The output of the clock gating unit is connected to the input of the internal selector. Each standard on-chip clock controller is configured in multiple asynchronous clock domains. Its characteristic is that it further includes: The front-end selector is configured at the front end of each standard on-chip clock controller. Its first input receives a high-speed function clock signal, its second input receives a low-speed test clock signal, its selection terminal receives a path selection signal, and its output terminal is connected to the high-speed clock input terminal of the standard on-chip clock controller. In this system, the selection terminal of the internal selector of each standard on-chip clock controller is configured to always select the high-speed clock output path; the high-speed clock outputs of the standard on-chip clock controllers are asynchronous, making the low-speed test clock signal asynchronous.

2. The on-chip clock controller for design-for-testability according to claim 1, characterized in that, The selector pin of the internal selector of each standard on-chip clock controller is fixed to a logic low level so that it always selects the high-speed clock output path.

3. An optimization method for an on-chip clock controller for design-for-testability, characterized in that, include: S1: Using the DFT tool with the gate-level netlist as input, insert at least two asynchronous clock domains into the standard on-chip clock controller to obtain the netlist after the scan chain is inserted; S2: Optimize the generated standard on-chip clock controller using a script, including: configuring the selection terminal of the internal selector of the standard on-chip clock controller to always select the high-speed clock output path; and adding a front-end selector to the front end of the standard on-chip clock controller, configuring its high-level terminal to receive the high-speed function clock signal, its low-level terminal to receive the low-speed test clock signal, its selection terminal to receive the path selection signal, and its output terminal to connect to the high-speed clock input terminal of the standard on-chip clock controller; the high-speed clock outputs of the standard on-chip clock controller are asynchronous, making the low-speed test clock signal asynchronous as well; S3: Generate a gate-level netlist containing the scan chain and the optimized on-chip clock controller, and perform placement and routing and static timing analysis in conjunction with the timing constraint file to obtain a timing-converged netlist file; S4: Use the ATPG tool to generate test vectors from the netlist file, and set up a simulation environment to perform simulation verification of the netlist and test vectors.

Images