Partition-based multi-thread clock tree construction method

By adopting a partition-based multi-threaded clock tree construction method, the problems of high computational complexity and poor balance of traditional multi-threaded clock tree synthesis algorithms at the nanoscale are solved, and fast and efficient clock tree construction and optimization are achieved.

CN121706720APending Publication Date: 2026-03-20HUAXIN GIANTS (HANGZHOU) MICROELECTRONICS CO LTD
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Patent Information

Application Number
CN202511915136.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-12-18
Publication Date
2026-03-20

AI Technical Summary

Technical Problem

Traditional single-threaded clock tree synthesis algorithms suffer from exponentially increasing computational complexity at the nanoscale, while multi-threaded methods suffer from data imbalance and difficulty in achieving global balance through local optimization, leading to clock tree failure to converge properly.

Method used

A partition-based multi-threaded clock tree construction method is adopted. By dividing the clock tree by module, location and load quantity, the load distribution is optimized by K-Means location clustering algorithm, and local and global adaptation is performed at different stages, including buffer insertion, clock tree balancing and power consumption optimization.

Benefits of technology

Fast clock tree construction was achieved, all indicators met the target, and a greater speedup was obtained, while maintaining good consistency with single-threaded results.

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Abstract

The invention discloses a partition-based multi-thread clock tree construction method, and belongs to the field of integrated circuits. Dividing according to the modules, the positions and the number of loads; executing the insertion of a buffer, and dividing the clock tree into an upper part and a lower part; wherein the upper sub-tree is from a root node of the clock tree to a newly inserted buffer, and the lower sub-tree is from the newly inserted buffer to a real clock tree load; the division is used as multiple threads, a buffer is used as a root node of a lower sub-tree, and the multiple threads are established to respectively process construction and balance of the tree; and processing the upper sub-tree, taking the next level of the buffer as a temporary load of the upper sub-tree so as to optimize the buffer of the upper sub-tree, and adding the maximum delay of the sub-tree corresponding to the root node of the clock tree in the current upper sub-tree to the delay of the buffer. According to the multi-thread method, the higher speed-up ratio is obtained, and meanwhile good consistency with a single-thread result is maintained.
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Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for constructing a multi-threaded clock tree based on partitioning. Background Technology

[0002] In VLSI design, clock tree synthesis, as a crucial link connecting physical layout and signal routing, directly determines chip timing convergence, power efficiency, and signal integrity. As process nodes evolve to the nanometer scale, clock networks need to drive millions of synchronization units, posing an exponential challenge to traditional single-threaded clock tree synthesis algorithms in terms of computational complexity. To address this, multi-threaded parallelization techniques have been introduced into clock tree construction, significantly improving synthesis efficiency through task decomposition and concurrent processing.

[0003] The core idea of ​​the multi-threaded clock tree is to employ a "divide and conquer" strategy, dividing the clock network topology during the initialization phase. Based on physical location clustering or hierarchical clock structures, the global clock tree is decoupled into multiple independent or weakly correlated sub-regions. Each sub-region can perform operations such as load balancing, buffer insertion, and latency optimization in parallel, achieving efficient utilization of computing resources through multi-threaded scheduling. This parallel architecture is particularly suitable for heterogeneous multi-core processor platforms, fully leveraging the parallel computing capabilities of modern computing devices.

[0004] From the perspective of optimization objectives, multi-threaded clock tree synthesis needs to collaboratively handle multiple constraints: design rule violations, reduction of maximum clock path latency, power consumption reduction, and balancing clock skew. Each optimization stage implements thread-level pipelined processing through a task queue mechanism, while employing lock-independent data structures and atomic operations to ensure multi-threaded safety.

[0005] Traditional multithreaded methods for clock trees may employ modular partitioning or subgraph partitioning. However, these approaches have several drawbacks. First, modular and subgraph partitioning can lead to uneven data volume among sub-threads, significantly impacting efficiency, and modular partitioning is ineffective for single-module designs. Second, this design often only considers the results of a local clock tree, making it difficult to achieve global clock tree balance. Third, the lack of adaptation for different multithreading stages may result in inefficient processing at different stages of the clock tree. Ultimately, this leads to multithreaded algorithms failing to provide the expected acceleration in some designs, and instead causing the clock tree to fail to converge properly. Summary of the Invention

[0006] The purpose of this invention is to provide a partition-based multi-threaded clock tree construction method to solve the problems in the background art.

[0007] To address the aforementioned technical problems, this invention provides a partition-based multi-threaded clock tree construction method, comprising: Divided according to module, location, and load quantity; The insertion of the buffer divides the clock tree into two parts: the upper subtree is from the clock tree root node to the newly inserted buffer, and the lower subtree is from the newly inserted buffer to the actual clock tree load. The above division is used as a multi-threaded approach, with the buffer as the root node of the lower subtree, and multiple threads are established to handle the construction and balancing of the tree respectively. Process the upper subtree by using the next level of the buffer as a temporary load for the upper subtree to optimize the buffer of the upper subtree, and add the maximum delay of the subtree corresponding to the clock tree root node in the current upper subtree to the delay of this buffer.

[0008] In one implementation, the module division is performed using a hierarchical clustering method, including: The number of module nodes connected to the root node is selected as the clustering basis, and then the modules are clustered according to their positions to obtain a partitioning result. For each cluster in the partitioning results, positional clustering is performed, with the objective function being the bus length and the standard deviation of the number of loads in each cluster. This location clustering will divide the workload into groups based on the number of loads, selecting... The load is divided into several partitions and then clustered using the K-Means positional clustering method until all loads in each cluster are selected whose load count is less than the load threshold. The most suitable clustering scheme is selected by comparing the objective functions. in, It is the total load. It is the load threshold, which is the set load quantity.

[0009] In one implementation, the partition-based multi-threaded clock tree construction method further includes adaptation for local and global conditions, comprising the following steps: During the design rule violation repair phase, consider the results under the current subtree, since only the problem of the current subtree is involved; During the maximum clock latency reduction phase, consider the results under the current subtree, because when the local maximum latency of each subtree is reduced to the minimum, the global maximum clock latency will also be reduced accordingly. During the power reduction phase, using a smaller buffer to reduce power consumption can lead to increased latency. Therefore, it is necessary to consider the global latency in order to fully reduce the power consumption of each subtree. At the same time, to avoid increasing the maximum latency, global data is collected and passed to the thread at the beginning of thread creation. During the clock tree balancing phase, local clock skew is considered to ensure that the clock skew in each subtree is small. If the delays of the subtrees are different, the different delays of the subtrees are balanced in the balancing of the upper subtrees by adjusting the upper subtrees. In other words, the reduction of local clock skew is a sufficient condition for the reduction of global clock skew.

[0010] In one implementation, the division based on modules, locations, and load quantities includes: The load of the same module is concentrated in a certain area and has more internal timing paths. Putting them together makes its internal skew smaller and the common clock path longer. The location is clustered using a clustering algorithm to ensure that loads that are close in location are grouped together for clock tree construction; The load is a set threshold. When the load exceeds this threshold, all loads are clustered and partitioned to prevent any sub-problem from becoming too large. At the same time, the load of each thread is controlled to be close, so that the load of each thread is balanced and concurrency is improved.

[0011] The present invention provides a partition-based multi-threaded clock tree construction method, which can quickly complete the clock tree construction and meet all clock tree indicators, while maintaining good consistency with single-threaded results while achieving a greater speedup. Attached Figure Description

[0012] Figure 1 This is a schematic diagram illustrating the selection of the most suitable clustering scheme provided by the present invention.

[0013] Figure 2 This is a schematic diagram of the partitioned clock tree and thread structure provided by the present invention. Detailed Implementation

[0014] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the partition-based multi-threaded clock tree construction method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0015] This invention relates to the clock tree synthesis part of electronic design automation (EDA), which is the clock tree construction process performed after placement optimization. During the placement phase, the clock tree is often considered an ideal clock tree, meaning there are no design rule violations, zero clock delay, and zero clock skew. However, the clock tree construction phase typically aims for zero clock skew. Different clock tree construction phases have different objectives and require consideration of different factors. The main considerations can be categorized as: design rule violations, power consumption, maximum clock delay, and clock skew. The clock tree construction process revolves around these factors.

[0016] The multithreading method of this invention employs a partition-based approach. In the initial stage, the workload is divided based on module, location, and load quantity. Since the load of the same module is generally concentrated in a certain area, and its internal timing paths are often numerous, they are placed together as much as possible. This minimizes internal skew and extends the common clock path, reducing the impact of on-chip differences. Location is clustered using a clustering algorithm, ensuring that loads in close proximity are grouped together for clock tree construction. The load quantity is a set threshold; when it exceeds this threshold, all loads are clustered and partitioned to prevent any single sub-problem from becoming too large. Simultaneously, the load quantity for each thread is kept as close as possible to ensure load balance and improve concurrency.

[0017] Hierarchical clustering is a method for clustering modules, such as... Figure 1 As shown, the number of module nodes connected to the root node is selected as the clustering criterion. Then, the modules are clustered according to their location to obtain a partitioning result. Next, positional clustering is performed on each cluster in the partitioning result, with the objective function being the bus length and the standard deviation of the load count in each cluster. This positional clustering will partition based on the number of loads, selecting... The load is divided into several partitions, and the K-Means positional clustering method is used until all loads satisfying the condition that the number of loads in each cluster is less than the load threshold are selected. Then, the objective function is compared to select the most suitable clustering scheme. It is the total load. It is the load threshold, which is the set load quantity.

[0018] Applying the K-Means location clustering method to the load involves the following steps: The K-Means algorithm divides the system into K partitions. Step 1: Initialization K loads are randomly selected as the initial cluster centroids; Step 2: Iterate repeatedly until the centroid no longer changes significantly (convergence). This loop contains two main steps: 1. Allocation Steps For each data point in the dataset, calculate its distance to each of the K centroids; Each data point is assigned to the cluster containing the nearest centroid. After this step is completed, all data points are assigned to one of the K clusters.

[0019] 2. Update Steps For each cluster that has just been assigned, recalculate the centroid of that cluster; The new centroid location is the average of all dimensions of all data points in the cluster.

[0020] For example, on a two-dimensional plane, the (x,y) coordinates of the new centroid are the average of the x-coordinates and the average of the y-coordinates of all points in the cluster.

[0021] Step 3: End The algorithm stops when the centroid moves less than a certain threshold (or the number of iterations reaches the upper limit), indicating that it has converged.

[0022] After a suitable clustering scheme is selected, the buffer insertion is performed. First, select appropriate library components and place them in suitable positions within the boundary and central region of the clustering scheme. At this point, the clock tree is divided into two parts: the upper part is from the clock tree root node to the newly inserted buffer, and the lower part is from the newly inserted buffer to the actual clock tree load. This division can then be used for multi-threading.

[0023] The lower part uses the buffer as the root node of the subtree. Since the load in different clusters does not overlap, the subtrees become independent subproblems. Multiple threads are used to handle the tree construction and balancing separately. After the lower part finishes processing, the threads are recycled, and then the main thread begins processing the upper clock tree. During upper-level processing, the next level of the buffer is used as temporary load for the upper subtree. This allows for optimization of the root node buffer of the upper subtree, avoiding design rule violations after the initial processing. When processing the upper subtree, the maximum latency of the subtree corresponding to the current upper subtree root node needs to be added to the latency of this buffer. This ensures latency balance for the entire tree during upper-level balancing. The partitioned clock tree and thread allocation are as follows: Figure 2 As shown.

[0024] The adaptation of different steps for local and global scenarios is designed as follows: For the design rule violation correction phase, only the result of the current subtree needs to be considered, as it only involves the problem of the current subtree. Similarly, the maximum clock latency reduction phase only needs to consider the result of the current subtree, because minimizing the local maximum latency of each subtree will correspondingly reduce the global maximum clock latency. In the power consumption reduction phase, using a smaller buffer to reduce power consumption would increase latency, so global latency needs to be considered. This effectively reduces the power consumption of each subtree. To avoid increasing the maximum latency, global data is collected and passed to the thread at the beginning of thread creation. In the clock tree balancing phase, local clock skew is considered. As long as the clock skew in each subtree is small, even if the latency of the subtrees differs, the differences in subtree latency can still be balanced by adjusting the upper subtree. In other words, reducing local clock skew is a sufficient condition for reducing global clock skew.

[0025] Relying on this multi-threaded partitioning method and the adapted clock tree synthesis process, the clock tree can be constructed quickly, and all clock tree indicators can meet the standards.

[0026] This embodiment uses test cases to test various results. A clock tree with approximately 100,000 loads was constructed, and the test node was an SMIC-14nm. The results were compared between multi-threading without multi-threading, multi-threading using subgraphs, and multi-threading of this invention (partition-based multi-threading) (8 threads). Various metrics of the clock tree were collected.

[0027] As can be seen from the table above, the multi-threaded method of the present invention maintains good consistency with the single-threaded results while achieving a greater speedup ratio.

[0028] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for constructing a multi-threaded clock tree based on partitioning, characterized in that, include: Divided according to module, location, and load quantity; The insertion of the buffer divides the clock tree into two parts: the upper subtree is from the clock tree root node to the newly inserted buffer, and the lower subtree is from the newly inserted buffer to the actual clock tree load. The above division is used as a multi-threaded approach, with the buffer as the root node of the lower subtree, and multiple threads are established to handle the construction and balancing of the tree respectively. Process the upper subtree by using the next level of the buffer as a temporary load for the upper subtree to optimize the buffer of the upper subtree, and add the maximum delay of the subtree corresponding to the clock tree root node in the current upper subtree to the delay of this buffer.

2. The partition-based multi-threaded clock tree construction method as described in claim 1, characterized in that, The module division is achieved through hierarchical clustering, including: The number of module nodes connected to the root node is selected as the clustering basis, and then the modules are clustered according to their positions to obtain a partitioning result. For each cluster in the partitioning results, positional clustering is performed, with the objective function being the bus length and the standard deviation of the number of loads in each cluster. This location clustering will divide the workload by quantity, selecting... The loads between the partitions are clustered using the K-Means positional clustering method until all loads that satisfy the condition that the number of loads in each cluster is less than the load threshold are selected. The objective function is compared to select the most suitable clustering scheme. in, It is the total load. It is the load threshold, which is the set load quantity.

3. The partition-based multi-threaded clock tree construction method as described in claim 1, characterized in that, The partition-based multi-threaded clock tree construction method also includes local and global adaptations, including the following steps: During the correction phase of design rule violations, consider the results under the current subtree, since only the problem of the current subtree is involved; During the maximum clock latency reduction phase, consider the results under the current subtree, because as the local maximum latency of each subtree is reduced to the minimum, the global maximum clock latency will also be reduced accordingly. During the power reduction phase, using a smaller buffer to reduce power consumption can lead to increased latency. Therefore, it is necessary to consider the global latency in order to fully reduce the power consumption of each subtree. At the same time, to avoid increasing the maximum latency, global data is collected and passed to the thread at the beginning of thread creation. During the clock tree balancing phase, local clock skew is considered to ensure that the clock skew in each subtree is small. If the delays of the subtrees are different, the different delays of the subtrees are balanced in the balancing of the upper subtrees by adjusting the upper subtrees. In other words, the reduction of local clock skew is a sufficient condition for the reduction of global clock skew.

4. The partition-based multi-threaded clock tree construction method as described in claim 1, characterized in that, The division based on modules, locations, and load quantities includes: The load of the same module is concentrated in a certain area and has more internal timing paths. Putting them together makes its internal skew smaller and the common clock path longer. The location is clustered using a clustering algorithm to ensure that loads that are close in location are grouped together for clock tree construction; The load is a set threshold. When the load exceeds this threshold, all loads are clustered and partitioned to prevent any sub-problem from becoming too large. At the same time, the load of each thread is controlled to be close, so that the load of each thread is balanced and concurrency is improved.