Quantum circuit mapping method and system based on deep reinforcement learning

Abstract

The application relates to the technical field of quantum computing, and discloses a quantum circuit mapping method and system based on deep reinforcement learning. The method is characterized in that: the original logical quantum circuit is parsed and simplified into a ZX-graph, and then the ZX-graph is converted into a quantum circuit dependency graph, so that the calculation complexity is significantly reduced, the mapping task of a large-scale quantum circuit can be processed within a reasonable time, a Markov decision process environment is constructed by using the quantum circuit dependency graph and quantum chip parameters, a deep reinforcement learning intelligent agent is trained by using the Markov decision process environment, an optimal mapping strategy optimization model is obtained, and the optimal mapping strategy optimization model can output the corresponding optimal quantum bit mapping scheme of the current logical circuit to be mapped, so that the quantum chip of various topological structures can be adapted, and the generalization ability and adaptability of the mapping scheme are improved.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a quantum circuit mapping method and system based on deep reinforcement learning. Background Technology

[0002] Quantum circuit mapping is a core and crucial step in quantum computing that connects logical quantum circuits to physical quantum processors. Its core task is to allocate logical qubits to physical qubits and optimize the execution timing of quantum gates to ensure that logical circuits can be executed efficiently and with high fidelity on actual physical hardware.

[0003] Its performance directly determines the execution efficiency and fidelity of quantum algorithms on real hardware.

[0004] Existing quantum circuit mapping techniques face the combinatorial explosion problem when dealing with large-scale quantum circuits (logic bits ≥ 20), resulting in high computational complexity and difficulty in outputting an effective mapping scheme within a reasonable time. Furthermore, they are mostly designed for quantum chips with specific topologies or specific types of quantum circuits, lacking generalization ability and having poor adaptability. Summary of the Invention

[0005] In view of this, in order to solve the above-mentioned technical problems, the present invention provides a quantum circuit mapping method and system based on deep reinforcement learning.

[0006] The first aspect of this invention provides a quantum circuit mapping method based on deep reinforcement learning, comprising:

[0007] Obtain the original logic quantum circuit, analyze and simplify the original logic quantum circuit into a ZX-graph, and transform the ZX-graph into a quantum circuit dependency graph;

[0008] Obtain the quantum chip parameters, and construct a Markov decision process environment based on the quantum circuit dependency graph and the quantum chip parameters;

[0009] Based on the Markov decision process environment, a deep reinforcement learning agent is trained to obtain an optimal mapping strategy optimization model.

[0010] Obtain the current logic circuit to be mapped and the corresponding current quantum chip parameters, and combine the optimal mapping strategy optimization model to generate the optimal qubit mapping scheme for the current logic circuit to be mapped.

[0011] Preferably, the step of resolving and simplifying the original logic quantum circuit into a ZX-graph, and converting the ZX-graph into a quantum circuit dependency graph, includes:

[0012] Each single quantum gate in the original logical quantum circuit is mapped to a single node in the ZX-graph, and each double quantum gate in the original logical quantum circuit is mapped to a node and a first directed edge in the ZX-graph. Node parameters are labeled for each single node and the node to form a parameterized ZX-graph; wherein, the first directed edge is used to characterize the entanglement relationship between qubits.

[0013] Based on the spider fusion, boundary elimination, and phase cancellation rules of ZX calculus, the parameterized ZX-graph is optimized and simplified to obtain a logically equivalent simplified ZX-graph.

[0014] Each node in the simplified ZX-graph is mapped to a node in the quantum circuit dependency graph, and the causal dependencies between quantum gates are used as the second directed edges in the quantum circuit dependency graph to construct the quantum circuit dependency graph that reflects the constraints on the execution order of quantum gates.

[0015] Preferably, constructing the Markov decision process environment based on the quantum circuit dependency graph and the quantum chip parameters includes:

[0016] Based on the quantum circuit dependency diagram and the quantum chip parameters, multiple feature vectors of the current quantum mapping scenario are determined, and the multiple feature vectors of the current quantum mapping scenario are standardized and then concatenated to form a state space;

[0017] Determining the action space includes the initial allocation of qubits, the scheduling of SWAP gates, and the control of tunable couplers;

[0018] Define the state transition function as a deterministic transition, and construct a multi-objective weighted reward function based on the quantum gate execution fidelity as the reward, and the circuit depth, the number of SWAP gates and the number of tunable coupler controls as the penalty.

[0019] The Markov decision process environment is constructed based on the state space, the action space, the state transition function, and the multi-objective weighted reward function, and by introducing a discount factor.

[0020] Preferably, the quantum chip parameters include static topology parameters, dynamic calibration parameters, and qubit mapping relationships; the feature vectors include chip topology feature vectors, quantum circuit dependency graph feature vectors, qubit mapping relationship feature vectors, and hardware dynamic parameter feature vectors.

[0021] The step of determining multiple feature vectors of the current quantum mapping scenario based on the quantum circuit dependency graph and the quantum chip parameters, and then standardizing and concatenating these feature vectors to form a state space, includes:

[0022] The quantum circuit dependency graph is used to extract features by a graph attention network to obtain the features of all nodes in the quantum circuit dependency graph, and the features of all nodes in the quantum circuit dependency graph are then globally pooled to obtain the feature vector of the quantum circuit dependency graph.

[0023] Using the static topology parameters, an adjacency matrix is ​​constructed, and a Laplacian matrix is ​​constructed from the adjacency matrix. The Laplacian matrix is ​​then subjected to eigenvalue decomposition, and the first 32 dimensions of the Laplacian feature vector are extracted and fused with the adjustable coupler position code to obtain the chip topology feature vector.

[0024] After normalizing the dynamic calibration parameters, they are concatenated to form the feature vector of the hardware dynamic parameters;

[0025] A mapping matrix is ​​constructed based on the quantum bit mapping relationship, and the mapping matrix is ​​vectorized to obtain the feature vector of the quantum bit mapping relationship;

[0026] The state space is formed by concatenating the chip topology feature vector, the quantum circuit dependency graph feature vector, the quantum bit mapping relationship feature vector, and the hardware dynamic parameter feature vector after standardization.

[0027] Preferably, the step of training the deep reinforcement learning agent based on the Markov decision process environment to obtain the optimal mapping policy optimization model includes:

[0028] Construct an agent that is jointly trained by a policy network and a value network based on the PPO algorithm. The agent is a shared backbone structure that incorporates an action masking mechanism and integrates a graph neural network and a fully connected network.

[0029] Based on the PPO algorithm, the agent selects and executes a legal action from the action probability distribution output by the policy network according to the current state space in the Markov decision process environment and the action masking mechanism.

[0030] After the legal action is executed, the state space is updated through the state transition function, the immediate reward is calculated through the multi-objective weighted reward function, and the long-term cumulative reward after the legal action is executed is calculated in combination with the discount factor.

[0031] By estimating the generalized advantage, the advantage function value is updated based on the long-term cumulative reward. Combined with the updated advantage function value, the parameters of the policy network and the value network are updated by minimizing the clipped objective function until the fluctuation range of the average instantaneous reward for a preset number of consecutive training iterations tends to converge. Then, the latest agent is output as the optimal mapping policy optimization model.

[0032] Preferably, the step of obtaining the current logic circuit to be mapped and the current quantum chip parameters corresponding to the current logic circuit to be mapped, and combining the optimal mapping strategy optimization model to generate the optimal qubit mapping scheme for the current logic circuit to be mapped, includes:

[0033] Obtain the current logic circuit to be mapped and the current quantum chip parameters corresponding to the current logic circuit to be mapped, and determine the current quantum circuit dependency graph based on the current logic circuit to be mapped;

[0034] Based on the current quantum circuit dependency graph and the current quantum chip parameters, determine the current state space corresponding to the current logic circuit to be mapped;

[0035] The current state space is input into the optimal mapping strategy optimization model, and the optimal action space of the current logic line to be mapped is output.

[0036] After decoding and deduplication of the optimal action space, a simplified action space is obtained;

[0037] The simplified action space is validated for legitimacy, and the action space that passes the validation is transformed into a standardized optimal qubit mapping scheme.

[0038] Preferably, the step of obtaining the current logic circuit to be mapped and the current quantum chip parameters corresponding to the current logic circuit to be mapped, and generating the optimal qubit mapping scheme for the current logic circuit to be mapped by combining the optimal mapping strategy optimization model, further includes:

[0039] Based on the optimal qubit mapping scheme, multi-dimensional performance evaluation indicators are determined; wherein, the multi-dimensional performance evaluation indicators include at least one of circuit fidelity, execution time, constraint satisfaction rate, resource efficiency, and robustness indicators.

[0040] If any of the multi-dimensional performance evaluation metrics fails to reach the preset threshold, the multi-dimensional performance evaluation metrics are fed back to the optimal mapping strategy optimization model, the reward weight of the optimal mapping strategy optimization model is adjusted, and the training process of the optimal mapping strategy optimization model is re-executed until all the multi-dimensional performance evaluation metrics reach the preset threshold, and the latest quantum bit mapping scheme is obtained and updated as the optimal quantum bit mapping scheme.

[0041] Secondly, the present invention also provides a quantum circuit mapping system based on deep reinforcement learning, comprising:

[0042] The dependency graph transformation module is used to obtain the original logical quantum circuit, parse and simplify the original logical quantum circuit into a ZX-graph, and transform the ZX-graph into a quantum circuit dependency graph;

[0043] An environment construction module is used to acquire quantum chip parameters and construct a Markov decision process environment based on the quantum circuit dependency graph and the quantum chip parameters.

[0044] The optimized model training module is used to train the deep reinforcement learning agent based on the Markov decision process environment to obtain the optimal mapping strategy optimization model.

[0045] The mapping scheme optimization module is used to obtain the current logic line to be mapped and the current quantum chip parameters corresponding to the current logic line to be mapped, and generate the optimal quantum bit mapping scheme for the current logic line to be mapped by combining the optimal mapping strategy optimization model.

[0046] Thirdly, the present invention also provides an electronic device, the electronic device including a memory and a processor, the memory storing a computer program, the computer program being executed by the processor causing the processor to perform the steps of the quantum circuit mapping method based on deep reinforcement learning as described in the first aspect.

[0047] Fourthly, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed, implements the steps of the quantum circuit mapping method based on deep reinforcement learning as described in the first aspect.

[0048] As can be seen from the above technical solutions, this invention significantly reduces computational complexity by analyzing and simplifying the original logical quantum circuits into ZX-graphs, and then transforming the ZX-graphs into quantum circuit dependency graphs. This enables the processing of large-scale quantum circuit mapping tasks within a reasonable time. Furthermore, a Markov decision process environment is constructed using the quantum circuit dependency graphs and quantum chip parameters. The deep reinforcement learning agent is trained using this Markov decision process environment to obtain an optimal mapping strategy optimization model. This optimal mapping strategy optimization model can output the corresponding optimal qubit mapping scheme for the current logical circuit to be mapped, thereby adapting to quantum chips with various topologies and improving the generalization and adaptability of the mapping scheme. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 An application environment diagram of a quantum circuit mapping method based on deep reinforcement learning provided in an embodiment of the present invention;

[0051] Figure 2 A flowchart illustrating a quantum circuit mapping method based on deep reinforcement learning, provided as an embodiment of the present invention;

[0052] Figure 3 A schematic diagram of a quantum circuit mapping system based on deep reinforcement learning provided in an embodiment of the present invention;

[0053] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0054] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] The quantum circuit mapping method based on deep reinforcement learning provided in this application can be applied to, for example... Figure 1 In the application environment shown, terminal 101 communicates with server 102 via a network. A data storage system can store the data that server 102 needs to process. The data storage system can be integrated onto server 102 or placed in the cloud or on another network server. Terminal 101 or server 102 acquires the original logical quantum circuit, parses and simplifies it into a ZX-graph, and transforms the ZX-graph into a quantum circuit dependency graph; acquires the quantum chip parameters, and constructs a Markov decision process environment based on the quantum circuit dependency graph and the quantum chip parameters; trains a deep reinforcement learning agent based on the Markov decision process environment to obtain an optimal mapping strategy optimization model; acquires the current logical circuit to be mapped and the corresponding current quantum chip parameters, and combines this with the optimal mapping strategy optimization model to generate the optimal qubit mapping scheme for the current logical circuit to be mapped.

[0056] Terminal 101 can be, but is not limited to, various personal computers, laptops, smartphones, and tablets.

[0057] Server 102 can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides cloud computing services.

[0058] like Figure 2 As shown, this application provides a quantum circuit mapping method based on deep reinforcement learning, which can be applied to... Figure 1 Taking terminal 101 or server 102 as an example, the explanation includes the following steps S1 to S4. Wherein:

[0059] Step S1: Obtain the original logic quantum circuit, analyze and simplify the original logic quantum circuit into a ZX-graph, and transform the ZX-graph into a quantum circuit dependency graph.

[0060] The original logic quantum circuit is usually in QASM format or quantum circuit description language format. It is a high-level abstract circuit that is designed by the user or generated by quantum algorithms and has not been hardware adapted. It contains a series of logic quantum gates and their qubit indices.

[0061] To achieve a more tractable and optimizable form, reduce the computational complexity of subsequent mapping processes, and preserve the core logic and performance characteristics of the circuit, the original logical quantum circuit is parsed and simplified into a ZX-graph. The ZX-graph is a graphical formalism-based quantum circuit representation method that concisely and intuitively describes the effects of quantum gates and the entanglement relationships between qubits. Through the specific rules of ZX calculus, efficient simplification of quantum circuits can be achieved, removing redundant quantum gates and reducing circuit depth without altering the circuit's logical function and fidelity characteristics.

[0062] A quantum circuit dependency graph is a directed acyclic graph (DAG) in which nodes represent quantum gate operations and edges represent causal dependencies at the qubit level. This graph accurately depicts the sequential constraints and parallel potential of each gate execution, providing a structured input basis for subsequent modeling of gate scheduling and bit allocation in an MDP environment.

[0063] Step S2: Obtain the quantum chip parameters and construct a Markov decision process environment based on the quantum circuit dependency graph and the quantum chip parameters.

[0064] Among them, the Markov Decision Process Environment (MDP) is the core framework for formally modeling the quantum circuit mapping problem. It transforms the quantum circuit mapping problem into a Markov decision process. By constructing an MDP environment that includes quantum hardware characteristics, quantum circuit structure, and mapping relationships, it is used to train a deep reinforcement learning agent, enabling it to autonomously learn the optimal qubit allocation, gate scheduling, and coupler control strategies, and finally generate a globally optimal mapping scheme that satisfies hardware constraints and achieves multi-objective optimization.

[0065] Step S3: Based on the Markov decision process environment, train the deep reinforcement learning agent to obtain the optimal mapping strategy optimization model.

[0066] In this process, by training the agent, it can autonomously learn the optimal mapping strategy in the MDP environment, achieving multi-objective optimization and hardware constraint satisfaction. Thus, during the training process, the agent can continuously interact with the MDP environment, update the policy network and value network by collecting trajectory data, and obtain the optimal mapping strategy optimization model.

[0067] Step S4: Obtain the current logic circuit to be mapped and the current quantum chip parameters corresponding to the current logic circuit to be mapped, and combine the optimal mapping strategy optimization model to generate the optimal quantum bit mapping scheme for the current logic circuit to be mapped.

[0068] The current logic circuit to be mapped, also known as the logic quantum circuit, can be obtained by combining the logic quantum circuit with the aforementioned step S1 to obtain its corresponding quantum circuit dependency graph. Then, the current chip parameters are input into the trained optimal mapping strategy optimization model. The model analyzes the features of the circuit dependency graph and the features corresponding to the current chip parameters in real time to output the optimal quantum bit mapping scheme for the current logic circuit to be mapped. This quantum bit mapping scheme is used to guide the quantum chip execution layer to map the logic gate sequence to physical bit pairs to handle the mapping task of large-scale quantum circuits.

[0069] It should be noted that the embodiments of this application significantly reduce computational complexity by parsing and simplifying the original logical quantum circuits into ZX-graphs, and then transforming the ZX-graphs into quantum circuit dependency graphs. This enables the processing of large-scale quantum circuit mapping tasks within a reasonable time. Furthermore, a Markov decision process environment is constructed using the quantum circuit dependency graphs and quantum chip parameters. The deep reinforcement learning agent is trained using the Markov decision process environment to obtain an optimal mapping strategy optimization model. This optimal mapping strategy optimization model can output the corresponding optimal qubit mapping scheme for the current logical circuit to be mapped, thereby adapting to quantum chips with various topologies and improving the generalization and adaptability of the mapping scheme.

[0070] In some embodiments, the specific process of "analyzing and simplifying the original logical quantum circuit into a ZX-graph and transforming the ZX-graph into a quantum circuit dependency graph" in step S1 includes: mapping each single quantum gate in the original logical quantum circuit to a single node in the ZX-graph, and mapping each double quantum gate in the original logical quantum circuit to a node and a first directed edge in the ZX-graph, and labeling each single node and node with node parameters to form a parameterized ZX-graph; wherein, the first directed edge is used to characterize the entanglement relationship between qubits; based on the spider fusion, boundary elimination and phase cancellation rules of ZX calculus, the parameterized ZX-graph is optimized and simplified to obtain a logically equivalent simplified ZX-graph; mapping each node in the simplified ZX-graph to a node in the quantum circuit dependency graph, and using the causal dependency relationship between each quantum gate as the second directed edge in the quantum circuit dependency graph to construct a quantum circuit dependency graph that reflects the quantum gate execution order constraint.

[0071] For example, the original logic quantum circuit (usually in QASM format or Quantum Circuit Description Language format) is parsed line by line. Each single quantum gate (such as X, Y, Z, H gates) is transformed into a single node in the ZX-graph (corresponding to different types of spider nodes), and each double quantum gate (such as CNOT, CZ gates) is transformed into a node and directed edges in the ZX-graph (directed edges are used to represent the entanglement relationship between qubits). At the same time, node parameters are labeled for each node, including key information such as quantum gate type, active qubit number, ideal fidelity, and execution time, forming a parameterized ZX-graph.

[0072] Based on the spider fusion, boundary elimination, and phase cancellation rules of ZX calculus, the parameterized ZX-graph is optimized and simplified, where:

[0073] Spider fusion rule: Adjacent spider nodes of the same type and phase can be directly merged into a single node, eliminating redundant edges in the middle and not changing the quantum logic function;

[0074] Boundary elimination rule: Isolated nodes located at the boundary of the ZX-graph and without subsequent entanglement are directly deleted without affecting the overall line;

[0075] Phase cancellation rule: Node pairs with complementary phases cancel each other out, eliminating the corresponding quantum gate operations and effectively compressing the circuit depth.

[0076] The simplified ZX-graph must be verified through quantum state simulation and pass the quantum circuit equivalence verification (using quantum state simulation comparison, with the same initial quantum state as input, the output quantum state fidelity of the ZX-graph before and after simplification must be ≥1, i.e., completely equivalent). After successful verification, the simplified circuit depth D′ is recorded, satisfying D′≤D, and the circuit logic function is completely equivalent to the original circuit. Here, the quantum circuit depth D is defined as the number of quantum gates contained in the longest quantum gate execution path in the circuit, and its mathematical expression is:

[0077]

[0078] In the formula, A set of logical qubits Let be the ordered set of all quantum gates on the i-th logical qubit according to their execution time. The summation operation is used to count the total number of quantum gates on the path, and the max operation is used to select the longest number of gates in all logical qubit paths, i.e., the path depth.

[0079] The simplified ZX-graph is transformed into a quantum circuit dependency graph (directed acyclic graph DAG). Each quantum gate is a node, and the execution causal relationship between quantum gates is a directed edge (e.g., if gate g1 can only be executed after gate g2 is executed, then a directed edge from g1 to g2 is constructed). Finally, an acyclic dependency graph is formed, which clarifies the sequential execution constraints between each quantum gate and provides input for subsequent MDP environment modeling.

[0080] In some embodiments, the specific process of "constructing a Markov decision process environment based on the quantum circuit dependency graph and quantum chip parameters" in step S2 includes: determining multiple feature vectors of the current quantum mapping scenario based on the quantum circuit dependency graph and quantum chip parameters, and standardizing and concatenating the multiple feature vectors of the current quantum mapping scenario to form a state space; determining the action space including the initial allocation action of qubits, the SWAP gate scheduling action, and the tunable coupler control action; defining the state transition function as a deterministic transition, and constructing a multi-objective weighted reward function based on the quantum gate execution fidelity as the reward, and the circuit depth, the number of SWAP gates, and the number of tunable coupler controls as penalty terms; and constructing a Markov decision process environment based on the state space, action space, state transition function, and multi-objective weighted reward function, and introducing a discount factor.

[0081] In this context, the Markov decision process environment uses a quintuple M = (S, A, P, R, ... The formal definition is as follows, where the meaning of each element corresponds to the mathematical definition:

[0082] The state space S is used to comprehensively describe all the key information of the current mapping scenario. In one example, the quantum chip parameters include static topology parameters, dynamic calibration parameters, and quantum bit mapping relationships; the feature vectors include chip topology feature vectors, quantum circuit dependency graph feature vectors, quantum bit mapping relationship feature vectors, and hardware dynamic parameter feature vectors. In this context, based on the quantum circuit dependency graph and quantum chip parameters, multiple feature vectors of the current quantum mapping scenario are determined. These feature vectors are then standardized and concatenated to form a state space. This process includes: extracting features from the quantum circuit dependency graph using a graph attention network to obtain the features of all nodes in the graph, and then globally pooling these features to obtain the quantum circuit dependency graph feature vector; constructing an adjacency matrix using static topology parameters, then constructing a Laplace matrix from the adjacency matrix, performing eigenvalue decomposition on the Laplace matrix, extracting the first 32 dimensions of the Laplace feature vector, and fusing it with the tunable coupler position encoding to obtain the chip topology feature vector; normalizing the dynamic calibration parameters and concatenating them to form the hardware dynamic parameter feature vector; constructing a mapping matrix based on the quantum bit mapping relationship and vectorizing it to obtain the quantum bit mapping relationship feature vector; and then standardizing and concatenating the chip topology feature vector, the quantum circuit dependency graph feature vector, the quantum bit mapping relationship feature vector, and the hardware dynamic parameter feature vector to form the state space.

[0083] The graph attention network (GAT) is used to extract features from the quantum circuit dependency graph. The specific steps are as follows: Initial feature encoding (including gate type, active bits, ideal fidelity, etc.) is performed on each node (quantum gate) in the quantum circuit dependency graph; node features are aggregated through two GAT layers to learn the dependencies between nodes; and global pooling is performed on all node features to obtain a fixed-dimensional feature vector of the circuit dependency graph. (Preferred to be 64 dimensions) to ensure consistent dimensionality of output features across quantum circuits of different sizes. This vector is the D vector in the subsequent reward function. penalty The calculation of (line depth) provides line support.

[0084] The static topology parameters include the number of qubits *m*, the connection method (hexagonal / square / linear topology), and the position and structure of the tunable couplers. These are obtained by analyzing the chip electronic design file (EDF file) or the topology description file provided by the chip manufacturer. These parameters are then encoded into a standardized chip topology feature vector. The specific steps are as follows: First, construct the adjacency matrix A∈{0,1} using static topological parameters. m×m Its definition is:

[0085]

[0086] In the formula, The element in the i-th row and j-th column of the adjacency matrix takes only the value 0 or 1.

[0087] Then construct the Laplace matrix from the adjacency matrix A. (Λ is the degree matrix, and the diagonal elements are the number of adjacent bits for the corresponding physical bit). Then, the Laplacian matrix L is decomposed into eigenvalues, and the first 32-dimensional Laplacian eigenvectors are extracted as the chip topology feature vectors. The core representation is then fused with the binary encoded vector of the adjustable coupler position, linearly projected, and concatenated with the aforementioned features to finally form a chip topology feature vector with fixed dimensions. .

[0088] The dynamic calibration parameters include the decoherence time of the qubits (T1, T2, in microseconds µs), readout fidelity, quantum gate error rate, and coupler coupling strength. These parameters fluctuate with chip operating time and ambient temperature, and need to be periodically obtained through the quantum chip's real-time calibration interface (the calibration period is preferably 5 minutes). After normalizing all dynamic parameters (mapping them to the [0,1] interval), they are concatenated to form a hardware dynamic parameter feature vector. This vector provides hardware support for the calculation of fidelity in the subsequent reward function.

[0089] Furthermore, based on the qubit mapping relationship, a qubit mapping tracking mechanism is constructed, using a mapping matrix M∈{0,1}. n×m The mapping relationship (where n is the number of logical bits and m is the number of physical bits) is defined as follows:

[0090]

[0091] In the formula, The element in the i-th row and j-th column of the mapping matrix takes only the value 0 or 1, satisfying the constraint condition:

[0092]

[0093] The physical meaning of this constraint is: each logical qubit must and can only be mapped to one physical qubit, and each physical qubit can be mapped to at most one logical qubit. Subsequently, the mapping matrix M is vectorized to obtain a fixed-dimensional mapping relationship feature vector. This vector provides a basis for judging the legitimacy of initial allocation and position adjustment in the subsequent action space.

[0094] Through the chip topology feature vector mentioned above Quantum circuit dependency graph eigenvectors eigenvectors of quantum bit mapping relationship and hardware dynamic parameter feature vector After standardization and concatenation, a state space with unified dimensions is obtained (dimensional optimization). ):

[0095]

[0096] In the formula, s is a high-dimensional eigenvector, and T is the matrix transpose.

[0097] The action space A defines all legal mapping actions that the agent can execute. It is a discrete set of actions. Combined with hardware constraints (such as the requirement that adjacent bits must be adjacent to execute the SWAP gate), the action space includes qubit initial allocation actions, SWAP gate scheduling actions, and tunable coupler control actions.

[0098]

[0099] In the formula, The initial allocation action subset for qubits (containing all legal combinations of logical-to-physical bit allocations). This is a subset of SWAP gate scheduling actions (containing all adjacent physical bit pairs of SWAP operations). It is a subset of adjustable coupler control actions (including the opening / closing / adjustment actions of all adjustable couplers), and the three do not overlap with each other, together forming a complete action space.

[0100] The state transition function P defines the state transition rules after an action is performed, namely:

[0101]

[0102] Among them, the state transition is a deterministic transition, that is, given the current state s and the action a, the transition will necessarily lead to a uniquely determined next state. Since there are no probabilistic fluctuations, the state transition function... The value is 1 (corresponding to the only valid value). 0 (corresponding to other illegal states).

[0103] A multi-objective weighted reward function R is used to evaluate the merits of actions and guide the agent to learn the optimal policy. Mathematically, it is expressed as:

[0104] R: S×A×S→ (Supplementing the next state) The output is a real-valued reward, with positive values ​​indicating advantageous actions and negative values ​​indicating disadvantageous actions. Larger absolute values ​​indicate greater impact. To achieve multi-objective optimization, its core form is a weighted combination (with pre-defined weight parameters):

[0105]

[0106] In the formula, As a reward value, Assigning a reward weight to circuit fidelity. For line depth penalty weight, The penalty weight for the number of SWAP gates (taking into account both execution time and hardware constraints). The adjustable coupler control cycle penalty weights are used (hardware constraints and overhead optimization). Each reward weight strictly satisfies the normalization constraint α+β+γ+δ=1, ensuring that the reward / penalty magnitudes of each objective can be directly compared, avoiding imbalance of optimization objectives due to differences in weight weights. This constraint remains consistent throughout the MDP environment and PPO principle.

[0107] In one example, α=0.51, β=0.2, γ=0.19, and δ=0.1. This set of weights was determined through a large number of comparative experiments, covering 10 typical quantum circuits (QFT, VQE, QAOA, etc.) and 5 mainstream chip topologies. Finally, the weight combination with the best comprehensive performance in multiple scenarios was selected, which has strong generalization ability.

[0108] This is a circuit fidelity bonus item, with a value range of [0,1]. The calculation logic is as follows: ,in, For the ideal fidelity of quantum gate g, The fidelity attenuation coefficient of g after mapping is related to the eigenvector of hardware dynamic parameters. (related to decoherence time and coupling strength in the process). For a set of quantum gates, the higher the fidelity, the better. The larger the value, the more likely the intelligent agent will prioritize ensuring the correct execution of the circuit.

[0109] This is a line depth penalty term; the greater the line depth, the heavier the penalty. Since line depth is positively correlated with execution time (greater depth, longer execution time, and more significant decoherence effects), this weight indirectly optimizes execution time by suppressing line depth, achieving a synergistic optimization of "shallower depth, faster execution, and higher fidelity." Specifically:

[0110]

[0111] In the formula, The line depth of the current mapping scheme is determined by... statistics.

[0112] The number of SWAP gates inserted for the current action. Each SWAP gate inserted deducts the corresponding weight's reward value. SWAP gates not only increase line depth (extending execution time) but also introduce additional noise (reducing fidelity). At the same time, their execution must meet the hardware constraint of "adjacent physical bits" (determined by the adjacency matrix A). This weight optimizes execution time and reduces the risk of hardware constraint violation by reducing the insertion of SWAP gates.

[0113] This represents the number of times the adjustable coupler is controlled by the current action. Each control operation deducts a reward value corresponding to the weight. Frequent coupler adjustments introduce hardware overhead (energy consumption, latency), and some couplers have a "stabilization time after adjustment" constraint. By reducing the number of adjustments, we can ensure that the dynamic hardware constraints are met while reducing execution overhead.

[0114] Furthermore, to address the dynamic nature of implicit hardware constraints, an additional penalty term is introduced into the reward function. The corrected reward function takes effect immediately when an action triggers a latent violation such as an excessively high coupler adjustment frequency.

[0115]

[0116] The revised reward function forces agents to learn compliant strategies, forming a dual guarantee of hard constraints and soft penalties with the action masking mechanism.

[0117] Discount factor ∈ (0,1], used to balance immediate rewards and long-term rewards, in this application, discount factor The value is set to 0.95. This value ensures the stability of policy convergence while giving sufficient weight to the long-term optimization objective, allowing the agent to consider both the single-step swap cost and the global path fidelity decay trend in mapping decisions. The long-term cumulative reward is:

[0118]

[0119] In the formula, To accumulate reward value over a long period of time, As a discount factor, This is the instant reward at step t+k.

[0120] In some embodiments, the specific process of "training a deep reinforcement learning agent based on a Markov decision process environment to obtain an optimal mapping policy optimization model" in step S3 includes: constructing an agent jointly trained by a policy network and a value network based on the PPO algorithm, wherein the agent is a shared backbone structure fused with a graph neural network and a fully connected network by introducing an action masking mechanism; based on the PPO algorithm, the agent selects and executes a legal action from the action probability distribution output by the policy network according to the current state space in the Markov decision process environment, combined with the action masking mechanism; after executing a legal action, the state space is updated through a state transition function, and the immediate reward is calculated through a multi-objective weighted reward function, and the long-term cumulative reward after executing the legal action is calculated by combining a discount factor; through generalized advantage estimation, the advantage function value is updated according to the long-term cumulative reward, and the parameters of the policy network and the value network are updated by minimizing the clipped objective function based on the updated advantage function value, until the fluctuation range of the average immediate reward for a consecutive preset number of training iterations tends to converge, and the latest agent is output as the optimal mapping policy optimization model.

[0121] Among them, the PPO (Proximal Policy Optimization) algorithm is an advanced policy gradient algorithm. Its core lies in constraining the policy update magnitude by pruning the probability ratio, thereby ensuring the stability and robustness of the training process.

[0122] In this application, an agent jointly trained by a policy network and a value network based on the PPO algorithm is first constructed. The agent's network architecture includes an input layer, a backbone layer, branch layers, and an action mask module. The input layer receives the high-dimensional state vector s of the MDP. The backbone layer consists of two ReLU-activated fully connected layers stacked with a graph neural network (GNN) layer. The branch layers include a policy network branch and a value network branch. The policy network branch outputs the action probability distribution πθ(a|s), and the value network branch outputs the state value estimate V(s). The action mask module is embedded at the output of the policy branch, introducing an action mask mechanism to generate an action mask M in real time based on the current MDP environment state. a Filter illegal actions, action mask M a ∈{0,1} |A| Precise encoding of hardware constraints, action mask M a The definition of is:

[0123]

[0124] This action masking mechanism ensures that the agent only selects legal actions, avoiding violations of hardware constraints from the source, and is key to ensuring the feasibility of the mapping scheme.

[0125] The agent receives the current state space of the Markov decision process environment. After encoding by the input layer, the state vector s is processed sequentially through the fully connected backbone layer and the GNN. The policy network branch outputs the original action probability distribution, which is then filtered by the action mask module to obtain legal actions. The legal actions are then executed, and the state is updated. The value network synchronously outputs the state value estimate, and the next state s′ is generated through the state transition function. The immediate reward is then calculated by the multi-objective weighted reward function, and the long-term cumulative reward is obtained by weighted summation according to the discount factor. Finally, the advantage function is calculated through generalized potential estimation. Among them, the dominance function Used to measure action a t The degree to which an action is better than average depends directly on long-term cumulative rewards, i.e.:

[0126]

[0127] in, , The value of an action is the value of performing action a. t The expected value of long-term cumulative rewards in the future; V(s) t Let be the state value, which is the expected long-term cumulative reward of randomly selected actions in the current state. In engineering practice, the GAE (Generalized Approximation of Values) form is used for efficient approximation calculation, as follows:

[0128]

[0129] In the formula, The dominant cutoff coefficient is λ = 0.95. For time-series difference residuals; where:

[0130]

[0131] In the formula, For instant rewards.

[0132] Policy update: By fixing the policy parameters θ from the previous round old =θ, the current policy parameter θ is updated by minimizing the clipped objective function, and the policy update step size is restricted to the interval [0.8, 1.2]; where: the clipped objective function is:

[0133]

[0134] In the formula, The value of the clipped objective function. For strategy ratio, For editing parameters, =0.2, used to limit the fluctuation range of the strategy ratio. To avoid strategy crashes caused by excessively large strategy updates, This is the clipping function.

[0135] By substituting the aforementioned advantage function value into the clipped objective function, gradient descent optimization is completed, ensuring that each update is within a safe range. At the same time, the fluctuation range of the average instantaneous reward after a series of preset training iterations (e.g., 100 times) converges quickly, and the latest agent is output as the optimal mapping strategy to optimize the model.

[0136] For example, in this embodiment of the application, a course-based learning training method is adopted (phased implementation to ensure smooth training convergence): the agent is trained step by step in three phases, and the environment configuration, training focus, and convergence criteria for each phase are clearly defined and implemented. Furthermore, the initialization parameters of subsequent phases are inherited from the previous phase to avoid policy oscillations, as detailed below:

[0137] Phase 1: Training in an Ideal Fully Connected Chip Environment (Basic Introduction):

[0138] Environment configuration: shielding chip topology constraints (assuming all physical bits are fully connected, and the adjacency matrix A is a matrix of all 1s), shielding hardware dynamic noise, and retaining only the subset A of initial quantum bit allocation actions. map .

[0139] Training requirements: Enable the agent to master basic quantum bit allocation logic, learn the optimal initial scheme for allocating logical bits to physical bits, without considering SWAP gate scheduling, and understand the core fidelity objective of α=0.51 in the reward function.

[0140] Training parameters: number of rounds Learning rate Batch size = 32, discount factor γ d =0.95.

[0141] Convergence criterion: The average reward value fluctuation over 100 consecutive training rounds is less than 0.01.

[0142] The first stage output is the trained basic policy model θ1, which serves as the initialization parameter for the next stage to ensure the implementation of basic capabilities.

[0143] Phase Two: Static Chip Topology Training (Advanced)

[0144] Environment configuration: Enable real chip topology constraints (adjacency matrix A is the real chip topology), enable SWAP gate scheduling action subset A. swap It still shields dynamic hardware noise.

[0145] Training requirements: The agent should learn the SWAP gate scheduling strategy under topological constraints, solve the problem that the entanglement relationship between logical bits cannot be directly realized on physical bits, learn to adjust the position of physical bits through SWAP gates to satisfy the execution constraints of the two quantum gates, and understand the SWAP gate penalty target of γ=0.19 in the reward function.

[0146] Training parameters: number of rounds Learning rate Batch size = 64, initialization parameter is θ1, discount factor γ d =0.95.

[0147] Convergence criterion: The average reward value fluctuation over 100 consecutive training rounds is less than 0.01.

[0148] The second stage output is the trained advanced policy model θ2, which serves as the initialization parameter for the next stage to ensure the implementation of advanced capabilities.

[0149] Phase 3: Full Hardware Constraint Training (Global Optimum):

[0150] Environment configuration: Enable full hardware constraints and enable all action subsets.

[0151] Training requirements: The agent should learn a globally optimal strategy that balances multiple objectives, including high fidelity (α=0.51), short execution time (β=0.2), and low hardware overhead (γ=0.19, δ=0.1), to adapt to the dynamic characteristics of real hardware.

[0152] Training parameters: number of rounds Learning rate Batch size = 64, initialization parameter is θ2, discount factor γ d =0.95, PPO editing parameter=0.2.

[0153] Convergence criterion: The average reward value fluctuation over 100 consecutive training rounds is less than 0.01.

[0154] Third-stage output: The final globally optimal policy model after training. This is used for generating subsequent mapping schemes.

[0155] After each training phase is completed, a policy freeze verification is performed to ensure that the core capabilities of that phase have been mastered and to avoid policy oscillations caused by cross-phase training. This is the key to enabling the agent to efficiently learn the globally optimal policy.

[0156] After all three stages of training are completed, save the final policy model. After completing the training of the intelligent agent, the model can be directly used to generate mapping schemes for real quantum circuits.

[0157] In some embodiments, the specific process of "obtaining the current logic circuit to be mapped and the current quantum chip parameters corresponding to the current logic circuit to be mapped, and generating the optimal qubit mapping scheme for the current logic circuit to be mapped by combining the optimal mapping strategy optimization model" in step S4 includes: obtaining the current logic circuit to be mapped and the current quantum chip parameters corresponding to the current logic circuit to be mapped, and determining the current quantum circuit dependency graph based on the current logic circuit to be mapped; determining the current state space corresponding to the current logic circuit to be mapped based on the current quantum circuit dependency graph and the current quantum chip parameters; inputting the current state space into the optimal mapping strategy optimization model and outputting the optimal action space of the current logic circuit to be mapped; decoding and deduplicating the optimal action space to obtain the simplified action space; performing legal verification on the simplified action space, and transforming the action space that passes the legal verification into a standardized optimal qubit mapping scheme.

[0158] Understandably, the current logic circuit to be mapped is simplified into a current quantum circuit dependency graph. Based on the current quantum circuit dependency graph and the current quantum chip parameters, the current state space corresponding to the current logic circuit to be mapped is determined. The optimal mapping strategy optimization model outputs the action probability distribution based on the current state space, selects the optimal action through a greedy strategy, and after executing the action, updates the mapping matrix and the next state according to the state transition function P. This process is iterated until all quantum gates have been executed, resulting in the complete original action sequence, i.e., the optimal action space sequence.

[0159] By decoding the optimal action space sequence, the decoding process involves processing each action 'a' in the original action sequence. t Type identification and parameter extraction are performed to establish the correspondence between actions and mapping operations. The specific decoding rules are as follows:

[0160] If a t ∈A map Decoding is done by mapping logical bits li to physical bits p. j The allocation operation extracts the parameter (i,j) to update the element in the i-th row and j-th column of the mapping matrix M;

[0161] If a t ∈A swap Decoding to physical bits p x Physical bit p y The SWAP operation extracts the parameter (x, y) and is used to swap the elements in the x-th column and the y-th column of the mapping matrix M.

[0162] If a t ∈A ctrl : Decode into coupler c kThe control operation of the mapped state v (v is the on / off / adjustment intensity) is used to extract the parameters (k,v) to generate coupler control commands.

[0163] Decoding yields a structured sequence of actions with parameters, laying the foundation for subsequent conversion into a mapping scheme.

[0164] Next, deduplication is performed on the decoded structured action sequence to remove consecutively repeated coupler controls, invalid swaps, and redundant allocation actions. The deduplication rules are as follows:

[0165] Continuous repetitive coupler control actions: if adjacent actions are all coupler c k Mapping to state v, only the first action is retained, and subsequent duplicate actions are deleted (to avoid frequent repeated adjustments of the coupler and reduce hardware overhead).

[0166] Invalid SWAP action: If neither of the two physical bits of a SWAP action is mapped to a logical bit, delete the action (it has no actual mapping meaning, reducing redundant operations).

[0167] Repeated qubit allocation actions: If there are multiple allocation actions for the same logical bit li, only the last valid allocation action is retained (to ensure the uniqueness of the mapping relationship).

[0168] After deduplication, a simplified and effective sequence of actions is obtained, reducing invalid operations and improving the execution efficiency of the mapping scheme.

[0169] Next, the simplified motion space after deduplication is validated for validity. The validation rules are as follows:

[0170] Hardware constraint verification: Check whether the two physical bits of the SWAP action are adjacent (whether they meet the constraints of the adjacency matrix A) and whether the coupler control action meets the adjustment frequency limit (whether it meets the constraints of the hardware dynamic parameters). If they are violated, they are marked as illegal actions.

[0171] Mapping relationship verification: Check whether the mapping matrix M satisfies the constraint that "each logical bit maps to only one physical bit and each physical bit maps to at most one logical bit". If it is violated, it is marked as an illegal action.

[0172] Quantum gate execution verification: Check whether all two quantum gates can be executed on the mapped physical bits (whether there is a direct coupling edge), and mark the violation as an illegal action.

[0173] After successful verification, a valid sequence of actions is obtained. If an illegal action exists, the process is backtracked to the most recent valid state, and the agent is called again to generate supplementary actions until all actions are valid.

[0174] The action space sequence after passing the validity verification is compiled, and the actions are transformed into a standardized optimal mapping scheme M.* =(Q map G sched ,Cc trl ,P perf The specific transformation logic is as follows:

[0175] Quantum bit allocation table Q map Based on the decoded qubit allocation and swap operations, the final logical bit to physical bit mapping relationship is extracted and presented in tabular form to ensure clarity and traceability.

[0176] Quantum gate scheduling time table G sched Based on the quantum circuit dependency graph and action sequence, the execution time slot, execution physical bit, and required SWAP gate operation of each quantum gate are determined to form a timing scheduling scheme to ensure that the quantum gates are executed efficiently according to causal relationships.

[0177] Coupler control instruction table C ctrl Based on the decoded coupler control actions, coupler control instructions that can be recognized by the quantum chip are generated, including the controlled object, control state, and execution time, to ensure that the coupler works accurately as required.

[0178] Performance Prediction Parameter Table P perf Based on the reward function and evaluation formula, predict the circuit fidelity F of the mapping scheme. pred Execution time T pred Resource efficiency E res These parameters provide a reference for subsequent performance evaluation.

[0179] Finally, the mapping scheme is parsed into control instructions that the quantum chip can recognize (such as the QASM instruction set or the chip's native instruction set) to ensure that the scheme can be executed directly on the actual quantum chip.

[0180] In some embodiments, step S4, which involves "obtaining the current logic circuit to be mapped and the current quantum chip parameters corresponding to the current logic circuit to be mapped, and generating the optimal qubit mapping scheme for the current logic circuit to be mapped by combining the optimal mapping strategy optimization model," further includes: determining multi-dimensional performance evaluation indicators based on the optimal qubit mapping scheme; wherein the multi-dimensional performance evaluation indicators include at least one of circuit fidelity, execution time, constraint satisfaction rate, resource efficiency, and robustness indicators; if any of the multi-dimensional performance evaluation indicators fails to reach a preset indicator threshold, the multi-dimensional performance evaluation indicators are fed back to the optimal mapping strategy optimization model, the reward weight of the optimal mapping strategy optimization model is adjusted, and the training process of the optimal mapping strategy optimization model is re-executed until all multi-dimensional performance evaluation indicators reach the preset indicator threshold, thus obtaining the latest qubit mapping scheme updated as the optimal qubit mapping scheme.

[0181] For example, a multi-dimensional performance evaluation system is established to comprehensively evaluate the mapping scheme from five core dimensions: circuit fidelity, execution time, constraint satisfaction rate, resource efficiency, and robustness indicators. The mathematical definitions of each evaluation indicator are as follows:

[0182] Circuit fidelity F eval : Measures the correctness of quantum circuit execution under the mapping scheme, with a value range of [0,1]. The closer to 1, the higher the fidelity. The mathematical expression is:

[0183]

[0184] In the formula, K is the number of evaluation samples (preferred). ), The actual circuit fidelity of the k-th evaluation sample is obtained through quantum chip measurement or high-precision quantum simulation; the circuit fidelity F eval The threshold of the index F thresh ≥0.85.

[0185] Execution time T eval The mathematical expression for measuring the execution efficiency of a quantum circuit under a mapping scheme is:

[0186]

[0187] In the formula, The total number of time slots for the circuit to execute. Let T be the execution duration of the t-th time slot (consisting of the quantum gate execution time and the SWAP gate overhead). eval The threshold of the index T thresh The value is 150 μs.

[0188] Constraint satisfaction rate C sat The mathematical expression for measuring the degree to which a mapping scheme adheres to hardware constraints is:

[0189]

[0190] In the formula, For the number of legal actions, Let C be the total number of actions and the constraint satisfaction rate. sat The threshold of the index C thresh The value is 1, which means that the mapping scheme must fully satisfy the hardware constraints.

[0191] Resource efficiency E res The mathematical expression for measuring the resource utilization efficiency of a mapping scheme is:

[0192]

[0193] In the formula, The line depth for the final mapping scheme, This represents the original line depth. This represents the total number of SWAP gates used. The resource efficiency Eres threshold value is E. thresh It is 0.75.

[0194] Robustness index R rob The mathematical expression for measuring the adaptability of a mapping scheme to fluctuations in hardware parameters is:

[0195]

[0196] In the formula, Evaluate the fidelity of the circuit under the i-th perturbation scenario (perturbation scenarios include qubit decoherence time fluctuations, gate error rate fluctuations, etc.). To evaluate the fidelity of the circuit in a baseline scenario, the robustness index R is used. rob The threshold value for the indicator, Rthresh, is 0.9.

[0197] According to the above formula, the circuit fidelity, execution time, constraint satisfaction rate, resource efficiency and robustness indicators are calculated in sequence. Each indicator is compared with its own preset indicator threshold. If all indicators meet the standard, the final optimized mapping scheme is output; if any indicator fails to meet the standard, the feedback optimization process is initiated.

[0198] The feedback optimization process involves using the evaluation results (the specific values ​​of the indicators that did not meet the targets) as additional reward signals, inputting them into the training process of the optimal mapping strategy optimization model. This adjusts the reward weights of the corresponding targets in the reward function; for example, if the fidelity target is not met, the reward weight for circuit fidelity is increased. If the execution time exceeds the limit, the penalty weight for the number of SWAP gates will be increased. If the constraint satisfaction rate fails to meet the target, the penalty weight for increasing the number of WAP gates will be increased. Adjustable coupler control number of penalty weights If resource efficiency fails to meet the standard, the penalty weight for the number of SWAP gates will be increased. and line depth penalty weight If the robustness index fails to meet the standard, the reward weight for circuit fidelity will be increased. After retraining for 500-1000 rounds, a new mapping scheme is generated and evaluated again until all indicators meet the standards, at which point the final optimal qubit mapping scheme is output. This comprehensively integrates the static topological constraints (connectivity) and dynamic hardware characteristics of the quantum chip. Through the dual guarantees of action masking and reward / penalty mechanisms, it ensures that the generated mapping scheme strictly meets hardware constraints and can be directly executed on actual chips. Furthermore, through performance evaluation and feedback mechanisms, the mapping strategy can be continuously optimized as hardware performance changes and circuit types expand, adapting to new quantum chips and quantum circuits without manual intervention.

[0199] Based on the same inventive concept, this application also provides a quantum circuit mapping system based on deep reinforcement learning for implementing the quantum circuit mapping method based on deep reinforcement learning described above.

[0200] The solution provided by this system is similar to the solution described in the above method. Therefore, the specific limitations of one or more embodiments of the quantum circuit mapping system based on deep reinforcement learning provided below can be found in the limitations of the quantum circuit mapping method based on deep reinforcement learning above, and will not be repeated here.

[0201] like Figure 3 As shown in the embodiments of this application, a quantum circuit mapping system based on deep reinforcement learning is also provided, including:

[0202] The dependency graph transformation module 100 is used to obtain the original logical quantum circuit, parse and simplify the original logical quantum circuit into a ZX-graph, and transform the ZX-graph into a quantum circuit dependency graph.

[0203] Environment construction module 200 is used to acquire quantum chip parameters and construct a Markov decision process environment based on the quantum circuit dependency graph and quantum chip parameters;

[0204] The optimization model training module 300 is used to train a deep reinforcement learning agent in a Markov decision process environment to obtain an optimal mapping policy optimization model.

[0205] The mapping scheme optimization module 400 is used to obtain the current logic circuit to be mapped and the current quantum chip parameters corresponding to the current logic circuit to be mapped, and generate the optimal quantum bit mapping scheme for the current logic circuit to be mapped by combining the optimal mapping strategy optimization model.

[0206] In some embodiments, the dependency graph transformation module 100 is used for:

[0207] Each single quantum gate in the original logical quantum circuit is mapped to a single node in the ZX-graph, and each double quantum gate in the original logical quantum circuit is mapped to a node and a first directed edge in the ZX-graph. Node parameters are labeled for each single node and node to form a parameterized ZX-graph. The first directed edge is used to characterize the entanglement relationship between qubits.

[0208] Based on the spider fusion, boundary elimination, and phase cancellation rules of ZX calculus, the parameterized ZX-graph is optimized and simplified to obtain a logically equivalent simplified ZX-graph.

[0209] Each node in the simplified ZX-graph is mapped to a node in the quantum circuit dependency graph, and the causal dependencies between quantum gates are used as the second directed edge in the quantum circuit dependency graph to construct a quantum circuit dependency graph that reflects the constraints on the execution order of quantum gates.

[0210] In some embodiments, the environment building module 200 includes:

[0211] The state space definition module is used to determine multiple feature vectors of the current quantum mapping scenario based on the quantum circuit dependency graph and quantum chip parameters, and then standardize and concatenate the multiple feature vectors of the current quantum mapping scenario to form a state space.

[0212] The action space definition module is used to determine the action space, including the initial allocation action of qubits, the SWAP gate scheduling action, and the tunable coupler control action;

[0213] The state transition and reward definition module is used to define the state transition function as a deterministic transition, and to construct a multi-objective weighted reward function based on the quantum gate execution fidelity as the reward, and the circuit depth, the number of SWAP gates and the number of tunable coupler control operations as the penalty.

[0214] The process environment determination module is used to construct the Markov decision process environment based on the state space, action space, state transition function, and multi-objective weighted reward function, and by introducing a discount factor.

[0215] In some embodiments, quantum chip parameters include static topology parameters, dynamic calibration parameters, and qubit mapping relationships; feature vectors include chip topology feature vectors, quantum circuit dependency graph feature vectors, qubit mapping relationship feature vectors, and hardware dynamic parameter feature vectors.

[0216] The state space definition module is used for:

[0217] A graph attention network is used to extract features from a quantum circuit dependency graph to obtain the features of all nodes in the quantum circuit dependency graph. The features of all nodes in the quantum circuit dependency graph are then globally pooled to obtain the feature vector of the quantum circuit dependency graph.

[0218] By using static topology parameters, an adjacency matrix is ​​constructed, and a Laplacian matrix is ​​constructed from the adjacency matrix. The Laplacian matrix is ​​then subjected to eigenvalue decomposition, and the first 32 dimensions of the Laplacian eigenvectors are extracted and fused with the adjustable coupler position code to obtain the chip topology feature vector.

[0219] After normalizing the dynamic calibration parameters, they are spliced ​​together to form a feature vector of hardware dynamic parameters;

[0220] A mapping matrix is ​​constructed based on the qubit mapping relationship, and the mapping matrix is ​​vectorized to obtain the qubit mapping relationship feature vector;

[0221] The chip topology feature vector, quantum circuit dependency graph feature vector, qubit mapping relationship feature vector, and hardware dynamic parameter feature vector are standardized and then concatenated to form a state space.

[0222] In some embodiments, the optimized model training module 300 is used for:

[0223] Construct an agent based on the PPO algorithm that is jointly trained by a policy network and a value network. The agent is a shared backbone structure that incorporates an action masking mechanism and is fused with a graph neural network and a fully connected network.

[0224] Based on the PPO algorithm, the agent selects and executes legal actions from the action probability distribution output by the policy network according to the current state space of the Markov decision process environment and the action masking mechanism.

[0225] After a legal action is performed, the state space is updated through a state transition function, and the immediate reward is calculated through a multi-objective weighted reward function. The long-term cumulative reward after performing the legal action is calculated in combination with a discount factor.

[0226] By using generalized advantage estimation, the advantage function value is updated based on the long-term cumulative reward. Combined with the updated advantage function value, the parameters of the policy network and value network are updated by minimizing the clipped objective function until the fluctuation range of the average instantaneous reward for a preset number of training iterations tends to converge. Then, the latest agent is output as the optimal mapping policy optimization model.

[0227] In some embodiments, the mapping scheme optimization module 400 is used for:

[0228] Obtain the current logic circuit to be mapped and the corresponding current quantum chip parameters, and determine the current quantum circuit dependency graph based on the current logic circuit to be mapped;

[0229] Based on the current quantum circuit dependency graph and the current quantum chip parameters, determine the current state space corresponding to the current logic circuit to be mapped;

[0230] Input the current state space into the optimal mapping strategy optimization model, and output the optimal action space of the current logic circuit to be mapped;

[0231] After decoding and deduplication of the optimal action space, a simplified action space is obtained;

[0232] The simplified action space is validated for legality, and the action space that passes the validation is transformed into a standardized optimal qubit mapping scheme.

[0233] In some embodiments, the system further includes: a feedback optimization module, used for:

[0234] Based on the optimal qubit mapping scheme, multi-dimensional performance evaluation indicators are determined; among them, the multi-dimensional performance evaluation indicators include at least one of the following: circuit fidelity, execution time, constraint satisfaction rate, resource efficiency, and robustness.

[0235] If any of the multi-dimensional performance evaluation metrics fails to reach the preset threshold, the multi-dimensional performance evaluation metrics are fed back to the optimal mapping strategy optimization model. The reward weight of the optimal mapping strategy optimization model is adjusted, and the training process of the optimal mapping strategy optimization model is re-executed until all multi-dimensional performance evaluation metrics reach the preset threshold, and the latest quantum bit mapping scheme is obtained and updated as the optimal quantum bit mapping scheme.

[0236] like Figure 4 As shown, this application provides an electronic device. The electronic device 10 includes a memory 20 and a processor 30. The memory 20 stores a computer program. When the computer program is executed by the processor 30, the processor 30 performs the steps of the quantum circuit mapping method based on deep reinforcement learning as described in the above embodiment.

[0237] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed, implements the steps of the quantum circuit mapping method based on deep reinforcement learning as described in the above embodiments.

[0238] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, electronic devices, and computer storage media described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0239] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product or device.

[0240] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0241] In the embodiments provided by this invention, it should be understood that the disclosed systems, electronic devices, computer storage media, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units through some interfaces, and may be electrical, mechanical, or other forms.

[0242] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0243] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0244] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for executing all or part of the steps of the methods described in the various embodiments of the present invention through a computer device (which may be a personal computer, a server, or a network device, etc.). The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0245] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A quantum circuit mapping method based on deep reinforcement learning, characterized in that, include: Obtain the original logic quantum circuit, analyze and simplify the original logic quantum circuit into a ZX-graph, and transform the ZX-graph into a quantum circuit dependency graph, including: Each single quantum gate in the original logical quantum circuit is mapped to a single node in the ZX-graph, and each double quantum gate in the original logical quantum circuit is mapped to a node and a first directed edge in the ZX-graph. Node parameters are labeled for each single node and the node to form a parameterized ZX-graph; wherein, the first directed edge is used to characterize the entanglement relationship between qubits. Based on the spider fusion, boundary elimination, and phase cancellation rules of ZX calculus, the parameterized ZX-graph is optimized and simplified to obtain a logically equivalent simplified ZX-graph. Each node in the simplified ZX-graph is mapped to a node in the quantum circuit dependency graph, and the causal dependency between each quantum gate is used as the second directed edge in the quantum circuit dependency graph to construct the quantum circuit dependency graph that reflects the quantum gate execution order constraint. Obtaining quantum chip parameters, and constructing a Markov decision process environment based on the quantum circuit dependency graph and the quantum chip parameters, including: Based on the quantum circuit dependency diagram and the quantum chip parameters, multiple feature vectors of the current quantum mapping scenario are determined, and the multiple feature vectors of the current quantum mapping scenario are standardized and then concatenated to form a state space; Determining the action space includes the initial allocation of qubits, the scheduling of SWAP gates, and the control of tunable couplers; Define the state transition function as a deterministic transition, and construct a multi-objective weighted reward function based on the quantum gate execution fidelity as the reward, and the circuit depth, the number of SWAP gates and the number of tunable coupler controls as the penalty. Based on the state space, the action space, the state transition function, and the multi-objective weighted reward function, and by introducing a discount factor, the Markov decision process environment is constructed. The quantum chip parameters include static topology parameters, dynamic calibration parameters, and qubit mapping relationships; the feature vectors include chip topology feature vectors, quantum circuit dependency graph feature vectors, qubit mapping relationship feature vectors, and hardware dynamic parameter feature vectors; the process of determining multiple feature vectors for the current quantum mapping scenario based on the quantum circuit dependency graph and the quantum chip parameters, and then standardizing and concatenating these multiple feature vectors to form a state space, includes: The quantum circuit dependency graph is used to extract features by a graph attention network to obtain the features of all nodes in the quantum circuit dependency graph, and the features of all nodes in the quantum circuit dependency graph are then globally pooled to obtain the feature vector of the quantum circuit dependency graph. Using the static topology parameters, an adjacency matrix is ​​constructed, and a Laplacian matrix is ​​constructed from the adjacency matrix. The Laplacian matrix is ​​then subjected to eigenvalue decomposition, and the first 32 dimensions of the Laplacian feature vector are extracted and fused with the adjustable coupler position code to obtain the chip topology feature vector. After normalizing the dynamic calibration parameters, they are concatenated to form the feature vector of the hardware dynamic parameters; A mapping matrix is ​​constructed based on the quantum bit mapping relationship, and the mapping matrix is ​​vectorized to obtain the feature vector of the quantum bit mapping relationship; The state space is formed by standardizing the chip topology feature vector, the quantum circuit dependency graph feature vector, the quantum bit mapping relationship feature vector and the hardware dynamic parameter feature vector, and then concatenating them. Based on the Markov decision process environment, a deep reinforcement learning agent is trained to obtain an optimal mapping strategy optimization model. Obtain the current logic circuit to be mapped and the corresponding current quantum chip parameters, and combine the optimal mapping strategy optimization model to generate the optimal qubit mapping scheme for the current logic circuit to be mapped.

2. The quantum circuit mapping method based on deep reinforcement learning according to claim 1, characterized in that, The process of training a deep reinforcement learning agent based on the Markov decision process environment to obtain an optimal mapping policy optimization model includes: Construct an agent that is jointly trained by a policy network and a value network based on the PPO algorithm. The agent is a shared backbone structure that incorporates an action masking mechanism and integrates a graph neural network and a fully connected network. Based on the PPO algorithm, the agent selects and executes a legal action from the action probability distribution output by the policy network according to the current state space in the Markov decision process environment and the action masking mechanism. After the legal action is executed, the state space is updated through the state transition function, the immediate reward is calculated through the multi-objective weighted reward function, and the long-term cumulative reward after the legal action is executed is calculated in combination with the discount factor. By estimating the generalized advantage, the advantage function value is updated based on the long-term cumulative reward. Combined with the updated advantage function value, the parameters of the policy network and the value network are updated by minimizing the clipped objective function until the fluctuation range of the average instantaneous reward for a preset number of consecutive training iterations tends to converge. Then, the latest agent is output as the optimal mapping policy optimization model.

3. The quantum circuit mapping method based on deep reinforcement learning according to claim 1, characterized in that, The step of obtaining the current logic circuit to be mapped and the corresponding current quantum chip parameters, and combining the optimal mapping strategy optimization model to generate the optimal qubit mapping scheme for the current logic circuit to be mapped, includes: Obtain the current logic circuit to be mapped and the current quantum chip parameters corresponding to the current logic circuit to be mapped, and determine the current quantum circuit dependency graph based on the current logic circuit to be mapped; Based on the current quantum circuit dependency graph and the current quantum chip parameters, determine the current state space corresponding to the current logic circuit to be mapped; The current state space is input into the optimal mapping strategy optimization model, and the optimal action space of the current logic line to be mapped is output. After decoding and deduplication of the optimal action space, a simplified action space is obtained; The simplified action space is validated for legitimacy, and the action space that passes the validation is transformed into a standardized optimal qubit mapping scheme.

4. The quantum circuit mapping method based on deep reinforcement learning according to claim 1, characterized in that, The process of obtaining the current logic circuit to be mapped and the corresponding current quantum chip parameters, and generating the optimal qubit mapping scheme for the current logic circuit to be mapped by combining the optimal mapping strategy optimization model, further includes: Based on the optimal qubit mapping scheme, multi-dimensional performance evaluation indicators are determined; wherein, the multi-dimensional performance evaluation indicators include at least one of circuit fidelity, execution time, constraint satisfaction rate, resource efficiency, and robustness indicators. If any of the multi-dimensional performance evaluation metrics fails to reach the preset threshold, the multi-dimensional performance evaluation metrics are fed back to the optimal mapping strategy optimization model, the reward weight of the optimal mapping strategy optimization model is adjusted, and the training process of the optimal mapping strategy optimization model is re-executed until all the multi-dimensional performance evaluation metrics reach the preset threshold, and the latest quantum bit mapping scheme is obtained and updated as the optimal quantum bit mapping scheme.

5. A quantum circuit mapping system based on deep reinforcement learning, characterized in that, include: The dependency graph transformation module is used to obtain the original logical quantum circuit, parse and simplify the original logical quantum circuit into a ZX-graph, and transform the ZX-graph into a quantum circuit dependency graph; Obtain the original logic quantum circuit, analyze and simplify the original logic quantum circuit into a ZX-graph, and transform the ZX-graph into a quantum circuit dependency graph, including: Each single quantum gate in the original logical quantum circuit is mapped to a single node in the ZX-graph, and each double quantum gate in the original logical quantum circuit is mapped to a node and a first directed edge in the ZX-graph. Node parameters are labeled for each single node and the node to form a parameterized ZX-graph; wherein, the first directed edge is used to characterize the entanglement relationship between qubits. Based on the spider fusion, boundary elimination, and phase cancellation rules of ZX calculus, the parameterized ZX-graph is optimized and simplified to obtain a logically equivalent simplified ZX-graph. Each node in the simplified ZX-graph is mapped to a node in the quantum circuit dependency graph, and the causal dependency between each quantum gate is used as the second directed edge in the quantum circuit dependency graph to construct the quantum circuit dependency graph that reflects the quantum gate execution order constraint. An environment construction module is used to acquire quantum chip parameters and construct a Markov decision process environment based on the quantum circuit dependency graph and the quantum chip parameters. Obtaining quantum chip parameters, and constructing a Markov decision process environment based on the quantum circuit dependency graph and the quantum chip parameters, including: Based on the quantum circuit dependency diagram and the quantum chip parameters, multiple feature vectors of the current quantum mapping scenario are determined, and the multiple feature vectors of the current quantum mapping scenario are standardized and then concatenated to form a state space; Determining the action space includes the initial allocation of qubits, the scheduling of SWAP gates, and the control of tunable couplers; Define the state transition function as a deterministic transition, and construct a multi-objective weighted reward function based on the quantum gate execution fidelity as the reward, and the circuit depth, the number of SWAP gates and the number of tunable coupler controls as the penalty. Based on the state space, the action space, the state transition function, and the multi-objective weighted reward function, and by introducing a discount factor, the Markov decision process environment is constructed. The quantum chip parameters include static topology parameters, dynamic calibration parameters, and qubit mapping relationships; the feature vectors include chip topology feature vectors, quantum circuit dependency graph feature vectors, qubit mapping relationship feature vectors, and hardware dynamic parameter feature vectors; the process of determining multiple feature vectors for the current quantum mapping scenario based on the quantum circuit dependency graph and the quantum chip parameters, and then standardizing and concatenating these multiple feature vectors to form a state space, includes: The quantum circuit dependency graph is used to extract features by a graph attention network to obtain the features of all nodes in the quantum circuit dependency graph, and the features of all nodes in the quantum circuit dependency graph are then globally pooled to obtain the feature vector of the quantum circuit dependency graph. Using the static topology parameters, an adjacency matrix is ​​constructed, and a Laplacian matrix is ​​constructed from the adjacency matrix. The Laplacian matrix is ​​then subjected to eigenvalue decomposition, and the first 32 dimensions of the Laplacian feature vector are extracted and fused with the adjustable coupler position code to obtain the chip topology feature vector. After normalizing the dynamic calibration parameters, they are concatenated to form the feature vector of the hardware dynamic parameters; A mapping matrix is ​​constructed based on the quantum bit mapping relationship, and the mapping matrix is ​​vectorized to obtain the feature vector of the quantum bit mapping relationship; The state space is formed by standardizing the chip topology feature vector, the quantum circuit dependency graph feature vector, the quantum bit mapping relationship feature vector and the hardware dynamic parameter feature vector, and then concatenating them. The optimized model training module is used to train the deep reinforcement learning agent based on the Markov decision process environment to obtain the optimal mapping strategy optimization model. The mapping scheme optimization module is used to obtain the current logic line to be mapped and the current quantum chip parameters corresponding to the current logic line to be mapped, and generate the optimal quantum bit mapping scheme for the current logic line to be mapped by combining the optimal mapping strategy optimization model.

6. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores a computer program, which, when executed by the processor, causes the processor to perform the steps of the quantum circuit mapping method based on deep reinforcement learning as described in any one of claims 1-4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the steps of the quantum circuit mapping method based on deep reinforcement learning as described in any one of claims 1-4.

Images