AI target detection parallel optimization method for low-power-consumption FPGA heterogeneous system in lunar surface extreme environment

Abstract

The invention discloses an AI target detection parallel optimization method for a low-power-consumption FPGA heterogeneous system in a lunar surface extreme environment, and the method comprises the steps: selecting a lightweight YOLOv5s algorithm as an AI target detection algorithm when an FPGA heterogeneous system is adopted to execute a lunar surface target detection task based on the intense radiation and energy limited environmental conditions of a lunar surface; quantifying indexes of AI target detection algorithm requirements and hardware capability in the FPGA heterogeneous system, and constructing different FPGA heterogeneous resource dynamic mapping modes according to different requirements to perform resource matching; a dynamic power consumption management mechanism of radiation perception is constructed by combining low power consumption and real-time requirements in a lunar surface extreme environment; by monitoring radiation and energy states in real time, the working mode and resource configuration of the FPGA heterogeneous system are dynamically adjusted, and collaborative optimization of radiation resistance and low power consumption requirements is achieved. According to the method, the FPGA heterogeneous resources and the AI target detection algorithm are matched, the working mode and resource configuration of the system are optimized and dynamically adjusted, and the operation power consumption of the system is minimized.

Description

Technical Field

[0001] This invention relates to the field of FPGA heterogeneous system optimization technology, and more specifically to a parallel optimization method for AI target detection in low-power FPGA heterogeneous systems under extreme lunar environments. Background Technology

[0002] In the process of lunar exploration, lunar surface target detection tasks (such as landing site marker identification, lunar rover path obstacle detection, lunar resource exploration target positioning, etc.) are core technologies to ensure the safe and efficient execution of exploration missions. Their performance directly determines the success rate and scientific output of exploration missions.

[0003] The lunar environment differs significantly from Earth's near-Earth space, representing a typical extreme environment characterized by strong radiation, low power consumption constraints, and real-time requirements. AI target detection technologies (such as YOLO and Faster R-CNN algorithms based on convolutional neural networks) have become the mainstream solution for lunar target detection due to their high accuracy and robustness. However, AI target detection algorithms have extremely high computational complexity, especially in the multiplication and addition operations of convolutional layers and the storage and transmission of feature maps, posing a severe challenge to the parallel processing capabilities of computing systems.

[0004] Field-Programmable Gate Arrays (FPGAs), as a reconfigurable heterogeneous computing chip, have unique advantages such as "customizable hardware, strong parallelism, and controllable power consumption." They provide an ideal hardware platform for solving the problem of AI target detection in the extreme environment of the lunar surface. Their heterogeneous resource architecture can achieve customized acceleration of AI detection algorithms through hardware reconfiguration. At the same time, the static and dynamic power consumption of FPGAs are significantly lower than those of GPUs, and their reliability in strong radiation environments can be improved through radiation hardening design.

[0005] However, current FPGA-based lunar AI detection systems still face two major challenges: First, the scheduling of heterogeneous resources is unreasonable. Traditional static resource allocation schemes do not fully consider the computational characteristics and storage requirements of each module in the AI ​​detection algorithm, resulting in low FPGA resource utilization, with some resources overloaded while others are idle. This affects the real-time performance of the detection algorithm and causes unnecessary power consumption. Second, there is a lack of coordinated optimization between radiation resistance and low power consumption. Existing radiation resistance designs often adopt conservative strategies such as "overall frequency reduction" and "redundancy backup." Although these strategies can improve the system's anti-interference capability, they can lead to increased overall power consumption or increased hardware resource usage, failing to achieve coordinated optimization of "anti-interference performance, low power consumption requirements, and real-time requirements."

[0006] Therefore, optimizing FPGA heterogeneous systems to meet the needs of AI target detection tasks in extreme environments is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of the above problems, the present invention is proposed to provide a parallel optimization method for AI target detection in a low-power FPGA heterogeneous system under the extreme environment of the lunar surface, which overcomes or at least partially solves the above problems.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: This invention provides a parallel optimization method for AI target detection in a low-power FPGA heterogeneous system under extreme lunar conditions, including: Given the strong radiation and energy-constrained environment on the lunar surface, when using an FPGA heterogeneous system to perform lunar target detection tasks, the lightweight YOLOv5s algorithm is selected as the AI ​​target detection algorithm. The indicators of AI target detection algorithm requirements and hardware capabilities in the FPGA heterogeneous system are quantified, and different dynamic mapping methods for FPGA heterogeneous resources are constructed according to different requirements to perform resource matching. To meet the requirements of low power consumption and real-time operation in the extreme environment of the lunar surface, a dynamic power management mechanism based on radiation sensing is constructed. By monitoring radiation and energy status in real time, the working mode and resource configuration of the FPGA heterogeneous system are dynamically adjusted to achieve synergistic optimization of radiation resistance and low power consumption requirements.

[0009] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a parallel optimization method for AI target detection in a low-power FPGA heterogeneous system under extreme lunar environments, which has the following beneficial effects: 1. Achieve efficient collaborative adaptation between algorithm and hardware: By constructing a refined mapping model between the YOLOv5s target detection algorithm and FPGA heterogeneous resources, the convolutional layer, NMS non-maximum suppression layer and feature cache layer are matched to the DSP digital signal processing unit, LUT logic unit and BlockRAM block random access memory, respectively, which significantly improves the utilization of hardware resources and avoids the uneven load and energy waste caused by traditional static allocation.

[0010] 2. Achieved triple synergistic optimization of radiation resistance, low power consumption and real-time performance: Proposed a dynamic power consumption management mechanism based on radiation sensing, integrating real-time TID radiation monitoring and battery remaining capacity assessment, dynamically switching nine working modes to meet the comprehensive requirements of long-term lunar missions for high reliability, low power consumption and real-time response.

[0011] 3. Supports seamless mode switching to ensure task continuity: When switching working modes, an uninterrupted detection and fast response mechanism is adopted. The frequency adjustment, voltage scaling, redundancy strategy activation and power gating are completed during the inter-frame idle period to ensure that the AI ​​target detection pipeline runs uninterruptedly and effectively avoids system interruption or performance drop caused by sudden environmental changes. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0013] Figure 1 This is a flowchart of the parallel optimization method for AI target detection in a low-power FPGA heterogeneous system under extreme lunar conditions provided in this embodiment of the invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This invention discloses a flowchart of a parallel optimization method for AI target detection in a low-power FPGA heterogeneous system under extreme lunar conditions. (Refer to...) Figure 1 As shown, it includes: Given the strong radiation and energy-constrained environment on the lunar surface, when using an FPGA heterogeneous system to perform lunar target detection tasks, the lightweight YOLOv5s algorithm is selected as the AI ​​target detection algorithm. The quantitative indicators of AI target detection algorithm requirements and hardware capabilities in FPGA heterogeneous systems are used to construct different dynamic mapping methods for FPGA heterogeneous resources based on different requirements, and to perform resource matching. To meet the requirements of low power consumption and real-time operation in the extreme lunar environment, a dynamic power management mechanism based on radiation sensing is constructed. By monitoring radiation and energy status in real time, the working mode and resource configuration of the FPGA heterogeneous system are dynamically adjusted to achieve synergistic optimization of radiation resistance and low power consumption requirements.

[0016] This embodiment addresses the core requirements of AI target detection tasks in extreme environments by optimizing an FPGA heterogeneous computing system. The main content includes three aspects: First, analyzing the hardware adaptability of lunar AI target detection algorithms. For typical lunar target detection tasks, the lightweight AI algorithm YOLOv5s, suitable for embedded scenarios, is selected. The computational complexity, data throughput, and storage requirements of each module of the algorithm are analyzed, and an adaptability model of "algorithm module-hardware resources" is established, providing a theoretical basis for the subsequent design of FPGA resource scheduling strategies. Second, considering the characteristics of FPGA heterogeneous resources and the hardware adaptability requirements of each module of the lunar AI detection algorithm, a dynamic mapping strategy for FPGA heterogeneous resources is proposed: For computationally intensive convolutional layer modules, a pipelined convolutional accelerator is designed using the parallel multiply-accumulate capability of DSP units to improve computational efficiency; for logic control intensive NMS layers, the parallel multiply-accumulate capability of logic units is utilized to improve computational efficiency. Flexible programmability is achieved through the design of parallelized NMS processing circuits to reduce detection latency. For high-frequency access feature cache modules, the high bandwidth of BlockRAM is utilized to design a multi-level cache architecture, reducing data access power consumption. This strategy achieves precise matching between "algorithm modules and hardware resources," resulting in an optimal balance between resource utilization and power consumption. Thirdly, in the FPGA parallel circuit design, a radiation detection module is integrated to monitor high-energy particle interference signals in real time. Based on the intensity and range of the interference signals, a dynamic power management mechanism for radiation sensing is constructed: when slight interference is detected, only the operating frequency of non-critical parallel units is reduced to ensure the normal operation of the core detection module; when severe interference is detected, local circuit reconfiguration is triggered to prevent fault propagation. This mechanism ensures detection accuracy while avoiding the power waste of traditional overall frequency reduction mode, achieving synergistic optimization of radiation resistance and low power consumption requirements.

[0017] The implementation steps of this embodiment are described in detail below: The first step is to select an AI object detection algorithm; Extreme environment exploration scenarios impose mandatory constraints on the "lightweight, highly robust, and low-latency" requirements of AI target detection algorithms. On the one hand, lunar surface equipment is limited by energy and size, resulting in limited computing and storage resources, making it impossible to support the real-time operation of complex models (such as YOLOv7 and the full version of Faster R-CNN). On the other hand, the lunar surface experiences complex interferences such as alternating strong and weak light during day and night, crater shadows, and target morphology wear (such as landing site markers), requiring algorithms to have strong environmental adaptability. Considering algorithm accuracy, computational complexity, and hardware adaptability, this embodiment selects the lightweight convolutional neural network YOLOv5s as the core algorithm. This algorithm achieves a detection accuracy of 86.8% on the COCO dataset, has only 7.5M model parameters, fast inference speed, and an accuracy of over 90% for identifying small lunar targets (such as landing site markers and small rocks) with diameters of 0.5-1m, perfectly matching the requirements of lunar exploration missions.

[0018] To achieve deep adaptation between the algorithm and FPGA hardware, this embodiment disassembles the core modules of YOLOv5s, clarifying the computational characteristics, data patterns, and resource requirements of each module. The lightweight YOLOv5s algorithm includes: convolutional layers, NMS (Non-Maximum Suppression) layers, and feature buffer layers. Among them, the convolutional layer is the computationally intensive core unit, generating key features such as target texture and edges through sliding window multiplication and addition operations between the convolutional kernel and the input feature map. Its core characteristics are reflected in high computational complexity and fixed data flow direction; from a computational perspective, the computational cost of a single convolutional layer is calculated as follows:

[0019] in, and These represent the number of channels in the input and output feature maps, respectively. Indicates the kernel size. and These represent the height and width of the output feature map, respectively.

[0020] Taking the third convolutional layer of YOLOv5s as an example, , , , , The amount of computation per batch reaches Multiply-accumulate operations (MACs) account for 18%-22% of the total computation of the algorithm, making them typical computationally intensive modules.

[0021] From a data flow perspective, the convolutional layer follows a fixed pipeline pattern of "input feature map → convolutional kernel → output feature map," with a clear data access pattern, providing a foundation for hardware pipeline parallel acceleration. Regarding accuracy adaptability, experiments show that quantizing data from 32-bit floating-point (FP32) to 16-bit fixed-point (INT16) only decreases detection accuracy by 1.2%-1.5%, while reducing hardware resource consumption by over 40%, providing room for accuracy optimization in FPGA implementations.

[0022] The Non-Maximum Suppression (NMS) layer is a logic-intensive unit. As the post-processing core of YOLOv5s, NMS removes redundant boxes with an overlap greater than 0.5 from candidate detection boxes, retains the target boxes with the highest confidence, and outputs the target category and coordinates. Its core characteristics are strong logical dependencies and dynamic data volume. From a logical perspective, NMS requires four steps: "candidate box sorting → overlap calculation (IoU) → threshold filtering → remaining box update". Each step has a strict sequential dependency. For example, IoU calculation needs to be based on the sorted candidate boxes, and the filtering results need to be fed back to update the remaining boxes. It cannot be accelerated by simple parallel pipelines.

[0023] From a data perspective, the number of candidate boxes dynamically changes with the lunar surface scene. When there are few targets, such as only 1-2 landing site markers, the number of candidate boxes is about 20-50. When the targets are dense, such as in rocky areas, the number of candidate boxes increases to 100-150, requiring the hardware to have flexible logical adaptation capabilities.

[0024] In terms of resource requirements, NMS only accounts for 3%-5% of the total computation of the algorithm, but it has high logic control requirements. For example, the equivalent number of logic gates is about 80K gates. If a fixed hardware architecture is adopted, it is easy to waste logic resources or have excessive latency.

[0025] The feature cache layer is a storage-intensive unit. It temporarily stores feature map data and pre-trained convolutional kernel parameters between convolutional layers in YOLOv5s, serving as a crucial link between "front-end feature extraction" and "back-end object detection." Its core characteristics are high-frequency data access and large-capacity storage requirements. From the perspective of access frequency, intermediate feature maps, such as the outputs of YOLOv5s layers 5 and 8, need to be repeatedly accessed by subsequent 3-5 convolutional layers. If external dynamic random access memory is relied upon for storage, data transfer delays can lead to a system throughput decrease of over 30%.

[0026] In terms of storage capacity, taking the maximum feature map of YOLOv5s as an example, the output of the first layer, , , INT16 quantization, single-sheet storage capacity reaches 3.1MB, and the total storage requirement for intermediate feature maps in the algorithm is approximately 12-15MB. From a power consumption perspective, external storage consumes 5-8 times more power than internal FPGA storage. If all resources are relied upon from external storage, data access power consumption will account for more than 40% of the total system power consumption. Therefore, low-power, high-bandwidth internal storage resources should be prioritized.

[0027] The FPGA heterogeneous resource architecture includes LUT logic units, DSP digital signal processing units, and BlockRAM, making it an ideal hardware platform for meeting the "low power consumption, high parallelism, and strong radiation resistance" requirements of lunar surface AI detection systems. This embodiment selects the Xilinx Kintex UltraScale KU040 as the target chip, which has been radiation hardened (single-particle flip section < 10). -12 With a static power consumption of only 2.8W and a dynamic power consumption as low as 5W, the heterogeneous resource configuration is balanced and fully adapted to the needs of the extreme lunar environment.

[0028] The logic unit is a flexible and programmable control core. The FPGA logic unit is based on a 6-input lookup table (LUT6). Each LUT6 can implement any combinational logic with 6 inputs and 1 output, and can also be configured as a 16-bit flip-flop (FF) to store intermediate results. The KU040 chip contains 19,584 LUT6 units, equivalent to 39,168 4-input lookup tables (LUT4) or 19,584 flip-flops, with a logic resource density of 2.3 Mgates.

[0029] Its core characteristics are high flexibility and weak parallel computing capability. In terms of flexibility, LUTs can quickly implement complex logic control through Verilog HDL, such as candidate box sorting and IoU calculation logic in NMS, and support dynamic adjustment of data processing paths to adapt to the dynamic data volume requirements of NMS modules. In terms of computing power, a single LUT can only implement simple arithmetic operations (such as addition and XOR). If used for multiply-add operations in convolutional layers, multiple LUTs need to be cascaded, and the resource utilization rate is only 1 / 8 to 1 / 10 of that of DSPs, while the operation latency increases by 3 to 5 times. In terms of power consumption, the dynamic power consumption of a single LUT is about 0.5mW, which is only 1 / 4 of that of DSPs, making it suitable for implementing low-power logic control modules.

[0030] The digital signal processing unit is a highly efficient parallel computing core. The DSP is a hardware accelerator designed by the FPGA specifically for multiply-add (MAC) operations. The KU040 contains 288 DSP48E1 units, each of which can perform a single-cycle operation of "25-bit × 18-bit multiplication + 48-bit addition". It supports 1-8 stage pipeline configuration and is compatible with multiple data formats such as FP32, FP16, INT32, and INT16.

[0031] Its core features are high parallel computing efficiency and low power consumption. In terms of computing performance, a single DSP48E1 has a peak computing performance of 1 MAC / cycle. With an 8-stage pipeline configuration, the equivalent computing performance at 100MHz frequency is 800MIPS. When 288 DSPs work in parallel, the theoretical peak performance reaches 230.4 GOPS, far exceeding the total computing requirement of 1.2 GOPS for the YOLOv5s algorithm. In terms of power consumption, a single DSP48E1 consumes only 2.1mW of power dynamically at 100MHz. When achieving the same amount of computation, its power consumption is 1 / 5 of that of a LUT and 1 / 20 of that of a GPU, making it the optimal carrier for multiply-accumulate operations in convolutional layers. In terms of precision adaptation, the DSP supports data bit width pruning (e.g., pruning a 25×18-bit multiplier to 16×16 bits). Experiments show that after pruning, resource utilization is reduced by 30%, power consumption is reduced by 25%, and the precision requirements of YOLOv5sINT16 quantization are fully met. Block RAM is a high-bandwidth, low-latency storage core. BlockRAM is a static random access memory (SRAM) integrated inside the FPGA. The KU040 contains 144 BlockRAM cells, each with a basic capacity of 36Kbit (which can be split into two 18Kbit sub-modules), for a total storage capacity of 5.184Mbit (approximately 648KB).

[0032] Its core features are high bandwidth and low latency. In terms of bandwidth, each BlockRAM supports simultaneous access from two ports (36 bits / cycle read / write bandwidth per port), with a single peak bandwidth of 7.2Gbps at 100MHz, and a total peak bandwidth of 1036.8Gbps for 144 blocks, more than 50 times that of external DDR (approximately 20Gbps). In terms of latency, the BlockRAM access latency is only 1-2 clock cycles (10-20ns), which is 1 / 100 of that of external DDR (100-200ns). The 0-bit capacity significantly reduces the data access latency of the feature cache module. In terms of storage mode, it supports multiple configurations such as single-port RAM, dual-port RAM, and FIFO. For example, intermediate feature maps that are frequently read and written can be configured as dual-port RAM to achieve parallel "read and write" operation, while static convolution kernel parameters can be configured as single-port RAM to reduce resource consumption. In terms of power consumption, the dynamic power consumption of a single BlockRAM is about 1.2mW, and the total power consumption of 144 fully loaded BlockRAMs is only 0.17W, which is 1 / 10 of that of external storage, perfectly matching the low power consumption requirements of the feature cache module.

[0033] The second step is to construct a quantitative indicator system for both algorithm requirements and hardware capabilities. The YOLOv5s algorithm's target detection process can be broken down into convolutional layers for feature extraction, NMS layers for post-processing, and feature caching layers for data support. The required metrics for each module need to be determined based on the actual data volume and computational cost of the lunar target detection scenario, as shown in Table 1 below. Table 1 Requirements for the Algorithm Module

[0034] In this embodiment, the heterogeneous resources of the KU040 FPGA are the core carrier for adapting to the requirements of YOLOv5s. Its performance indicators need to be optimized in combination with chip hardware parameters and the requirements of low power consumption and high reliability, as shown in Table 2: Table 2 Hardware Capability Indicators

[0035] This embodiment constructs different dynamic mapping methods for FPGA heterogeneous resources according to different needs.

[0036] This embodiment focuses on matching computational performance and adapts convolutional layers to DSP.

[0037] Convolutional layers are the computational core of YOLOv5s (accounting for over 85% of the total computation), and their core requirements are "high computational throughput + low latency." Therefore, they need to be adapted to the high parallel multiply-accumulate capabilities of DSPs. The adaptation process involves three steps: Step 1: Quantitative matching of needs and capabilities.

[0038] Taking the third convolutional layer of YOLOv5s (a typical computationally intensive layer) as an example: Algorithm requirements: 128 MMACs per batch, INT16 data bit width (precision loss after quantization is only 1.2%), and real-time requirement of single-frame processing latency ≤25ms.

[0039] Hardware capabilities: A single DSP48E1, configured at 100MHz with an 8-stage pipeline, can achieve a computing performance of 0.8GMMACs / s, and supports INT16×INT16 multiplication + 32-bit addition; Resource requirement calculation: Number of DSPs required = Convolutional layer computational load / (Single DSP performance × Allowable latency) = 128MMACs / (0.8GMMACs / s × 0.025s) = 64 (KU040 has a total of 288 DSPs, and the remaining resources can support other convolutional layers).

[0040] Step 2: Optimize the architecture to enhance compatibility.

[0041] To further improve adaptation efficiency, a "multi-channel parallel pipeline" architecture was designed to specifically address the convolutional layer requirement of "fixed data flow". First, channel splitting is performed: the input feature map is split into 64 parallel streams according to the number of output channels (each stream corresponds to 1 DSP). Each DSP is responsible for the multiplication and addition operations of 1 input channel and 1 output channel, realizing "channel-level parallelism".

[0042] Secondly, pipeline scheduling was implemented: a three-stage pipeline of "input buffer → multiplication → accumulation → output buffer" was designed in the DSP array, with each stage having a delay of 1 clock cycle (10ns@100MHz). The total delay of a single convolutional layer was reduced from 450ns in serial processing to 7.2ns, which fully met the real-time requirements.

[0043] Finally, precision adaptation was performed: the DSP was configured to "16-bit × 16-bit multiplication" mode, and "redundant high-bit pruning logic" was added to the input of the multiplier through Verilog HDL (discarding the sign extension bits after FP32 quantization to INT16). The DSP resource utilization rate was reduced by 30% compared to the FP32 mode, and the dynamic power consumption was reduced by 25%.

[0044] Step 3: Dynamically adjust to cope with resource fluctuations.

[0045] When multiple convolutional layers run in parallel, such as when the backbone network and neck convolution are started simultaneously, resulting in DSP utilization > 90%, dynamic adaptation adjustment is triggered: First, demand identification is performed: the resource status monitoring layer detects that the number of idle DSPs is less than 30 through the Resource Monitor IP, and identifies "shallow convolution" as a non-core computing task.

[0046] Secondly, capability migration was carried out: shallow convolution was migrated to the "lightweight multiply-accumulate unit" implemented by LUT. Although the single operation latency increased from 7.2ns to 21.6ns, the DSP resource supply of core convolutional layers, such as deep convolution, was guaranteed, and the total system throughput only decreased by 5%, avoiding task blocking.

[0047] The adaptation of the NMS (Non-Maximum Suppression) layer to the LUT (Locked Under Test) focuses on "logic flexibility matching." The core requirements of the NMS layer are "dynamic logic adaptation + low control latency," which necessitates adapting to the LUT's "programmable logic + low-latency control" capabilities. The adaptation process involves three steps: Step 1: Quantitative matching of needs and capabilities.

[0048] Taking a high-density scene on the lunar surface (150 candidate boxes) as an example: Algorithm requirements: Logic control complexity of 100K gates, dynamic data volume must support switching of 20~150 candidate boxes, and control latency ≤20ms.

[0049] Hardware capabilities: The KU040 has a total logic density of 2.3Mgate for LUT6, supports rapid reconfiguration of logic paths via Verilog HDL, and controls signal transmission bandwidth of 5GB / s.

[0050] Resource requirement calculation: Number of LUTs required = logic control complexity / logic density of a single LUT = 100Kgate / 0.002Kgate / LUT ≈ 5000. KU040 has a total of 19584 LUTs, and the remaining resources can support the mode switching state machine.

[0051] Step 2: Optimize the architecture to enhance compatibility.

[0052] Design a "configurable state machine + dynamic comparator array" architecture to adapt to the "strong logical dependencies + dynamic data volume" requirements of NMS: Configurable State Machine: Five states are implemented using a LUT: "Candidate Box Reading → Sorting → IoU Calculation → Filtering → Output". The logic circuitry for each state is dynamically adjusted via configuration registers. With 20 candidate boxes: 8 comparators are enabled, logic resources occupy 3000 LUTs, and the delay is 12ms.

[0053] When there are 150 candidate boxes: 32 comparators are automatically enabled (4 groups of 8-stage pipelines), the logic resource usage is 5000 LUTs, and the latency is 18ms, all of which meet the requirement of ≤20ms.

[0054] IoU calculation optimization: "Coordinate difference preprocessing logic" is implemented through LUT. First, the x / y coordinate difference of the candidate box is calculated, and then the absolute value of the difference is multiplied by LUT. This avoids the complex multiplication when directly calculating the area. The logic resource usage is reduced from 80Kgate to 55Kgate, and the latency is reduced from 25ns to 18ns.

[0055] Step 3: Dynamically adjust to cope with energy fluctuations.

[0056] When lunar energy is scarce and solar output is less than 3W, the low-power adaptation of the NMS module is triggered: Demand identification: The energy monitoring unit detected that the SOC is less than 30%, and the power consumption of the NMS module needs to be reduced from 0.6W to 0.4W.

[0057] Capability adjustment: By shutting down the clock signal of idle comparators through the "clock gating logic" of the LUT, the sorting logic is simplified, the logic resource usage is reduced to 2800 LUTs, the dynamic power consumption is reduced to 0.38W, and the detection accuracy is not lost.

[0058] The adaptation of the feature cache layer to BlockRAM is centered on "bandwidth and capacity matching"; the core requirement of the feature cache layer is "high-frequency access with low latency + large-capacity storage", which needs to adapt to the "high bandwidth + low latency" capabilities of BlockRAM. The adaptation process consists of three steps: Step 1: Quantitative matching of needs and capabilities.

[0059] Taking the maximum intermediate feature map of YOLOv5s as an example: Algorithm requirements: storage capacity 3.1MB / page, data access frequency 3.2GB / s, access latency ≤20ns.

[0060] Hardware capabilities: The KU040 has a total BlockRAM capacity of 648MB, a single-unit dual-port bandwidth of 7.2GB / s, and an access latency of 10~20ns.

[0061] Resource requirement calculation: Number of BlockRAMs required = Single feature map storage capacity / Single BlockRAM capacity = 3.1MB / 4.5MB ≈ 1.

[0062] Step 2: Optimize the architecture to enhance compatibility.

[0063] The "L1-L2-L3 three-level cache" architecture is designed to specifically address the issues of "high-frequency access + capacity requirements": The L1 cache is used for the input feature map: 16 BlockRAMs are configured as dual-port RAMs (one for reading and one for writing), with a bandwidth of 7.2GB / s × 16 = 115.2GB / s, which meets the input feature map reading requirement of 2.4GB / s and has a latency of 10ns.

[0064] L2 cache for convolution kernel parameters: Configure 8 BlockRAMs as single-port RAM (read only), bandwidth 3.6GB / s × 8 = 28.8GB / s, meeting the convolution kernel read requirement of 0.3GB / s, reducing resource consumption by 50% compared to dual-port mode; L3 cache is a temporary feature map: 24 BlockRAMs are configured in FIFO mode to achieve "first-in, first-out" temporary data storage, avoiding storage conflicts when multiple convolutional layers access the data at the same time, and the cache hit rate reaches 98.7%.

[0065] Step 3: Dynamically adjust to cope with storage fluctuations When the remaining capacity of BlockRAM is less than 10%, dynamic adaptation is triggered: Demand identification: The resource status monitoring layer detected that the number of free Block RAMs was less than 15, and also identified a "low-frequency access feature map".

[0066] Capability migration: The low-frequency feature map is migrated to the external dynamic random access memory (DDR). The DDR access latency is reduced through the "prefetch cache" logic. At the same time, the original 8 BlockRAM blocks are released to the high-frequency feature map. The storage latency only increases from 19ns to 35ns, and the power consumption increases by less than 0.2W.

[0067] This embodiment defines the degree of matching between demand and capability based on an indicator system. The formula is as follows:

[0068] in, Indicates computational complexity. Indicates computational performance. Indicates the maximum allowable delay. Indicates logic implementation density, Indicates hardware power. Indicates the complexity of logical control. Indicates storage capacity. Indicates storage requirements, Indicates data bandwidth. Indicates the frequency of data access; , , and These represent the weighting coefficients; The higher the matching degree, the better the adaptability.

[0069] The third step is to construct a radiation-sensing dynamic power management mechanism: the RADPM mechanism.

[0070] The RADPM mechanism adopts a closed-loop control architecture of "perception-evaluation-decision-execution", including: (1) Perception layer: Collects multi-dimensional data.

[0071] The sensing layer serves as the mechanism's "data entry point," collecting radiation and energy parameters in real time through three types of monitoring units to provide raw data for subsequent assessments. SEU monitoring unit: Based on the error detection and correction circuit built into the FPGA, it reads the configuration data of CRAM, register and BlockRAM every 1μs, compares it with the pre-stored "golden configuration", records the SEU error count and error location, and has a false negative rate of <1.3%.

[0072] TID evaluation unit: Combines on-chip temperature sensor and leakage current monitoring circuit to estimate cumulative total dose through integral model.

[0073] Energy monitoring unit: Uses INA219 current sensor to collect the output power of solar array and the remaining capacity of battery, with a sampling period of 100ms and SOC estimation error of ±3%.

[0074] (2) Status assessment layer: quantitative level indicators.

[0075] The status assessment layer is the "decision center" of the mechanism, which transforms the raw parameters collected by the perception layer into "level indicators" that can be directly used for strategy selection, specifically including radiation risk level and energy status level.

[0076] The core raw parameters all come from the preprocessing of the perception layer and are defined as follows: Eseu: SEU error count (times / minute), reflecting the "sudden disturbance intensity" of the radiation environment; TID: Total Cumulative Dose (krad (Si)), which reflects the "long-term damage level" of the radiation environment; SOC: Remaining battery capacity (%), reflecting the status of "reserved energy"; Psolar: Solar power output (W), reflecting the ability to supply "on-demand energy".

[0077] Radiation risk levels are classified into three levels—Level 0 (low risk), Level 1 (medium risk), and Level 2 (high risk)—based on the intensity of sudden interference and the degree of long-term damage. Level explanation: Level 0 (low risk): SEU occurrence rate is extremely low, 0.5~1 times / (device). Level 1 (Medium Risk): The TID does not exceed the "low damage threshold" of the KU040 chip, so no additional anti-radiation measures are required, and low power consumption and high performance are prioritized; Level 2 (High Risk): The SEU occurrence rate increases or the TID reaches the "medium damage threshold", and the FPGA leakage current begins to increase, so basic anti-radiation measures (such as BlockRAMEDAC encoding) need to be activated; Level 3 (High Risk): SEU occurs frequently, at 32 times / day, or the TID exceeds the "high damage threshold" (60krad(Si)), so the highest level of anti-radiation measures (such as full-path TMR redundancy) need to be activated.

[0078] The energy status level needs to be divided into three levels: Level 0 (Sufficient), Level 1 (Balanced), and Level 2 (Scarce), based on both reserve energy and immediate energy. The judgment logic is as follows: Level 0 (Sufficient): Battery reserves are sufficient or solar output far exceeds the system's peak power consumption (4.2W), and high-performance mode can be operated; Level 1 (Balanced): Energy supply just matches system demand, and a balance needs to be struck between performance and power consumption; Level 2 (Scarce): Energy reserves are low or solar output is insufficient, and the lowest power consumption mode needs to be activated, retaining only core functions.

[0079] This embodiment constructs nine operating modes based on radiation risk level and energy status level, as shown in Table 3 below: Table 3. Nine Working Modes of the RADPM Mechanism

[0080] (3) Decision-making level: The decision-making level dynamically switches between different working modes based on the radiation risk and energy status generated by the assessment level; (4) Execution layer: hardware configuration and control.

[0081] The execution layer translates the strategies output by the decision layer into specific hardware configuration instructions, which are then executed through the FPGA dynamic interface and the power management unit (PMU). The core control functions include: Clock and voltage control: The clock frequency (40~120MHz) is dynamically adjusted through the PLL IP core, and the core voltage (0.8~1.0V) is configured through the MPM3610 buck converter. The voltage switching adopts a soft-start mechanism (slope 50mV / ms) to avoid impact. Resource power consumption control: Enable clock gating (CGC) to shut down the clock of idle modules and dynamically disable redundant DSPs / LUTs; Radiation protection measures are activated: TMR redundancy, EDAC encoding, or CRAM configuration refresh are activated according to strategy requirements. The activation time of the measures is <1ms to ensure that the detection task is not interrupted.

[0082] This embodiment designs detailed hardware configuration schemes for the four most representative working modes, balancing reliability, power consumption, and performance: S0: High-performance mode Core configuration: 100MHz clock, 1.0V core voltage, full resource enable; Optimization goal: Maximize detection frame rate (≥10FPS), power consumption ≤4.2W; Implementation details: All clock gating is disabled, DSP / LUT / BlockRAM is running at full load, radiation immunity redundancy is disabled to reduce latency, and the YOLOv5s algorithm is fully enabled, including all convolutional layers and the detection head.

[0083] S2: Energy Saving Mode Core configuration: 50MHz clock, 0.8V core voltage, 60% resources enabled; Optimization goals: power consumption ≤ 2.0W, detection frame rate ≥ 5FPS; Implementation details: For non-critical convolutional layers, including shallow feature preprocessing, clock gating is enabled with a 50% duty cycle. BlockRAM is switched to low-power mode, automatic refresh is disabled, the NMS module reduces the number of comparators, and YOLOv5s removes the neck redundant layer.

[0084] S3: Radiation Hardening Mode Core configuration: 80MHz clock, 1.0V core voltage, critical path TMR redundancy; Optimization goals: Improve SEU fault tolerance by 100 times, and increase power consumption by ≤30%; Implementation details: The convolutional layer output register and NMS result register adopt TMR triple redundancy, and the single-event flip is corrected by a majority voter; BlockRAM enables EDAC encoding, and a 7-bit check code is added to every 32 bits of data; CRAM configuration is refreshed every 100ms to clear configuration errors caused by radiation.

[0085] S8: Emergency Hardening - Lowest Power Mode Core configuration: 40MHz clock, 0.8V core voltage, only core detection path retained + full hardening; Optimization goals: power consumption ≤ 1.5W, detection frame rate ≥ 1FPS, mean time between failures (MTBF) ≥ 100 hours; Implementation details: Only the YOLOv5s backbone network is retained, and the neck and head redundant layers are removed. All registers and BlockRAM are protected by TMR+EDAC dual protection. Non-core modules, including data preprocessing and result postprocessing, are completely powered off. The solar array and battery work together to provide power, with priority given to solar energy to reduce battery consumption.

[0086] When switching working modes in this embodiment, the requirements of "uninterrupted detection" and "fast response" must be met. The triggering condition for mode switching is: when the radiation risk level or energy status level changes continuously for more than 3 sampling cycles (e.g., SEU count ≥ 5 times / minute for 3 consecutive minutes), mode switching is triggered; before switching, the current frame detection must be completed to avoid incomplete data.

[0087] The switching process includes: preloading target mode configuration parameters: voltage, frequency, and resource list, and gradually adjusting the clock frequency and voltage (each adjustment ≤20% to avoid voltage overshoot).

[0088] Enabling / disabling radiation protection measures requires TMR configuration to be completed during inter-frame intervals to reduce time consumption.

[0089] The self-test sequence confirms that the function is normal and verifies the validity of the new configuration. If a functional error is detected after switching, i.e., the self-test fails, the system will automatically revert to the previous stable mode and record the error log for subsequent analysis.

[0090] This embodiment discusses the parallel optimization of AI target detection in a low-power FPGA heterogeneous computing system under extreme lunar conditions. Addressing the challenges of strong lunar radiation, low power consumption constraints, and real-time requirements, the lightweight YOLOv5s algorithm is first selected. The characteristics of its convolutional layer (computationally intensive), NMS layer (logic-control intensive), and feature cache layer (storage intensive) are analyzed. Simultaneously, the performance of the heterogeneous resources (DSP, LUT, and BlockRAM) of the Xilinx KU040 FPGA is analyzed, establishing an "algorithm-hardware" adaptation model. Based on this, a dynamic mapping strategy for FPGA heterogeneous resources is designed, achieving precise matching and dynamic power management between modules and hardware resources through a "perception-decision-execution" architecture.

[0091] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0092] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A parallel optimization method for AI target detection in a low-power FPGA heterogeneous system under extreme lunar environment, characterized in that, include: Given the strong radiation and energy-constrained environment on the lunar surface, when using an FPGA heterogeneous system to perform lunar target detection tasks, the lightweight YOLOv5s algorithm is selected as the AI ​​target detection algorithm. The indicators of AI target detection algorithm requirements and hardware capabilities in the FPGA heterogeneous system are quantified, and different dynamic mapping methods for FPGA heterogeneous resources are constructed according to different requirements to perform resource matching. To meet the requirements of low power consumption and real-time operation in the extreme environment of the lunar surface, a dynamic power management mechanism based on radiation sensing is constructed. By monitoring radiation and energy status in real time, the working mode and resource configuration of the FPGA heterogeneous system are dynamically adjusted to achieve synergistic optimization of radiation resistance and low power consumption requirements.

2. The method as described in claim 1, characterized in that, The lightweight YOLOv5s algorithm includes: convolutional layers, NMS non-maximum suppression layers, and feature buffer layers; The heterogeneous resources of the FPGA heterogeneous system include: LUT logic units, DSP digital signal processing units, and BlockRAM block random access memory.

3. The method as described in claim 2, characterized in that, The requirements and hardware capabilities of the AI ​​target detection algorithm in the FPGA heterogeneous system; Specifically, it includes: The hardware capability indicators of the heterogeneous FPGA resources include: the computing performance of the DSP digital signal processing unit in a pipelined configuration, the logic implementation density of the LUT logic unit, and the storage capacity and data bandwidth of the BlockRAM random access memory. The algorithm requirements for the lightweight YOLOv5s algorithm include: the single-batch computation complexity of the convolutional layer, the logical control complexity of the NMS non-maximum suppression layer, and the storage capacity and data access frequency of the feature cache layer.

4. The method as described in claim 3, characterized in that, The aforementioned method for constructing different dynamic mapping methods for heterogeneous FPGA resources according to different needs includes: The computational performance of the DSP digital signal processing unit and the convolutional layer is matched; a multi-channel parallel pipeline architecture is constructed to meet the fixed data flow requirements of the convolutional layer; when the resource utilization rate of the DSP digital signal processing unit is too high as the first preset threshold, the non-core convolutional tasks are migrated to the lightweight multiply-accumulate unit of the LUT logic unit. Logical flexibility matching is performed on the LUT logic unit and the NMS non-maximum suppression layer; a configurable state machine plus dynamic comparator array architecture is constructed to adapt to the dynamic data volume requirements imposed by the logical dependency of the NMS non-maximum suppression layer; when the lunar energy state is below the second preset threshold and is scarce, the clock signal of the idle comparator is turned off through the clock gating logic of the LUT logic unit. The BlockRAM random access memory and the feature cache layer are matched in terms of bandwidth and capacity. A three-level cache architecture based on input feature maps, convolution kernel parameters, and temporary feature maps is constructed to meet the high-frequency access and capacity requirements of the feature cache layer. When the remaining capacity of the BlockRAM random access memory is lower than a third preset threshold, the low-frequency access feature maps are migrated to external dynamic random access memory to reduce the access latency of the external dynamic random access memory and release the BlockRAM random access memory for high-frequency feature maps.

5. The method as described in claim 4, characterized in that, The matching degree of the resource matching process is expressed by the formula: α+β+λ+δ=1 in, Indicates computational complexity. Indicates computational performance. Indicates the maximum allowable delay. Indicates logic implementation density, Indicates hardware power. Indicates the complexity of logical control. Indicates storage capacity. Indicates storage requirements, Indicates data bandwidth. Indicates the frequency of data access; , , and These represent the weighting coefficients for the computational dimension, logical dimension, storage dimension, and read / write speed dimension, respectively.

6. The method as described in claim 1, characterized in that, The dynamic power consumption management mechanism for radiation sensing adopts a closed-loop control architecture from sensing, evaluation, decision-making to execution. Collect multi-dimensional data through the perception layer; The multi-dimensional data includes: SEU error counts and total cumulative radiation dose (TID) caused by single-event flips under extreme lunar conditions, and the remaining battery capacity and solar power output in the FPGA heterogeneous system. The multi-dimensional data is evaluated using an assessment layer to generate corresponding radiation risk levels and energy status levels. The radiation risk levels are classified based on the intensity of sudden interference and the degree of long-term damage, including high, medium, and low risk levels. The energy status levels are classified based on reserve energy and immediate energy, including sufficient, balanced, and scarce status levels. Nine working modes are constructed, and the decision-making level dynamically switches between different working modes based on the radiation risk and energy status generated by the assessment level. The execution layer dynamically adjusts hardware resource configuration and operating parameters based on the working mode selected by the decision layer in order to minimize power consumption.

7. The method as described in claim 6, characterized in that, The nine operating modes are constructed based on the radiation risk level and energy status level, including: High-performance mode S0: Low radiation risk, sufficient energy status; Balanced Mode S1: Low radiation risk, balanced energy status; Energy Saving Mode S2: Low radiation risk, energy shortage; Radiation hardening mode S3: Medium risk level of radiation, sufficient energy status; Hardening and Balancing Mode S4: Risk and energy status balance within the radiation level; Reinforcement and Energy Saving Mode S5: Medium risk in radiation level, energy shortage; Emergency Hardening Mode S6: High radiation risk, sufficient energy. Emergency reinforcement and balancing mode S7: High risk of radiation level, balanced energy status; Emergency reinforcement and energy-saving mode S8: High risk of radiation level and energy shortage.

8. The method as described in claim 7, characterized in that, The low-risk radiation level corresponds to the following state: the SEU error count rate is lower than the first count threshold, the TID does not exceed the chip's low damage threshold, no additional anti-radiation measures are required, and low power consumption and high performance are pursued. The risk status corresponding to the radiation level is as follows: the SEU error count rate is between the first and second count thresholds, or the TID reaches the moderate damage threshold, leakage current begins to appear in the FPGA heterogeneous system, and basic anti-radiation measures need to be initiated. The high-risk radiation level corresponds to the following conditions: the SEU error count rate is higher than the second count threshold or the TID exceeds the high damage threshold, requiring the activation of the highest level of radiation protection measures. The state of sufficient energy is when the battery is more than half full or the solar output exceeds the system's peak power consumption, thus meeting the requirements for high-performance mode operation. The state corresponding to the energy state balance is: when the battery reserve is less than half or the solar output cannot meet the average power consumption of the system, it is necessary to start the balance mode operation that weighs performance and power consumption. The state of insufficient energy is when the battery reserve is less than half full and the solar output cannot meet the average power consumption of the system, requiring the activation of the lowest power consumption energy-saving mode.

9. The method as described in claim 1, characterized in that, The dynamic adjustment of the operating mode and resource configuration of the FPGA heterogeneous system includes: When the change in radiation risk level or energy status level exceeds a preset number of sampling cycles, the working mode switch is triggered, and the current frame detection must be completed before the switch. Load the target mode configuration parameters, gradually adjust the clock frequency and voltage, and enable or disable the corresponding anti-radiation measures; The new configuration is validated through a self-test sequence; if the self-test fails, the switching is stopped and the system reverts to the previous stable mode; if the self-test succeeds, the system switches to the target mode, thus meeting the requirements of uninterrupted detection and rapid response.

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