A forward converter soft switching control circuit

Abstract

The application discloses a forward converter soft switching control circuit and belongs to the technical field of analog integrated circuits, and aims to solve the problems of poor self-adaptation, low precision and difficulty in compensating system delay of an existing dead zone control scheme; the circuit comprises a zero-voltage switching detection circuit, a charge pump phase detector and a voltage-controlled dead zone time circuit, and the three components form a closed-loop negative feedback loop; the zero-voltage switching detection circuit monitors the drain voltage of a main switch tube and generates a ZVS pulse when the voltage is zero; the charge pump phase detector compares the phase difference between the ZVS pulse and the rising edge of a main switch tube driving signal and outputs an error voltage; and the voltage-controlled dead zone time circuit linearly adjusts the dead zone time according to the error voltage, so that the rising edge of the driving signal is aligned with the zero point of the drain voltage. The circuit can automatically compensate the driving delay, adaptively track the working condition change, realize soft switching, reduce the loss, optimize EMI and balance the high frequency and high efficiency of the converter.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, specifically to a soft-switching control circuit for a forward converter, which can be applied to an active clamp forward converter to achieve soft switching by adaptively adjusting the dead time and automatically compensate for the dead time without being affected by changes in external conditions. Background Technology

[0002] With the ever-increasing demands for power density in consumer electronics, industrial control, and new energy sectors, the operating frequency of switching power supplies is constantly trending towards higher frequencies. While higher frequencies can effectively reduce the size and weight of passive components such as inductors and capacitors and improve power supply integration, in traditional hard-switching operation, the voltage and current of the switching transistor overlap during turn-on and turn-off, causing switching losses to increase linearly with frequency. At the same time, voltage spikes and current oscillations generated by high-frequency switching operations exacerbate electromagnetic interference (EMI) problems. This not only requires additional filtering components to meet electromagnetic compatibility standards but also interferes with the normal operation of surrounding sensitive circuits, becoming a core bottleneck restricting the balance between high frequency and high efficiency in switching power supplies.

[0003] To address the switching losses and EMI issues brought about by high-frequency operation, soft-switching technology, especially zero-voltage switching (ZVS) technology, has become a key research direction in the field of switching power supplies. In mainstream topologies such as active-clamped forward converters, ZVS is typically achieved by setting a dead time and utilizing the resonant process formed by the parasitic inductance and capacitance of the converter during the dead time phase. This allows the drain-source voltage of the main switch to drop to zero before it turns on. However, the value of the dead time has a significant impact on system efficiency: if the dead time is too long, the body diode of the main switch will generate additional conduction losses due to prolonged conduction, especially under high-current conditions, where this loss will increase significantly; if the dead time is too short, the main switch will turn on prematurely before the drain-source voltage has completely returned to zero, leading to the recurrence of hard-switching, resulting in severe switching losses and voltage stress, and even damage to the switching devices.

[0004] Existing dead-time control schemes struggle to meet the high-precision adaptive requirements under complex operating conditions. Fixed dead-time schemes, due to their non-adjustable parameters, can only achieve soft switching under specific conditions. When external conditions such as converter output load, input voltage, and ambient temperature change, the dead-time deviates significantly from the optimal value, drastically worsening the soft-switching effect. Model-based predictive control schemes rely on accurate circuit models, but nonlinear variations in parasitic parameters in actual converters can lead to model inaccuracies, resulting in poor control robustness and difficulty adapting to parameter differences between different batches of devices. Schemes based on zero-crossing detection of the rate of change of voltage (dv / dt) can directly capture the switching transistor voltage state, but require high-precision dv / dt sampling. The prototype circuit and signal conditioning module are complex and costly, and cannot compensate for the inherent transmission delay of the drive circuit, resulting in a deviation between the actual dead time and the theoretical calculation value, thus limiting the control accuracy. The dead time control scheme using a digital counter is limited by the clock frequency and counting step, and there are inherent bottlenecks in adjustment accuracy and response speed: if the clock frequency is too low, the dead time adjustment granularity will be coarse, and fine control cannot be achieved; if the clock frequency is too high, it will increase the power consumption and complexity of the digital circuit, and in high-frequency switching scenarios, the counter's response speed is difficult to match the dynamic changes of the switching transistor, which is prone to adjustment lag problems.

[0005] Therefore, there is an urgent need for a control scheme that can achieve high-precision adaptive adjustment of dead time through a simple and reliable circuit structure, while automatically compensating for system delay and adapting to different operating conditions and changes in device parameters, so as to further improve the efficiency and stability of active clamp forward converters. Summary of the Invention

[0006] Based on the above-mentioned technical problems, this application discloses a soft-switching control circuit for a forward converter, including a zero-voltage switching detection circuit, a charge pump phase detector, and a voltage-controlled dead time circuit. The zero-voltage switching detection circuit, the charge pump phase detector, and the voltage-controlled dead time circuit are connected in series to form a closed-loop negative feedback loop.

[0007] The zero-voltage switch detection circuit is used to acquire the drain voltage signal of the main switch in real time, and generate and output a ZVS pulse signal when the drain voltage of the main switch reaches the zero crossing point.

[0008] The input terminal of the charge pump phase detector receives the ZVS pulse signal and the main switch drive signal, respectively, to detect the phase difference between the rising edges of the two signals, and outputs the corresponding error voltage V based on the phase difference. CP ;

[0009] The voltage-controlled dead time circuit receives the error voltage V. CP According to V CPThe voltage amplitude is linearly adjusted to shorten the dead time of the next working cycle, so that the rising edge of the main switch drive signal is precisely aligned with the zero-crossing point of the drain voltage of the main switch, thus achieving soft switching control.

[0010] Preferably, the charge pump phase detector includes a PMOS transistor MP, an NMOS transistor MN, and an integrating capacitor C. CP Charging and discharging current source I charge Charging and discharging current source I discharge The system comprises a first SR latch U1, a second SR latch U2, and an AND gate U3. The Q terminal of the first SR latch U1 is electrically connected to the first input terminal of the AND gate U3, and the QN terminal of the first SR latch U1 is electrically connected to the gate of the PMOS transistor MP. The Q terminal of the second SR latch U2 is electrically connected to the second input terminal of the AND gate U3 and the gate of the NMOS transistor MN, respectively. The R terminals of both the first SR latch U1 and the second SR latch U2 are electrically connected to the output terminal of the AND gate U3. The source of the PMOS transistor MP is connected to the charging / discharging current source I. charge The lower end is electrically connected to the charging / discharging current source I. charge The upper end of the transistor is electrically connected to the power supply VDD; the source of the NMOS transistor MN is connected to the charging / discharging current source I. discharge The upper end is electrically connected to the charging / discharging current source I. discharge The lower end is electrically connected to ground potential; the drain of the NMOS transistor MN and the drain of the PMOS transistor MP are connected to the integrating capacitor C. CP The upper plate is electrically connected, and the integrating capacitor C is... CP The lower electrode is electrically connected to ground potential.

[0011] Preferably, the charge pump phase detector controls the on / off states of the PMOS transistor MP and the NMOS transistor MN through the logical cooperation of the first SR latch U1, the second SR latch U2, and the AND gate U3, thereby switching the charging and discharging current source I. charge For the integrating capacitor C CP Charging mode or charging / discharging current source I discharge For the integrating capacitor C CP The discharge mode causes the integrating capacitor C to... CP An error voltage V is generated at both ends, corresponding to the time difference between the rise edges of the ZVS pulse signal and the main switch drive signal. CP .

[0012] Preferably, the voltage-controlled dead time circuit includes a reset NMOS transistor M. rst Charging capacitor C d Constant current source I d The system consists of an OR gate U1, a third SR latch U2, and a comparator U3; the output of the OR gate U1 is connected to the reset NMOS transistor M. rstThe gate electrical connection of the reset NMOS transistor M; rst The drain of each capacitor is connected to the charging capacitor C. d The upper electrode plate, constant current source I d The lower end of the circuit is electrically connected to the positive input terminal of comparator U3; the reset NMOS transistor M rst The source electrode and charging capacitor C d The lower plates of the constant current source I are all electrically connected to ground potential; d The upper end of the comparator is electrically connected to the power supply VDD; the output of the comparator U3 is electrically connected to the S terminal of the third SR latch U2, and the Q terminal of the third SR latch U2 is electrically connected to the input of the logic OR gate U1.

[0013] Preferably, the operation of the voltage-controlled dead time circuit includes a reset phase and a charging phase, specifically:

[0014] During the reset phase, the OR gate U1 outputs a high level, causing the reset NMOS transistor M to... rst When the circuit is turned on, the charging capacitor Cd is activated by the reset NMOS transistor M. rst Discharge back to the initial state;

[0015] During the charging phase, the OR gate U1 outputs a low level, resetting the NMOS transistor M. rst Turn off, constant current source I d For charging capacitor C d Perform constant current charging until the capacitor C is charged. d The voltage across the terminals reaches the error voltage V CP At this time, comparator U3 outputs a trigger signal to the third SR latch U2, completing one dead time cycle;

[0016] The total dead time of the voltage-controlled dead time circuit includes the charging time of the charging phase, the rise time of the main switch drive signal, and the transmission delay of the drive module itself.

[0017] Compared with the prior art, the technical solution of this application has the following technical effects:

[0018] This invention achieves adaptive and precise control of dead time through a closed-loop negative feedback mechanism, improving the overall performance of the active clamp forward converter. The zero-voltage switching detection circuit captures the zero-crossing point of the drain voltage of the main switch in real time, the charge pump phase detector accurately identifies the phase difference and outputs an error voltage, and the voltage-controlled dead time circuit linearly adjusts the dead time accordingly. The three work together to ensure that the main switch is always turned on at the optimal time, avoiding the increase in body diode conduction loss caused by an excessively long dead time and preventing hard switching loss caused by an excessively short dead time. This significantly reduces switching losses, reduces voltage spikes and current oscillations, effectively optimizes electromagnetic interference, and meets EMI standards without the need for additional filtering components.

[0019] This invention incorporates inherent system delays, such as drive delay, into the feedback loop for automatic compensation, solving the control deviation problem caused by delay in traditional solutions. The circuit adopts a pure analog architecture, eliminating the need for complex models or high-frequency clocks. It can adaptively track changes in parasitic parameters, output current, input voltage, and other conditions, maintaining a stable soft-switching state even under load fluctuations and temperature drift, significantly enhancing robustness. Furthermore, the continuous stepless adjustment characteristics of the analog circuit improve dead-time adjustment accuracy and response speed compared to digital counter solutions. The circuit structure is also simple, reducing chip area and cost, providing reliable support for the design of high-frequency, high-efficiency, and highly integrated switching power supplies.

[0020] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings.

[0021] The above and other objects, advantages and features of this application will become more apparent to those skilled in the art from the following detailed description of specific embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0023] Based on the description of the figures and their corresponding technical content in the document, the titles of the figures are as follows:

[0024] Figure 1 This is an overall system framework diagram of a soft-switching control circuit for a forward converter according to the present invention;

[0025] Figure 2 This is a detailed circuit diagram of the charge pump phase detector in the soft-switching control circuit of a forward converter according to the present invention.

[0026] Figure 3 This is a detailed circuit diagram of the voltage-controlled dead zone in the soft-switching control circuit of a forward converter according to the present invention;

[0027] Figure 4 This is a schematic diagram of the system loop in a soft-switching control circuit for a forward converter according to the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. In the following description, specific details such as specific configurations and components are provided merely to help fully understand the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. In addition, for clarity and brevity, descriptions of known functions and structures are omitted in the embodiments.

[0029] It should be understood that the phrase "an embodiment" or "this embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "an embodiment" or "this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0030] Furthermore, reference numerals and / or letters may be repeated in different examples within this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0031] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" in this article describes another type of relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the related objects before and after it are in an "or" relationship.

[0032] In this article, the term "at least one" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0033] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0034] Example 1

[0035] The following is in conjunction with the appendix Figure 1-4 The soft-switching control circuit of the forward converter of the present invention will be described in further detail. The device naming rules are as follows: M for transistors, C for capacitors, U for logic modules, and I for reference current sources. The parameters are defined as follows: This is the capacitance value of the charge pump integrating capacitor. The capacitance value for the voltage-controlled dead zone charging capacitor. The magnitude of the voltage-controlled dead-zone constant current source current;

[0036] like Figure 1 As shown, the adaptive dead-time control circuit of this invention achieves soft-switching control through a closed-loop negative feedback logic of detection-phase detection-adjustment. The specific process is as follows:

[0037] During the zero-voltage detection phase, the zero-voltage switch detection circuit acquires the drain voltage (SW node) of the main switch in real time. When the voltage drops to the zero-crossing point, the voltage comparison module inside the circuit is triggered to flip, generating and outputting a narrow pulse ZVS signal. The rising edge of this signal precisely corresponds to the moment when the voltage at the SW node crosses zero.

[0038] During the phase error detection stage, the charge pump phase detector receives the ZVS signal and the main switch drive signal (OUT_A). Through its internal logic module and charging / discharging circuit, it converts the time difference between the rising edges of the two signals into the corresponding error voltage V. CP If the rising edge of OUT_A lags behind the rising edge of the ZVS signal, V CP The voltage increases, and vice versa;

[0039] During the dead time adjustment stage, the voltage-controlled dead time circuit uses V CP To control the baseline, the dead time length of the next work cycle is linearly adjusted, when V CP As V increases, the dead time lengthens. CP When the voltage is reduced, the dead time is shortened, so that the rising edge of OUT_A is precisely aligned with the zero-crossing point of the SW node voltage, forming a stable negative feedback closed loop, ensuring that the main switch is always turned on in a zero-voltage state.

[0040] The working principle of a charge pump phase detector, such as... Figure 2 As shown, the charge pump phase detector consists of a PMOS transistor MP, an NMOS transistor MN, and an integrating capacitor C. CP Charging and discharging current source I charge (Right now , (The current amplitude of the charge pump phase detector charging and discharging current source) and I discharge (With I chargeIt consists of a first SR latch U1, a second SR latch U2, and an AND gate U3 (with equal current amplitudes). Its core function is to convert time difference into voltage difference. The specific working process is as follows:

[0041] Initial state: The R terminals of U1 and U2 are both connected to the output of U3. Initially, U3 outputs a low level, U1 and U2 are in the set state, the Q terminal of U1 outputs a high level, and the QN terminal outputs a low level. MP is turned on because its gate is connected to a low level. The Q terminal of U2 outputs a low level, and MN is turned off because its gate is connected to a low level. At this time, I charge For C CP Charging, C CP Upper plate voltage (i.e., V) CP A slow increase;

[0042] Signal triggering and logic control: When the rising edge of the ZVS signal arrives first, the set S terminal of the signal input U2 triggers the set of U2, the Q terminal of U2 flips to a high level, and MN is turned on because its gate is connected to a high level. discharge For C CP Start discharging; when the rising edge of the OUT_A signal arrives first, the set S terminal of the signal input U1 triggers U1 to set, the Q terminal of U1 to flip to high level and the QN terminal to flip to low level, MP is turned on, I charge For C CP When charging is initiated, the logic actions triggered by the two signals correspond to different charging and discharging modes, accurately responding to the phase difference state.

[0043] Error voltage generation: When the rising edges of both the ZVS and OUT_A signals arrive, the Q terminals of U1 and U2 both flip to high level. Both inputs of the AND gate U3 are also high, resulting in a high output. U1 and U2 are reset under the influence of this high-level signal. This process continues until the start of the next working cycle. Throughout this process, C... CP The charging and discharging duration is determined by the time difference between the rising edges of the two signals. Decide, The final V is the time difference between the rising edges of the drive signal and the ZVS signal. CP The voltage value satisfies the formula: ,Right now and They exhibit a linear positive correlation, enabling precise conversion from time difference to voltage difference.

[0044] like Figure 3 As shown, the voltage-controlled dead time circuit consists of a reset NMOS transistor M. rst Charging capacitors constant current source It consists of a logic OR gate U1, a third SR latch U2, and a comparator U3. Its core function is to determine the logic gate based on the logic gate U1. The dead time is adjusted linearly, and the specific working process is as follows:

[0045] Reset Phase: After the clamping transistor's on-time ends, the duty cycle inverted signal PWML toggles to a low level. This signal is input to the logic OR gate U1, and U1 outputs a high level to M. rst The gate, M rst Conduction, By rapidly discharging Mrst, the voltage on the upper plate drops to 0V, and the circuit returns to its initial state.

[0046] Charging phase: When PWML toggles to high level, U1 outputs low level, M rst Shutdown, constant current source start Perform constant current charging. Upper plate voltage (denoted as V) S It increases linearly at a constant rate;

[0047] Dead time trigger: The positive input of comparator U3 is connected to V. S Negative input terminal connected When V S Rise to equal When comparator U3 outputs a high level, it triggers U2 to set, and the Q output of U2 outputs a high level to the input of U1. U1 then outputs a high level again. rst Conduction, Discharge completes one dead time cycle;

[0048] Total dead time composition: where V S Charging from 0V to The duration is the initial dead time. It satisfies the formula: In practical applications, the total dead time... The inherent delay of the drive path needs to be added, and the rise time of the main switch drive signal from low level to the conduction threshold needs to be added. and the transmission delay within the driver module. Therefore, the total dead time satisfies: This ensures that the dead time calculation covers the entire signal path.

[0049] like Figure 4 As shown, to verify the stability of the closed-loop negative feedback system, small-signal analysis of the loop transfer function is required. The specific process is as follows:

[0050] Linear approximation premise: When the phase difference between the rising edges of OUT_A and ZVS signals is sufficiently small (typically less than 10% of the switching period), the system can be approximated as a linear system; if the system loop bandwidth is much lower than the switching frequency... (Usually the loop bandwidth is less than) / 20), which can approximate the periodic regulation behavior of discrete time as a continuous time system, simplifying the analysis model;

[0051] Derivation of the loop transfer function: System loop transfer function Transfer function by charge pump phase detector Transfer function with voltage-controlled dead-time circuit A joint decision, in which Error voltage The ratio of the phase difference to the error phase (i.e.) (Based on the error phase, it is converted into the corresponding error voltage). For error phase and error voltage The ratio (i.e.) Adjusting the corresponding error phase based on the error voltage, and then combining this with the phase transition relationship corresponding to the switching frequency ( The final loop transfer function satisfies: ;

[0052] From T(s), we know that the system has only one pole at the origin and no zeros in the right half-plane, therefore the system is necessarily stable. In practical parameter design, it is necessary to balance the loop bandwidth and output jitter, and increase... and , reduce With C CP It can increase loop bandwidth and speed up phase adjustment, but it will cause V CP Increased voltage fluctuations lead to increased output signal jitter; conversely, decreased loop bandwidth and slower regulation speed result in more stable output. Parameter trade-offs must be made based on the actual operating conditions of the converter (such as load fluctuation frequency and switching frequency). In typical designs… Values ​​range from 50-200 μA, C CP Values ​​range from 1 to 10 nF. Values ​​range from 10 to 50 μA. A value of 10-100pF can meet the requirements of most active clamp forward converters.

[0053] This detailed description of the embodiment achieves adaptive dead-time control through closed-loop negative feedback. The zero-voltage switching detection circuit accurately captures the zero-crossing point of the drain voltage of the main switch, and the charge pump phase detector converts the signal phase difference into an error voltage. The voltage-controlled dead-time circuit linearly adjusts the dead-time duration accordingly, ensuring that the main switch is always conducting with zero voltage, significantly reducing switching losses and diode conduction losses. Simultaneously, the system incorporates drive delay into feedback compensation to adapt to changes in parasitic parameters, load, and other operating conditions. Furthermore, the pure analog architecture improves adjustment accuracy and response speed, optimizes electromagnetic interference, and simplifies the circuit structure, providing reliable support for the high-frequency, high-efficiency operation of the converter.

[0054] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any changes, modifications, substitutions, integrations, and parameter changes made to these embodiments within the spirit and principles of the present invention, without departing from the principles and spirit of the present invention, through conventional substitutions or to achieve the same function, fall within the scope of protection of the present invention.

Claims

1. A soft-switching control circuit for a forward converter, characterized in that, Applied to an active clamp forward converter topology, it includes a zero-voltage switching detection circuit, a charge pump phase detector, and a voltage-controlled dead time circuit. The zero-voltage switching detection circuit, the charge pump phase detector, and the voltage-controlled dead time circuit are connected in series to form a closed-loop negative feedback loop for automatic compensation of drive transmission delay. The zero-voltage switch detection circuit is used to acquire the drain SW node voltage signal of the main switch in real time. When the drain voltage of the main switch reaches the zero crossing point, it generates and outputs a narrow pulse ZVS pulse signal. The rising edge of the ZVS pulse precisely corresponds to the zero crossing moment of the drain voltage. The input terminal of the charge pump phase detector receives the ZVS pulse signal and the main switch drive signal, respectively, to detect the phase difference between the rising edges of the two signals, and outputs the corresponding error voltage VCP according to the phase difference, satisfying the formula: ,in For the charge pump charging and discharging current, This is the capacitance value of the integrating capacitor. The time difference between the rising edges of the two signals; The charge pump phase detector includes a PMOS transistor MP, an NMOS transistor MN, and an integrating capacitor C. CP Charging and discharging current source I charge Charging and discharging current source I discharge The first SR latch U1, the second SR latch U2, and the logic AND gate U3; The Q terminal of the first SR latch U1 is electrically connected to the first input terminal of the AND gate U3, the S terminal of the first SR latch U1 is connected to the main switch drive signal, and the QN terminal of the first SR latch U1 is electrically connected to the gate of the PMOS transistor MP; the Q terminal of the second SR latch U2 is electrically connected to the second input terminal of the AND gate U3 and the gate of the NMOS transistor MN, respectively, and the S terminal of the second SR latch U2 is connected to the ZVS pulse signal; the R terminals of the first SR latch U1 and the second SR latch U2 are both electrically connected to the output terminal of the AND gate U3; The source of the PMOS transistor MP is connected to the charging / discharging current source I. charge The lower end is electrically connected to the charging / discharging current source I. charge The upper end of the transistor is electrically connected to the power supply VDD; the source of the NMOS transistor MN is electrically connected to the upper end of the charging / discharging current source Idischarge. discharge The lower end of the capacitor is electrically connected to ground potential; the drain of the NMOS transistor MN and the drain of the PMOS transistor MP are both electrically connected to the upper plate of the integrating capacitor CCP, and the lower plate of the integrating capacitor CCP is electrically connected to ground potential. The voltage-controlled dead time circuit receives the error voltage VCP and linearly adjusts the dead time length of the next working cycle according to the voltage amplitude of VCP, so that the rising edge of the main switch drive signal is precisely aligned with the zero-crossing point of the drain voltage of the main switch, thereby realizing soft switching control.

2. The soft-switching control circuit for a forward converter according to claim 1, characterized in that, The charge pump phase detector, through the logical cooperation of the first SR latch U1, the second SR latch U2, and the AND gate U3, controls the on and off states of the PMOS transistor MP and the NMOS transistor MN, thereby switching the charging and discharging current source I. charge For the integrating capacitor C CP Charging mode or charging / discharging current source I discharge For the integrating capacitor C CP The discharge mode causes the integrating capacitor C to... CP An error voltage VCP is generated at both ends, corresponding to the time difference between the rising edges of the ZVS pulse signal and the main switch drive signal.

3. The soft-switching control circuit for a forward converter according to claim 1, characterized in that, The voltage-controlled dead time circuit includes a reset NMOS transistor M. rst Charging capacitor C d Constant current source I d The system consists of an OR gate U1, a third SR latch U2, and a comparator U3. The output of the OR gate U1 is connected to the reset NMOS transistor M. rst The gate electrical connection of the reset NMOS transistor M; rst The drain of each capacitor is connected to the charging capacitor C. d The upper electrode plate, constant current source I d The lower end of the circuit is electrically connected to the positive input terminal of comparator U3; the reset NMOS transistor M rst The source electrode and charging capacitor C d The lower plates of the constant current source I are all electrically connected to ground potential; d The upper end is electrically connected to the power supply VDD; The output of the comparator U3 is electrically connected to the S terminal of the third SR latch U2, and the Q terminal of the third SR latch U2 is electrically connected to the input of the logic OR gate U1. The negative input terminal of comparator U3 is directly connected to the error voltage VCP, and the charging capacitor C d The voltage across the terminals varies with the constant current source I d Linear increase.

4. The soft-switching control circuit for a forward converter according to claim 3, characterized in that, The operation of the voltage-controlled dead-time circuit includes a reset phase and a charging phase, specifically: During the reset phase, the OR gate U1 outputs a high level, causing the reset NMOS transistor M to... rst On, charging capacitor C d By resetting NMOS transistor M rst Discharge back to the initial state; During the charging phase, the OR gate U1 outputs a low level, resetting the NMOS transistor M. rst Turn off, constant current source I d For charging capacitor C d Perform constant current charging until the capacitor C is charged. d When the voltage across the terminals reaches the error voltage VCP, the comparator U3 outputs a trigger signal to the third SR latch U2, completing one dead time cycle. The total dead time of the voltage-controlled dead time circuit comprises the superposition of three fixed delays: the charging duration during the charging phase, the rise time of the main switch drive signal, and the transmission delay of the drive module itself, satisfying the formula: The total dead time is The rise time of the main switch drive signal from low level to the turn-on threshold is required. Transmission delay within the driver module The initial dead time is .

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