Highly reliable flip-chip LED chip and method of manufacturing the same

Abstract

The application relates to the technical field of optoelectronic manufacturing, and particularly discloses a high-reliability flip LED chip and a preparation method thereof. The flip LED chip comprises a substrate, an epitaxial layer, a first insulating layer, a first reflecting layer, a second insulating layer, a P-type metal connecting layer, an N-type metal connecting layer, a third insulating layer, a P-type pad layer and an N-type pad layer; a thermal buffer layer, the first insulating layer, the second insulating layer and the third insulating layer are sequentially stacked on the sidewall and / or the bottom wall of an isolation groove; the thermal expansion coefficient of the thermal buffer layer is smaller than the thermal expansion coefficient of the N-type semiconductor layer and larger than the thermal expansion coefficient of the first insulating layer; and the thermal expansion coefficient of the thermal buffer layer is smaller than the thermal expansion coefficient of the substrate. The reliability of the flip LED chip can be improved by implementing the application.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic manufacturing technology, and in particular to a high-reliability flip-chip and its fabrication method. Background Technology

[0002] During the fabrication of flip-chip LEDs, multiple layers of SiO2 thin films are prepared as protective layers. At the isolation trench, these SiO2 thin films are essentially fabricated directly on the side of the GaN epitaxial layer. During the use of flip-chip LEDs, especially under high current conditions, the junction temperature rises, and after power is cut off, the LEDs cool rapidly. In this process of rapid heating, constant temperature heating, and rapid cooling, microcracks are generated in the SiO2 thin film on the side of the GaN epitaxial layer. This allows moisture to travel along the microcrack channels of the SiO2 thin film directly to the GaN epitaxial layer and react with the GaN, ultimately causing the flip-chip LED to leak and fail. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a highly reliable flip-chip LED chip with strong reliability.

[0004] Accordingly, the present invention also provides a method for preparing the above-mentioned high-reliability flip-chip.

[0005] To address the aforementioned technical problems, this invention provides a highly reliable flip-chip LED, comprising a substrate, an epitaxial layer, a first insulating layer, a first reflective layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, a third insulating layer, a P-type pad layer, and an N-type pad layer stacked on the substrate.

[0006] The epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate. A light-emitting structure, an N-type conductive step, and an isolation trench are formed on the epitaxial layer. The N-type conductive step is disposed on one side of the light-emitting structure. The isolation trench is disposed around the light-emitting structure. The sidewall of the isolation trench exposes the N-type semiconductor layer, and the bottom wall of the isolation trench exposes the substrate.

[0007] A thermal buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer are sequentially stacked on the sidewalls and / or bottom wall of the isolation trench; the thermal expansion coefficient of the thermal buffer layer is less than that of the N-type semiconductor layer and greater than that of the first insulating layer; the thermal expansion coefficient of the thermal buffer layer is less than that of the substrate.

[0008] As an improvement to the above technical solution, the thermal buffer layer includes alternating layers of first SiO2 layer and HfO2 layer, with a period number of 2 to 4.

[0009] The thickness of a single first SiO2 layer is 100 Å to 200 Å, and the thickness of a single HfO2 layer is 50 Å to 100 Å.

[0010] As an improvement to the above technical solution, along the growth direction of the heat buffer layer, the thickness of the HfO2 layer in the later cycle is less than the thickness of the HfO2 layer in the previous cycle, and the thickness of the first SiO2 layer in the later cycle is greater than the thickness of the first SiO2 layer in the previous cycle.

[0011] As an improvement to the above technical solution, in the heat buffer layer of the first cycle, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer is 1:1 to 1.5:1.

[0012] In the heat buffer layer of the last cycle, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer is 2.5:1 to 3.5:1.

[0013] As an improvement to the above technical solution, the first insulating layer is made of SiO2 and / or silicon nitride, and its thickness is 5000Å~8000Å;

[0014] The second insulating layer is made of SiO2 and / or silicon nitride, and its thickness is 8000 Å to 10000 Å;

[0015] The third insulating layer is made of SiO2 and / or silicon nitride, and has a thickness of 8000 Å to 12000 Å.

[0016] As an improvement to the above technical solution, the first insulating layer is made of SiO2 and has a thickness of 5000Å~6000Å.

[0017] The second insulating layer is made of SiO2 and has a thickness of 8000 Å to 9000 Å;

[0018] The third insulating layer is made of SiO2 and has a thickness of 9000 Å to 11000 Å.

[0019] As an improvement to the above technical solution, the N-type semiconductor layer is an N-type GaN layer.

[0020] As an improvement to the above technical solution, the reflective layer includes an Ag reflective layer and a protective layer stacked sequentially. The protective layer includes alternating Ti and Ni layers. The thickness of the Ag reflective layer is 1000 Å to 2000 Å, the thickness of the Ti layer is 500 Å to 1500 Å, and the thickness of the Ni layer is 500 Å to 2000 Å.

[0021] As an improvement to the above technical solution, a heat buffer layer, a first insulating layer, a second insulating layer and a third insulating layer are sequentially stacked on the side wall of the isolation groove;

[0022] The bottom wall of the isolation groove is layered with a first insulating layer, a second insulating layer and a third insulating layer in sequence.

[0023] Accordingly, the present invention also discloses a method for fabricating a high-reliability flip-chip, which includes the following steps:

[0024] (1) An epitaxial layer is formed on a substrate, the epitaxial layer comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially stacked on the substrate;

[0025] (2) Etching forms the light-emitting structure, N-type conductive steps, and isolation trenches;

[0026] (3) A thermal buffer layer is formed on the sidewall and / or bottom wall of the isolation groove;

[0027] (4) A first insulating layer is formed on the light-emitting structure, the isolation groove, the N-type conductive step, and a first through hole is formed to expose the top of the light-emitting structure of the P-type semiconductor layer, and a second through hole is formed to expose the N-type conductive step;

[0028] (5) A reflective layer is formed in the first through hole and on the first insulating layer of a predetermined width located at the top of the light-emitting structure to obtain a first intermediate body;

[0029] (6) A second insulating layer is formed on the first intermediate body, and a third through hole is formed to expose the reflective layer and a fourth through hole is formed to expose the N-type conductive step;

[0030] (7) A P-type metal interconnect layer and an N-type metal interconnect layer are formed on the second insulating layer to obtain a second intermediate;

[0031] (8) A third insulating layer is formed on the second intermediate, and a fifth through hole and a sixth through hole are formed to expose the P-type metal interconnect layer;

[0032] (9) A P-type pad layer is formed in the fifth through hole, and an N-type pad layer is formed in the sixth through hole.

[0033] Implementing this invention has the following beneficial effects:

[0034] In one embodiment of the present invention, a thermal buffer layer is provided on the bottom wall and / or side wall of the isolation trench in the flip-chip. The thermal expansion coefficient of the thermal buffer layer is less than that of the N-type semiconductor layer and greater than that of the first insulating layer. The thermal expansion coefficient of the thermal buffer layer is less than that of the substrate. Based on this, during the heating and cooling process of the flip-chip, the thermal mismatch between the N-type semiconductor layer / substrate and the first insulating layer can be effectively adjusted, preventing the formation of microcracks during the cooling process, thereby effectively improving the reliability of the flip-chip. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the structure of a high-reliability flip-chip LED in one embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the structure of the thermal buffer layer in one embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the structure of the first intermediate obtained in step (5) of an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the structure of the first intermediate after step (6) in one embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of the structure of the second intermediate after step (8) in one embodiment of the present invention;

[0040] In the figure, 100 is the substrate, 121 is the N-type semiconductor layer, 122 is the light-emitting layer, 123 is the P-type semiconductor layer, 124 is the N-type conductive step, 125 is the isolation trench, 126 is the light-emitting structure, 130 is the current spreading layer, 140 is the first insulating layer, 141 is the first via, 142 is the second via, 150 is the reflective layer, 160 is the second insulating layer, 161 is the third via, 162 is the fourth via, 171 is the P-type metal connection layer, 172 is the N-type metal connection layer, 180 is the third insulating layer, 181 is the fifth via, 182 is the sixth via, 191 is the P-type pad layer, 192 is the N-type pad layer, 200 is the thermal buffer layer, 210 is the first SiO2 layer, and 220 is the HfO2 layer. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It is hereby declared that the directional terms such as up, down, left, right, front, back, inside, and outside used in this text are based solely on the accompanying drawings and are not intended to specifically limit the invention.

[0042] Please see Figure 1 , Figure 2 An embodiment of the present invention provides a high-reliability flip-chip LED, which includes a substrate 100, an epitaxial layer, a first insulating layer 140, a reflective layer 150, a second insulating layer 160, a P-type metal interconnect layer 171, an N-type metal interconnect layer 172, a third insulating layer 180, a P-type pad layer 191, an N-type pad layer 192, and a thermal buffer layer 200 disposed on the substrate 100.

[0043] In the vertical direction (i.e., the thickness direction of the substrate 100), the epitaxial layer includes an N-type semiconductor layer 121, a light-emitting layer 122, and a P-type semiconductor layer 123 sequentially stacked on the substrate. A light-emitting structure 126, an isolation trench 125, and an N-type conductive step 124 are formed on the epitaxial layer. The isolation trench 125 is used to divide the substrate 100 and the epitaxial layer to form multiple flip-chip LEDs, which are arranged around the light-emitting structure 126. The N-type conductive step 124 is located on one side of the light-emitting structure 126, exposing the N-type semiconductor layer 121, and is used to form electrical connections with the N-type metal interconnect layer 172 and the N-type pad layer 192. The light-emitting structure 126 emits light, and its top is a P-type semiconductor layer 123, which is used to form electrical connections with the P-type metal interconnect layer 171 and the P-type pad layer 191.

[0044] Specifically, the substrate 100 is a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited to these. The N-type semiconductor layer 121 can be an N-type GaAs layer, an N-type GaN layer, or an N-type AlGaN layer, but is not limited to these. The light-emitting layer 122 can be an InGaN-GaN type multiple quantum well layer, an InGaN-AlGaN type multiple quantum well layer, an AlGaN-AlGaN type multiple quantum well layer, or an AlGaInP-AlGaInP type multiple quantum well layer, but is not limited to these. The P-type semiconductor layer 123 can be a P-type GaN layer, a P-type AlGaInP layer, or a P-type AlGaN layer, but is not limited to these. Preferably, in some embodiments, the substrate 100 is a sapphire substrate, the N-type semiconductor layer 121 is an N-type GaN layer, the light-emitting layer 122 is an InGaN-GaN type multiple quantum well layer, and the P-type semiconductor layer 123 is a P-type GaN layer.

[0045] Specifically, the sidewalls of the isolation trench 125 expose the N-type semiconductor layer 121, and its bottom wall exposes the substrate 100. A thermal buffer layer 200, a first insulating layer 140, a second insulating layer 160, and a third insulating layer 180 are sequentially stacked on the sidewalls and / or bottom wall of the isolation trench 125. The thermal expansion coefficient of the thermal buffer layer 200 is less than that of the N-type semiconductor layer 121 and greater than that of the first insulating layer 140. The thermal expansion coefficient of the thermal buffer layer 200 is less than that of the substrate 100. Therefore, during the heating and cooling processes of the flip-chip LED, the thermal mismatch between the N-type semiconductor layer 121 / substrate 100 and the first insulating layer 140 can be effectively adjusted, preventing microcracks from forming during cooling and thus effectively improving the reliability of the flip-chip LED.

[0046] Specifically, the heat buffer layer 200 can be made of one or more of silicon nitride, HfO2, Ta2O5, and SiO2, but is not limited to these. The thickness of the heat buffer layer 200 is 500 Å to 2000 Å. If its thickness is too small, it will be difficult to effectively buffer thermal stress; if its thickness is too large, it may lead to stress accumulation, which may cause cracking and reduce reliability.

[0047] Preferably, in some embodiments, a current spreading layer 130 is further disposed on the P-type semiconductor layer 123 at the top of the light-emitting structure 126, which is an ITO layer, an IZO layer, or an AZO layer, but is not limited thereto. The projection of the current spreading layer 130 on the substrate 100 is located inside the projection of the P-type semiconductor layer 123 on the substrate 100. The current spreading layer 130 can enhance current diffusion and avoid current congestion.

[0048] Among them, see Figure 1 , Figure 3 The first insulating layer 140 covers the N-type conductive step 124, the isolation trench 125, and the sidewalls of the light-emitting structure 126. That is, the surfaces exposed during the etching process to form the light-emitting structure 126, the isolation trench 125, and the N-type conductive step 124 are all covered by the first insulating layer 140. This can passivate the dangling bonds formed during the etching process, improving the reliability of the flip-chip LED. Simultaneously, the first insulating layer 140 effectively prevents the reflective layer 150 from conducting with the N-type semiconductor layer 121, avoiding short circuits. A first via 141 exposing the P-type semiconductor layer 123 and a second via 142 exposing the N-type conductive step 124 are formed on the first insulating layer 140. The first via 141 is used to achieve an electrical connection between the P-type semiconductor layer 123 and the P-type metal interconnect layer 171. The second via 142 is used to achieve an electrical connection between the N-type semiconductor layer 121 and the N-type metal interconnect layer 172.

[0049] Specifically, the first insulating layer 140 is made of SiO2, silicon nitride, or Al2O3, but is not limited to these. The thickness of the first insulating layer 140 is ≥5000 Å. More specifically, its thickness is 5000 Å to 8000 Å. This thickness range ensures good insulation performance, effectively isolating the reflective layer 150 from the N-type semiconductor layer 121 to prevent leakage or short circuits, while also avoiding stress accumulation and defects such as cracking or peeling in subsequent processes due to excessive thickness of the first insulating layer 140. Preferably, in some embodiments, the first insulating layer 140 is made of SiO2 and / or silicon nitride, with a thickness of 5000 Å to 8000 Å; this first insulating layer 140 has higher thermal matching with the thermal buffer layer 200, which can further improve the reliability of the flip-chip LED. More preferably, the first insulating layer is made of SiO2, with a thickness of 5000 Å to 6000 Å; this first insulating layer 140 has lower internal stress, which is beneficial to improving the crystal quality of subsequent grown layers.

[0050] The reflective layer 150 is located on the light-emitting structure 126 and is used to transmit light emitted from the light-emitting layer 122, allowing light to exit from one side of the substrate 100. The reflective layer 150 covers the first via 141 and the first insulating layer 140 of a predetermined width. More specifically, the orthographic projection of the reflective layer 150 on the substrate 100 is completely coincident with or slightly smaller than the orthographic projection of the light-emitting structure 126 on the substrate 100, to ensure maximum light reflection efficiency.

[0051] Specifically, the reflective layer 150 is a stacked structure formed by one or at least two of Ag, Al, or Au reflective layers, but is not limited thereto. The thickness of the reflective layer 150 is 1000 Å to 3000 Å. Preferably, in some embodiments, the reflective layer 150 includes an Ag reflective layer and a protective layer sequentially stacked on the light-emitting structure 126, wherein the thickness of the Ag reflective layer is 1000 Å to 2000 Å, exemplaryly 1200 Å, 1400 Å, 1600 Å, or 1800 Å, but is not limited thereto. The protective layer may be one or more of a Ni metal layer, a TiW alloy layer, or a Pt / Pd alloy layer, but is not limited thereto. The thickness of the protective layer is 5000 Å to 30000 Å. Preferably, in some embodiments, the protective layer comprises alternating layers of Ti and Ni, with a period number of 2 to 5. The thickness of a single Ti layer is 500 Å to 1500 Å, exemplarily 600 Å, 800 Å, 1000 Å, 1200 Å, or 1400 Å, but not limited thereto. The thickness of a single Ni layer is 500 Å to 2000 Å, exemplarily 800 Å, 1100 Å, 1400 Å, 1700 Å, or 1900 Å, but not limited thereto. More preferably, the thickness of the Ag reflective layer is 1500 Å to 2000 Å, the thickness of a single Ti layer is 500 Å to 1000 Å, and the thickness of a single Ni layer is 1000 Å to 2000 Å.

[0052] Specifically, see Figure 1 , Figure 4 The second insulating layer 160 covers the first insulating layer 140 and the reflective layer 150, and a third through hole 161 exposing the reflective layer 150 and a fourth through hole 162 exposing the N-type conductive step 124 are formed on the second insulating layer 160.

[0053] Specifically, the second insulating layer 160 is made of one or more of SiO2, silicon nitride, and Al2O3, but is not limited thereto. The thickness of the second insulating layer 160 is 6000 Å to 12000 Å. Preferably, in some embodiments, the second insulating layer 160 is made of SiO2 and / or silicon nitride, and its thickness is 8000 Å to 10000 Å; this second insulating layer 160 can better improve the reliability of flip-chip LEDs. More preferably, the second insulating layer 160 is made of SiO2, and its thickness is 8000 Å to 9000 Å; this second insulating layer 160 has lower internal stress, which is beneficial to improving the crystal quality of subsequent grown layers.

[0054] Specifically, both the P-type metal connection layer 171 and the N-type metal connection layer 172 are disposed above the second insulating layer 160. The P-type metal connection layer 171 contacts the reflective layer 150 through the third through-hole 161, and the N-type metal connection layer 172 contacts the N-type conductive step 124 through the fourth through-hole 162. Both the P-type metal connection layer 171 and the N-type metal connection layer 172 are common single-layer or multi-layer metal structures in the art, and can be made of one or more of Cr, Al, Ti, Pt, Ni, Au, Cu, and Ag, but are not limited thereto. Preferably, in some embodiments, both the P-type metal bonding layer 171 and the N-type metal bonding layer 172 include sequentially stacked Cr layer, Al layer, Ti layer, Pt layer, Ti layer, Pt layer, Ti layer, Au layer, Pt layer and Ti layer, with thicknesses of 30Å~50Å, 1200Å~2000Å, 500Å~1000Å, 500Å~1000Å, 500Å~1000Å, 500Å~1000Å, 500Å~1000Å, 8000Å~10000Å, 2000Å~3000Å ​​and 30Å~50Å.

[0055] Specifically, see Figure 1 , Figure 5 The third insulating layer 180 covers the P-type metal connection layer 171, the N-type metal connection layer 172 and the second insulating layer 160. A fifth through hole 181 exposing the P-type metal connection layer 171 and a sixth through hole 182 exposing the N-type metal connection layer 172 are formed on the third insulating layer 180.

[0056] Specifically, the third insulating layer 180 is made of one or more of SiO2, silicon nitride, and Al2O3, but is not limited thereto, and the thickness of the third insulating layer 180 is 8000 Å to 12000 Å. Preferably, in some embodiments, the third insulating layer 180 is made of SiO2 and / or silicon nitride, and its thickness is 8000 Å to 12000 Å. This third insulating layer 180 can further improve the reliability of flip-chip LEDs. More preferably, the third insulating layer 180 is made of SiO2, and its thickness is 9000 Å to 11000 Å. This third insulating layer 180 has lower internal stress, which is beneficial to improving the crystal quality of subsequent grown layers.

[0057] The P-type pad layer 191 can be disposed above the third insulating layer 180 and contact the P-type metal connection layer 171 through the fifth through-hole 181, or it can be entirely disposed within the fifth through-hole 181, but is not limited thereto. Similarly, the N-type pad layer 192 can be disposed above the third insulating layer 180 and contact the N-type metal connection layer 172 through the sixth through-hole 182, or it can be entirely disposed within the sixth through-hole 182, but is not limited thereto. Specifically, the P-type pad layer 191 and the N-type pad layer 192 are common metal pad structures in the art, such as a stacked structure composed of one or more of Ti, Sn, Ni, Au, etc., but are not limited thereto. Preferably, both the P-type pad layer 191 and the N-type pad layer 192 include Ti layer, Al layer, Ti layer, Pt layer, Ni layer and Au layer stacked sequentially, with thicknesses of 1000Å~2000Å, 10000Å~15000Å, 1000Å~2000Å, 1000Å~2000Å, 8000Å~12000Å and 300Å~600Å, respectively.

[0058] Preferably, please refer to Figure 2In some embodiments, the thermal buffer layer 200 includes alternating layers of a first SiO2 layer 210 and an HfO2 layer 220, with a cycle number of 2 to 4. This thermal buffer layer 200 not only effectively alleviates the thermal stress of the flip-chip during operation, but also significantly improves the interfacial bonding strength between the thermal buffer layer 200 and the substrate 100, the N-type semiconductor layer 121, and the first insulating layer 140, further enhancing the reliability of the flip-chip and extending its service life. Specifically, the thickness of the first SiO2 layer 210 is 100 Å to 200 Å, exemplarily 120 Å, 140 Å, 160 Å, or 180 Å, but is not limited thereto. Preferably, it is 100 Å to 175 Å. The thickness of the HfO2 layer 220 is 50 Å to 100 Å, exemplarily 65 Å, 75 Å, 85 Å, or 95 Å, but is not limited thereto. Preferably, it is 60 Å to 100 Å. By controlling the number of cycles and the thickness of each layer of the thermal buffer layer 200, the thermal buffer layer 200 can maintain good adhesion and mechanical strength in high temperature and high humidity environments, while effectively suppressing interface cracking caused by thermal expansion mismatch, thereby improving the working stability and reliability of flip-chip LEDs under high temperature and high humidity conditions.

[0059] Preferably, in some embodiments, along the growth direction of the heat buffer layer 200, the thickness of the HfO2 layer 220 in a later cycle is less than the thickness of the HfO2 layer 220 in the previous cycle, and the thickness of the first SiO2 layer 210 in a later cycle is greater than the thickness of the first SiO2 layer 210 in the previous cycle. This gradient thickness design can further optimize the distribution of thermal stress, reduce the interface stress concentration caused by the difference in the interlayer thermal expansion coefficient, and effectively avoid crack initiation and propagation. At the same time, this gradient structure allows the heat buffer layer 200 to maintain structural integrity after undergoing multiple thermal cycles, significantly reducing the probability of interface defects, thereby improving the long-term operational stability of the flip-chip LED.

[0060] More specifically, in the first cycle of the heat buffer layer 200, the thickness ratio of the first SiO2 layer 210 to the thickness of the HfO2 layer 220 is 1:1 to 1.5:1; in the last cycle of the heat buffer layer 200, the thickness ratio of the first SiO2 layer 210 to the thickness of the HfO2 layer 220 is 2.5:1 to 3:1. In the intermediate cycles, the thickness ratio of the two layers varies with a gradient, which can be linear or nonlinear, but is not limited to this. More preferably, the number of cycles of the heat buffer layer 200 is 4, and in the first to fourth cycles, the thickness ratio of the first SiO2 layer 210 to the thickness of the HfO2 layer 220 is 1:1 to 1.2:1, 1.1:1 to 1.4:1, 1.5:1 to 2.3:1, and 2.8:1 to 3:1, respectively.

[0061] It should be noted that the bottom wall and side walls of the isolation trench 125 of this application can be sequentially stacked with a heat buffer layer 200, a first insulating layer 140, a second insulating layer 160, and a third insulating layer 180, and each layer continuously covers the bottom wall and side walls of the isolation trench 125. Preferably, in some embodiments, only the side walls of the isolation trench 125 are provided with the heat buffer layer 200, the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180, while the bottom wall of the isolation trench 125 is only covered with the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180. Since the bottom wall of the isolation trench 125 directly exposes the substrate 100, and the lattice difference between the substrate 100 (sapphire) and HfO2 is large, the crystal quality is poor. When splitting along the isolation trench 125, microcracks are easily generated and extend upward, affecting the reliability of the flip-chip LED. Therefore, it is preferable to form the heat buffer layer 200 only on the side walls of the isolation trench 125.

[0062] Accordingly, the present invention also discloses a method for preparing a flip-chip LED, which specifically includes the following steps:

[0063] (1) Forming an epitaxial layer on a substrate;

[0064] Specifically, an N-type semiconductor layer 121, a light-emitting layer 122, and a P-type semiconductor layer 123 are sequentially formed on a substrate 100 using methods such as MOCVD, MBE, and PVD, thus obtaining an epitaxial layer.

[0065] (2) Etching forms a light-emitting structure, an N-type conductive step, and an isolation trench exposing the substrate;

[0066] Specifically, a mask (photoresist layer or SiO2 layer) can be formed on the epitaxial layer first, and then the P-type semiconductor layer 123, the light-emitting layer 122 and the N-type semiconductor layer 121 of a predetermined thickness in the preset area can be removed by wet etching or dry etching to form an N-type conductive step 124, an isolation trench 125 and a light-emitting structure 126, but it is not limited to this.

[0067] Preferably, in some embodiments, after etching to form the N-type conductive step 124 and the isolation trench 125, a current spreading layer 130 is formed on the surface of the N-type conductive step 124, the isolation trench 125 and the light-emitting structure 126. Then, photolithography is used to etch away the current spreading layer 130 on the sidewall of the N-type conductive step 124, the isolation trench 125 and the light-emitting structure 126, leaving only the current spreading layer 130 on the P-type semiconductor layer 123.

[0068] (3) A thermal buffer layer is formed on the sidewalls and / or bottom wall of the isolation tank;

[0069] Specifically, the thermal buffer layer 200 can be formed by electron beam evaporation, PECVD, MOCVD or PVD, but is not limited to these methods.

[0070] Preferably, in some embodiments, a photoresist layer is first formed using negative photoresist, and then the photoresist layer on the sidewall and / or bottom wall of the isolation tank 125 is removed by exposure and development. Then, the first SiO2 layer 210 and the HfO2 layer 220 are alternately deposited using an electron beam evaporation process until a thermal buffer layer 200 is obtained. Then, the thermal buffer layer 200 located on the photoresist layer is removed using a blue film stripping process, and finally the photoresist layer is removed.

[0071] (4) A first insulating layer is formed on the N-type conductive step, the isolation groove, and the sidewall of the light-emitting structure;

[0072] Specifically, in some embodiments, a first insulating layer 140 is formed by PECVD, a photoresist layer is then formed on the first insulating layer 140, the photoresist layer in a preset area is removed by exposure and development, and a first via 141 and a second via 142 are formed by dry etching.

[0073] (5) A reflective layer is formed inside the first through hole and on the first insulating layer of a predetermined width located at the top of the light-emitting structure to obtain the first intermediate body;

[0074] Specifically, a metal stack can be formed through electron beam evaporation or PVD processes to obtain the reflective layer 150, but it is not limited to these methods.

[0075] Preferably, in some embodiments, a photoresist layer is first formed using negative photoresist, and then the photoresist layer of a predetermined width inside the first through hole 141, on the light-emitting structure 126, and on the isolation trench 125 is removed by exposure and development. Then, multiple metals are sequentially deposited by electron beam evaporation to form a reflective layer 150. Then, the metals located on the photoresist layer are removed by blue film stripping process, and finally the photoresist layer is removed.

[0076] (6) A second insulating layer is formed on the first intermediate, and a third through hole exposing the reflective layer and a fourth through hole exposing the N-type conductive step are formed;

[0077] Specifically, the second insulating layer 160 can be formed by processes such as ALD, PECVD, and LPCVD, and then the third through hole 161 and the fourth through hole 162 can be etched, but it is not limited to this.

[0078] Preferably, in some embodiments, a second insulating layer 160 is formed on a first intermediate by PECVD. Then, a photoresist layer is formed on the second insulating layer 160, the second insulating layer 160 in a predetermined area is exposed and developed, and then a third via 161 and a fourth via 162 are etched, and then the photoresist layer is removed.

[0079] (7) A P-type metal interconnect layer and an N-type metal interconnect layer are formed on the second insulating layer to obtain a second intermediate;

[0080] Specifically, metal stacks can be formed through electron beam evaporation or PVD processes to obtain a P-type metal interconnect layer 171 and an N-type metal interconnect layer 172, but are not limited to these methods.

[0081] Preferably, in some embodiments, a photoresist layer is first formed in the second insulating layer 160, the third through-hole 161, and the fourth through-hole 162. Then, the photoresist layer in the preset area is removed by exposure and development. Then, a metal stack is deposited by electron beam evaporation to form a P-type metal interconnect layer 171 and an N-type metal interconnect layer 172. Then, the metal on the photoresist layer is removed by blue film stripping. Finally, the photoresist layer is removed to obtain the second intermediate.

[0082] (8) A third insulating layer is formed on the second intermediate, and a fifth through hole exposing the P-type metal interconnect layer and a sixth through hole exposing the N-type metal interconnect layer are formed;

[0083] Specifically, the third insulating layer 180 can be formed by processes such as ALD, PECVD, and LPCVD, and then the fifth through hole 181 and the sixth through hole 182 can be etched, but it is not limited to this.

[0084] Preferably, in some embodiments, a third insulating layer 180 is first formed on a second intermediate by PECVD. Then, a photoresist layer is formed on the third insulating layer 180, and the third insulating layer 180 in a predetermined area is exposed by exposure and development. Then, a fifth via 181 and a sixth via 182 are etched, and then the photoresist layer is removed.

[0085] (9) A P-type pad layer is formed in the fifth through hole, and an N-type pad layer is formed in the sixth through hole.

[0086] Specifically, metal layers can be formed through electron beam evaporation or PVD processes to obtain P-type pad layer 191 and N-type pad layer 192, but are not limited to these.

[0087] Preferably, in some embodiments, a photoresist layer is first formed in the third insulating layer 180, the fifth through hole 181 and the sixth through hole 182, and then the photoresist layer in the preset area is removed by exposure and development. Then, a metal stack is deposited by electron beam evaporation to form a P-type pad layer 191 and an N-type pad layer 192. Then, the metal on the photoresist layer is removed by blue film stripping process, and finally the photoresist layer is removed.

[0088] Preferably, in some embodiments, the method for preparing flip-chip LEDs further includes: splitting the LED wafer obtained in step (9) along the isolation groove, and then testing and sorting to obtain flip-chip LEDs.

[0089] The present invention will be further described below with reference to specific embodiments:

[0090] Example 1

[0091] This embodiment provides a flip-chip LED, which includes a substrate, an epitaxial layer, a first insulating layer, a reflective layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, a third insulating layer, a P-type pad layer, an N-type pad layer, and a thermal buffer layer disposed on the substrate.

[0092] The substrate is a sapphire substrate, and the epitaxial layer includes an N-type GaN layer, an InGaN-GaN type multiple quantum well layer, and a P-type GaN layer sequentially stacked on the substrate. A light-emitting structure, an isolation trench, and an N-type conductive step are formed on the epitaxial layer. The N-type conductive step is located on one side of the light-emitting structure and exposes the N-type GaN layer. The isolation trench surrounds the light-emitting structure, with its sidewalls exposing the N-type GaN layer and its bottom wall exposing the substrate. A thermal buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer are sequentially stacked on the sidewalls of the isolation trench. The thermal buffer layer includes alternating layers of a first SiO2 layer and a HfO2 layer, with a period of 3. In the first period, the thickness of the first SiO2 layer is 100 Å, and the thickness of the HfO2 layer is 100 Å; in the second period, the thickness of the first SiO2 layer is 135 Å, and the thickness of the HfO2 layer is 88 Å; in the third period, the thickness of the first SiO2 layer is 170 Å, and the thickness of the HfO2 layer is 75 Å.

[0093] The P-type GaN layer has a current spreading layer, which is an ITO layer with a thickness of 800 Å.

[0094] The first insulating layer covers the N-type conductive steps, the sidewalls of the isolation trench, the bottom wall of the isolation trench, and the light-emitting structure. The first insulating layer is made of SiO2 and has a thickness of 6500 Å. The first insulating layer has a first through-hole exposing the current spreading layer and a second through-hole exposing the N-type conductive steps.

[0095] The reflective layer covers the first through-hole and a first insulating layer of a predetermined width located above the light-emitting structure. The reflective layer comprises sequentially stacked Ag reflective layers and a protective layer, with the Ag reflective layer having a thickness of 1500 Å. The protective layer comprises alternately stacked Ti and Ni layers with a period of 4, the thickness of a single Ti layer being 800 Å and the thickness of a single Ni layer being 1400 Å.

[0096] The second insulating layer covers the first insulating layer, the reflective layer, and the exposed N-type conductive steps. A third via exposing the reflective layer and a fourth via exposing the N-type conductive steps are formed on the second insulating layer. The second insulating layer is a SiO2 layer with a thickness of 8500 Å.

[0097] Both the P-type and N-type metal interconnect layers are disposed above the first insulating layer. The P-type metal interconnect layer contacts the reflective layer through a third via, and the N-type metal interconnect layer contacts the N-type conductive step through a fourth via. Both the P-type and N-type metal interconnect layers consist of sequentially stacked Cr, Al, Ti, Pt, Ti, Pt, Ti, Au, Pt, and Ti layers, with thicknesses of 50 Å, 1400 Å, 800 Å, 800 Å, 600 Å, 600 Å, 8000 Å, 9500 Å, 2400 Å, and 40 Å, respectively.

[0098] Specifically, the third insulating layer covers the P-type metal interconnect layer, the N-type metal interconnect layer, and the second insulating layer. A fifth via exposing the P-type metal interconnect layer and a sixth via exposing the N-type metal interconnect layer are formed on the third insulating layer. The third insulating layer is a SiO2 layer with a thickness of 11000 Å.

[0099] The P-type pad layer is disposed in the third via, and the N-type pad layer is disposed in the fourth via. Specifically, both the P-type and N-type pad layers consist of sequentially stacked Ti, Al, Pt, Ni, and Au layers, with thicknesses of 1500 Å, 14000 Å, 1300 Å, 1500 Å, 9500 Å, and 450 Å, respectively.

[0100] Example 2

[0101] This embodiment provides a flip-chip LED, whose basic structure is the same as that of Embodiment 1. The difference between it and Embodiment 1 is:

[0102] In the second cycle of the heat buffer layer, the thickness of the first SiO2 layer is 125 Å and the thickness of the HfO2 layer is 90 Å; in the third cycle of the heat buffer layer, the thickness of the first SiO2 layer is 150 Å and the thickness of the HfO2 layer is 80 Å; in the fourth cycle of the heat buffer layer, the thickness of the first SiO2 layer is 175 Å and the thickness of the HfO2 layer is 60 Å.

[0103] Comparative Example 1

[0104] This comparative example provides a flip-chip LED, whose basic structure is the same as that of Example 1. The difference between it and Example 1 is:

[0105] The sidewalls of the isolation tank are not equipped with a thermal buffer layer.

[0106] The flip-chip LEDs of Examples 1-2 and Comparative Example 1 were fabricated to a size of 1400μm × 1400μm. They were then subjected to high-temperature and high-humidity aging in an environment with a temperature of 85℃ and a humidity of 85%. During the aging process, a current of 2A was continuously applied. Every 72 hours, the aging board was removed, and a voltage of -10V was applied to the chip to test its reverse leakage current IR. When IR was greater than 0.5μA, it indicated that the chip had failed due to leakage. The current aging time point was recorded as the aging failure point. Specific test data are as follows:

[0107]

[0108] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A high-reliability flip-chip LED, characterized in that, It includes a substrate, an epitaxial layer, a first insulating layer, a first reflective layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, a third insulating layer, a P-type pad layer, and an N-type pad layer stacked on the substrate; The epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate. A light-emitting structure, an N-type conductive step, and an isolation trench are formed on the epitaxial layer. The N-type conductive step is disposed on one side of the light-emitting structure. The isolation trench is disposed around the light-emitting structure. The sidewall of the isolation trench exposes the N-type semiconductor layer, and the bottom wall of the isolation trench exposes the substrate. A thermal buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer are sequentially stacked on the sidewalls and / or bottom wall of the isolation trench; the thermal expansion coefficient of the thermal buffer layer is less than that of the N-type semiconductor layer and greater than that of the first insulating layer; the thermal expansion coefficient of the thermal buffer layer is less than that of the substrate. The heat buffer layer comprises alternating layers of first SiO2 and HfO2, with a period number of 2 to 4. The thickness of a single first SiO2 layer is 100 Å to 200 Å, and the thickness of a single HfO2 layer is 50 Å to 100 Å.

2. The high-reliability flip-chip LED as described in claim 1, characterized in that, Along the growth direction of the heat buffer layer, the thickness of the HfO2 layer in the later cycle is less than the thickness of the HfO2 layer in the previous cycle, and the thickness of the first SiO2 layer in the later cycle is greater than the thickness of the first SiO2 layer in the previous cycle.

3. The high-reliability flip-chip LED as described in claim 2, characterized in that, In the heat buffer layer of the first cycle, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer is 1:1 to 1.5:1; In the heat buffer layer of the last cycle, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer is 2.5:1 to 3.5:

1.

4. The high-reliability flip-chip LED as described in claim 1, characterized in that, The first insulating layer is made of SiO2 and / or silicon nitride, and its thickness is 5000 Å to 8000 Å; The second insulating layer is made of SiO2 and / or silicon nitride, and its thickness is 8000 Å to 10000 Å; The third insulating layer is made of SiO2 and / or silicon nitride, and has a thickness of 8000 Å to 12000 Å.

5. The high-reliability flip-chip LED as described in claim 1, characterized in that, The first insulating layer is made of SiO2 and has a thickness of 5000 Å to 6000 Å; The second insulating layer is made of SiO2 and has a thickness of 8000 Å to 9000 Å; The third insulating layer is made of SiO2 and has a thickness of 9000 Å to 11000 Å.

6. The high-reliability flip-chip LED as described in claim 1, characterized in that, The N-type semiconductor layer is an N-type GaN layer.

7. The high-reliability flip-chip LED as described in any one of claims 1 to 6, characterized in that, The reflective layer comprises an Ag reflective layer and a protective layer stacked sequentially. The protective layer comprises alternating Ti and Ni layers. The thickness of the Ag reflective layer is 1000 Å to 2000 Å, the thickness of the Ti layer is 500 Å to 1500 Å, and the thickness of the Ni layer is 500 Å to 2000 Å.

8. The high-reliability flip-chip LED as described in claim 1, characterized in that, A heat buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer are stacked sequentially on the sidewall of the isolation groove. The bottom wall of the isolation groove is layered with a first insulating layer, a second insulating layer and a third insulating layer in sequence.

9. A method for fabricating a high-reliability flip-chip, used to fabricate the high-reliability flip-chip as described in any one of claims 1 to 8, characterized in that, Includes the following steps: (1) An epitaxial layer is formed on a substrate, the epitaxial layer comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially stacked on the substrate; (2) Etching forms a light-emitting structure, an N-type conductive step, and an isolation trench exposing the substrate; (3) A thermal buffer layer is formed on the sidewall and / or bottom wall of the isolation groove; (4) A first insulating layer is formed on the light-emitting structure, the isolation groove, the N-type conductive step, and a first through hole is formed to expose the top of the light-emitting structure of the P-type semiconductor layer, and a second through hole is formed to expose the N-type conductive step; (5) A reflective layer is formed in the first through hole and on the first insulating layer of a predetermined width located at the top of the light-emitting structure to obtain a first intermediate body; (6) A second insulating layer is formed on the first intermediate body, and a third through hole is formed to expose the reflective layer and a fourth through hole is formed to expose the N-type conductive step; (7) A P-type metal interconnect layer and an N-type metal interconnect layer are formed on the second insulating layer to obtain a second intermediate; (8) A third insulating layer is formed on the second intermediate, and a fifth through hole and a sixth through hole are formed to expose the P-type metal interconnect layer; (9) A P-type pad layer is formed in the fifth through hole, and an N-type pad layer is formed in the sixth through hole.

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