A CMOS temperature sensor based on RC phase delay detection

Abstract

The application relates to a CMOS temperature sensor based on RC phase delay detection. A first output end of a voltage-controlled oscillator is connected with an input end of a frequency divider, a first output end and a second output end of the frequency divider are connected with positive-phase input ends and inverse-phase input ends of a multilayer metal RC temperature-sensing front end respectively, a third output end of the frequency divider is connected with a first input end of a phase detector, first output ends and second output ends of the multilayer metal RC temperature-sensing front end are connected with positive-phase input ends and inverse-phase input ends of a cross comparator respectively, an output end of the cross comparator is connected with a second input end of the phase detector, first output ends and second output ends of the phase detector are connected with inverse-phase switch signal input ends and positive-phase switch signal input ends of a switched capacitor integration filter respectively, and an output end of the switched capacitor integration filter is connected with an input end of the voltage-controlled oscillator. The temperature sensor has the advantages of strong process migration, more compact area, lower power consumption and simpler structure.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a CMOS temperature sensor based on RC phase delay detection. Background Technology

[0002] With the continuous increase in the integration of system-on-chips (SoCs) and the evolution of advanced process nodes, the power density per unit area within chips has increased significantly, making the problem of localized hot spots increasingly prominent. This is especially true in high-performance digital systems such as AI chips, CPU / GPU processors, and AI accelerators, where elevated local temperatures can easily lead to clock link drift and reduced circuit phase margin, affecting overall system stability. Therefore, it is necessary to deploy a large number of temperature sensors within the chip to achieve real-time monitoring and closed-loop compensation of hot spots.

[0003] Existing on-chip temperature sensors mainly include three types: bipolar junction transistors (BJTs), metal-oxide semiconductor field-effect transistors (MOS-FETs), and resistive sensors. BJT-type temperature sensors are widely used in traditional process nodes, but they face several problems in advanced complementary metal-oxide semiconductor (CMOS) processes: (1) they require the use of bipolar transistors or dedicated devices, resulting in poor process compatibility; (2) their output depends on analog links such as operational amplifiers, bandgap converters, or analog-to-digital converters (ADCs), resulting in a large circuit area and high power consumption, making them unsuitable for large-scale on-chip deployment. Although the MOS-FET subthreshold temperature-sensitive structure has a relatively small area, it is sensitive to device matching, bias current, and PVT (process, voltage, and temperature) fluctuations, making it difficult to guarantee stability under low-voltage digital processes.

[0004] In contrast, resistive temperature sensors utilize resistive materials with high temperature coefficients (such as polyresistors, silicide resistors, etc.) to construct Wien bridges or Wheatstone bridges, and obtain temperature information through analog readout circuits. This type of structure has the advantages of simple manufacturing and clear principles, but it also faces inherent limitations:

[0005] (1) It requires a bridge structure consisting of four highly matched resistors, which occupies a large area, typically about 0.03 mm²–0.08 mm².

[0006] (2) The voltage readout link needs to be completed with the help of operational amplifiers, modem circuits or ADCs, and the analog module is complex and has high static power consumption;

[0007] (3) In advanced process nodes, the process fluctuations of poly resistors and siliconized resistors are aggravated, making it difficult to improve temperature accuracy and device consistency.

[0008] In chip thermal monitoring systems, applications that require dozens or even hundreds of temperature sampling points to be distributed on the chip cannot meet the requirements of traditional temperature sensors in terms of area, power consumption, and process portability.

[0009] Existing resistive temperature sensors generally use polysilicon resistors or silicided resistors to form a Wien bridge or Wheatstone bridge to construct the temperature sensing front-end structure. This requires four highly matched temperature sensing resistors with high temperature coefficients, is greatly affected by process deviations, occupies a large area, and has a complex readout link, making it difficult to meet the chip requirements for a compact area, low cost, and high energy efficiency for large-scale integrated temperature sensors. Summary of the Invention

[0010] Therefore, it is necessary to provide a CMOS temperature sensor based on RC phase delay detection to address the above-mentioned technical problems.

[0011] A CMOS temperature sensor based on RC phase delay detection, the CMOS temperature sensor based on RC phase delay detection includes: a voltage-controlled oscillator, a frequency divider, a multilayer metal RC temperature sensing front end, a cross comparator, a phase detector, and a switched capacitor integral filter;

[0012] The first output terminal of the voltage-controlled oscillator is connected to the input terminal of the frequency divider. The first output terminal of the frequency divider is connected to the non-inverting input terminal of the multilayer metal RC temperature sensing front end and the first enable input terminal of the cross comparator. The second output terminal of the frequency divider is connected to the inverting input terminal of the multilayer metal RC temperature sensing front end and the second enable input terminal of the cross comparator. The third output terminal of the frequency divider is connected to the first input terminal of the phase detector. The first output terminal of the multilayer metal RC temperature sensing front end is connected to the non-inverting input terminal of the cross comparator. The second output terminal of the multilayer metal RC temperature sensing front end is connected to the inverting input terminal of the cross comparator. The output terminal of the cross comparator is connected to the second input terminal of the phase detector. The first output terminal of the phase detector is connected to the inverting switch signal input terminal of the switched capacitor integrator filter. The second output terminal of the phase detector is connected to the non-inverting switch signal input terminal of the switched capacitor integrator filter. The output terminal of the switched capacitor integrator filter is connected to the input terminal of the voltage-controlled oscillator. The second output terminal of the voltage-controlled oscillator is used to output a signal whose frequency is inversely proportional to the temperature.

[0013] In one embodiment, the multilayer metal RC temperature sensing front end includes a first metal resistor, a second metal resistor, a first capacitor, and a second capacitor;

[0014] One end of the second metal resistor and one end of the first capacitor serve as the positive input terminal of the multilayer metal RC temperature sensing front end, the other end of the first capacitor and one end of the first metal resistor serve as the first output terminal of the multilayer metal RC temperature sensing front end, the other end of the second metal resistor and one end of the second capacitor serve as the second output terminal of the multilayer metal RC temperature sensing front end, and the other end of the first metal resistor and the other end of the second capacitor serve as the inverting input terminal of the multilayer metal RC temperature sensing front end.

[0015] In one embodiment, the first metal resistor and the second metal resistor are metal resistors with the same structure;

[0016] The metal resistor is composed of a first shielding layer, N layers of metal interconnects, and a second shielding layer stacked sequentially.

[0017] One end of the first metal interconnect layer serves as one end of the metal resistor. The other end of the first metal interconnect layer is vertically interconnected to one end of the second metal interconnect layer through a via. The other end of the second metal interconnect layer is vertically interconnected to one end of the third metal interconnect layer through a via, and so on, until the other end of the (N-1)th metal interconnect layer is vertically interconnected to one end of the Nth metal interconnect layer through a via. The other end of the Nth metal interconnect layer serves as the other end of the metal resistor.

[0018] In one embodiment, each metal interconnect layer uses metal interconnects of equal width and length arranged in a serpentine pattern.

[0019] In one embodiment, the cross comparator includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor;

[0020] The gates of the first NMOS transistor and the first PMOS transistor serve as the non-inverting input of the crossover comparator; the gates of the second NMOS transistor and the second PMOS transistor serve as the inverting input of the crossover comparator; the drains of the first NMOS transistor, the second NMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are connected to the power supply; the drains of the first PMOS transistor and the second PMOS transistor are grounded; the sources of the fifth NMOS transistor and the sixth NMOS transistor are grounded; the sources of the first NMOS transistor, the first PMOS transistor, the gates of the fifth PMOS transistor, the third NMOS transistor, the drain of the sixth PMOS transistor, and the drain of the fourth NMOS transistor serve as the output of the crossover comparator.

[0021] The source of the second NMOS transistor, the source of the second PMOS transistor, the drain of the fifth PMOS transistor, the drain of the third NMOS transistor, the gate of the sixth PMOS transistor, and the gate of the fourth NMOS transistor are connected together; the gate of the third PMOS transistor and the gate of the fourth PMOS transistor serve as a second enable input terminal; the drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor; the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor; the gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor serve as a first enable input terminal; the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor; and the drain of the sixth NMOS transistor is connected to the source of the fourth NMOS transistor.

[0022] In one embodiment, the switched capacitor integrator filter includes: a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third capacitor, and a fourth capacitor;

[0023] The gates of the seventh NMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the eighth NMOS transistor serve as the inverting switch signal input terminals of the switched-capacitor integrator filter; the drain of the seventh NMOS transistor is connected to the power supply; the sources of the seventh NMOS transistor, the ninth NMOS transistor, and the seventh PMOS transistor are connected to one end of the third capacitor; the gates of the ninth NMOS transistor and the tenth NMOS transistor serve as the non-inverting switch signal input terminals of the switched-capacitor integrator filter; the drains of the ninth NMOS transistor, the tenth NMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are connected to the drain of the eighth NMOS transistor; the source of the eighth NMOS transistor, the other end of the third capacitor, and one end of the fourth capacitor are grounded; the drain of the tenth NMOS transistor, the source of the eighth PMOS transistor, and the other end of the fourth capacitor serve as the output terminals of the switched-capacitor integrator filter.

[0024] In one embodiment, the thickness of the first shielding layer is greater than the thickness of the metal interconnect layer.

[0025] In one embodiment, the thickness of the second shielding layer is greater than the thickness of the metal interconnect layer.

[0026] The aforementioned CMOS temperature sensor based on RC phase delay detection connects the first output of a voltage-controlled oscillator (VCO) to the input of a frequency divider. The first output of the frequency divider is connected to the non-inverting input of a multilayer metal RC temperature sensing front-end. The second output of the frequency divider is connected to the inverting input of the multilayer metal RC temperature sensing front-end. The third output of the frequency divider is connected to the first input of a phase detector. The first output of the multilayer metal RC temperature sensing front-end is connected to the non-inverting input of a cross comparator. The second output of the multilayer metal RC temperature sensing front-end is connected to the inverting input of the cross comparator. The output of the cross comparator is connected to the second input of the phase detector. The first output of the phase detector is connected to the inverting switch signal input of a switched-capacitor integrating filter. The second output of the phase detector is connected to the non-inverting switch signal input of the switched-capacitor integrating filter. The output of the switched-capacitor integrating filter is connected to the input of the VCO. The second output of the VCO is used to output a signal whose frequency is inversely proportional to the temperature. This results in a temperature sensor with strong process mobility, a more compact area, lower power consumption, and a simpler structure. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a CMOS temperature sensor based on RC phase delay detection in one embodiment;

[0028] Figure 2This is a schematic diagram of the circuit structure of the multilayer metal resistor RC temperature sensing front end in one embodiment;

[0029] Figure 3 This is a schematic diagram of the structure of a metal resistor in one embodiment;

[0030] Figure 4 This is a schematic diagram of the circuit structure of a cross comparator in one embodiment;

[0031] Figure 5 This is a schematic diagram of the circuit structure of a switched capacitor integrator filter in one embodiment;

[0032] Figure 6 This is a schematic diagram illustrating the relationship between the output frequency and temperature of a CMOS temperature sensor based on RC phase delay detection in one embodiment.

[0033] Figure 7 This is a simulation diagram of the timing relationship of key node signals of a CMOS temperature sensor in one embodiment. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0035] In one embodiment, such as Figure 1 As shown, a CMOS temperature sensor based on RC phase delay detection is provided, including: a voltage-controlled oscillator, a frequency divider, a multilayer metal RC temperature sensing front end, a cross comparator, a phase detector, and a switched capacitor integral filter;

[0036] The first output of the voltage-controlled oscillator (VCO) is connected to the input of the frequency divider. The first output of the frequency divider is connected to the non-inverting input of the multilayer metal RC temperature sensing front-end and the first enable input of the cross comparator. The second output of the frequency divider is connected to the inverting input of the multilayer metal RC temperature sensing front-end and the second enable input of the cross comparator. The third output of the frequency divider is connected to the first input of the phase detector. The first output of the multilayer metal RC temperature sensing front-end is connected to the non-inverting input of the cross comparator. The second output of the multilayer metal RC temperature sensing front-end is connected to the inverting input of the cross comparator. The output of the cross comparator is connected to the second input of the phase detector. The first output of the phase detector is connected to the inverting switch signal input of the switched capacitor integrator filter. The second output of the phase detector is connected to the non-inverting switch signal input of the switched capacitor integrator filter. The output of the switched capacitor integrator filter is connected to the input of the VCO. The second output of the VCO is used to output a signal whose frequency is inversely proportional to the temperature.

[0037] Among them, the voltage-controlled oscillator, frequency divider, multilayer metal RC temperature sensing front end, cross comparator, phase detector and switched capacitor integral filter are electrically connected to form a closed-loop frequency lock structure.

[0038] The first signal output from the first output terminal of the voltage-controlled oscillator (VCO) is denoted as FVCO. The first output terminal of the VCO is connected to the input terminal of the frequency divider. The first signal FVCO, after being divided by 1 / 4 by the frequency divider, outputs a first differential signal VIN+ from the first output terminal of the frequency divider to drive the multilayer metal RC temperature sensing front-end and the cross comparator. The second output terminal of the frequency divider outputs a second differential signal VIN- to drive the multilayer metal RC temperature sensing front-end and the cross comparator. The third output terminal of the frequency divider outputs a reference signal Q to the phase detector. The first differential signal V... IN+ is input from the non-inverting input terminal of the multilayer metal RC temperature sensing front end, the second differential signal VIN- is input from the inverting input terminal of the multilayer metal RC temperature sensing front end, the third differential signal output from the first output terminal of the multilayer metal RC temperature sensing front end is denoted as VRC+, the fourth differential signal output from the second output terminal of the multilayer metal RC temperature sensing front end is denoted as VRC-, the third differential signal VRC+ is input from the non-inverting input terminal of the cross comparator, and the fourth differential signal VRC- is input from the inverting input terminal of the cross comparator; the cross comparator captures the crossover time of the input signals and outputs a rising edge signal Vcx at the crossover point. The rising edge signal Vcx is input from the second input terminal of the phase detector and compared with the reference signal Q to read the phase difference. This causes the phase detector to output a positive switching signal Vsw and an anti-phase switching signal VNsw containing temperature information. The positive switching signal Vsw and the anti-phase switching signal VNsw are input from the positive switching signal input terminal and the anti-phase switching signal input terminal of the switched capacitor integrator, respectively. The positive switching signal Vsw and the anti-phase switching signal VNsw control the charging and discharging of the integrating capacitor in the switched capacitor integrator, thereby generating a control signal Vcon. The control signal Vcon is input to the voltage-controlled oscillator to adjust the output frequency of the voltage-controlled oscillator, thereby outputting the second signal FOUT.

[0039] Specifically, a first differential signal VIN+ and a second differential signal VIN-, whose frequency is divided by one-quarter of the original signal frequency by the first signal FVCO output from the voltage-controlled oscillator, are used, along with a reference signal Q that is 90° out of phase with the first differential signal VIN+. The first differential signal VIN+ and the second differential signal VIN- are respectively input to the RC temperature sensing front end of the multilayer metal. The RC temperature sensing front end of the multilayer metal outputs a third differential signal VRC+ and a fourth differential signal VRC-, which undergo phase shift under temperature. The first differential signal VIN+ and the second differential signal VIN- are input to a cross comparator, driving the cross comparator to capture the rising edge of the third differential signal VRC+ and... The falling edge of the fourth differential signal VRC- crosses at the point where the cross comparator outputs a rising edge signal Vcx aligned with the rising edge at the crossover point. The phase detector connects the input rising edge signal Vcx with the reference signal Q to generate a positive switching signal Vsw and an anti-phase switching signal VNsw. The positive switching signal Vsw and the anti-phase switching signal VNsw serve as control signals for the switched capacitor integrator filter, controlling the output of the switched capacitor integrator filter to control the output of the voltage-controlled oscillator (VCO) to Vcon. Under the control of the control signal Vcon, the VCO outputs a second signal FOUT whose frequency is inversely proportional to the temperature, and the corresponding temperature information can be directly read by an external counter circuit.

[0040] Among them, the rising edge signal Vcx is a square wave signal.

[0041] Among them, the second signal FOUT is a square wave signal.

[0042] The aforementioned CMOS temperature sensor based on RC phase delay detection utilizes the temperature phase shift characteristics of a multilayer metal RC sensing front-end, captures phase change information using crossover point detection, and inputs it into a closed-loop frequency-locked structure, thereby outputting a frequency signal corresponding to the temperature (i.e., the second signal FOUT). By employing a multilayer metal RC sensing front-end and a frequency-locked loop readout structure, replacing the traditional Wienbridge or Wheatstone bridge and analog-to-digital converter (ADC) readout architecture, the circuit area and power consumption are significantly reduced while maintaining temperature measurement accuracy, and good process portability is also achieved. This application can be applied to high-density integration within a system-on-a-chip (SoC), enabling real-time detection of multi-point temperature distribution and hotspot monitoring on the chip.

[0043] In one embodiment, such as Figure 2As shown, the multilayer metal RC temperature sensing front end includes a first metal resistor Rmetal1, a second metal resistor Rmetal2, a first capacitor C1, and a second capacitor C2. One end of the second metal resistor Rmetal2 and one end of the first capacitor C1 serve as the non-inverting input terminal of the multilayer metal RC temperature sensing front end. The other end of the first capacitor C1 and one end of the first metal resistor Rmetal1 serve as the first output terminal of the multilayer metal RC temperature sensing front end, outputting a third differential signal VRC+. The other end of the second metal resistor Rmetal2 and one end of the second capacitor C2 serve as the second output terminal of the multilayer metal RC temperature sensing front end, outputting a fourth differential signal VRC-. The other end of the first metal resistor Rmetal1 and the other end of the second capacitor C2 serve as the inverting input terminal of the multilayer metal RC temperature sensing front end.

[0044] In one embodiment, the first metal resistor Rmetal1 and the second metal resistor Rmetal2 are metal resistors with the same structure;

[0045] The metal resistor comprises a first shielding layer, N layers of metal interconnects, and a second shielding layer stacked sequentially. One end of the first metal interconnect layer serves as one end of the metal resistor. The other end of the first metal interconnect layer is vertically interconnected to one end of the second metal interconnect layer through a via. The other end of the second metal interconnect layer is vertically interconnected to one end of the third metal interconnect layer through a via, and so on, until the other end of the (N-1)th metal interconnect layer is vertically interconnected to one end of the Nth metal interconnect layer through a via. The other end of the Nth metal interconnect layer serves as the other end of the metal resistor.

[0046] In one embodiment, each metal interconnect layer uses metal interconnects of equal width and length arranged in a serpentine pattern.

[0047] The materials of the first shielding layer, the second shielding layer, and the Nth metal interconnect layer can be determined by the process platform. Under the same process platform, the same metal system, such as copper or aluminum, can usually be used. Different metals can also be used.

[0048] The metal thickness of the first shielding layer can be thicker than that of the metal interconnect layer to achieve a better shielding effect; the metal thickness of the first shielding layer can also be the same as that of the metal interconnect layer, or it can be thinner than that of the metal interconnect layer; different metal layers have certain differences in thickness and unit sheet resistance, and the specific thickness can be determined according to the actual required resistance value.

[0049] The metal thickness of the second shielding layer can be thicker than that of the metal interconnect layer for better shielding effect; the metal thickness of the second shielding layer can also be the same as that of the metal interconnect layer, or it can be thinner than that of the metal interconnect layer; different metal layers have certain differences in thickness and unit sheet resistance, and the specific thickness can be determined according to the actual required resistance value.

[0050] The first shielding layer can be made of metal strips arranged side by side at equal intervals, or a single piece of metal.

[0051] The second shielding layer can be made of metal strips arranged at equal intervals side by side, or a single piece of metal.

[0052] If the first shielding layer uses metal strips arranged side by side with equal spacing, the gap between each metal strip can be 1 to 2 times the minimum spacing specified in the process.

[0053] If the second shielding layer uses metal strips arranged at equal intervals, the gap between each metal strip can be 1 to 2 times the minimum spacing specified in the process.

[0054] Among them, the N-layer metal interconnect can be made of the same material, have the same thickness, and have the same length.

[0055] In this case, the gap between the metal interconnects arranged side by side in the metal interconnect layer is smaller than the width of the metal interconnect.

[0056] In this case, the metal interconnects of two adjacent metal interconnect layers are perpendicular to each other.

[0057] In one embodiment, the thickness of the first shielding layer is greater than the thickness of the metal interconnect layer.

[0058] In one embodiment, the thickness of the second shielding layer is greater than the thickness of the metal interconnect layer.

[0059] It should be understood that the metal resistor consists of multiple layers of metal interconnects and shielding layers (i.e., the first and second shielding layers) to enhance anti-interference capabilities and improve resistance consistency. The multiple metal interconnects serve as the effective conductive path for the temperature-sensing resistor. The metal interconnect lines in the metal interconnects are arranged as straight lines of equal width and length in a serpentine layout, and are vertically interconnected level by level through vias. The metal interconnect lines in each layer maintain the same geometric dimensions on the layout, forming a continuous high-resistance resistor unit. Metal layers (i.e., the top and bottom layers, with the bottom layer being the metal layer closest to the substrate) are placed above and below the metal resistor structure as shielding layers. The metal resistor is further connected to a capacitor with a metal-oxide-metal (MOM) structure to form the multilayer metal resistor RC temperature-sensing front end.

[0060] In one example, such as Figure 3 As shown, the metal resistor is formed by stacking a first shielding layer M0, five metal interconnect layers M1-M5, and a second shielding layer M6 in sequence. Each metal interconnect layer uses metal interconnects of equal width and length arranged in a serpentine pattern. One end of the first metal interconnect layer M1 serves as one end of the metal resistor. The other end of the first metal interconnect layer M1 is vertically interconnected to one end of the second metal interconnect layer M2 through a via. The other end of the second metal interconnect layer M2 is vertically interconnected to one end of the third metal interconnect layer M3 through a via, and so on, until the other end of the fourth metal interconnect layer M4 is vertically interconnected to one end of the fifth metal interconnect layer M5 through a via. The other end of the fifth metal interconnect layer M5 serves as the other end of the metal resistor.

[0061] In one embodiment, such as Figure 4 As shown, the cross comparator includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6.

[0062] The gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 serve as the non-inverting input of the cross comparator, inputting the third differential signal VRC+; the gates of the second NMOS transistor MN2 and the second PMOS transistor MP2 serve as the inverting input of the cross comparator, inputting the fourth differential signal VRC-; the drains of the first NMOS transistor MN1, the second NMOS transistor MN2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to the power supply VDD; the drains of the first PMOS transistor MP1 and the second PMOS transistor MP2 are grounded to GND; the sources of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are grounded to GND; the sources of the first NMOS transistor MN1, the first PMOS transistor MP1, the fifth PMOS transistor MP5, the third NMOS transistor MN3, the sixth PMOS transistor MP6, and the fourth NMOS transistor MN4 serve as the output of the cross comparator, outputting the rising edge signal Vcx;

[0063] The source of the second NMOS transistor MN2, the source of the second PMOS transistor MP2, the drain of the fifth PMOS transistor MP5, the drain of the third NMOS transistor MN3, the gate of the sixth PMOS transistor MP6, and the gate of the fourth NMOS transistor MN4 are connected together; the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 serve as the second enable input terminal to input the second differential signal VIN-; the drain of the third PMOS transistor MP3 is connected to the source of the fifth PMOS transistor MP5; the drain of the fourth PMOS transistor MP4 is connected to the source of the sixth PMOS transistor MP6; the gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 serve as the first enable input terminal to input the first differential signal VIN+; the source of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN5; and the drain of the sixth NMOS transistor MN6 is connected to the source of the fourth NMOS transistor MN4.

[0064] Among them, the first differential signal VIN+ and the second differential signal VIN- serve as the enable signals of the cross comparator, controlling the start and stop of the cross comparator.

[0065] In one embodiment, such as Figure 5 As shown, the switched capacitor integrator filter includes: the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the third capacitor C3, and the fourth capacitor C4.

[0066] The gates of the seventh NMOS transistor MN7, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the eighth NMOS transistor MN8 serve as the inverting switch signal input terminals for the switched capacitor integrating filter, receiving the inverting switch signal VNsw. The drain of the seventh NMOS transistor MN7 is connected to the power supply VDD. The sources of the seventh NMOS transistor MN7, the ninth NMOS transistor MN9, and the drain of the seventh PMOS transistor MP7 are connected to one end of the third capacitor C3. The gates of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 serve as the switching capacitor integrating filter... The pulse width signal Vsw is input to the non-inverting switching signal input terminal of the filter; the drain of the ninth NMOS transistor MN9, the source of the tenth NMOS transistor MN10, the source of the seventh PMOS transistor MP7, the drain of the eighth PMOS transistor MP8, and the drain of the eighth NMOS transistor MN8 are connected; the source of the eighth NMOS transistor MN8, the other end of the third capacitor C3, and one end of the fourth capacitor C4 are connected to ground GND; the drain of the tenth NMOS transistor MN10, the source of the eighth PMOS transistor MP8, and the other end of the fourth capacitor C4 serve as the output terminal of the switched capacitor integrator filter, outputting the control signal Vcon.

[0067] Compared with the prior art, this application has the following significant technical effects and comprehensive advantages:

[0068] (1) The area is significantly reduced, making it suitable for large-scale on-chip deployment.

[0069] The multilayer metal RC temperature sensing front end used in this application is a compact RC temperature sensing front end composed of multilayer metal stacked metal resistors and MOM-structured capacitors. Only two metal resistors and two capacitors are needed to complete phase temperature-sensitive modulation. The overall temperature sensor structure does not rely on resistor bridges, operational amplifiers or ADC readout links, which greatly reduces the layout area.

[0070] With 40nm CMOS technology, the area of ​​the multilayer metal RC temperature sensing front end can be reduced to 0.003mm. 2 The entire CMOS temperature sensor area is approximately 0.005 mm². 2 Compared to traditional poly resistor bridge or op-amp + ADC architectures (typically 0.03mm), 2 -0.08mm 2 It can reduce area overhead by 70%–85%, making it more suitable for the distributed deployment needs of a large number of compact sensor units in on-chip hotspot monitoring.

[0071] (2) Extremely low power consumption and compatible with low voltage power supply.

[0072] This application utilizes RC phase delay as a temperature information carrier and forms a closed-loop structure with a cross-comparator and a voltage-controlled oscillator, thus avoiding the static current consumption of traditional analog links.

[0073] The voltage-controlled oscillator adopts a low swing structure with a typical power consumption of 6μW–8μW; the switched capacitor integral filter has no static power consumption, and the total power consumption of the overall CMOS temperature sensor can be controlled within 8μW–10μW.

[0074] Compared to solutions that rely on analog amplification and ADC (with power consumption typically ranging from 20μW to 100μW), this application has significant energy efficiency advantages and is particularly suitable for high-performance AI chips, CPU / GPU local hotspot monitoring, and on-chip low-power temperature tracking.

[0075] (3) The system has a simple structure, a high degree of digitalization, and stable temperature conversion accuracy.

[0076] This application utilizes the RC phase shift generated by the temperature change of multi-layer metal stacked metal resistors to make the phase form a monotonically linear relationship with temperature; a cross comparator accurately detects the differential phase, and a switched capacitor integral filter replaces the traditional charge pump to realize phase error integration, thus forming a digitally friendly closed-loop frequency locking structure.

[0077] This architecture effectively avoids static offset caused by current source mismatch, exhibits low PVT sensitivity, and provides stable temperature-frequency conversion characteristics. Within the full temperature range of -40°C to 80°C, the phase changes by approximately 0.32° for every 1°C temperature change, with the corresponding temperature output error controllable within ±0.8°C.

[0078] Since the output is a pure digital frequency signal, the temperature can be read directly by an external low-cost counter without the need for an ADC or analog link, which facilitates rapid integration into digital system chips.

[0079] The aforementioned CMOS temperature sensor based on RC phase delay detection features strong process transferability, more compact area, lower power consumption, and simpler structure. It is also a novel temperature sensor that can directly output digital frequency signals.

[0080] like Figure 6 The diagram illustrates the relationship between the output frequency of the CMOS temperature sensor based on RC phase delay detection and temperature in this embodiment of the application. It can be seen that within the shown temperature range, the frequency of the output second signal FOUT exhibits a monotonic relationship with increasing temperature, and the change trend is smooth and continuous, without any abrupt changes or reversals, demonstrating excellent linearity. This indicates that the CMOS temperature sensor of this application can stably map changes in ambient temperature to corresponding changes in output frequency, achieving effective temperature sensing and quantification.

[0081] like Figure 7 The figure shown is a simulation diagram of the timing relationship of the key node signals of the CMOS temperature sensor in the embodiment of this application.

[0082] This application presents a compact, high-efficiency CMOS temperature sensor. It employs an RC network-based phase detection scheme, with a closed-loop frequency-locked structure outputting a temperature-corresponding frequency signal (i.e., the second signal FOUT). A multi-layer metal RC sensing front-end converts temperature changes into phase shifts, which are detected by a designed cross-comparator, and the result is fed into the closed-loop frequency-locked structure. The frequency-locked structure uses a designed switched-capacitor integral filter instead of a traditional charge pump, avoiding the current source mismatch problem inherent in charge pump structures. This allows the application to significantly reduce area footprint and power consumption while maintaining temperature measurement accuracy.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A CMOS temperature sensor based on RC phase delay detection, characterized in that, The CMOS temperature sensor based on RC phase delay detection includes: a voltage-controlled oscillator, a frequency divider, a multilayer metal RC temperature sensing front end, a cross comparator, a phase detector, and a switched capacitor integral filter. The first output terminal of the voltage-controlled oscillator is connected to the input terminal of the frequency divider. The first output terminal of the frequency divider is connected to the non-inverting input terminal of the multilayer metal RC temperature sensing front end and the first enable input terminal of the cross comparator. The second output terminal of the frequency divider is connected to the inverting input terminal of the multilayer metal RC temperature sensing front end and the second enable input terminal of the cross comparator. The third output terminal of the frequency divider is connected to the first input terminal of the phase detector. The first output terminal of the multilayer metal RC temperature sensing front end is connected to the non-inverting input terminal of the cross comparator. The second output terminal of the multilayer metal RC temperature sensing front end is connected to the inverting input terminal of the cross comparator. The output terminal of the cross comparator is connected to the second input terminal of the phase detector. The first output terminal of the phase detector is connected to the inverting switch signal input terminal of the switched capacitor integrator filter. The second output terminal of the phase detector is connected to the non-inverting switch signal input terminal of the switched capacitor integrator filter. The output terminal of the switched capacitor integrator filter is connected to the input terminal of the voltage-controlled oscillator. The second output terminal of the voltage-controlled oscillator is used to output a signal whose frequency is inversely proportional to the temperature.

2. The CMOS temperature sensor based on RC phase delay detection according to claim 1, characterized in that, The multilayer metal RC temperature sensing front end includes a first metal resistor, a second metal resistor, a first capacitor, and a second capacitor; One end of the second metal resistor and one end of the first capacitor serve as the positive input terminal of the multilayer metal RC temperature sensing front end, the other end of the first capacitor and one end of the first metal resistor serve as the first output terminal of the multilayer metal RC temperature sensing front end, the other end of the second metal resistor and one end of the second capacitor serve as the second output terminal of the multilayer metal RC temperature sensing front end, and the other end of the first metal resistor and the other end of the second capacitor serve as the inverting input terminal of the multilayer metal RC temperature sensing front end.

3. The CMOS temperature sensor based on RC phase delay detection according to claim 2, characterized in that, The first metal resistor and the second metal resistor are metal resistors with the same structure; The metal resistor is composed of a first shielding layer, N layers of metal interconnects, and a second shielding layer stacked sequentially. One end of the first metal interconnect layer serves as one end of the metal resistor. The other end of the first metal interconnect layer is vertically interconnected to one end of the second metal interconnect layer through a via. The other end of the second metal interconnect layer is vertically interconnected to one end of the third metal interconnect layer through a via, and so on, until the other end of the (N-1)th metal interconnect layer is vertically interconnected to one end of the Nth metal interconnect layer through a via. The other end of the Nth metal interconnect layer serves as the other end of the metal resistor.

4. The CMOS temperature sensor based on RC phase delay detection according to claim 3, characterized in that, Each metal interconnect layer uses metal interconnects of equal width and length arranged in a serpentine pattern.

5. The CMOS temperature sensor based on RC phase delay detection according to claim 1, characterized in that, The cross comparator includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; The gates of the first NMOS transistor and the first PMOS transistor serve as the non-inverting input of the crossover comparator; the gates of the second NMOS transistor and the second PMOS transistor serve as the inverting input of the crossover comparator; the drains of the first NMOS transistor, the second NMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are connected to the power supply; the drains of the first PMOS transistor and the second PMOS transistor are grounded; the sources of the fifth NMOS transistor and the sixth NMOS transistor are grounded; the sources of the first NMOS transistor, the first PMOS transistor, the gates of the fifth PMOS transistor, the third NMOS transistor, the drain of the sixth PMOS transistor, and the drain of the fourth NMOS transistor serve as the output of the crossover comparator. The source of the second NMOS transistor, the source of the second PMOS transistor, the drain of the fifth PMOS transistor, the drain of the third NMOS transistor, the gate of the sixth PMOS transistor, and the gate of the fourth NMOS transistor are connected together; the gate of the third PMOS transistor and the gate of the fourth PMOS transistor serve as a second enable input terminal; the drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor; the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor; the gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor serve as a first enable input terminal; the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor; and the drain of the sixth NMOS transistor is connected to the source of the fourth NMOS transistor.

6. The CMOS temperature sensor based on RC phase delay detection according to claim 1, characterized in that, The switched capacitor integrator filter includes: a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third capacitor, and a fourth capacitor; The gates of the seventh NMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the eighth NMOS transistor serve as the inverting switch signal input terminals of the switched-capacitor integrator filter; the drain of the seventh NMOS transistor is connected to the power supply; the sources of the seventh NMOS transistor, the ninth NMOS transistor, and the seventh PMOS transistor are connected to one end of the third capacitor; the gates of the ninth NMOS transistor and the tenth NMOS transistor serve as the non-inverting switch signal input terminals of the switched-capacitor integrator filter; the drains of the ninth NMOS transistor, the tenth NMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are connected to the drain of the eighth NMOS transistor; the source of the eighth NMOS transistor, the other end of the third capacitor, and one end of the fourth capacitor are grounded; the drain of the tenth NMOS transistor, the source of the eighth PMOS transistor, and the other end of the fourth capacitor serve as the output terminals of the switched-capacitor integrator filter.

7. The CMOS temperature sensor based on RC phase delay detection according to claim 3, characterized in that, The thickness of the first shielding layer is greater than the thickness of the metal interconnect layer.

8. The CMOS temperature sensor based on RC phase delay detection according to claim 3, characterized in that, The thickness of the second shielding layer is greater than the thickness of the metal interconnect layer.

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