Temperature self-adaptive adjusting method and system of eMMC memory
By monitoring the temperature change rate of the eMMC memory in real time and adjusting the voltage, frequency, and signal timing in stages, the problem of insufficient performance and reliability of eMMC memory under extreme temperatures is solved, achieving higher operational reliability and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-04
- Publication Date
- 2026-03-24
AI Technical Summary
Existing eMMC memories suffer from insufficient performance and reliability when operating at extreme temperatures. They lack real-time adaptive adjustment mechanisms, leading to problems such as signal latch position offset, insufficient data retention time, high bit error rate, and abnormal power supply ripple.
By monitoring the rate of temperature change in real time through temperature sensors and ADC modules, voltage, frequency, IO drive capability, and signal timing are adjusted in segments. Combined with diagnostic testing and a fast response mechanism, the parameters are adaptively adjusted to prevent thermal shock damage.
This improves the reliability and performance stability of eMMC memory over a wide temperature range, reduces high-temperature failure rate and low-temperature data error rate, extends temperature cycle life, and achieves the best balance between performance and power consumption.
Smart Images
Figure CN121722318A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of embedded memory technology, and in particular to a method and system for temperature adaptive regulation of eMMC memory. Background Technology
[0002] Embedded multimedia cards (eMMC), as an embedded storage solution integrating NAND Flash memory and a controller, are widely used in smartphones, tablets, IoT devices, industrial control, and automotive electronics due to their compact structure and simplified interface design. Although existing wide-temperature eMMC products can operate in extreme temperatures, their performance and reliability still face significant challenges in practical applications, especially in high-speed data transmission modes such as HS400 and high frequencies such as 50MHz and above. This is mainly due to the high sensitivity of eMMC's electrical characteristics to temperature changes. In high-speed modes, timing deviations can be caused by factors such as differences in silicon process technology, operating temperature and voltage variations, PCB load, and fluctuations in the output timing of the eMMC device itself.
[0003] Existing tuning algorithms may not be able to respond to dynamic temperature changes in real time. If the temperature changes significantly during device operation, the initial tuning settings may no longer be optimal, leading to problems such as signal latch position offset and insufficient data setup / hold time. This, in turn, affects the stability of high-speed data transmission and increases the risk of bit error rate. The quality and stability of the power supply for the eMMC interface are crucial for the normal operation of the device. When the performance indicators of the eMMC power supply circuit are affected by low temperatures, abnormal ripple may be output, causing the eMMC to fail to start normally. In high-temperature environments, unstable power supply voltage can also cause read / write anomalies. Problems such as interface electrical parameter mismatch, controller logic timing disorder, and overall system performance degradation caused by drastic temperature changes lack effective means for real-time, adaptive closed-loop control at the system level.
[0004] Therefore, it is essential to provide a temperature adaptive adjustment method and system for eMMC memory that can automatically, collaboratively, and in real time adjust the core operating parameters of eMMC according to temperature changes, thereby fundamentally improving the operating reliability, performance stability, and product lifespan of eMMC in a wide temperature range environment. Summary of the Invention
[0005] In view of this, the present invention proposes a temperature adaptive adjustment method and system for eMMC memory that adaptively adjusts operating parameters according to the current temperature to keep the memory in the optimal operating state.
[0006] On one hand, the present invention provides a temperature adaptive adjustment method for eMMC memory, comprising the following steps: Obtain the real-time temperature and temperature change rate of the eMMC memory; If the temperature change rate does not exceed the change rate threshold, execute the corresponding parameter adjustment strategy according to the change of the preset temperature range where the real-time temperature of the eMMC memory is located; After the parameter adjustment, run the diagnostic test session to evaluate the performance of the eMMC memory under the current parameters, and according to the result of the performance evaluation, activate the current configuration or roll back to restore the configuration before the parameter adjustment; If the temperature change rate exceeds the change rate threshold, regardless of the real-time temperature of the eMMC memory, directly interrupt the current process and enter the fast response process, skip the diagnostic test session, directly apply the predefined conservative parameters to the eMMC memory until the temperature change rate returns to normal and then execute the parameter adjustment strategy, or reduce the performance of the eMMC memory to the lowest level.
[0007] Based on the above technical solutions, preferably, the obtaining of the real-time temperature and temperature change rate of the eMMC memory is to configure a temperature sensor and an ADC module connected in series electrically. The temperature sensor is set on the eMMC memory and is used to obtain an analog signal proportional to the temperature and output it to the ADC module. The ADC module converts the analog signal into a digital value, filters out the instantaneous noise, and obtains a sequence of temperature values at different times. The temperature change rate is calculated by dividing the difference between adjacent temperature sequence values by the sampling time period.
[0008] Based on the above technical solutions, preferably, the preset temperature range includes a normal temperature range T_low ≤ T < T_high; a high temperature protection range T_high ≤ T < T_critical_high; an extreme high temperature range T ≥ T_critical_high; a low temperature compensation range T_critical_low ≤ T < T_low; an extreme low temperature range T < T_critical_low; where T is the real-time temperature of the eMMC memory, T_low is the low temperature threshold, T_critical_low is the extreme low temperature threshold, T_high is the high temperature threshold, and T_critical_high is the extreme high temperature threshold.
[0009] Preferably, the change of the preset temperature range means that when the real-time temperature T enters the adjacent preset temperature range from the current preset temperature range, if the real-time temperature T is more than 5°C above the lower temperature threshold of the adjacent preset temperature range or less than 5°C below the upper temperature threshold of the adjacent preset temperature range, and maintains for more than 5 odd sampling periods, it is determined that the preset temperature range corresponding to the real-time temperature T has changed.
[0010] Preferably, the corresponding parameter adjustment strategy is executed according to the preset temperature range in which the real-time temperature T of the eMMC memory is located. This involves adjusting the voltage parameters, frequency parameters, IO drive capability, and signal timing of the eMMC memory based on the range in which the real-time temperature T of the eMMC memory is located, and temporarily storing the adjusted parameters in a register. Among them, the voltage parameter is adjusted as follows: when the real-time temperature T is in the normal temperature range, the default voltage value is used; when the real-time temperature T is in the high temperature protection range or the extreme high temperature range, the voltage value is reduced based on the default voltage value; when the real-time temperature T is in the low temperature compensation range or the extreme low temperature range, the voltage value is increased based on the default voltage value. The frequency parameter is adjusted so that when the real-time temperature T is within the normal temperature range, the default frequency is [value missing]. f 0, and adaptively adjusts according to the load of the eMMC memory; when the real-time temperature T is within the high-temperature protection range, the frequency changes from the default value. f 0 is reduced by 20%-50%; when the real-time temperature T is in the extreme high-temperature range, the frequency is reduced from the default value. f 0% reduction; when the real-time temperature T is within the low-temperature compensation range, the frequency of the eMMC memory is maintained at the default value. f 0 or from the default value f 0. Increase by 5%-10%; when the real-time temperature T is in the extreme low temperature range, the frequency increases from the default value. f The frequency reduction is 0, and the extent of the reduction is related to temperature; the lower the temperature, the higher the frequency reduction ratio. The IO drive capability is adjusted such that when the real-time temperature T is within the normal temperature range and the continuous transfer rate is ≤20 MB / s, the on-chip termination resistor ODT is not enabled, and the slew rate remains at its initial value. SR 0, drive current is I 0; When the real-time temperature T is within the normal temperature range and the continuous transmission rate is within the range of (20MB / s, 50MB / s), the on-chip termination resistor ODT is not enabled, and the slew rate remains at its initial value. SR 0, drive current adjusted to 2 I 0; When the real-time temperature T is within the high-temperature protection range or the continuous transmission rate is ≥50MB / s, the on-chip terminating resistor ODT is enabled, and the slew rate is adjusted to 1.67. SR 0, drive current adjusted to 3 I 0, 4 I 0; When the real-time temperature T is within the low-temperature compensation range, extreme low-temperature range, or extreme high-temperature range, the on-chip terminating resistor ODT is activated, adjusting the slew rate to 2.4. SR 0, drive current adjusted to 5 I 0, 6 I 0, 8 I 0; The signal timing is adjusted as follows: when the real-time temperature T is within the normal temperature range, the setup time, hold time, and phase of the switch signal remain unchanged from their initial values, with a duty cycle of 50%; when the real-time temperature T is within the high-temperature protection range, the setup time, hold time, and phase of the switch signal are all reduced from their initial values, with the duty cycle adjusted to 51%; when the real-time temperature T is within the extreme high-temperature range, the setup time, hold time, and phase of the switch signal are further reduced from the parameters corresponding to the high-temperature protection range, with the duty cycle adjusted to 52%; when the real-time temperature T is within the low-temperature compensation range, the setup time, hold time, and phase of the switch signal are all increased from their initial values, with the duty cycle adjusted to 49%; when the real-time temperature T is within the extreme low-temperature range, the setup time, hold time, and phase of the switch signal are further increased from the parameters corresponding to the low-temperature compensation range, with the duty cycle adjusted to 48%.
[0011] Further preferably, after parameter adjustment, a diagnostic test is run to evaluate the performance of the eMMC memory under the current parameters, including the following: First, the parameters selected for the parameter adjustment strategy are verified for safety to ensure that the selected parameters are within the set range; after passing the safety verification, the stability test of the eMMC memory in the current state is further performed. The stability test includes signal integrity analysis, bit error rate test and timing margin test.
[0012] More preferably, the signal integrity analysis includes the following: indirectly evaluating the eye diagram quality by measuring the jitter and level stability of the data signal near the sampling point, with the eye height and eye width of the eye diagram reaching more than 60% of the ideal value; capturing the peak-to-peak value during signal transitions, with overshoot / undershoot not exceeding 20% of the signal amplitude, and confirming that the peak jitter does not exceed 10% of the clock cycle; The bit error rate (BER) test includes the following: In write test mode, a pseudo-random sequence or a specific bit sequence is written to the eMMC memory, then the written data is read, and the number of error bits compared to the original data of the input sequence is checked. This read-write process is repeated multiple times, and the BER is calculated. The BER test criterion is: the target uncorrectable bit error rate is less than 10. -12 The warning threshold is 10. -10 The error threshold is 10. -8 ; Timing margin testing assesses timing margin by adjusting the phase of the data gating signal to find a window that can be correctly sampled. An adjustable phase offset is applied to the data gating signal, and a scan is performed from 0 to 360 degrees. Read and write tests are performed at each phase point, and the range of error-free phases is recorded. The setup time and hold time margins are obtained by multiplying the phase range by the time corresponding to each phase step. The criteria for timing margin testing are: setup time margin is greater than 10% of the clock cycle, hold time margin is greater than 10% of the clock cycle, and the effective data window is inside the eye diagram's open area and is not less than 15% of the ideal eye diagram area.
[0013] Further preferably, based on the performance evaluation results, the rollback is triggered after performing stability testing on the eMMC memory in its current state and finding any of the following situations: 1) After applying the new parameter adjustment strategy, if any of the signal integrity analysis, bit error rate test, or timing margin test in the current state of the stability test fails, the register parameters corresponding to the most recently used stable configuration are restored; 2) If the temperature change rate of the eMMC memory exceeds the change rate threshold after applying the new parameter adjustment strategy, the register parameters corresponding to the most recently used stable configuration are restored; 3) If there is a command response delay in the eMMC memory or continuous errors in data transmission, the register parameters corresponding to the most recently used stable configuration are restored; 4) If the voltage or frequency of the eMMC memory cannot be stabilized at the adjusted value after applying the new parameter adjustment strategy, the register parameters corresponding to the most recently used stable configuration are restored; 5) If the temperature of the eMMC memory exceeds the limit operating temperature, the rollback is triggered to the most conservative historical register parameters.
[0014] More preferably, the fast response process involves assigning predefined conservative parameters to the eMMC memory and performing a stability test on the eMMC memory based on these predefined conservative parameters. If the stability test is passed, the current state is maintained until the temperature stabilizes. After maintaining the temperature change rate below a threshold for several consecutive sampling periods, a normal parameter adjustment strategy is executed. If the eMMC memory still fails the stability test using the predefined conservative parameters, or if an abnormal temperature occurs again or the temperature change rate exceeds the threshold during the execution of the normal parameter adjustment strategy, then a safe mode is forcibly entered, and a warning message is issued.
[0015] On the other hand, the present invention provides a temperature adaptive regulation system for eMMC memory, used to implement the above-mentioned method, characterized in that it includes: The temperature sensing module is used to acquire the real-time temperature sensing signal of the eMMC memory, and after ADC conversion and filtering, calculate the temperature change rate by taking the sequence value corresponding to the real-time temperature. The control core module communicates with the temperature sensing module and is used to further determine the preset temperature range in which the real-time temperature is located when the temperature change rate of the eMMC memory does not exceed the temperature change rate threshold. Based on the preset temperature range in which the real-time temperature is located, it makes a decision on parameter adjustment strategy; when the temperature change rate of the eMMC memory does not exceed the temperature change rate threshold, it makes a decision on rapid response; after the execution of the decision, the control core module also evaluates the performance of the eMMC memory and selectively retains the current decision or rolls back the decision content. The parameter execution module communicates with the control core module and is used to adjust the parameters of the eMMC memory based on the decisions of the control core module.
[0016] The present invention provides a temperature adaptive adjustment method and system for eMMC memory, which has the following advantages compared with the prior art: 1. This solution first classifies the cases based on the rate of temperature change. In cases of abnormal temperature change rate, a fast response mechanism is implemented for the eMMC memory, entering a conservative parameter mode to effectively prevent thermal shock damage to the memory. In cases where the rate of temperature change does not exceed the threshold, the temperature is continuously adjusted in five levels to match the optimal memory performance. Compared with traditional technology, the high temperature failure rate and low temperature data error rate are significantly reduced, and the temperature cycle life and mean time between failures are extended. 2. The mechanism of multi-parameter coordinated adjustment of voltage, frequency, IO drive capability and timing adjustment is used to replace the conventional single parameter adjustment, which prevents the system instability caused by single parameter adjustment, finds the best balance between performance, power consumption and reliability, avoids sudden changes in system performance when switching parameters, and achieves a smooth transition. 3. Upgraded fault prevention capabilities, coupled with rollback mechanisms for five scenarios, covering all scenarios of signal integrity / bit error rate / temperature mutation / response anomaly / voltage instability, improving the applicability of the solution. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a flowchart illustrating the temperature adaptive adjustment method and system for eMMC memory according to the present invention. Figure 2 This invention relates to a temperature adaptive adjustment method and system memory architecture for eMMC memory; Figure 3 This is a structural diagram of the control core module and parameter execution module of the temperature adaptive adjustment method and system for eMMC memory of the present invention. Detailed Implementation
[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0020] Existing eMMC memories have relatively fixed parameter configurations and lack the ability to automatically adjust operating parameters based on real-time temperature changes, resulting in an inability to maintain optimal operating conditions during rapid temperature fluctuations. Current technologies lack coordinated adjustment mechanisms for key parameters such as voltage, frequency, I / O drive capability, and signal timing; individual parameter adjustments may lead to system instability or performance degradation. Traditional temperature compensation schemes rely on simple threshold judgments and cannot achieve fine-grained gradient adjustment. Furthermore, after parameter compensation, there is a lack of feedback adjustment mechanisms based on real-time performance monitoring. When the temperature reaches or exceeds a critical value, existing technologies lack rapid response emergency handling mechanisms, failing to effectively prevent device damage and data loss. Therefore, if... Figure 1 As shown, in one aspect, the present invention provides a temperature adaptive adjustment method for eMMC memory, comprising the following steps: S100: Obtain the real-time temperature and temperature change rate of the eMMC memory; execute further steps based on the temperature change rate. In this embodiment, the temperature change rate threshold can be set to 5℃ / ms.
[0021] Specifically, to obtain the real-time temperature and temperature change rate of the eMMC memory, a temperature sensor and an ADC module are configured with sequential electrical connections. The temperature sensor is installed on the eMMC memory to acquire an analog signal proportional to the temperature and output it to the ADC module. The ADC module converts the analog signal into a digital value, filters and eliminates instantaneous noise, and obtains a sequence of temperature values at different times. The temperature change rate is calculated by dividing the difference between the sequence values of adjacent temperatures by the sampling time period.
[0022] Typical characteristics of the temperature sensor: 10mV / s, output 500mV at 0°C; ADC module resolution is 8-12 bits, accuracy ±1°C, sampling rate 10-100Hz; real-time temperature T is obtained through the following conversion: T = T0 + (Vadc - V0) / k, where T0 is the reference temperature point during sensor calibration, Vadc is the voltage corresponding to the digital quantity of the output value of the ADC module, V0 is the reference voltage, and k is the temperature coefficient.
[0023] After obtaining the sequence values of temperature, calculate the temperature change rate △T / △t = (Tcurrent - Tprevious) / △t, where Tcurrent is the temperature at the current moment, Tprevious is the temperature at the previous sampling moment, and △t is the temperature sampling period.
[0024] S200: If the temperature change rate does not exceed the change rate threshold, then according to the change situation of the preset temperature range where the real-time temperature of the eMMC memory is located, execute the corresponding parameter adjustment strategy; after parameter adjustment, run the diagnostic test link to evaluate the performance of the eMMC memory under the current parameters, and according to the result of the performance evaluation, activate the current configuration or roll back to restore the configuration before parameter adjustment.
[0025] In this step, the preset temperature range includes the normal temperature range T_low ≤ T < T_high; the high-temperature protection range T_high ≤ T < T_critical_high; the extreme high-temperature range T ≥ T_critical_high; the low-temperature compensation range T_critical_low ≤ T < T_low; the extreme low-temperature range T < T_critical_low; where T is the real-time temperature of the eMMC memory, T_low is the low-temperature threshold, T_critical_low is the extreme low-temperature threshold, T_high is the high-temperature threshold, and T_critical_high is the extreme high-temperature threshold.
[0026] [[ID=!12]]In one embodiment, T_critical_high reaches 125 °C, T_high is 70 °C, T_low is -20 °C, and T_critical_low is -40 °C. <!
[0027] Since the five preset temperature ranges are continuous, in order to avoid frequent switching between different temperature ranges due to temperature fluctuations, this embodiment adopts a hysteresis setting. The change situation of the preset temperature range under the hysteresis setting means that when the real-time temperature T enters the adjacent preset temperature range from the current preset temperature range, the real-time temperature T is more than 5 °C above the lower temperature threshold of the adjacent preset temperature range or less than 5 °C below the upper temperature threshold of the adjacent preset temperature range, and maintains more than 5 odd sampling periods, then it is considered that the preset temperature range corresponding to the real-time temperature T has changed. In this way, even if there are occasional temperature fluctuations, it will not be regarded as a switch of the preset temperature range.
[0028] Note: There seems to be an issue with the tag numbering in the original text as "!12" and "!0000104" are not standard tag formats. I've translated them as best as possible while keeping the non-standard tags intact. You may want to check and correct those if they are errors in the original.In the above content, the corresponding parameter adjustment strategy is executed according to the preset temperature range in which the real-time temperature T of the eMMC memory is located. This means that the voltage parameters, frequency parameters, IO drive capability, and signal timing of the eMMC memory are adjusted according to the range in which the real-time temperature T of the eMMC memory is located, and the adjusted parameters are temporarily stored in the register. Among them, A, the voltage parameter adjustment is as follows: when the real-time temperature T is in the normal temperature range, the default voltage value is used; when the real-time temperature T is in the high temperature protection range or the extreme high temperature range, the voltage value is reduced based on the default voltage value; when the real-time temperature T is in the low temperature compensation range or the extreme low temperature range, the voltage value is increased based on the default voltage value.
[0029] In addition to the five larger preset temperature ranges mentioned above, the preset temperature ranges can be further subdivided into different temperature segments to achieve more precise voltage parameter adjustment. The precise range division is as follows: the positive or negative sign before the voltage adjustment amount represents the magnitude of the increase or decrease relative to the default voltage value, such as the nominal voltage of 1.8V.
[0030] B. The frequency parameter is adjusted so that when the real-time temperature T is within the normal temperature range, the default frequency is [value missing]. f 0, and adaptively adjusts according to the load of the eMMC memory; when the real-time temperature T is within the high-temperature protection range, the frequency changes from the default value. f 0 is reduced by 20%-50%; when the real-time temperature T is in the extreme high-temperature range, the frequency is reduced from the default value. f 0% reduction; when the real-time temperature T is within the low-temperature compensation range, the frequency of the eMMC memory is maintained at the default value. f 0 or from the default value f 0. Cautiously increase by 5%-10%; when the real-time temperature T is in the extreme low temperature range, the frequency will be adjusted from the default value. f The frequency is reduced by 0, and the extent of the reduction is temperature-dependent; the lower the temperature, the higher the frequency reduction ratio. The actual frequency is expressed using quantization relationships. f for: Normal temperature range: , For load factor, ; High temperature protection zone: ; Extreme high temperature range: ; Low temperature compensation range: ; Extreme low temperature range: .
[0031] C. For example Figure 2As shown, the IO drive capability is adjusted when the real-time temperature T is within the normal temperature range and the continuous transmission rate is ≤20 MB / s, the on-chip termination resistor ODT is not enabled, and the slew rate is maintained at its initial value. SR 0, drive current is I 0; When the real-time temperature T is within the normal temperature range and the continuous transmission rate is within the range of (20MB / s, 50MB / s), the on-chip termination resistor ODT is not enabled, and the slew rate remains at its initial value. SR 0, drive current adjusted to 2 I 0; When the real-time temperature T is within the high-temperature protection range or the continuous transmission rate is ≥50MB / s, the on-chip terminating resistor ODT is enabled, and the slew rate is adjusted to 1.67. SR 0, drive current adjusted to 3 I 0, 4 I 0; When the real-time temperature T is within the low-temperature compensation range, extreme low-temperature range, or extreme high-temperature range, the on-chip terminating resistor ODT is activated, adjusting the slew rate to 2.4. SR 0, drive current adjusted to 5 I 0, 6 I 0, 8 I 0.
[0032] The aforementioned IO-driven capabilities can be further categorized into the following applicable scenarios:
[0033] Different gears n The expression for the driving current is: , These are the Kronecker delta functions, the former in n = 0 is 1, otherwise it is 0, the latter is in n =7 is 1, otherwise it is 0. It can be seen that the de-stressing current increases sequentially for different ranges. The state of the internal terminating resistor is 0 for off and 1 for on.
[0034] D. Signal timing adjustment: When the real-time temperature T is within the normal temperature range, the setup time, hold time, and phase of the switch signal remain unchanged from their initial values, with a duty cycle of 50%. When the real-time temperature T is within the high-temperature protection range, the setup time, hold time, and phase of the switch signal are all reduced from their initial values, with the duty cycle adjusted to 51%. When the real-time temperature T is within the extreme high-temperature range, the setup time, hold time, and phase of the switch signal are further reduced from the parameters corresponding to the high-temperature protection range, with the duty cycle adjusted to 52%. When the real-time temperature T is within the low-temperature compensation range, the setup time, hold time, and phase of the switch signal are all increased from their initial values, with the duty cycle adjusted to 49%. When the real-time temperature T is within the extreme low-temperature range, the setup time, hold time, and phase of the switch signal are further increased from the parameters corresponding to the low-temperature compensation range, with the duty cycle adjusted to 48%.
[0035] The signal timing adjustments are summarized in the table below.
[0036]
[0037] Protective timing adjustments: Typically, when a rapid temperature change is detected or the temperature is about to reach its limit, more conservative timing parameters are used, such as increasing setup and hold times, to ensure data reliability and prevent timing violations.
[0038] High-temperature protection and compensation for extreme temperatures: Under high-temperature conditions, the delay of semiconductor devices increases and the carrier mobility decreases, resulting in slower transistor switching speeds. Therefore, timing controllers need to adjust timing parameters, such as increasing the clock cycle or adjusting the phase of the data strobe signal, to compensate for this delay and ensure that data is sampled at the correct time.
[0039] Extreme Low Temperature Compensation: While low temperatures reduce the latency of semiconductor devices, they can also cause other problems, such as degraded signal integrity. Timing controllers may need to adjust timing parameters, for example, by increasing settling time to accommodate changes in signal propagation delay or adjusting drive strength to ensure stability.
[0040] After parameter tuning is completed, the next step is to conduct diagnostic testing to evaluate the performance of the eMMC memory under the current parameters. This includes the following: First, the parameters selected for the parameter tuning strategy are verified for safety to ensure that the selected parameters are within the set range. After passing the safety verification, the stability of the eMMC memory in the current state is further tested. The stability test includes signal integrity analysis, bit error rate testing, and timing margin testing.
[0041] Signal integrity analysis includes the following: indirectly evaluating eye diagram quality by measuring jitter and level stability of the data signal near the sampling point, with eye height and eye width reaching more than 60% of the ideal value; capturing peak-to-peak values during signal transitions, with overshoot / undershoot not exceeding 20% of the signal amplitude, and confirming that peak jitter does not exceed 10% of the clock cycle; Bit error rate (BER) testing includes the following: In write test mode, a pseudo-random sequence or a specific bit sequence is written to the eMMC memory, then the written data is read, and the number of error bits compared to the original data of the input sequence is checked. This read-write process is repeated multiple times, and the BER is calculated. The BER test criterion is: the target uncorrectable bit rate is less than 10. -12 The warning threshold is 10. -10 The error threshold is 10. -8 The specific bit sequence here is a binary number consisting entirely of 0s, all of 1s, or alternating 0s and 1s.
[0042] Timing margin testing assesses timing margin by adjusting the phase of the data gating signal to find a window that can be correctly sampled. An adjustable phase offset is applied to the data gating signal, and a scan is performed from 0 to 360 degrees. Read and write tests are performed at each phase point, and the range of error-free phases is recorded. The setup time and hold time margins are obtained by multiplying the phase range by the time corresponding to each phase step. The criteria for timing margin testing are: setup time margin is greater than 10% of the clock cycle, hold time margin is greater than 10% of the clock cycle, and the effective data window is inside the eye diagram's open area and is not less than 15% of the ideal eye diagram area.
[0043] Finally, based on the performance evaluation results, the rollback is triggered either by applying the current configuration or by reverting to the configuration prior to parameter adjustment. This rollback is initiated after performing stability testing on the eMMC memory in its current state and finding any of the following: 1) If, after applying the new parameter adjustment strategy, any of the signal integrity analysis, bit error rate test, or timing margin test results in the current state's stability test fail, the register parameters corresponding to the most recently used stable configuration are restored; 2) If, after applying the new parameter adjustment strategy, the temperature change rate of the eMMC memory exceeds the change rate threshold, the register parameters corresponding to the most recently used stable configuration are restored; 3) If there is command response delay in the eMMC memory or continuous errors in data transmission, the register parameters corresponding to the most recently used stable configuration are restored; 4) If, after applying the new parameter adjustment strategy, the voltage or frequency of the eMMC memory cannot stabilize at the adjusted value, the register parameters corresponding to the most recently used stable configuration are restored; 5) If the temperature of the eMMC memory exceeds the limit operating temperature, the rollback is initiated to the most conservative historical register parameters.
[0044] Before the rollback, the parameters corresponding to the current parameter adjustment strategy stored in the current register will be deleted after an error log is generated and sent to the relevant controller.
[0045] S300: If the temperature change rate exceeds the change rate threshold, regardless of the real-time temperature of the eMMC memory, the current process will be interrupted and a fast response process will be entered directly. The diagnostic test will be skipped, and predefined conservative parameters will be applied to the eMMC memory directly until the temperature change rate returns to normal before the parameter adjustment strategy is executed, or the performance of the eMMC memory will be reduced to the lowest level.
[0046] like Figure 1 As shown, the fast response process mentioned here involves assigning predefined conservative parameters to the eMMC memory and performing stability tests based on these parameters. If the stability test passes, the current state is maintained until the temperature stabilizes. After maintaining the temperature change rate below a threshold for several consecutive sampling periods, normal parameter adjustment strategies are executed. If the eMMC memory still fails the stability test using the predefined conservative parameters, or if an abnormal temperature occurs again or the temperature change rate exceeds the threshold during the normal parameter adjustment process, it is forced into a safe mode, and a warning message is issued. The parameters for safe mode may be lower than the predefined conservative parameters.
[0047] After adopting the temperature adaptive adjustment method of the present invention, the temperature adaptability of the eMMC memory is significantly enhanced. The comparison results are shown in the table below:
[0048] Power consumption change: At room temperature: this application can save 8% to 15% energy; at high temperature: this application can save 25-30% energy by reducing frequency and voltage; at low temperature: this application can improve performance while only increasing power consumption by 10%. In addition, due to the reduction in chip junction temperature, the heat dissipation requirements can also be reduced accordingly.
[0049] Another aspect, such as Figure 2 and Figure 3 As shown, the present invention provides a temperature adaptive regulation system for eMMC memory, used to implement the above-mentioned method, comprising: The temperature sensing module is used to acquire the real-time temperature sensing signal of the eMMC memory, and after ADC conversion and filtering, calculate the temperature change rate by taking the sequence value corresponding to the real-time temperature. The control core module communicates with the temperature sensing module and is used to further determine the preset temperature range in which the real-time temperature is located when the temperature change rate of the eMMC memory does not exceed the temperature change rate threshold. Based on the preset temperature range in which the real-time temperature is located, it makes a decision on parameter adjustment strategy; when the temperature change rate of the eMMC memory does not exceed the temperature change rate threshold, it makes a decision on rapid response; after the execution of the decision, the control core module also evaluates the performance of the eMMC memory and selectively retains the current decision or rolls back the decision content. The parameter execution module communicates with the control core module and is used to adjust the parameters of the eMMC memory based on the decisions of the control core module.
[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for adaptive temperature control of eMMC memory, characterized in that, It includes the following steps: Obtain the real-time temperature and temperature change rate of the eMMC memory; If the temperature change rate does not exceed the change rate threshold, execute the corresponding parameter adjustment strategy according to the change situation of the preset temperature range where the real-time temperature of the eMMC memory is located; after parameter adjustment, run the diagnostic test session, evaluate the performance of the eMMC memory under the current parameters, and according to the result of the performance evaluation, activate the current configuration or roll back to restore the configuration before parameter adjustment; If the temperature change rate exceeds the change rate threshold, regardless of the real-time temperature of the eMMC memory, directly interrupt the current process and enter the fast response process, skip the diagnostic test session, directly apply the predefined conservative parameters to the eMMC memory, and then execute the parameter adjustment strategy until the temperature change rate returns to normal, or reduce the performance of the eMMC memory to the lowest level.
2. The temperature adaptive adjustment method for an eMMC memory according to claim 1, characterized in that, The obtaining of the real-time temperature and temperature change rate of the eMMC memory is to configure a temperature sensor and an ADC module that are electrically connected in sequence. The temperature sensor is set on the eMMC memory and is used to obtain an analog signal proportional to the temperature and output it to the ADC module. The ADC module converts the analog signal into a digital value, filters out instantaneous noise, and obtains a sequence of temperature values at different times. The temperature change rate is calculated by dividing the difference between adjacent temperature sequence values by the sampling time period.
3. The temperature adaptive adjustment method for an eMMC memory according to claim 1, characterized in that, The preset temperature range includes a normal temperature range T_low ≤ T < T_high; a high-temperature protection range T_high ≤ T < T_critical_high; an extreme high-temperature range T ≥ T_critical_high; a low-temperature compensation range T_critical_low ≤ T < T_low; an extreme low-temperature range T < T_critical_low; where T is the real-time temperature of the eMMC memory, T_low is the low-temperature threshold, T_critical_low is the extreme low-temperature threshold, T_high is the high-temperature threshold, and T_critical_high is the extreme high-temperature threshold.
4. The temperature adaptive adjustment method for an eMMC memory according to claim 3, characterized in that, The change situation of the preset temperature range means that when the real-time temperature T enters the adjacent preset temperature range from the current preset temperature range, if the real-time temperature T is more than 5°C above the lower temperature threshold of the adjacent preset temperature range or less than 5°C below the upper temperature threshold of the adjacent preset temperature range, and maintains for more than 5 odd sampling periods, it is determined that the preset temperature range corresponding to the real-time temperature T has changed.
5. The temperature adaptive adjustment method for an eMMC memory according to claim 3, characterized in that, Executing the corresponding parameter adjustment strategy according to the preset temperature range where the real-time temperature of the eMMC memory is located is to adjust the voltage parameter, frequency parameter, IO drive ability, and signal timing of the eMMC memory according to the range where the real-time temperature T of the eMMC memory is located, and temporarily store the adjusted parameters in the register; Among them, the voltage parameter is adjusted as follows: when the real-time temperature T is in the normal temperature range, the default voltage value is used; when the real-time temperature T is in the high temperature protection range or the extreme high temperature range, the voltage value is reduced based on the default voltage value; when the real-time temperature T is in the low temperature compensation range or the extreme low temperature range, the voltage value is increased based on the default voltage value. The frequency parameter is adjusted so that when the real-time temperature T is within the normal temperature range, the default frequency is [value missing]. f 0, and adaptively adjusts according to the load of the eMMC memory; when the real-time temperature T is within the high-temperature protection range, the frequency changes from the default value. f 0 is reduced by 20%-50%; when the real-time temperature T is in the extreme high-temperature range, the frequency is reduced from the default value. f 0% reduction; when the real-time temperature T is within the low-temperature compensation range, the frequency of the eMMC memory is maintained at the default value. f 0 or from the default value f 0. Increase by 5%-10%; when the real-time temperature T is in the extreme low temperature range, the frequency increases from the default value. f The frequency reduction is 0, and the extent of the reduction is related to temperature; the lower the temperature, the higher the frequency reduction ratio. The IO drive capability is adjusted such that when the real-time temperature T is within the normal temperature range and the continuous transfer rate is ≤20 MB / s, the on-chip termination resistor ODT is not enabled, and the slew rate remains at its initial value. SR 0, drive current is I 0; When the real-time temperature T is within the normal temperature range and the continuous transmission rate is within the range of (20MB / s, 50MB / s), the on-chip termination resistor ODT is not enabled, and the slew rate remains at its initial value. SR 0, drive current adjusted to 2 I 0; When the real-time temperature T is within the high-temperature protection range or the continuous transmission rate is ≥50MB / s, the on-chip terminating resistor ODT is enabled, and the slew rate is adjusted to 1.
67. SR 0, drive current adjusted to 3 I 0, 4 I 0; When the real-time temperature T is within the low-temperature compensation range, extreme low-temperature range, or extreme high-temperature range, the on-chip terminating resistor ODT is activated, adjusting the slew rate to 2.
4. SR 0, drive current adjusted to 5 I 0, 6 I 0, 8 I 0; The signal timing is adjusted as follows: when the real-time temperature T is within the normal temperature range, the setup time, hold time, and phase of the switch signal remain unchanged from their initial values, with a duty cycle of 50%; when the real-time temperature T is within the high-temperature protection range, the setup time, hold time, and phase of the switch signal are all reduced from their initial values, with the duty cycle adjusted to 51%; when the real-time temperature T is within the extreme high-temperature range, the setup time, hold time, and phase of the switch signal are further reduced from the parameters corresponding to the high-temperature protection range, with the duty cycle adjusted to 52%; when the real-time temperature T is within the low-temperature compensation range, the setup time, hold time, and phase of the switch signal are all increased from their initial values, with the duty cycle adjusted to 49%; when the real-time temperature T is within the extreme low-temperature range, the setup time, hold time, and phase of the switch signal are further increased from the parameters corresponding to the low-temperature compensation range, with the duty cycle adjusted to 48%.
6. The temperature adaptive adjustment method for an eMMC memory according to claim 5, characterized in that, After parameter adjustment, a diagnostic test is run to evaluate the performance of the eMMC memory under the current parameters. This includes the following: First, the parameters selected for the parameter adjustment strategy are verified for safety to ensure that the selected parameters are within the set range. After passing the safety verification, the stability test of the eMMC memory in the current state is further performed. The stability test includes signal integrity analysis, bit error rate test, and timing margin test.
7. The temperature adaptive adjustment method for an eMMC memory according to claim 6, characterized in that, The signal integrity analysis includes the following: indirectly evaluating eye diagram quality by measuring the jitter and level stability of the data signal near the sampling point, with the eye height and eye width of the eye diagram reaching more than 60% of the ideal value; capturing the peak-to-peak value during signal transitions, with overshoot / undershoot not exceeding 20% of the signal amplitude, and confirming that peak jitter does not exceed 10% of the clock cycle; The bit error rate (BER) test includes the following: In write test mode, a pseudo-random sequence or a specific bit sequence is written to the eMMC memory, then the written data is read, and the number of error bits compared to the original data of the input sequence is checked. This read-write process is repeated multiple times, and the BER is calculated. The BER test criterion is: the target uncorrectable bit error rate is less than 10. -12 The warning threshold is 10. -10 The error threshold is 10. -8 ; Timing margin testing assesses timing margin by adjusting the phase of the data gating signal to find a window that can be correctly sampled. An adjustable phase offset is applied to the data gating signal, and a scan is performed from 0 to 360 degrees. Read and write tests are performed at each phase point, and the range of error-free phases is recorded. The setup time and hold time margins are obtained by multiplying the phase range by the time corresponding to each phase step. The criteria for timing margin testing are: setup time margin is greater than 10% of the clock cycle, hold time margin is greater than 10% of the clock cycle, and the effective data window is inside the eye diagram's open area and is not less than 15% of the ideal eye diagram area.
8. The temperature adaptive adjustment method for an eMMC memory according to claim 7, characterized in that, Based on the performance evaluation results, the rollback is triggered when either the current configuration is applied or the configuration prior to parameter adjustment is rolled back after stability testing of the eMMC memory in the current state, and any of the following situations are found: 1) After applying the new parameter adjustment strategy, if any of the signal integrity analysis, bit error rate test, or timing margin test in the current state stability test fails, the register parameters corresponding to the most recently used stable configuration are restored; 2) If the temperature change rate of the eMMC memory exceeds the change rate threshold after applying the new parameter adjustment strategy, the register parameters corresponding to the most recently used stable configuration are restored; 3) If there is a command response delay in the eMMC memory or continuous errors in data transmission, the register parameters corresponding to the most recently used stable configuration are restored; 4) If the voltage or frequency of the eMMC memory cannot be stabilized at the adjusted value after applying the new parameter adjustment strategy, the register parameters corresponding to the most recently used stable configuration are restored; 5) If the temperature of the eMMC memory exceeds the limit operating temperature, the rollback is triggered to the most conservative historical register parameters.
9. The temperature adaptive adjustment method for an eMMC memory according to claim 6, characterized in that, The rapid response process involves assigning predefined conservative parameters to the eMMC memory and performing a stability test based on these parameters. If the stability test is passed, the current state is maintained until the temperature stabilizes. After maintaining the temperature change rate below a threshold for several consecutive sampling periods, a normal parameter adjustment strategy is executed. If the eMMC memory still fails the stability test using the predefined conservative parameters, or if an abnormal temperature occurs again or the temperature change rate exceeds the threshold during the execution of the normal parameter adjustment strategy, the system is forced into a safe mode and a warning message is issued.
10. A temperature adaptive regulation system for eMMC memory, used to implement the method as described in any one of claims 1-9, characterized in that, include: The temperature sensing module is used to acquire the real-time temperature sensing signal of the eMMC memory, and after ADC conversion and filtering, calculate the temperature change rate by taking the sequence value corresponding to the real-time temperature. The control core module communicates with the temperature sensing module and is used to further determine the preset temperature range in which the real-time temperature is located when the temperature change rate of the eMMC memory does not exceed the temperature change rate threshold. Based on the preset temperature range in which the real-time temperature is located, it makes a decision on parameter adjustment strategy; when the temperature change rate of the eMMC memory does not exceed the temperature change rate threshold, it makes a decision on rapid response; after the execution of the decision, the control core module also evaluates the performance of the eMMC memory and selectively retains the current decision or rolls back the decision content. The parameter execution module communicates with the control core module and is used to adjust the parameters of the eMMC memory based on the decisions of the control core module.