Method and system for cooperative management of gpu memory controller ecc
By modifying the ECC layout in the GPU memory controller to store ECC in each cache line, the ECC hit rate is improved and DRAM access is reduced, solving the problems of low ECC hit rate and high bandwidth consumption in the prior art, and achieving performance and energy efficiency improvements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN TEXTILE UNIV
- Filing Date
- 2026-02-13
- Publication Date
- 2026-05-19
AI Technical Summary
The layout of in-band ECC in existing GPU memory controllers results in low ECC hit rate and high memory bandwidth consumption, leading to performance bottlenecks and increased hardware costs.
By modifying the layout of in-band ECC, ECC is stored in each cache line and aggregated based on the physical interleaving dimension of memory, improving the cache hit rate. When a hit occurs, ECC is directly extracted for data verification, and when a miss occurs, the ECC sector is read from DRAM to update the mapping relationship.
It improves ECC cache hit rate, reduces DRAM access and bandwidth usage, lowers memory bandwidth consumption, and enhances the performance and energy efficiency of GPU workloads.
Smart Images
Figure CN121722604B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory controller technology, and in particular to a GPU memory controller ECC collaborative management method and system. Background Technology
[0002] Currently, GPUs face severe memory reliability challenges in fields such as high-performance computing and deep learning. Existing technologies employ two error correction code techniques to address the frequent occurrence of memory errors: sideband ECC and in-band ECC.
[0003] Sideband ECC provides independent storage space and transmission pins for ECC redundancy information, separating it from the data channel. While this approach can improve performance, it requires additional hardware (such as extra DRAM chips and pins), increasing hardware costs and limiting its applicability.
[0004] In-band ECC places redundant ECC information and data in the same memory channel and DRAM row, requiring no additional hardware and being inexpensive. However, this method encroaches on the space originally used for data storage, leading to significant performance bottlenecks.
[0005] Furthermore, existing in-band ECC layouts use a "line-end concentration" approach. For example, a typical 2KB DRAM line contains 16 128B cache lines, each containing four 32B data sectors, and each 32B data sector requires 2B of ECC protection. Existing technology concentrates the ECC of the first 15 cache lines into the four 32B data sectors of the 16th cache line (i.e., the ECC cache line).
[0006] However, the existing "end-of-row concentration" layout has led to a series of problems, such as:
[0007] First, the utilization rate of ECC cache lines is low. Although ECC cache lines are used to temporarily store ECC sectors to avoid duplicate accesses, due to memory interleaving mechanisms, logically adjacent data cache lines may be physically distributed in different BankGroups that are far apart (e.g., in a 16-channel configuration, the interval can be as high as 4KB). This results in the corresponding ECC sectors being physically scattered when accessing these data cache lines, and they cannot be covered by the same RCache entry. Therefore, RCache has extremely poor spatial locality and a low hit rate.
[0008] Second, the bandwidth overhead is significant. Due to the poor reusability of ECC, each data access is highly likely to trigger an independent 32B ECC sector access. For a single 32B sector access, the additional bandwidth overhead can reach 100% (when the RCache misses, an additional 32B ECC sector needs to be accessed) or 25% (in the optimal case, accessing a 128B ECC cache requires accessing a 32B ECC sector). This approach results in an average of 41.9% memory access amplification in actual workloads, severely wasting memory bandwidth. Summary of the Invention
[0009] To address the aforementioned problems and technical requirements, a GPU memory controller ECC collaborative management method and system are proposed. This method solves the problems of low ECC hit rate and high memory bandwidth consumption that occur when in-band ECC accesses data based on the "row-end concentration" layout in the existing technology. It improves the ECC hit rate and reduces memory bandwidth consumption by modifying the layout of in-band ECC.
[0010] This application provides a GPU memory controller ECC collaborative management method, the method comprising:
[0011] Step 101: Obtain the data read request sent by the streaming multisensor, wherein the data read request carries a first data physical address;
[0012] Step 102: Based on the preset mapping relationship between data physical address and ECC storage physical address, determine whether the cache can hit the first target ECC storage physical address corresponding to the first data physical address. If yes, proceed to step 103; otherwise, proceed to step 104. The mapping relationship is the correspondence between data physical address and ECC storage physical address in each cache line. Each cache line includes: data and ECC.
[0013] Step 103: Extract the first ECC at the physical address where the first target ECC is stored, use the extracted first ECC to verify the data to be read, and return the data to be read if the verification passes.
[0014] Step 104: Read the ECC sector from the DRAM, update the mapping relationship using the ECC sector, determine the first target ECC storage physical address corresponding to the first data physical address based on the updated mapping relationship, and execute step 103.
[0015] According to the GPU memory controller ECC collaborative management method provided in the embodiments of this application, each cache line includes four 32B sectors, each line includes 16 cache lines, the first 15 cache lines are used to store data, and the 16th cache line is used to store the ECC of the first 15 cache lines.
[0016] According to the GPU memory controller ECC cooperative management method provided in the embodiments of this application, reading ECC sectors from DRAM includes:
[0017] The first target ECC storage physical address is read from the ECC sector of the DRAM, and the data to be read is read from the data sector of the DRAM.
[0018] According to the GPU memory controller ECC collaborative management method provided in the embodiments of this application, after verifying the data to be read using the extracted first ECC, it further includes:
[0019] In the event of a verification failure, determine whether the error is correctable.
[0020] If the error is determined to be correctable, correct the error that caused the verification failure and return the data to be read;
[0021] If an error is determined to be uncorrectable, an exception signal is generated to trigger exception handling.
[0022] According to the GPU memory controller ECC collaborative management method provided in the embodiments of this application, the method further includes:
[0023] Obtain a data write request sent by a streaming multisensor, wherein the data write request includes: the data to be written and a second data physical address;
[0024] Based on the data write request, perform a data write operation: write the data to be written to the second data physical address; based on the preset ECC allocation table, determine the second target ECC storage physical address corresponding to the second data physical address, generate a second ECC corresponding to the second data physical address, and store the second ECC at the second target ECC storage physical address;
[0025] Update the mapping relationship of the cache line after the write operation is performed.
[0026] According to the GPU memory controller ECC collaborative management method provided in the embodiments of this application, after performing a write operation, it further includes:
[0027] The updated second target ECC storage physical address is merged into the corresponding ECC sector, and the merged ECC sector is written into DRAM, as well as the updated data sector is written into DRAM.
[0028] This application embodiment also provides a GPU memory controller ECC collaborative management system based on a GPU memory controller ECC collaborative management method, the system including: a GPU memory controller, a streaming multiprocessor, and DRAM;
[0029] The GPU memory controller is configured to receive data read requests sent by the streaming multiprocessor, wherein the data read request carries a first data physical address; based on a preset mapping relationship between data physical addresses and ECC storage physical addresses, determine whether a cache hit can be achieved at a first target ECC storage physical address corresponding to the first data physical address, wherein the mapping relationship is the correspondence between data physical addresses and ECC storage physical addresses in each cache line, and each cache line includes: data and ECC; if yes, extract the first ECC at the first target ECC storage physical address, use the extracted first ECC to verify the data to be read, and return the data to be read if the verification passes; otherwise, read the ECC sector from DRAM, use the ECC sector to update the mapping relationship, determine the first target ECC storage physical address corresponding to the first data physical address based on the updated mapping relationship, and execute the steps of extracting the first ECC at the first target ECC storage physical address, using the extracted first ECC to verify the data to be read, and returning the data to be read if the verification passes.
[0030] According to the GPU memory controller ECC collaborative management system provided in the embodiments of this application, the GPU memory controller is further configured to acquire data write requests sent by streaming multi-sensor systems, wherein the data write request includes: data to be written and a second data physical address; based on the data write request, perform a data write operation: write the data to be written to the second data physical address; based on a preset ECC allocation table, determine a second target ECC storage physical address corresponding to the second data physical address, generate a second ECC corresponding to the second data physical address, store the second ECC at the second target ECC storage physical address; and update the mapping relationship corresponding to the cache line after the write operation is performed.
[0031] According to the GPU memory controller ECC collaborative management system provided in the embodiments of this application, the GPU memory controller includes: an address mapping module and a coordination module;
[0032] The address mapping module is used to receive the data read request sent by the streaming multiprocessor, and output the first target ECC storage physical address corresponding to the first data physical address based on the mapping relationship;
[0033] The coordination module is used to determine whether the cache can hit the physical address where the first target ECC is stored; if so, it extracts the first ECC at the physical address where the first target ECC is stored, uses the extracted first ECC to verify the data to be read, and returns the data to be read if the verification passes; otherwise, it reads the ECC sector from the DRAM, uses the ECC sector to update the mapping relationship, determines the physical address where the first target ECC is stored corresponding to the first data physical address based on the updated mapping relationship, and executes the steps of extracting the first ECC at the physical address where the first target ECC is stored, using the extracted first ECC to verify the data to be read, and returning the data to be read if the verification passes.
[0034] According to the GPU memory controller ECC collaborative management system provided in the embodiments of this application, the GPU memory controller further includes: an ECC layout management module;
[0035] The ECC layout management module is used to allocate ECC slots and update the ECC allocation table when performing data write operations.
[0036] The GPU memory controller ECC collaborative management method and system provided in this application obtains data read requests sent by streaming multisensors, wherein the data read request carries a first data physical address; based on a preset mapping relationship between the data physical address and the ECC storage physical address, it determines whether a cache hit can be achieved at the first target ECC storage physical address corresponding to the first data physical address. The mapping relationship is the correspondence between the data physical address and the ECC storage physical address in each cache line. Each cache line includes data and ECC. This application improves the data and ECC storage physical address by modifying the in-band ECC layout and performing ECC aggregation based on the memory physical interleaving dimension, storing ECC in each cache line. The application improves the ECC cache hit rate and, in the case of a hit, directly extracts the first ECC at the physical address where the first target ECC is stored. It then uses the extracted first ECC to verify the data to be read and returns the data if the verification passes. In the case of a miss, it reads the ECC sector from the DRAM, updates the mapping relationship using the ECC sector, and determines the physical address where the first target ECC is stored based on the updated mapping relationship. As can be seen, this application improves the ECC cache hit rate while reducing access to DRAM and reducing DRAM bandwidth usage. It achieves the goal of improving the ECC hit rate and reducing memory bandwidth consumption by modifying the layout of in-band ECCs. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 This is one of the flowcharts illustrating the GPU memory controller ECC collaborative management method provided in this application embodiment;
[0039] Figure 2 This is a schematic diagram of the ECC layout provided in an embodiment of this application;
[0040] Figure 3 This is the second flowchart of the GPU memory controller ECC collaborative management method provided in the embodiments of this application;
[0041] Figure 4 This is a schematic diagram of the structure of the GPU memory controller ECC collaborative management system provided in the embodiments of this application. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.
[0043] This application provides a GPU memory controller ECC collaborative management method. This method can be applied to smart terminals and servers. This application uses the application of this method in a server as an example for illustration, and some other descriptions in the embodiments are for illustrative purposes only and are not intended to limit the scope of protection of this application, and will not be described in detail thereafter. The specific implementation of the method is as follows... Figure 1 As shown:
[0044] Step 101: Obtain the data read request sent by the streaming multisensor.
[0045] The data read request carries the first data physical address.
[0046] Step 102: Based on the preset mapping relationship between the data physical address and the ECC storage physical address, determine whether the cache can hit the first target ECC storage physical address corresponding to the first data physical address. If yes, proceed to step 103; otherwise, proceed to step 104.
[0047] The mapping relationship is the correspondence between the physical address of the data in each cache line and the physical address where the ECC is stored. Each cache line includes: data and ECC.
[0048] Step 103: Extract the first ECC at the physical address where the first target ECC is stored, use the extracted first ECC to verify the data to be read, and return the data to be read if the verification passes.
[0049] Step 104: Read the ECC sector from the DRAM, update the mapping relationship using the ECC sector, determine the first target ECC storage physical address corresponding to the first data physical address based on the updated mapping relationship, and execute step 103.
[0050] The GPU memory controller ECC collaborative management method provided in this application obtains data read requests sent by streaming multi-sensor systems, wherein the data read requests carry a first data physical address; based on a preset mapping relationship between the data physical address and the ECC storage physical address, it determines whether a cache hit can be achieved at the first target ECC storage physical address corresponding to the first data physical address. The mapping relationship is the correspondence between the data physical address and the ECC storage physical address in each cache line. Each cache line includes data and ECC. This application improves the data-ECC collaborative management method by modifying the in-band ECC layout and performing ECC aggregation based on the memory physical interleaving dimension, storing ECC in each cache line. The application improves the ECC cache hit rate and, in the case of a hit, directly extracts the first ECC at the physical address where the first target ECC is stored. It then uses the extracted first ECC to verify the data to be read and returns the data if the verification passes. In the case of a miss, it reads the ECC sector from the DRAM, updates the mapping relationship using the ECC sector, and determines the physical address where the first target ECC is stored based on the updated mapping relationship. As can be seen, this application improves the ECC cache hit rate while reducing access to DRAM and reducing DRAM bandwidth usage. It achieves the goal of improving the ECC hit rate and reducing memory bandwidth consumption by modifying the layout of in-band ECCs.
[0051] Specifically, the mapping relationship is placed in the kernel, and page tables or intermediate tables are used to record the physical addresses stored in the ECC. Additionally, on some firmware-controlled platforms, this can be implemented solely through firmware / microcode, but hardware enhancement is recommended for optimal performance.
[0052] Specifically, the implementation of the mapping relationship includes:
[0053] First, the lower two digits of the column number are extracted to determine the target BankGroup (i.e., the column number is associated with the bankgroup; for columns 0-3, 4-7, 8-11, and 12-14, the lower two digits are the same, making it easy to intuitively display that the size of the cache row is the same as the column size).
[0054] Then, calculate which ECC sector the cache line should belong to (i.e., calculate the ECC sector number).
[0055] We can conclude that columns 0-3 should be located in the first ECC sector, columns 4-7 should be located in the second ECC sector, columns 8-11 should be located in the third ECC sector, and columns 12-14 should be located in the fourth ECC sector.
[0056] The ECC cache line is fixed at the 16th line.
[0057] In an ECC sector, four 8-byte granular slots are used as slots, each corresponding to an ECC for a data cache line. However, access is done at the data sector granularity, requiring more precise extraction and modification of the 2-byte ECC corresponding to each 8-byte slot.
[0058] The specific location is determined by adding the slot base address and the index of the data sector's position in the data cache line.
[0059] Correctly locate the ECC position. The process for determining the ECC address based on the physical address is as follows: change the bankgroup number to bg_target (the lower two digits of the column number); change the column number to the target column number (fixed to 15); determine the sector number (0-0-3, 1-4-7, 2-8-11, 3-12-14); determine the specific offset within the sector.
[0060] In one specific embodiment, each cache line includes four 32-byte sectors, and each line comprises 16 cache lines. The first 15 cache lines are used to store data, and the 16th cache line is used to store the ECC (Elastic Compute Code) of the first 15 cache lines. See details below. Figure 2 .
[0061] This embodiment uses a 16-channel GPU memory controller with each row (BankGroup, including BankGroup0, BankGroup1, BankGroup2 and BankGroup3) as an example, and assumes a configuration of 2B ECCs corresponding to each 32B data sector.
[0062] The 16th cache line (number 15) consists of 4 sectors (sector number, cache line number, and BankGroup number are all counted starting from 0). The first sector stores the ECC of the first 4 cache lines (i.e., the first sector stores the ECC of the four cache lines with sequence numbers 0-3, i.e., 0-0-3). The second sector stores the ECC of the next 4 cache lines (i.e., the second sector stores the ECC of the four cache lines with sequence numbers 4-7, i.e., 1-4-7). The third sector stores the ECC of the next 4 cache lines (i.e., the third sector stores the ECC of the four cache lines with sequence numbers 8-11, i.e., 2-8-11). The fourth sector stores the ECC of the three cache lines (i.e., the fourth sector stores the ECC of the three cache lines with sequence numbers 12-14, i.e., 3-12-14).
[0063] Specifically, this application replaces the four 32B sectors in the prior art with four 30B and four 2B sectors. Furthermore, storing the 30B data and the 2B ECC bit row-by-row in DRAM allows for simultaneous 32B access to obtain both data and parity bits (obtained based on ECC), reducing redundant accesses.
[0064] Specifically, if a hit occurs, the corresponding 2B ECC sector is read directly; if a miss occurs, the 32B ECC sector and the 32bB data sector are read.
[0065] For cross-bankgroup access, ideally, ECC can be provided for two cache lines. In the baseline case, RCache can hit at most one cache line. However, the layout method of this application (setting up an ECC cache in the memory controller, and determining whether a data read request will hit in the ECC cache first) conforms to the memory interleaving granularity and the memory access order, and can provide ECC for two cache lines (each 32B sector requires 2B ECC, that is, each 128B cache line requires 8B ECC, and a 32B ECC sector stores the ECC of four cache lines. This application improves the utilization from providing ECC for one cache line to providing it for two cache lines). The additional overhead of 25% (one 128B cache line / data - 32B ECC) in the baseline ideal case is reduced to 12.5% (two 128B cache lines / data, a total of 256B of data, require -32B ECC), which significantly reduces the ECC overhead and improves the ECC hit rate.
[0066] In one specific embodiment, the specific implementation of reading ECC sectors from DRAM includes:
[0067] Read the physical address of the first target ECC storage from the ECC sector of the DRAM, and read the data to be read from the data sector of the DRAM.
[0068] In one specific embodiment, after verifying the data to be read using the extracted first ECC, if the verification fails, it is determined whether the error is correctable; if it is determined to be correctable, the error that caused the verification failure is corrected and the data to be read is returned; if it is determined to be uncorrectable, an exception signal that triggers exception handling is generated.
[0069] Specifically, when the first ECC check indicates an error in the data to be read, the ECC decoding process is triggered. If the error correction fails, the error is reported and a rollback operation (including rollback write operation) is performed. The damaged data is copied to a preset backup location, and the error information is written to the log for offline analysis.
[0070] In one specific embodiment, if the layout method of this application cannot be used due to the influence of hardware performance or physical parameters, the existing layout method shall be restored.
[0071] If the frequency of uncorrectable errors exceeds the preset frequency, the layout of this application will be restored to the existing layout.
[0072] This application reduces memory access amplification, decreases DRAM bandwidth usage, and improves the overall performance of parallel GPU workloads by using spatially aware ECC aggregation and cache collaboration, while maintaining the original error correction strength. It also provides a variety of alternative implementations to balance the feasibility and cost of engineering deployment.
[0073] In one specific embodiment, the specific implementation during data writing is as follows: Figure 3 As shown:
[0074] Step 301: Obtain the data write request sent by the streaming multisensor.
[0075] Step 302: Based on the data write request, perform a data write operation: write the data to be written to the second data physical address; based on the preset ECC allocation table, determine the second target ECC storage physical address corresponding to the second data physical address, generate the second ECC corresponding to the second data physical address, and store the second ECC at the second target ECC storage physical address.
[0076] Step 303: Update the mapping relationship corresponding to the cache line after the write operation.
[0077] The data write request includes: the data to be written and the physical address of the second data.
[0078] Specifically, when performing a data write operation, this application writes the ECC to the ECC cache area to provide decision-making for ECC physical address lookup and retrieval during the read phase.
[0079] In one specific embodiment, in order to maintain data persistence, after performing the write operation, the updated second target ECC storage physical address is merged into the corresponding ECC sector, and the merged ECC sector is written into DRAM, and the updated data sector is written into DRAM.
[0080] Specifically, during the write operation, a 2B ECC is generated, the mapping is updated, and the generated 2B ECC is merged into a 32B ECC sector. Then, the merged entire sector is written to DRAM. Of course, the data sector of the write operation also needs to be written to DRAM.
[0081] This application addresses the bandwidth, capacity, and performance overhead issues caused by existing GPU in-band ECC layout and access mechanisms. By modifying the ECC layout, it significantly reduces bandwidth and capacity overhead while maintaining error correction capabilities and improving overall performance and deployability.
[0082] This application also provides a GPU memory controller ECC collaborative management system based on a GPU memory controller ECC collaborative management method, such as... Figure 4 As shown, the system includes: GPU memory controller 401, streaming multiprocessor 402, and DRAM 403.
[0083] The GPU memory controller 401 is used to receive data read requests sent by the streaming multiprocessor 402; based on a preset mapping relationship between data physical addresses and ECC storage physical addresses, it determines whether the cache can hit the first target ECC storage physical address corresponding to the first data physical address; if so, it extracts the first ECC at the first target ECC storage physical address, uses the extracted first ECC to verify the data to be read, and returns the data to be read if the verification passes; otherwise, it reads the ECC sector from the DRAM 403, uses the ECC sector to update the mapping relationship, determines the first target ECC storage physical address corresponding to the first data physical address based on the updated mapping relationship, and executes the steps of extracting the first ECC at the first target ECC storage physical address, using the extracted first ECC to verify the data to be read, and returning the data to be read if the verification passes.
[0084] The data read request carries the first data physical address.
[0085] The mapping relationship is the correspondence between the physical address of the data in each cache line and the physical address where the ECC is stored. Each cache line includes: data and ECC.
[0086] In one specific embodiment, the GPU memory controller 401 is further configured to acquire data write requests sent by streaming multisensors; based on the data write requests, perform a data write operation: write the data to be written to a second data physical address; based on a preset ECC allocation table, determine the second target ECC storage physical address corresponding to the second data physical address, generate a second ECC corresponding to the second data physical address, store the second ECC at the second target ECC storage physical address; and update the mapping relationship corresponding to the cache line after the write operation is performed.
[0087] The data write request includes: the data to be written and the physical address of the second data.
[0088] In one specific embodiment, the GPU memory controller 401 includes an address mapping module and a coordination module.
[0089] The address mapping module is used to receive data read requests sent by the streaming multiprocessor and, based on the mapping relationship, output the first target ECC storage physical address corresponding to the first data physical address.
[0090] The coordination module is used to determine whether the physical address where the first target ECC is stored can be cached. If so, the first ECC at the physical address where the first target ECC is stored is extracted, the extracted first ECC is used to verify the data to be read, and the data to be read is returned if the verification passes. Otherwise, the ECC sector is read from DRAM, the mapping relationship is updated using the ECC sector, the physical address where the first target ECC is stored is determined based on the updated mapping relationship, and the steps of extracting the first ECC at the physical address where the first target ECC is stored, verifying the data to be read using the extracted first ECC, and returning the data to be read if the verification passes are executed.
[0091] Specifically, the coordination unit manages each channel's 32BRCache, enabling ECC caching, lookup, and consistency maintenance operations.
[0092] In one specific embodiment, the GPU memory controller 401 further includes an ECC layout management module.
[0093] The ECC layout management module is used to allocate ECC slots and update the ECC allocation table when performing data write operations.
[0094] The ECC allocation table records the allocation status of ECC slots.
[0095] In one specific embodiment, the GPU memory controller 401 further includes: a strategy adjustment module, used to monitor the ECC hit rate, and when the ECC hit rate is lower than the preset hit rate within a preset time period, restore the layout method of this application to the existing layout method, and when the preset time period is reached, adjust to the layout method of this application, and continuously monitor.
[0096] In one specific embodiment, DRAM stores data and ECC sectors are determined based on the layout scheme of this application.
[0097] Specifically, the streaming multiprocessor is used to generate data read requests and data write requests, while the GPU memory controller is used to receive requests, perform address mapping, ECC management, and access DRAM.
[0098] Specifically, the streaming multiprocessor connects to the GPU memory controller via an interface, the address mapping module interacts with the ECC layout management module through an internal register interface, and the coordination module connects directly to the GPU memory controller's read / write channels and DRAM interface. All modules are interconnected within the GPU memory controller via an on-chip bus or dedicated data channel.
[0099] Specifically, the address mapping module is located at the front end of the GPU memory controller or exists as a separate module. It receives the physical address of the data, outputs the physical address for ECC storage, and provides the mapping relationship. The ECC layout management module maintains the ECC allocation table, allocates ECC slots and writes ECC metadata during the write phase, and provides ECC storage physical address lookup and retrieval decisions during the read phase. The coordination module is responsible for synchronizing ECC and data between the RCache and main memory to ensure consistency. When ECC and data are within the same memory access range, it initiates merged access to reduce the number of accesses. The policy adjustment module records the ECC access hit rate and bandwidth usage during access, and adjusts the mapping relationship or modifies the layout method based on the recorded results.
[0100] In addition, the streaming multiprocessor and the ECC layout management module exchange mapping relationships through a high-speed bus, and the coordination module and the ECC layout management module ensure a consistency protocol interface.
[0101] This application, through ECC layout optimization and RCache collaborative mechanism, can cover multiple data cache lines for one ECC sector in a single access, reducing the ECC transmission traffic required for 256B of data from 256B (100% overhead) in the traditional scheme or 64B (25% overhead) in the RCache scheme to 32B, achieving a minimum theoretical additional bandwidth overhead of 12.5%. It also exhibits good workload adaptability: in workloads with high "channel-level spatial locality" (such as PO-2MM, PA-LBM, etc.), the ECC multiplexing rate is significantly improved, the bandwidth amplification effect is effectively suppressed, and memory access amplification and bandwidth overhead are significantly reduced.
[0102] Compared to existing technologies, this application maintains an average IPC reduction of around 1%, with almost no performance loss in some high locality scenarios. Furthermore, it demonstrates significant performance improvements over existing technologies in most workloads, particularly in high locality scenarios where the IPC reduction can reach up to 50%, thereby enhancing system performance.
[0103] This application improves the ECC reuse rate, controlling the energy consumption increase according to the locality level as follows: approximately 28% for high locality workloads; approximately 30.7% for medium locality workloads; and approximately 50.3% for low locality workloads. While ensuring reliability, it significantly reduces the dynamic energy consumption introduced by ECC, effectively reducing system energy consumption and making it suitable for energy-sensitive mobile platforms and edge computing scenarios.
[0104] This application features low hardware complexity: it only requires adding lightweight address mapping logic to the memory controller, without modifying the cache hierarchy or introducing a dedicated codec. No software or protocol modifications are needed: the solution is implemented entirely within the memory controller, transparent to the upper-level operating system, drivers, programming models, and applications, requiring no software adaptation. It is easy to verify and integrate: the mapping rules are well-defined and standardized, simplifying RTL implementation and formal verification processes, reducing design risks and verification cycles. The overall implementation is simple and low-cost.
[0105] This application achieves similar performance improvements while significantly reducing hardware complexity, making it more suitable for practical chip integration. Furthermore, it eliminates the need for complex coding circuits, resulting in minimal latency and area overhead. In scenarios where random access is dominant, the ECC performance of this application remains on par with the baseline, demonstrating good degradation safety.
[0106] This application is also applicable to GPU workloads with strong sequential access characteristics, such as deep learning training, scientific computing, and image processing. It provides an achievable, highly reliable memory protection solution for cost-sensitive, energy-efficiency-priority GPU devices.
[0107] Through an innovative ECC layout and mapping mechanism, significant optimizations in bandwidth, performance, and energy efficiency are achieved with almost no increase in hardware and system complexity, providing a low-cost, high-efficiency, and easy-to-deploy reliability enhancement solution for GPU memory systems.
[0108] Finally, it should be noted that the above descriptions are merely preferred embodiments of this application, and this application is not limited to the above embodiments. It is understood that other improvements and variations directly derived or conceived by those skilled in the art without departing from the spirit and concept of this application should be considered to be included within the protection scope of this application.
Claims
1. A GPU memory controller ECC collaborative management method, characterized in that, The method includes: Step 101: Obtain the data read request sent by the streaming multisensor, wherein the data read request carries a first data physical address; Step 102: Based on the preset mapping relationship between data physical addresses and ECC storage physical addresses, determine whether the cache can hit the first target ECC storage physical address corresponding to the first data physical address. If yes, proceed to step 103; otherwise, proceed to step 104. The mapping relationship is the correspondence between data physical addresses and ECC storage physical addresses in each cache line. Each cache line includes data and ECC. Each cache line includes four 32-byte sectors. Each line includes 16 cache lines. The first 15 cache lines are used to store data, and the 16th cache line is used to store the ECC of the first 15 cache lines. The mapping relationship includes: extracting the lower 2 bits of the column number to determine the target BankGroup; calculating which ECC sector the cache line should belong to; determining the physical address where the ECC is stored based on the slot base address and the location index of the data sector in the data cache line; wherein, in the ECC sector, it is divided into four 8-byte granular slots, corresponding to the ECC of one data cache line. Step 103: Extract the first ECC at the physical address where the first target ECC is stored, use the extracted first ECC to verify the data to be read, and return the data to be read if the verification passes. Step 104: Read the ECC sector from the DRAM, update the mapping relationship using the ECC sector, determine the first target ECC storage physical address corresponding to the first data physical address based on the updated mapping relationship, and execute step 103.
2. The GPU memory controller ECC collaborative management method according to claim 1, characterized in that, Reading ECC sectors from DRAM includes: The first target ECC storage physical address is read from the ECC sector of the DRAM, and the data to be read is read from the data sector of the DRAM.
3. The GPU memory controller ECC collaborative management method according to claim 1, characterized in that, After verifying the extracted first ECC checksum of the data to be read, the following steps are also included: In the event of a verification failure, determine whether the error is correctable. If the error is determined to be correctable, correct the error that caused the verification failure and return the data to be read; If an error is determined to be uncorrectable, an exception signal is generated to trigger exception handling.
4. According to claim 1 3. The GPU memory controller ECC collaborative management method according to any one of the claims is characterized in that, The method further includes: Obtain a data write request sent by a streaming multisensor, wherein the data write request includes: the data to be written and a second data physical address; Based on the data write request, perform a data write operation: write the data to be written to the second data physical address; based on the preset ECC allocation table, determine the second target ECC storage physical address corresponding to the second data physical address, generate a second ECC corresponding to the second data physical address, and store the second ECC at the second target ECC storage physical address; Update the mapping relationship of the cache line after the write operation is performed.
5. The GPU memory controller ECC collaborative management method according to claim 4, characterized in that, After performing the write operation, the following is also included: The updated second target ECC storage physical address is merged into the corresponding ECC sector, and the merged ECC sector is written into DRAM, as well as the updated data sector is written into DRAM.
6. A GPU memory controller ECC collaborative management system based on a GPU memory controller ECC collaborative management method, characterized in that, The system includes: a GPU memory controller, a streaming multiprocessor, and DRAM; The GPU memory controller is configured to receive data read requests sent by the streaming multiprocessor, wherein the data read request carries a first data physical address; based on a preset mapping relationship between data physical addresses and ECC storage physical addresses, determine whether a cache hit can be achieved at a first target ECC storage physical address corresponding to the first data physical address, wherein the mapping relationship is the correspondence between data physical addresses and ECC storage physical addresses in each cache line, and each cache line includes: data and ECC; if yes, extract the first ECC at the first target ECC storage physical address, use the extracted first ECC to verify the data to be read, and return the data to be read if the verification passes; otherwise, read the ECC sector from DRAM, use the ECC sector to update the mapping relationship, determine the first target ECC storage physical address corresponding to the first data physical address based on the updated mapping relationship, and execute the steps of extracting the first ECC at the first target ECC storage physical address, using the extracted first ECC to verify the data to be read, and returning the data to be read if the verification passes. Each cache line consists of four 32-byte sectors, and each line contains 16 cache lines. The first 15 cache lines are used to store data, and the 16th cache line is used to store the ECC of the first 15 cache lines. The mapping relationship includes: extracting the lower 2 bits of the column number to determine the target BankGroup; calculating which ECC sector the cache line should belong to; and determining the physical address where the ECC is stored based on the slot base address and the location index of the data sector in the data cache line. In the ECC sector, it is divided into four 8-bit granular slots, corresponding to the ECC of one data cache line.
7. The GPU memory controller ECC collaborative management system according to claim 6, characterized in that, The GPU memory controller is further configured to acquire data write requests sent by streaming multisensors, wherein the data write request includes: data to be written and a second physical address; based on the data write request, perform a data write operation: write the data to be written to the second physical address; based on a preset ECC allocation table, determine the second target ECC storage physical address corresponding to the second physical address, generate a second ECC corresponding to the second physical address, and store the second ECC at the second target ECC storage physical address; update the mapping relationship corresponding to the cache line after the write operation is performed.
8. The GPU memory controller ECC collaborative management system according to claim 7, characterized in that, The GPU memory controller includes: an address mapping module and a coordination module; The address mapping module is used to receive the data read request sent by the streaming multiprocessor, and output the first target ECC storage physical address corresponding to the first data physical address based on the mapping relationship; The coordination module is used to determine whether the cache can hit the physical address where the first target ECC is stored; if so, it extracts the first ECC at the physical address where the first target ECC is stored, uses the extracted first ECC to verify the data to be read, and returns the data to be read if the verification passes; otherwise, it reads the ECC sector from the DRAM, uses the ECC sector to update the mapping relationship, determines the physical address where the first target ECC is stored corresponding to the first data physical address based on the updated mapping relationship, and executes the steps of extracting the first ECC at the physical address where the first target ECC is stored, using the extracted first ECC to verify the data to be read, and returning the data to be read if the verification passes.
9. The GPU memory controller ECC collaborative management system according to claim 8, characterized in that, The GPU memory controller also includes: an ECC layout management module; The ECC layout management module is used to allocate ECC slots and update the ECC allocation table when performing data write operations.