Electric signal transmission structure, chip and electronic equipment

Abstract

The embodiment of the invention provides an electric signal transmission structure, a processor and electronic equipment. The electric signal transmission structure comprises a first circuit module, a second circuit module and a first transmission channel group, the first circuit module comprises a plurality of first voltage isolation units, the second circuit module comprises a plurality of second voltage isolation units, the first transmission channel group comprises a plurality of transmission links, and each transmission link is configured to be connected with the first voltage isolation units and the second voltage isolation units in a one-to-one correspondence manner; wherein the first transmission channel group comprises a first transmission channel and at least one second transmission channel, and the first transmission channel comprises two transmission links which are configured to transmit a pair of differential signals and have the same transmission line length; and each transmission link corresponding to each of the at least one second transmission channel is arranged in a first area formed between the two transmission links of the first transmission channel. According to the electric signal transmission structure, the chip area can be effectively reduced, and higher noise interference resistance is realized.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an electrical signal transmission structure, chip, and electronic device. Background Technology

[0002] In circuit design, to ensure the reliability of signal transmission between the transmitter and receiver, it is necessary to improve noise immunity. However, methods such as adding isolation circuits can be effective, but these isolation circuits require a large circuit area. Therefore, effectively controlling the circuit area while improving noise immunity is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0003] At least one embodiment of this disclosure provides an electrical signal transmission structure, which includes a first circuit module, a second circuit module, and a first transmission channel group. The first circuit module includes a plurality of first voltage isolation units, the second circuit module includes a plurality of second voltage isolation units, and the first transmission channel group includes a plurality of transmission links, each transmission link being configured to connect one-to-one with the first voltage isolation unit and the second voltage isolation unit. The first transmission channel group includes a first transmission channel and at least one second transmission channel. The first transmission channel includes two transmission links configured to transmit a pair of differential signals and having the same transmission line length. The transmission links corresponding to each of the at least one second transmission channel are arranged in a first region formed between the two transmission links of the first transmission channel.

[0004] At least one embodiment of this disclosure provides a chip including at least one chip, on which an electrical signal transmission structure provided in any embodiment of this disclosure is disposed.

[0005] At least some embodiments of this disclosure provide an electronic device, which includes a chip provided in any embodiment of this disclosure. Attached Figure Description

[0006] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0007] Figure 1 A block diagram of a circuit layout structure is shown.

[0008] Figure 2 A block diagram of another circuit layout structure is shown.

[0009] Figure 3 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0010] Figure 4 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0011] Figure 5 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0012] Figure 6 A schematic diagram showing the effect comparison of noise gain when the signal gain is the same, provided by at least one embodiment of the present disclosure, is shown.

[0013] Figure 7 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0014] Figure 8 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0015] Figure 9 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0016] Figure 10 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0017] Figure 11 A block diagram of a chip provided in at least one embodiment of the present disclosure is shown.

[0018] Figure 12 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0020] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0021] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0022] In circuit design, isolators are commonly used to isolate electrical systems to improve safety and signal transmission quality. This is especially true in integrated circuits (such as chips), where the design of electrical isolation is crucial due to the high-speed and low-power requirements of integrated circuits.

[0023] Figure 1 A block diagram of a circuit layout structure is shown.

[0024] like Figure 1 The circuit layout shown includes circuit module 0 and circuit module 1, with multiple isolation channels between them. For example, circuit module 0 includes isolators I1, I2, I3, and I4 disposed within shielding ring 1, and circuit module 1 includes isolators I5, I6, I7, and I8 disposed within shielding ring 2. Two isolation channels, I and Isolation Channel 2, with different transmission directions are provided between circuit module 0 and circuit module 1.

[0025] Isolation channel 1 consists of transmission line wire1 connected between isolators I1 and I5, and transmission line wire2 connected between isolators I2 and I6. Isolation channel 1 is configured to transmit differential signals from the transmitting circuit (TX) of circuit module 0 to the receiving circuit (RX) of circuit module 1, and then amplify them by the differential amplifier Amp1 of circuit module 1 before outputting them. Transmission lines wire1 and wire2 are used to transmit a pair of differential signals.

[0026] Isolation channel 2 consists of transmission line wire3 connected between isolators I3 and I7, and transmission line wire4 connected between isolators I4 and I8. Isolation channel 2 is configured to transmit differential signals from the transmitting circuit of circuit module 1 to the receiving circuit of circuit module 0, and then amplify them by the differential amplifier Amp2 of circuit module 0 before output. Transmission lines wire3 and wire4 are used to transmit another pair of differential signals.

[0027] Differential signals are transmitted through a pair of transmission lines with opposite polarities, and a differential amplifier is used to perform differential operations on the two lines. When external noise is coupled to both lines simultaneously with the same amplitude and phase, they cancel each other out during the differential process, thereby suppressing common-mode interference.

[0028] For isolation channels 1 and 2, since they are formed by connecting transmission lines wire1, wire2, wire3, and wire4, these transmission lines will cause [problems] under high-frequency carrier conditions. Figure 1 The circuit layout shown introduces additional parasitic parameters, such as parasitic inductance, parasitic resistance, and / or parasitic capacitance.

[0029] Due to the mutual electric field distribution between multiple isolation channels, the parasitic parameters corresponding to the two transmission lines transmitting the same pair of differential signals between circuit module 0 and circuit module 1 are asymmetrical. For example, in isolation channel 1, the parasitic capacitance pC1 corresponding to transmission line wire1 is not equal to the parasitic capacitance pC2 corresponding to transmission line wire2; in isolation channel 2, the parasitic capacitance pC3 corresponding to transmission line wire3 is not equal to the parasitic capacitance pC4 corresponding to transmission line wire4.

[0030] When these parasitic parameters are asymmetrical, the common-mode noise ( Figure 1The noise source shown can couple to the transmitting circuit through the parasitic mismatch isolation channels 1 and 2. In this case, the common-mode noise cannot cancel each other out during the differential process, generating a certain degree of differential error signal. When the mismatch is severe or the noise is excessive, the differential error signal will also increase, even affecting the erroneous transmission of the receiving circuit (RX), causing the signal of the transmitting circuit (TX) to be unable to be transmitted correctly. Especially in integrated circuit design, the interaction between parasitic capacitance and the high-frequency carrier can induce resonance and edge degradation.

[0031] To avoid parasitic mismatch caused by mutual electric field interference between multiple isolation channels, the distance between the two isolation channels is increased, or further electric field shielding measures are set for each of the two isolation channels.

[0032] Figure 2 A block diagram of another circuit layout structure is shown.

[0033] like Figure 2 As shown, shielding rings are set for the two isolators corresponding to the same pair of differential signals. For example, transmission lines wire1 and wire2 of isolation channel 1 transmit one pair of differential signals, while transmission lines wire3 and wire4 of isolation channel 2 transmit another pair of differential signals. For example, isolators I1 and I2 of isolation channel 1 on circuit module 0 are placed in shielding ring 3, and isolators I3 and I4 of isolation channel 2 on circuit module 0 are placed in shielding ring 4; isolators I5 and I6 of isolation channel 1 on circuit module 1 are placed in shielding ring 5, and isolators I7 and I8 of isolation channel 2 on circuit module 1 are placed in shielding ring 6. This not only increases the distance between isolation channel 1 and isolation channel 2, but also improves the situation of asymmetric parasitic parameters corresponding to the two transmission lines (i.e., transmission lines wire1 and wire2 or transmission lines wire3 and wire4) transmitting the same pair of differential signals by setting shielding rings for the two sets of isolators of isolation channel 1 and the two sets of isolators of isolation channel 2 respectively.

[0034] However, even with increased spacing between multiple isolation channels, a certain degree of parasitic mismatch will theoretically still exist. The parasitic mismatch in each isolation channel is not eliminated; it is merely adjusted to an acceptable range. Furthermore, increasing the spacing between multiple isolation channels, and configuring shielding rings for each isolator in multiple isolation channels, both increase the circuit area. Especially in integrated circuit design, each additional isolation channel means an extra increase in area, which poses a significant challenge to integrated circuits in terms of both cost and package size.

[0035] At least one embodiment of this disclosure provides an electrical signal transmission structure, which includes: a first circuit module, a second circuit module, and a first transmission channel group; the first circuit module includes a plurality of first voltage isolation units, the second circuit module includes a plurality of second voltage isolation units, and the first transmission channel group includes a plurality of transmission links, each transmission link being configured to connect one-to-one with the first voltage isolation unit and the second voltage isolation unit; wherein, the first transmission channel group includes a first transmission channel and at least one second transmission channel, the first transmission channel including two transmission links configured to transmit a pair of differential signals and having the same transmission line length, and the transmission links corresponding to each of the at least one second transmission channel being arranged in a first region formed between the two transmission links of the first transmission channel.

[0036] In the electrical signal transmission structure of the above embodiments of this disclosure, by configuring a transmission channel group with multiple transmission links to place at least one second transmission channel in a first region formed between two transmission links with a first transmission channel, a certain electric field shielding effect is provided to the second transmission channel placed therein by two transmission links with the same transmission line length that transmit a pair of differential signals in the first transmission channel. Since the first transmission channel is not composed of the transmission lines of two adjacent transmission links, but is composed of two transmission links with similar functions (such as electric field shielding) when multiple transmission links are transmitting, and the transmission line lengths of the two transmission links are the same, the parasitic mismatch of the first transmission channel is also adjusted, thereby improving the ability of differential signals to transmit signals and resist interference through common-mode suppression.

[0037] Furthermore, in scenarios with multiple transmission links, at least one embodiment of this disclosure does not require increasing the distance between channels or setting a separate shielding ring for the voltage isolation unit of each channel. This improves the anti-interference capability of circuit signal transmission while reducing the required circuit area. Especially for integrated circuit design (such as chip design), the electrical signal transmission structure of at least one embodiment of this disclosure can effectively reduce the chip area while achieving higher noise interference immunity to ensure the reliability of signal transmission.

[0038] At least one embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same parts described in different drawings.

[0039] Figure 3 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0040] like Figure 3 As shown, the electrical signal transmission structure 100 includes circuit module 10 and circuit module 20.

[0041] For example, circuit module 10 is a first circuit module, and the multiple voltage isolation units C1, C2, C3 and C4 included in circuit module 10 are multiple first voltage isolation units; circuit module 20 is a second circuit module, and the multiple voltage isolation units C10, C20, C30 and C40 included in circuit module 20 are multiple second voltage isolation units.

[0042] Multiple transmission channels are provided between circuit module 10 and circuit module 20. Each transmission channel includes at least one transmission link. That is, the first transmission channel group provided between circuit module 10 and circuit module 20 includes multiple transmission links. Each transmission link is configured to connect to the first voltage isolation unit and the second voltage isolation unit in a one-to-one correspondence.

[0043] For example, the isolation unit can be a transformer, a digital isolator, or an isolation capacitor, etc., and the embodiments disclosed herein are not limited thereto. For example, the interference immunity of the isolation unit can be reflected in its common-mode transient immunity (CMTI) and ground noise transient immunity (GNTI) performance. Higher interference immunity ensures more reliable transmission of signals in harsh electrical application environments.

[0044] For example, multiple first voltage isolation units are disposed in the same first voltage shielding ring, and / or multiple second voltage isolation units are disposed in the same second voltage shielding ring.

[0045] For example, voltage isolation units C1, C2, C3, and C4 can be disposed within shielding ring 10, and voltage isolation units C10, C20, C30, and C40 can be disposed within shielding ring 20. For example, the shielding ring can be a metal shielding ring, a closed loop formed by a well region connected to ground potential, or a deep trench isolation ring (DTI ring) constructed using a deep trench oxide layer and polysilicon, etc., and this disclosure does not impose any limitations on these aspects. For example, the shielding ring can reduce the common-mode voltage stress borne by the isolation unit, thereby effectively releasing the CMTI / GNTI performance margin and preventing the isolation unit from failing due to overload.

[0046] However, it should be noted that although the CMTI / GNTI performance of the isolation unit can provide an isolation barrier to reduce the interference of common-mode noise on signal transmission, it cannot prevent the phenomenon of common-mode to differential-mode conversion caused by parasitic mismatch within the transmission channel transmitting a pair of differential signals.

[0047] For example, the aforementioned multiple transmission links may include: a first transmission link consisting of a transmission line Bondwire1 connecting a first voltage isolation unit C1 and a second voltage isolation unit C10; a second transmission link consisting of a transmission line Bondwire2 connecting a first voltage isolation unit C2 and a second voltage isolation unit C20; a third transmission link consisting of a transmission line Bondwire3 connecting a first voltage isolation unit C3 and a second voltage isolation unit C30; and a fourth transmission link consisting of a transmission line Bondwire4 connecting a first voltage isolation unit C4 and a second voltage isolation unit C40.

[0048] for Figure 3 Regarding the noise sources (external noise) shown, the first and fourth transmission links, which are more susceptible to noise due to their high dv / dt or continuous high-frequency, high-amplitude disturbances, will generate larger parasitic parameters, such as larger parasitic capacitances, compared to the second and third transmission links. The generation of parasitic capacitances is influenced by the distributed parameters of the circuit, such as pads, wiring, and package pins.

[0049] It should be noted that, although Figure 3 The noise source shown is drawn below the first transmission channel group in the electrical signal transmission structure. However, it is understood that the location of the noise source is only for illustration. In the actual circuit, the noise source exists in the environment in which the electrical signal transmission structure is located and can affect the signal transmission of the electrical signal transmission structure from all directions.

[0050] For example, the parasitic capacitance C1g in the first transmission link is the parasitic capacitance between transmission line Bondwire1 and the noise source; the parasitic capacitance C2g in the second transmission link is the parasitic capacitance between transmission line Bondwire2 and the noise source; the parasitic capacitance C3g in the third transmission link is the parasitic capacitance between transmission line Bondwire3 and the noise source; and the parasitic capacitance C4g in the fourth transmission link is the parasitic capacitance between transmission line Bondwire4 and the noise source.

[0051] For example, the parasitic capacitance C1g in the first transmission link is larger than that in the second transmission link, with a difference of approximately tens of fF (femtofarads). Similarly, the parasitic capacitance C4g in the fourth transmission link also differs by tens of femtofarads from that in the third transmission link, with C4g being significantly larger, where 1 fF = 1 × 10⁻⁶. -15 F (Farad).

[0052] For example, the frequency of the high-frequency carrier emitted by the transmitting circuit is determined by the high-frequency oscillator included in the transmitting circuit, and the frequency of the high-frequency oscillator is between 250MHz and 500MHz. For example, for the transmitting circuit according to 400MHz (i.e., 4×10⁻⁶), 8 When transmitting a high-frequency carrier wave (Hz), if the parasitic capacitance C1g and parasitic capacitance C2g differ by 20fF, and if the first transmission link and the second transmission link transmit a pair of differential signals together, the 20fF difference in parasitic capacitance between the two transmission links will lead to a significant degradation in common-mode rejection.

[0053] For example, impedance mismatch due to parasitic capacitance mismatch can occur, further leading to output errors in the differential pair. For instance, if the capacitance difference between the transmission lines of the two transmission links and ground (V=0, GND) is 20fF, this is equivalent to a 20kΩ impedance mismatch under a 400MHz high-frequency carrier. For example, for a noise edge of 100V / ns, this 20fF parasitic capacitance difference will generate a noise current of I = C·dV / dt = 2mA. Furthermore, due to the 20kΩ difference in impedance to ground between the two lines, this 2mA current is severely unevenly distributed across the two paths, causing common-mode noise to convert to differential-mode noise. Assuming that the load to ground (GND) of both the first and second transmission links in this differential pair is 50Ω, the aforementioned impedance mismatch will result in a differential noise voltage of approximately 100mV between the first and second transmission links. For example, when the amplitude of the useful signal transmitted through the first and second transmission links is small, this 100mV differential noise voltage can even cause a final output error.

[0054] Therefore, without increasing circuit area consumption due to additional isolation, since the first and fourth transmission links are symmetrically arranged on the outer side of multiple transmission channels, in at least one embodiment of this disclosure, the first and fourth transmission links can be used as the first transmission channel for the multiple transmission links included in the first transmission channel group. That is, although there is a large mismatch in parasitic capacitance between the first and second transmission links, the first and fourth transmission links are symmetrical in the multiple transmission channels arranged in parallel, thus the first and fourth transmission links of the first transmission channel have good system-level symmetry.

[0055] Furthermore, since the two transmission lines Bondwire1 and Bondwire4 in the first transmission channel are located on the outside, they can provide a certain electric field shielding for the transmission lines Bondwire2 and Bondwire3 used for signal transmission. This not only improves the common-mode rejection effect of the differential signal, but also enhances the anti-interference capability of the overall transmission channel.

[0056] For example, the first transmission channel includes two transmission links configured to transmit a pair of differential signals and having the same transmission line length; that is, transmission lines Bondwire1 and Bondwire4 are of equal length. This ensures that the two transmission lines transmitting a pair of differential signals maintain equal length, thereby avoiding common-mode noise. It should be noted that the "equal length" described in this disclosure does not mean strictly equal length; within acceptable error ranges, they can be considered as equal in length.

[0057] For example, see continue. Figure 3 The second and third transmission links can be used as the second transmission channel. Each transmission link corresponding to the second transmission channel is arranged in the first area formed between the two transmission links of the first transmission channel. That is, the transmission lines Bondwire2 and Bondwire3 corresponding to the second and third transmission links are respectively arranged in the first area formed between the transmission lines Bondwire1 and Bondwire4.

[0058] like Figure 3 As shown, the first transmission channel can be configured to transmit the input signal (IN) from the transmitting circuit of circuit module 20 to the receiving circuit of circuit module 10, and then output (OUT) after being amplified by the differential amplifier Amp10 of circuit module 10; the second transmission channel can be configured to transmit the input signal (IN) from the transmitting circuit of circuit module 10 to the receiving circuit of circuit module 20, and then output (OUT) after being amplified by the differential amplifier Amp20 of circuit module 20.

[0059] It should be noted that "at least one second transmission channel" refers to each transmission channel located in the first area between the first transmission channels, and the second transmission channel can be... Figure 3 The transmission channel shown can be a pair of differential signals, or it can be a transmission channel consisting of a single transmission link. This disclosure does not limit this to either. Furthermore, it is understood that multiple second transmission channels can be arranged in the first region if needed, and this disclosure does not limit this to either.

[0060] In some embodiments of this disclosure, the electrical signal transmission structure is implemented as an integrated circuit package structure or a part of an integrated circuit package structure, wherein the transmission line is a wire bond.

[0061] In integrated circuit packaging structures (such as chip packaging), wire bonding refers to the use of extremely fine metal wires to connect the pads on the die surface to the leads of the package casing or the substrate pads, achieving a crucial interconnection between the chip pads and external pins. Due to the length, curvature, and parasitic parameters of the wires, wire bonding is prone to introducing crosstalk and electromagnetic interference.

[0062] For example, Bondwire1, Bondwire2, Bondwire3, and Bondwire4 can all be bonded wires. The embodiments of this disclosure do not limit the material, specifications, or size of the transmission lines.

[0063] Since at least one chip in the chip includes any of the electrical signal transmission structures provided in the embodiments of this disclosure, therefore, compared to the above... Figure 1 and Figure 2 The circuit layout structure shown, in this integrated circuit package structure, using the electrical signal transmission structure provided in any embodiment of this disclosure, eliminates the need for a large distance between the two differential signal transmission channels (as described above). Figure 1 ), or separate electric field shielding for each of the two transmission channels (as described above) Figure 2 (A shielding ring is added separately). This not only improves the common-mode rejection effect when using wire bonding for differential signal transmission within the chip package structure, but also saves tens to hundreds of square micrometers of circuit area on the chip.

[0064] For example, the first circuit module and the second circuit module are respectively located in different chips of the integrated circuit.

[0065] In at least some embodiments of this disclosure, there are no routing crossings between the transmission lines of each transmission link. That is, there are no routing crossings between transmission lines Bondwire1, Bondwire2, Bondwire3, and Bondwire4.

[0066] In some embodiments of this disclosure, a plurality of first voltage isolation units in the first circuit module are arranged opposite to a plurality of second voltage isolation units in the second circuit module, and the transmission lines of each transmission link are routed along a straight line.

[0067] For example, the multiple voltage isolation units C1, C2, C3, and C4 of circuit module 10 are arranged relative to the multiple voltage isolation units C10, C20, C30, and C40 of circuit module 20. That is, voltage isolation unit C1 is arranged relative to voltage isolation unit C10, voltage isolation unit C2 is arranged relative to voltage isolation unit C20, voltage isolation unit C3 is arranged relative to voltage isolation unit C30, and voltage isolation unit C4 is arranged relative to voltage isolation unit C40.

[0068] By arranging the isolation units between the two circuit modules, the transmission lines of each transmission link can be routed in straight lines, which further reduces the length of the transmission lines. Especially for chip design, reducing the length of the wires is more beneficial for reducing interference from external noise and saving chip trace area.

[0069] It should be noted that the fact that each transmission link runs along a straight line does not mean that the transmission line itself must remain strictly straight. For example, because the actual circuit is a three-dimensional structure, the transmission line itself will appear as a curve with a certain curvature in three-dimensional space when connecting two isolation voltage units. For example, when the transmission line is a wire bond, the wire bond itself is limited by its characteristics and does not appear to be a strictly straight wire bond when running along a straight line. That is, the projection of a transmission line running along a straight line onto the circuit plane is approximately a straight line.

[0070] See also Figure 3 For example, multiple voltage isolation units C1, C2, C3 and C4 can be arranged with the same arrangement interval d1. For example, multiple voltage isolation units C10, C20, C30 and C40 can be arranged with arrangement interval d2 between voltage isolation units C10 and C20, and between voltage isolation units C40 and C30, and between voltage isolation units C20 and C30 with arrangement interval d3.

[0071] like Figure 3 As shown, for example, the arrangement interval d3 between voltage isolation units C20 and C30 can be smaller than the arrangement interval d2.

[0072] For example, in some embodiments of this disclosure, a plurality of first voltage isolation units are arranged at the same first arrangement interval, and a plurality of second voltage isolation units are arranged at the same second arrangement interval.

[0073] Figure 4 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0074] like Figure 4 As shown, for example, when multiple voltage isolation units C1, C2, C3 and C4 can be arranged with the same arrangement interval d1 (such as the first arrangement interval), multiple voltage isolation units C10, C20, C30 and C40 can be arranged with the same arrangement interval d2 (such as the second arrangement interval), wherein the arrangement interval d1 and the arrangement interval d2 are not equal.

[0075] For example, in some embodiments of this disclosure, the first arrangement interval is equal to the second arrangement interval, and the arrangement interval between the transmission lines of each transmission link in the first transmission channel and at least one second transmission channel is equal.

[0076] It should be noted that the equal spacing between transmission lines in each transmission link is not absolutely equal, but rather basically equal. Therefore, in actual circuits, within the allowable error range, the spacing between transmission lines can be considered equal.

[0077] Figure 5 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0078] like Figure 5 In the illustrated embodiment, for example, the transmission lines Bondwire1, Bondwire2, Bondwire3 and Bondwire4 are arranged with the same spacing.

[0079] Since each of the transmission links is configured to connect the first voltage isolation unit and the second voltage isolation unit in a one-to-one correspondence, the distance between each transmission link is also determined by the first arrangement interval of the first voltage isolation unit and the second arrangement interval of the second voltage isolation unit.

[0080] Figure 6 A schematic diagram showing the effect comparison of noise gain when the signal gain is the same, provided by at least one embodiment of the present disclosure, is shown.

[0081] Figure 6 The curve shown describes the frequency response characteristics of noise gain as a function of frequency. Figure 6 This disclosure Figure 5 Taking the electrical signal transmission structure shown as an example, and... Figure 1 The circuit layout shown is compared to the noise gain effect. The horizontal axis, frequency (freq) (Hz), uses a logarithmic scale to represent different frequency ranges; the vertical axis, MAG (μ), uses a dimensionless linear scale to represent the magnitude amplification of the output noise voltage compared to the input noise voltage, i.e., the noise gain. Under the same horizontal axis, a larger vertical axis value indicates that the same amount of input noise is amplified more on the output side.

[0082] like Figure 6 As shown, the noise source at a frequency of 250MHz (horizontal axis is 10). 8.4 Hz, log 10 (250×10 6 ) ≈8.4), in this disclosure Figure 5 The electrical signal transmission structure shown is similar to Figure 1 Compared to the circuit layout structure shown, Figure 1 The noise gain of the circuit layout is 66.7μ. Figure 5 The noise gain of the electrical signal transmission structure is 30.4 μ. Furthermore, compared to this disclosure... Figure 5 The electrical signal transmission structure shown is similar to Figure 1 The signal gain before differential amplifier amplification is shown in the circuit layout. Figure 5 Signal gain of electrical signal transmission structure and Figure 1The circuit layout is basically the same, both using 4.1m (magnitude), where m is a dimensionless unit representing the ratio of the output signal voltage to the input signal voltage amplitude. 4.1m means that the output voltage amplitude is 4.1 times the input voltage amplitude, that is, the signal is amplified by 4.1 times.

[0083] Therefore, this disclosure Figure 5 The electrical signal transmission structure in the illustrated embodiment not only does not lose signal gain, but also... Figure 1 The noise gain was reduced by 66.7 / 30.4 ≈ 2.2 times; from the perspective of signal-to-noise ratio (SNR), the SNR was improved by as much as 10 logarithmic times. 10 (2.2 2 ≈6.8dB.

[0084] In at least some embodiments of this disclosure, the first circuit module includes a first transmitting circuit and a second receiving circuit, the second circuit module includes a first receiving circuit corresponding to the first transmitting circuit and a second transmitting circuit corresponding to the second receiving circuit, and the transmission direction of the first transmission channel is opposite to that of at least one second transmission channel.

[0085] For example, see Figure 5 The circuit module 10 includes a transmitting circuit (such as a first transmitting circuit) that transmits a pair of differential signals to the receiving circuit (such as a first receiving circuit) of the circuit module 20 through a second transmission channel formed by transmission lines Bondwire2 and Bondwire3.

[0086] For example, circuit module 10 includes a receiving circuit (such as a second receiving circuit); the transmitting circuit (such as the second receiving circuit) of circuit module 20 transmits another pair of differential signals to the receiving circuit (such as the second receiving circuit) of circuit module 10 through a first transmission channel formed by transmission lines Bondwire1 and Bondwire4.

[0087] Alternatively, the first circuit module includes a transmitting circuit, the second circuit module includes a receiving circuit, and the first transmission channel and each of the second transmission channels have the same transmission direction.

[0088] Figure 7 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0089] like Figure 7As shown, the transmission direction of both the first transmission channel and the second transmission channel can be to transmit signals from circuit module 10 to circuit module 20. For example, circuit module 10 includes a transmitting circuit, and circuit module 20 includes a receiving circuit. Circuit module 10 transmits two pairs of differential signals to circuit module 20 through the first transmission channel and the second transmission channel, respectively.

[0090] It should be noted that, in one or more embodiments, the specific transmission directions of the first transmission channel and the second transmission channel are not limited in this disclosure.

[0091] Figure 8 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown. Figure 9 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0092] In some embodiments of this disclosure, at least one second transmission channel includes a first sub-transmission channel and a second sub-transmission channel, wherein the first sub-transmission channel includes two transmission links configured to transmit a pair of differential signals and having the same transmission line length.

[0093] The transmission links corresponding to the second sub-transmission channel are arranged in the first sub-region formed between the two transmission links of the first sub-transmission channel; or, the transmission links corresponding to the second sub-transmission channel are arranged outside the first sub-region.

[0094] That is, multiple second transmission channels are arranged in the first area, and the multiple second transmission channels include a first sub-transmission channel and a second sub-transmission channel.

[0095] like Figure 8 and Figure 9 As shown, circuit module 10 includes multiple first voltage isolation units C1, C2, C3, C4, C5 and C6; circuit module 20 includes multiple second voltage isolation units C10, C20, C30, C40, C50 and C60.

[0096] For example, the first transmission channel group can Figure 3 Based on this, it further includes a fifth transmission link consisting of a first voltage isolation unit C5 and a second voltage isolation unit C50 connected by a transmission line Bondwire 5; and a sixth transmission link consisting of a first voltage isolation unit C6 and a second voltage isolation unit C60 connected by a transmission line Bondwire 6.

[0097] For example, there is a parasitic capacitance C5g in the fifth transmission link and a parasitic capacitance C6g in the sixth transmission link; for example, the parasitic capacitance C5g in the fifth transmission link is the parasitic capacitance between transmission line Bondwire5 and the noise source; the parasitic capacitance C6g in the sixth transmission link is the parasitic capacitance between transmission line Bondwire6 and the noise source.

[0098] For example, the first transmission channel may consist of a transmission line Bondwire1 connecting voltage isolation unit C1 and voltage isolation unit C10, and a transmission line Bondwire6 connecting voltage isolation unit C6 and voltage isolation unit C60. The detailed description of the first transmission channel is the same as above and will not be repeated here.

[0099] For example, multiple second transmission channels can be arranged in the first region between transmission lines Bondwire1 and Bondwire6.

[0100] Similar to the principle described above, since the two transmission lines Bondwire1 and Bondwire6 in the first transmission channel constitute two symmetrically arranged transmission links on the outside of multiple transmission channels, the parasitic capacitances C1g and C6g corresponding to the two transmission lines Bondwire1 and Bondwire6 respectively also have system symmetry in the multiple transmission channels arranged in parallel due to factors such as the similar distance from the noise source. Therefore, they can play a certain electric field shielding role for the multiple second transmission channels arranged in the first region, thereby improving the common-mode rejection effect of differential signals and enhancing the anti-interference capability of the overall transmission channel.

[0101] In some embodiments of this disclosure, the transmission links corresponding to the second sub-transmission channel are arranged in a first sub-region formed between the two transmission links of the first sub-transmission channel.

[0102] like Figure 8 As shown, the first sub-transmission channel can be composed of a transmission line Bondwire2 connecting voltage isolation unit C2 and voltage isolation unit C20, and a transmission line Bondwire5 connecting voltage isolation unit C5 and voltage isolation unit C50, used to transmit a pair of differential signals. For example, the first sub-transmission channel transmits a pair of differential signals from circuit module 10 to circuit module 20, and the signals are amplified and output by the differential amplifier Amp20 of circuit module 20.

[0103] The second sub-transmission channel can be composed of a transmission line Bondwire3 connecting voltage isolation unit C3 and voltage isolation unit C30, and a transmission line Bondwire4 connecting voltage isolation unit C4 and voltage isolation unit C40, used to transmit another pair of differential signals. For example, the second sub-transmission channel transmits a pair of differential signals from circuit module 10 to circuit module 20, and the signals are amplified and output by the differential amplifier Amp30 of circuit module 20.

[0104] like Figure 8 As shown, the second sub-transmission channel, consisting of transmission lines Bondwire3 and Bondwire4, is arranged in the first sub-region formed between transmission lines Bondwire2 and Bondwire5.

[0105] Understandably, transmission lines Bondwire2 and Bondwire5 can also provide some electric field shielding for each transmission link of the second sub-transmission channel to a certain extent.

[0106] Alternatively, in some embodiments of this disclosure, such as Figure 9 As shown, the first sub-transmission channel can be composed of Bondwire2, a transmission line connecting voltage isolation unit C2 and voltage isolation unit C20, and Bondwire3, a transmission line connecting voltage isolation unit C3 and voltage isolation unit C30, for transmitting a pair of differential signals. The second sub-transmission channel can be composed of Bondwire4, a transmission line connecting voltage isolation unit C4 and voltage isolation unit C40, and Bondwire5, a transmission line connecting voltage isolation unit C5 and voltage isolation unit C50, for transmitting another pair of differential signals. That is, the transmission links corresponding to the second sub-transmission channel (such as the fourth and fifth transmission links) are arranged outside the first sub-region.

[0107] For example, such as Figure 9 As shown, the second sub-transmission channel includes two transmission links configured to transmit a pair of differential signals and having the same transmission line length; the second sub-transmission channel is located outside the first sub-region and is symmetrically arranged with the first sub-transmission channel within the first region.

[0108] It should be noted that the above Figure 8 and Figure 9 For illustrative purposes only, when there are multiple second transmission channels, such as three or four second transmission channels, the above can be applied. Figure 8 and Figure 9 Choose any of the examples to arrange them, or you can... Figure 8 and Figure 9 The arrangement shown is combined to arrange multiple second transmission channels, and this disclosure does not limit this arrangement.

[0109] Figure 10 A block diagram of an electrical signal transmission structure provided in at least one embodiment of the present disclosure is shown.

[0110] When the number of first voltage isolation units in the first circuit module is greater than the number of second voltage isolation units in the second circuit module, or the number of second voltage isolation units in the second circuit module is greater than the number of first voltage isolation units in the first circuit module, that is, after connecting the first voltage isolation units and the second voltage isolation units one by one to form a transmission link, there are still some voltage isolation units that cannot be matched and connected.

[0111] To address this, at least one third circuit module and at least one second transmission channel group can be set up. The third circuit module includes multiple third voltage isolation units, which are used to connect the remaining unmatched voltage isolation units one by one to form a new transmission link (i.e., the extended link below).

[0112] like Figure 10 As shown, for example, when circuit module 10 (first circuit module) includes multiple first voltage isolation units C1, C2, C3, C4, C5, C6, C7 and C8, but circuit module 20 (second circuit module) only includes multiple second voltage isolation units C10, C20, C30 and C40, circuit module 30 (third circuit module) can be set in the electrical signal transmission structure. Circuit module 30 includes multiple third voltage isolation units C15, C16, C17 and C18.

[0113] For example, multiple first voltage isolation units C1, C2, C3, C4, C5, C6, C7 and C8 can be configured such that voltage isolation units C1, C2, C3 and C4 are placed in one shielding ring, and voltage isolation units C5, C6, C7 and C8 are placed in another shielding ring.

[0114] For example, the second transmission channel group includes multiple extension links, each configured to connect one-to-one with the first voltage isolation unit and the third voltage isolation unit. That is, the second transmission channel group is a transmission channel group consisting of multiple extension links between circuit module 10 and circuit module 20. For example, each extension link in the second transmission channel group is configured to connect one-to-one with the first voltage isolation unit and the third voltage isolation unit.

[0115] For example, the multiple extension links in the second transmission channel group include: a first extension link consisting of a transmission line Bondwire 50 connecting the first voltage isolation unit C5 and the second voltage isolation unit C15; a second extension link consisting of a transmission line Bondwire 60 connecting the first voltage isolation unit C6 and the second voltage isolation unit C16; a third extension link consisting of a transmission line Bondwire 70 connecting the first voltage isolation unit C7 and the second voltage isolation unit C17; and a fourth extension link consisting of a transmission line Bondwire 80 connecting the first voltage isolation unit C8 and the second voltage isolation unit C18.

[0116] For example, multiple extended links in the second transmission channel group also have parasitic capacitances, such as parasitic capacitance C50g in the first extended link, parasitic capacitance C60g in the second extended link, parasitic capacitance C70g in the third extended link, and parasitic capacitance C80g in the fourth extended link.

[0117] For example, in the first extended link, there is a parasitic capacitance C50g between the transmission line Bondwire 50 and the noise source; in the second extended link, there is a parasitic capacitance C60g between the transmission line Bondwire 60 and the noise source; in the third extended link, there is a parasitic capacitance C70g between the transmission line Bondwire 70 and the noise source; and in the fourth extended link, there is a parasitic capacitance C80g between the transmission line Bondwire 80 and the noise source.

[0118] For example, the second transmission channel group includes a first extended channel and at least one second extended channel. The first extended channel includes two extended links configured to transmit a pair of differential signals and having the same transmission line length. The extended links corresponding to the at least one second extended channel are arranged in a second region formed between the two extended links.

[0119] For example, the first extended channel can be configured to consist of a first extended link and a fourth extended link, transmitting a pair of differential signals from the transmitting circuit of circuit module 30 to the receiving circuit of circuit module 10, and then amplified by the differential amplifier Amp50 of circuit module 10 before output. The second extended channel can be configured to consist of a second extended link and a third extended link, transmitting a pair of differential signals from the transmitting circuit of circuit module 10 to the receiving circuit of circuit module 30, and then amplified by the differential amplifier Amp40 of circuit module 30 before output.

[0120] For example, the second region is the area between transmission lines Bondwire50 and Bondwire80, and transmission lines Bondwire60 and Bondwire70 are arranged within the second region.

[0121] For example, Bondwire50 and Bondwire80 transmission lines are the same length.

[0122] The arrangement principle of each extended channel and each extended link in the second transmission channel group is the same as that of each transmission channel and each transmission link in the first transmission channel group described above, and will not be repeated here. Furthermore, the arrangement method of the second transmission channel group is also the same as that of the first transmission channel group described above. Therefore, the technical effects achieved by the arrangement method of the second transmission channel group are also the same as those achieved by the various arrangement methods of the first transmission channel group, as described above. This disclosure will not repeat them here.

[0123] In some embodiments of this disclosure, the first circuit module, the second circuit module, and the third circuit module are respectively disposed in different chips of the integrated circuit.

[0124] In some embodiments of this disclosure, a plurality of first voltage isolation units are disposed in the same first voltage shielding ring, a plurality of second voltage isolation units are disposed in the same second voltage shielding ring, and / or, a plurality of third voltage isolation units are disposed in the same third voltage shielding ring.

[0125] See also Figure 10 For example, multiple first voltage isolation units C1, C2, C3, C4, C5, C6, C7, and C8 can be arranged within the same shielding ring 10. However, to ensure that signal transmission between the first transmission channel group and the second transmission channel group is not interfered with, the distance between voltage isolation units C4 and C5 can be increased. For example, multiple second voltage isolation units C10, C20, C30, and C40 can be arranged within the shielding ring 20, and multiple third voltage isolation units C15, C16, C17, and C18 can be arranged within the shielding ring 30.

[0126] At least one embodiment of this disclosure also provides a chip, wherein the chip includes at least one chip having an electrical signal transmission structure as described in the at least one embodiment above. For example, the chip includes two or more chips, each having the electrical signal transmission structure described above, so that the chips can communicate with each other through the electrical signal transmission structure; for example, these chips are packaged in the chip using, for example, 2.5D or 3D encapsulation.

[0127] A die is a bare chip cut from a wafer; it is the unpackaged integrated circuit body. For example, a die includes a silicon wafer and metal layers. A chip is a complete, packaged device; at least one die is packaged into a chip through a chip packaging process.

[0128] For example, the chip in at least one embodiment of this disclosure includes a memory and a processor, for example, at least one of the memory and the processor is the aforementioned chip, including the electrical signal transmission structure of any of the above embodiments.

[0129] For example, the memory may include semiconductor memory cells, such as any memory with storage function, such as Dynamic Random Access Memory (DRAM), Random Access Memory (RAM), or Static Random Access Memory (SRAM).

[0130] For example, a processor can be any processing circuit that has processing capabilities implemented through hardware or firmware. For example, it can be a central processing unit (CPU) or coprocessor, a microcontroller unit (MCU) or a digital signal processor (DSP). For example, a coprocessor can be an accelerator (e.g., a graphics accelerator or digital signal processing unit), a graphics processing unit (GPU), a programmable logic array, or any other processor with instruction execution capabilities.

[0131] Figure 11 A block diagram of a chip provided in at least one embodiment of the present disclosure is shown.

[0132] like Figure 11 As shown, the chip 100 has multiple die1 to dieN, where N≥1 and N is a positive integer.

[0133] For example, the first circuit module and the second circuit module are respectively disposed in different chips of the integrated circuit. For example, the above Figure 3 The circuit module 10 can be installed on die 1, and the circuit module 20 can be installed on die 2.

[0134] For example, the first circuit module, the second circuit module, and the third circuit module are respectively disposed in different chips of the integrated circuit. For example, the above Figure 10 Circuit module 10 can be installed on die 1, circuit module 20 can be installed on die 2, and circuit module 30 can be installed on die 3.

[0135] For example, the above Figure 10The circuit modules 20 and 30 can be different circuit modules disposed on the die 2.

[0136] It should be noted that this disclosure does not limit the arrangement of the electrical signal transmission structure provided in any embodiment of the present disclosure on each chip.

[0137] The technical effects of the chip in the above embodiments of this disclosure are the same as those of the above electrical signal transmission structure, and therefore will not be repeated.

[0138] At least one embodiment of this disclosure also provides an electronic device, wherein the electronic device includes the electrical signal transmission structure described in the above-described at least one embodiment.

[0139] Figure 12 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0140] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers.

[0141] Figure 12 The illustrated electronic device 1000 is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0142] For example, refer to Figure 12 In some examples, electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003. For example, processing device 1001 may include the electrical signal transmission structure described in at least one of the above embodiments. Various programs and data required for the operation of the computer system are also stored in RAM 1003. Processing device 1001, ROM 1002, and RAM 1003 are connected via interconnection network 1004. Input / output (I / O) interface 1005 is also connected to interconnection network 1004.

[0143] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed. Although Figure 12 An electronic device 1000 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0144] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0145] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0146] The technical effects of the electronic devices in the above embodiments of this disclosure are the same as those of the above-described electrical signal transmission structures, and therefore will not be repeated here.

[0147] The following points need to be clarified regarding this disclosure:

[0148] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0149] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0150] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An electrical signal transmission structure, comprising: The first circuit module includes multiple first voltage isolation units. The second circuit module includes multiple second voltage isolation units. The first transmission channel group includes multiple transmission links, each of which is configured to connect the first voltage isolation unit and the second voltage isolation unit in a one-to-one correspondence; The first transmission channel group includes a first transmission channel and at least one second transmission channel. The first transmission channel includes two transmission links configured to transmit a pair of differential signals and having the same transmission line length. The transmission links corresponding to each of the at least one second transmission channel are arranged in a first region formed between the two transmission links of the first transmission channel.

2. The electrical signal transmission structure according to claim 1, wherein, The plurality of first voltage isolation units are arranged at the same first arrangement interval. The plurality of second voltage isolation units are arranged at the same second arrangement interval.

3. The electrical signal transmission structure according to claim 2, wherein, The first arrangement interval is equal to the second arrangement interval. The spacing between the transmission lines of each transmission link in the first transmission channel and the at least one second transmission channel is equal.

4. The electrical signal transmission structure according to claim 1, wherein, The first circuit module includes a transmitting circuit, and the second circuit module includes a receiving circuit; the transmission direction of the first transmission channel and each of the second transmission channels is the same; or, The first circuit module includes a first transmitting circuit and a second receiving circuit, and the second circuit module includes a first receiving circuit corresponding to the first transmitting circuit and a second transmitting circuit corresponding to the second receiving circuit. The transmission direction of the first transmission channel is opposite to that of at least one of the second transmission channels.

5. The electrical signal transmission structure according to claim 1, wherein, The at least one second transmission channel includes a first sub-transmission channel and a second sub-transmission channel, wherein the first sub-transmission channel includes two transmission links configured to transmit a pair of differential signals and having the same transmission line length; Wherein, each of the transmission links corresponding to the second sub-transmission channel is arranged in a first sub-region formed between the two transmission links of the first sub-transmission channel; or, each of the transmission links corresponding to the second sub-transmission channel is arranged outside the first sub-region.

6. The electrical signal transmission structure according to claim 5, wherein, The second sub-transmission channel includes two transmission links configured to transmit a pair of differential signals and having the same transmission line length; The second sub-transmission channel is arranged outside the first sub-region and is symmetrically arranged with the first sub-transmission channel within the first region.

7. The electrical signal transmission structure according to claim 1 further includes at least one third circuit module and at least one second transmission channel group. The third circuit module includes multiple third voltage isolation units; in, The second transmission channel group includes multiple extended links, each of which is configured to connect one-to-one with the first voltage isolation unit and the third voltage isolation unit; The second transmission channel group includes a first extended channel and at least one second extended channel. The first extended channel includes two extended links configured to transmit a pair of differential signals and having the same transmission line length. The extended links corresponding to the at least one second extended channel are arranged in a second region formed between the two extended links.

8. The electrical signal transmission structure according to claim 7, wherein, The first circuit module, the second circuit module, and the third circuit module are respectively disposed in different chips of the integrated circuit.

9. The electrical signal transmission structure according to claim 7, wherein, The plurality of first voltage isolation units are disposed in the same first voltage shielding ring, the plurality of second voltage isolation units are disposed in the same second voltage shielding ring, and / or, the plurality of third voltage isolation units are disposed in the same third voltage shielding ring.

10. The electrical signal transmission structure according to any one of claims 1-9, wherein, The electrical signal transmission structure is an integrated circuit package structure, and the transmission line is a wire bond.

11. The electrical signal transmission structure according to any one of claims 1-9, wherein, There are no wiring intersections between the transmission lines of the various transmission links.

12. The electrical signal transmission structure according to any one of claims 1-9, wherein, The plurality of first voltage isolation units in the first circuit module are arranged opposite to the plurality of second voltage isolation units in the second circuit module, and the transmission lines of each transmission link are routed along a straight line.

13. A chip, comprising: At least one core, wherein the at least one core is provided with an electrical signal transmission structure as described in any one of claims 1-11.

14. An electronic device comprising the chip as claimed in claim 12.

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