Two-row driving method for micro display device

Abstract

A method of driving a pixel array includes providing a ramp signal to one or more columns of the pixel array. For each cycle of the ramp signal, the method further includes providing a first row drive signal to at least a first row of the pixel array and a second row drive signal to a second row of the pixel array. The pixel array driver may include a ramp signal generator configured to generate a ramp signal, a first amplifier configured to receive the ramp signal and generate a first amplified ramp signal, and a second amplifier configured to receive the ramp signal and generate a second amplified ramp signal. The first amplified ramp signal may be electrically connected to a first set of pixels of the pixel array, and the second amplified ramp signal may be electrically connected to a second set of pixels of the pixel array.

Description

[0001] This application is a divisional application of application number 201680061063.5, filed on October 17, 2016, having the title "Two Row Drive Method for Microdisplay Devices". Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 243,411, filed October 19, 2015, and U.S. Provisional Patent Application No. 62 / 247,327, filed October 28, 2015. The entire teachings of the above applications are incorporated herein by reference. BACKGROUND

[0003] Mobile computing devices, such as notebook personal computers, smart phones, and tablet computing devices, are now common tools for generating, analyzing, communicating, and consuming data in both business and personal life. As high-speed wireless communication technology becomes ubiquitous, consumers continue to embrace a mobile digital lifestyle. The widespread use of mobile computing devices includes the display of large amounts of high-resolution computer graphics information and video content that often flows to the device in a wireless manner.

[0004] While these devices typically include a display screen, the preferred visual experience of a high-resolution large-format display cannot be easily replicated in such mobile devices because the physical size of such devices is limited by the mobility enhancement. Another drawback of the aforementioned type of device is that the user interface is hand-dependent, often requiring the user to input data or make selections using a keyboard (physical or virtual) or touch screen display.

[0005] Accordingly, consumers are now seeking a hands-free, high-quality, portable, color display solution to augment or replace their hand-dependent mobile devices. Such a display solution has practical size and weight limitations, which therefore limit the available power source (e.g., battery size). Given the limited power source, reducing the power consumption of the display increases the amount of time the display can operate on a single charge of the associated power source.

[0006] With some types of display devices, operation requires that a periodic ramp signal be provided to the columns of pixels of the array. While the power requirements of a ramp signal generator can depend on many factors, two primary contributing factors are generally (i) the number of pixels in the display, and (ii) the frequency of the ramp signal. Thus, with a fixed size display, the power requirements of the ramp signal generator, and thus the associated display device, are largely dependent on the ramp frequency.

[0007] Display applications of the prior art are driving a need for higher ramp signal frequencies, which, as noted above, drives higher power requirements. SUMMARY

[0008] Recently developed micro-displays can provide large-format, high-resolution color images and streaming video in very small form factors. One application of such displays can be incorporated into a wireless headset computer that is worn on the head of a user with the display located in the field of view of the user, which is similar in form to eyeglasses, audio headphones, or video eyewear.

[0009] A "wireless computing headset" device (also referred to herein as a headset computer (HSC) or a head-mounted display (HMD)) includes one or more small, high-resolution micro-displays and associated optical components for magnifying the images. These high-resolution micro-displays can provide super video graphics array (SVGA) (800 x 600) resolution or extended graphics array (XGA) (1024 x 768) resolution, or higher resolutions as are known in the art.

[0010] The wireless computing headset device contains one or more wireless computing and communication interfaces, enabling data and streaming video capabilities, and providing greater convenience and mobility through reliance on hand devices.

[0011] For more information on such devices, see the following co-pending patent applications: U.S. Patent Application No. 12 / 348,646, filed January 5, 2009, entitled "Mobile Wireless Display Software Platform for Controlling Other Systems and Devices"; PCT International Patent Application No. PCT / US09 / 38601, filed March 27, 2009, entitled "Handheld Wireless Display Devices Having High Resolution Display Suitable For Use as a Mobile Internet Device"; and U.S. Patent Application No. 61 / 638,419, filed April 25, 2012, entitled "Improved Headset Computer", the entire contents of each of which are incorporated herein by reference.

[0012] As used herein, "HSC" headset computer, "HMD" head-mounted display device, and "wireless computing headset" device are used interchangeably.

[0013] The embodiments described herein reduce power of a microdisplay (e.g., a microdisplay associated with an HSC) by one or more of: (i) reducing a frequency of a ramp signal used to drive a column of a microdisplay pixel array, and (ii) increasing a number of rows of the array that are driven for each cycle of the column drive ramp signal.

[0014] In one aspect, the present invention can be a method of driving a pixel array, the method comprising providing a ramp signal to one or more columns of the pixel array. For each cycle of the ramp signal, a first row drive signal is provided to a first row of the pixel array and a second row drive signal is provided to a second row of the pixel array.

[0015] One embodiment further includes providing a first amplifier and a second amplifier. Each of the first amplifier and the second amplifier receives an input ramp signal from a digital-to-analog converter and produces a first amplified ramp signal and a second amplified ramp signal, respectively. The first amplifier and the second amplifier can be unity gain amplifiers (i.e., a gain equal to one (1)), although the gain of the amplifiers can be fractional (i.e., between zero (0) and one (1)) or greater than one (1).

[0016] Another embodiment further includes coupling an output of the first amplifier to a first group of pixels of the pixel array and coupling an output of the second amplifier to a second group of pixels of the pixel array. The first group of pixels of the pixel array can be a first group of pixel columns, and the second group of pixels of the pixel array can be a second group of pixel columns. The first group of pixel columns and the second group of pixel columns can be spatially arranged on the pixel array (or on a substrate or other base that houses the pixel array) such that columns of the first group of pixel columns alternate with columns of the second group of pixel columns.

[0017] One embodiment further includes providing the first amplified ramp signal to the first group of pixels of the pixel array, and providing the second amplified ramp signal to the second group of pixels of the pixel array.

[0018] One embodiment further includes coupling an output of the first amplifier to a first group of pixels of the pixel array, and coupling an output of the second amplifier to a second group of pixels of the pixel array. The first group of pixels of the pixel array can be a first group of pixel rows (from a total of N rows of pixels in the pixel array), and the second group of pixels of the pixel array is a second group of pixel rows (from the total of N rows in the pixel array). The first group of pixel rows includes 1 to M rows of pixels, and the second group of pixels includes M+1 to N rows of pixels, where M and N are integers.

[0019] One embodiment further includes providing the first amplified ramp signal to the first group of pixel rows, and providing the second amplified ramp signal to the second group of pixel rows.

[0020] Another embodiment also includes coupling the output of the first amplifier to a first set of pixels of the pixel array, and coupling the output of the second amplifier to a second set of pixels of the pixel array. The first set of pixels of the pixel array is a first set of pixel rows, and the second set of pixels of the pixel array is a second set of pixel rows, the first set of pixel rows and the second set of pixel rows being spatially arranged on the pixel array such that rows of the first set of pixel rows alternate with rows of the second set of pixel rows.

[0021] One embodiment includes providing a digital-to-analog converter configured to generate a ramp signal.

[0022] In another aspect, the present invention can be a pixel array driver including a ramp signal generator configured to generate a ramp signal, a first amplifier configured to receive the ramp signal and generate a first amplified ramp signal, and a second amplifier configured to receive the ramp signal and generate a second amplified ramp signal. The first amplified ramp signal can be electrically connected to a first set of pixels of a pixel array, and the second amplified ramp signal can be electrically connected to a second set of pixels of the pixel array.

[0023] In one embodiment, the first set of pixels of the pixel array is a first set of pixel columns, and the second set of pixels of the pixel array is a second set of pixel columns. The first set of pixel columns and the second set of pixel columns can be spatially arranged (i.e., referring to the physical layout of the pixels) on the pixel array such that columns of the first set of pixel columns alternate with columns of the second set of pixel columns.

[0024] In another embodiment, the first set of pixel columns includes an Nth pixel column, and the second set of pixel columns includes an (N+l)th pixel column, where N refers to a consecutive even number starting with N=2. It should be understood that for all embodiments described herein, the total number of pixels (and thus the number of pixel columns) is finite, limited by the size and shape of the associated display device.

[0025] In another embodiment, the first set of pixel columns receives the first amplified ramp signal, and the second set of pixel columns receives the second amplified ramp signal.

[0026] In one embodiment, the first set of pixels and the second set of pixels of the pixel array are arranged in N rows. The first set of pixels includes rows 1 through M of pixels, and the second set of pixels includes rows M+1 through N of pixels, where M and N are integers.

[0027] The pixel array driver of claim 14, wherein rows 1 through M of pixels receive the first amplified ramp signal, and rows M+1 through N of pixels receive the second amplified ramp signal.

[0028] In another embodiment, the first set of pixels of the pixel array are a first set of pixel rows and the second set of pixels of the pixel array are a second set of pixel rows. The first set of pixel rows and the second set of pixel rows can be spatially arranged on the pixel array such that rows of the first set of pixel rows alternate with rows of the second set of pixel rows. For example, the first set of pixel rows can include the first, third, fifth, etc. rows, while the second set of pixel rows can include the second, fourth, sixth, etc. rows. The pixels of the first set of pixel rows can receive the first amplification ramp signal and the pixels of the second set of pixel rows can receive the second amplification ramp signal.

[0029] In another embodiment, the ramp signal generator includes a digital to analog converter. The ramp signal generator can also include a counter configured to generate a digital word and provide the digital word to the digital to analog converter, where the digital word counts from a starting value to an ending value, reverses to the starting value, and repeats the count from the starting value.

[0030] In another embodiment, the first and second amplifiers are unity gain amplifiers. In other embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0031] The foregoing will be apparent from the following more particular description of example embodiments of the application, as illustrated in the accompanying drawings in which like reference numbers denote like parts, in all different figures. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the application.

[0032] Figure 1 A simple example of a microdisplay is illustrated in accordance with an embodiment.

[0033] Figure 2 An example of a ramp DAC arrangement is illustrated.

[0034] Figure 3 An example timing diagram is shown for signals that can be used to drive Figure 2 the pixel array shown in FIG. 1.

[0035] Figure 4 Another example of a ramp DAC arrangement constructed in accordance with described embodiments is shown.

[0036] Figure 5 An example timing diagram is shown for signals that can be used to drive Figure 4 the pixel array shown in FIG. 1.

[0037] Figure 6 Yet another example of a ramp DAC arrangement constructed in accordance with described embodiments is shown.

[0038] Figure 7 An example timing diagram is shown for signals that can be used to drive Figure 6An exemplary timing diagram of the signals of the pixel array shown. Detailed Implementation

[0039] The following is a description of various exemplary embodiments of the present invention.

[0040] The microdisplay described herein generally comprises a pixel array 102 driven by multiple data and control signals 103, such as in Figure 1 As shown in the simplified example. To make the following description easier to understand, the exemplary microdisplay 100 includes 20 columns and 16 rows for a total of 320 pixels, although as mentioned above, actual microdisplays typically have more pixels (e.g., an XGA with 1024 columns and 768 rows).

[0041] The microdisplay includes a column driver 104 and a row driver 106 that jointly provide information to the pixel array 102. The column driver 104 provides image information to the pixels, and the row driver 106 provides control information to the pixels. The column driver signal 108 for a particular pixel column 110 may include multiple signals.

[0042] In some embodiments, such as LCoS (liquid crystal coated with silicon) or OLED (organic light-emitting diode) display devices, Figure 1 The column driver 104 shown may include a ramp digital-to-analog converter (DAC) and an amplifier to generate a voltage ramp signal.

[0043] A voltage ramp signal can be a periodic signal that linearly increases from a first voltage to a second voltage and then repeats (see example...). Figure 3 The voltage ramp can be sampled and held at specific times to produce the desired fixed voltage output for use by the relevant columns of pixels.

[0044] A DAC can be a device that receives a digital word (e.g., 8-bit, 16-bit, 32-bit, etc.) representing a binary value. The DAC generates a voltage output corresponding to the value of the digital word. For example, a voltage ramp signal can be generated by sequentially counting the digital word from low to high values ​​(e.g., from 00000000 to 11111111) and periodically repeating this count. For example, in one embodiment, a counter programmed to count from an initial value to an final value and then reverse back to the initial value and repeat can be used to generate such a sequence of digital words.

[0045] The amplifier receives a voltage ramp signal from the DAC and produces an output signal that is an amplified version of the received voltage ramp signal. In other words, the amplifier output = g (Voltage ramp signal) where g is the gain of the amplifier. In some embodiments, the gain g of the amplifier is a positive real number greater than one, although in other embodiments the gain g can be between zero and one.

[0046] Figure 2 An example of a ramp DAC arrangement is illustrated, which comprises a single ramp DAC 202 driving first and second amplifiers 204 and 206. In this embodiment, the amplifiers 204, 206 are arranged to drive a pixel array 208 from two portions of the array 208. The arrangement of pixels within the array 208 (as shown in Figure 2 ) is intended to be representative of the physical arrangement of the pixels (i.e. the physical layout). In this example, the two depicted portions are the top and bottom of the pixel array, although other depiction arrangements can alternatively be employed.

[0047] Figure 3 An exemplary timing diagram is shown for the signals that can be used to drive Figure 2 a pixel array 208. In this example, a 120 Hz HSYNC ramp signal 302 is generated by the ramp DAC 202, which is relayed through the amplifiers 204 and 206 to the pixels in the pixel array 208. For each cycle of the ramp signal 302, only one row is driven. In this example, an Nth row drive signal 304 (i.e. row drive signal N) is active during the depicted first cycle of the ramp signal 302, an N+1th row drive signal 306 (i.e. row drive signal N+1) is active during the depicted second cycle of the ramp signal 302, an N+2th row drive signal 308 (i.e. row drive signal N+2) is active during the depicted third cycle of the ramp signal 302, and an N+3th row drive signal 310 (i.e. row drive signal N+3) is active during the depicted fourth cycle of the ramp signal 302. The cycle of the 120 Hz ramp signal is 1 / 120 seconds = 8.333 mS, so four rows of pixels are driven with a time of approximately 4 x 8.33 mS = 33.33 mS.

[0048] Figure 4 Another example of a ramp DAC arrangement is shown, which comprises a single ramp DAC 402 driving first and second amplifiers 404 and 406, constructed in accordance with the described embodiments. In this embodiment, the amplifiers 404 and 406 are arranged to drive a pixel array 408 from both sides of the array 408 (i.e. from the top and bottom of the array 408, in the example shown). Figure 2 However, in this example, the pixel array 408 is arranged in a different manner to the example shown in Figure 4In one example, each amplifier 404 and 406 drives a portion of each column (in this case, half of each column); in other words, amplifiers 404 and 406 share the driving of the pixel column. In other embodiments, the amplifiers may drive more than or less than half of the shared column.

[0049] exist Figure 4 In an exemplary embodiment, the Tth top row drive signal (i.e., ROW DRV SIG T) and the Bth bottom row drive signal (i.e., ROW DRV SIG B) are active during the first ramp cycle, similar to... Figure 3 The ramp signal 302 shown interacts with the row drive signal N304. The T+1th top row drive signal (i.e., ROW DRV SIG T+1) and the B+1th bottom row drive signal (i.e., ROW DRV SIG B+1) are active during the second ramp cycle, similar to... Figure 3 The ramp signal 302 shown interacts with the row drive signal N+1. The T+2th top row drive signal (i.e., ROWDRV SIG T+2) and the B+2th bottom row drive signal (i.e., ROWDRV SIG B+2) are active during the third ramp cycle, similar to... Figure 3 The ramp signal 302 shown interacts with the row drive signal N+2.

[0050] because Figure 4 The configuration shown allows two rows to be driven simultaneously (e.g., row T and row B, row T+1 and row B+1, etc.), so it can be used in conjunction with... Figure 2 The array configuration shown is used to drive the entire array with less power. Figure 5 The diagram illustrates what can be used to drive Figure 4 An exemplary timing diagram of the signals of pixel array 408. In this example, a 60 Hz HSYNC ramp signal 502 is generated by ramp DAC 402, which is relayed to the pixels in pixel array 408 via amplifiers 404 and 406. Figure 5 As shown in the timing diagram, ramp signal 502 can be Figure 2 and Figure 3 The frequency of the ramp signal 302 is half (i.e., 60 Hz) because two rows are driven for each cycle of the ramp signal 502. During the first cycle depicted by the ramp signal 502, the row drive signals 504 and 506 for row T and row B, respectively, are active. During the second cycle depicted by the ramp signal 502, the row drive signals 508 and 510 for row T+1 and row B+1, respectively, are active.

[0051] The period of the 60 Hz ramp signal is 1 / 60 second = 16.66 ms, but since two lines are driven for each period of ramp signal 502, it takes approximately 2 × 16.66 ms = 33.33 ms to drive four lines. Therefore, Figure 4 and Figure 5 The arrangement shown is in relation to Figure 2 and Figure 3 The same four rows are driven in the same amount of time as the arrangement shown. But because Figure 4 and Figure 5 The arrangement uses ramp signal 502 (this ramp signal is in Figure 2 and Figure 3 (the frequency of the ramp signal 302 used in the arrangement shown is half of the frequency), so Figure 4 and Figure 5 The arrangement requires less power.

[0052] Figure 6 Further example of a ramp DAC arrangement constructed according to the described embodiment is shown, which includes a single ramp DAC 602 driving a first amplifier 604 and a second amplifier 606. In this embodiment, amplifiers 604, 606 are arranged from both sides of array 408 (in terms of...) Figure 2 In this example, the pixel array 608 is driven from both the top and bottom of the array. However, in Figure 6 In this example, amplifier 604 drives odd-numbered rows (e.g., rows 1, 3, 5, etc.) while amplifier 606 drives even-numbered rows (e.g., rows 2, 4, 6, etc.). Figure 7 The timing diagram shown is applicable to Figure 6 The arrangement shown is similar to... Figure 5 The timing diagram shown is shown below.

[0053] Figure 6 The arrangement shown offers several advantages. Pixels can be accepted in a standard scan order, requiring only a single row buffer in memory. Figure 4 The requirement for a half-frame buffer increases latency, which is very detrimental to VR (virtual reality) applications. Figure 6 The arrangement reduces the constraints on matching amplifiers 604 and 606, because the mismatch between even and odd rows will be far less noticeable than the mismatch between the top half and bottom half of the image. Figure 6 The arrangement reduces motion artifacts because all rows are scanned at almost the same time as their surroundings. Conversely, in Figure 4 In the layout, row T+2 is scanned long after row B. Figure 6 The arrangement shares the row lines between adjacent rows, so each row only needs half the pitch.

[0054] It should be pointed out that,Figure 6 The arrangement requires two column line pitches per column, and the necessary longer column lines will have slightly higher capacitance, although the number of pixels per column line remains the same as compared to the structure shown in Figure 4 Figure 6

[0055] The exemplary embodiments herein validate the disclosed subject matter by doubling the number of driven rows while halving the ramp frequency. It should be appreciated that other variations of the ramp frequency and the number of pixel rows (i.e., other than doubling and halving) can be used to reduce power while maintaining the number of driven pixels per unit time in accordance with the basic concept of the described embodiments.

[0056] It will be apparent to those skilled in the art that the one or more embodiments described herein can be implemented in many different forms of software and hardware. The software code and / or specialized hardware used to implement the described embodiments is not limiting of the present application. Thus, the operation and behavior of the embodiments were described, and the component elements were described in so far as to facilitate an understanding of the embodiments. It will thus be appreciated that those skilled in the art will be able to design many different software and / or hardware configurations to implement the embodiments based on the description herein, which is not limiting of the scope of the embodiments.

[0057] Furthermore, some or all of the embodiments of the present application can be implemented as logic encoded in one or more tangible computer readable storage media (e.g., hard disk drives or solid state memory). The logic, when executed by the one or more controllers or processors, performs at least some of the functions of the described embodiments. The computer readable storage media includes physical computer storage media (e.g., hard disks, solid state memory, etc.) and tangible computer storage media (e.g., Universal Serial Bus (USB) flash drives, memory cards, etc.). The logic encoded in the one or more tangible computer readable storage media can include instructions for performing at least some of the features of the described embodiments.

[0058] While the application has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope of the application encompassed by the appended claims.​

Claims

1. A method for driving a pixel array, comprising: The ramp signal is provided to one or more columns of the pixel array; For each cycle of the ramp signal, a first row drive signal is provided to the first row of the pixel array, and a second row drive signal is provided to the second row of the pixel array.

2. The method according to claim 1, further comprising: A first amplifier and a second amplifier are provided, each of the first amplifier and the second amplifier receiving an input ramp signal from a digital-to-analog converter and generating a first amplified ramp signal and a second amplified ramp signal, respectively.

3. The method according to claim 2, wherein the first amplifier and the second amplifier are unity-gain amplifiers.

4. The method according to claim 2, further comprising: The output of the first amplifier is coupled to a first group of pixels in the pixel array, and the output of the second amplifier is coupled to a second group of pixels in the pixel array. The first group of pixels in the pixel array is a first group of pixel columns, and the second group of pixels in the pixel array is a second group of pixel columns. The first group of pixel columns and the second group of pixel columns are arranged in space on the pixel array such that the columns of the first group of pixel columns alternate with the columns of the second group of pixel columns.

5. The method according to claim 4, further comprising: The first amplified ramp signal is provided to the first group of pixels in the pixel array, and the second amplified ramp signal is provided to the second group of pixels in the pixel array.

6. The method according to claim 2, further comprising: The output of the first amplifier is coupled to a first group of pixels in the pixel array, and the output of the second amplifier is coupled to a second group of pixels in the pixel array. The first group of pixels in the pixel array consists of N rows of pixels, and the second group of pixels in the pixel array consists of N rows of pixels. The first group of pixels includes pixels from row 1 to row M, and the second group of pixels includes pixels from row M+1 to row N, where M and N are integers.

7. The method according to claim 6, further comprising: The first amplified ramp signal is provided to the first group of pixel rows, and the second amplified ramp signal is provided to the second group of pixel rows.

8. The method according to claim 2, further comprising: The output of the first amplifier is coupled to a first group of pixels in the pixel array, and the output of the second amplifier is coupled to a second group of pixels in the pixel array. The first group of pixels in the pixel array is a first row of pixels, and the second group of pixels in the pixel array is a second row of pixels. The first and second groups of pixels are arranged in space on the pixel array such that the rows of the first and second groups of pixels alternate.

9. The method according to claim 1, further comprising: A digital-to-analog converter configured to generate the ramp signal is provided.

10. A pixel array driver, comprising: A ramp signal generator, the ramp signal generator being configured to generate a ramp signal; A first amplifier is configured to receive the ramp signal and generate a first amplified ramp signal. A second amplifier is configured to receive the ramp signal and generate a second amplified ramp signal; The first amplified ramp signal is electrically connected to a first group of pixels in the pixel array, and the second amplified ramp signal is electrically connected to a second group of pixels in the pixel array.

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