Redundant code bit protection method based on CRC and timestamp, medium and equipment
By performing an XOR operation between the timestamp and the CRC checksum during data transmission to generate a redundant code, the problem of independent protection of data timeliness and integrity is solved, achieving efficient and reliable intrinsic security protection, defending against replay attacks and ensuring the determinism of system state.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-18
- Publication Date
- 2026-03-24
AI Technical Summary
In existing technologies, data timeliness protection and integrity protection are independent of each other, which makes it impossible to effectively defend against replay attacks. Furthermore, the coupling between error handling and security guidance mechanisms is low, and the security response is not direct and uncertain.
By performing an XOR operation between the timestamp and the CRC checksum during data transmission, a sending checksum is generated. At the receiving end, corresponding logical operations are performed to generate a redundant code. The expected redundant code is generated only when both the timestamp and the CRC checksum pass; otherwise, an unexpected redundant code is generated to guide the data to the security side.
It achieves a deep integration of timeliness protection and integrity protection, directly and automatically generating security outputs, effectively defending against replay attacks, and ensuring the determinism and reliability of system status.
Smart Images
Figure CN121727801A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data transmission security technology, and in particular to a method, medium, and device for redundancy protection based on CRC and timestamp. Background Technology
[0002] In industries with high safety requirements, such as rail transportation and aerospace, multi-system (e.g., primary and backup) hot standby architectures (e.g., N*2oo2 architecture) are widely used, requiring real-time synchronization of critical data between systems. This data has extremely high requirements for timeliness (i.e., whether the data is up-to-date and not outdated) and integrity (i.e., whether the data has been tampered with or erroneous during transmission). Existing technologies typically employ separate technical means to handle timeliness protection and integrity protection.
[0003] Commonly, systems synchronize time information through independent physical channels (such as serial ports) and transmit service data and CRC checksums through network channels. The receiver determines whether the data has timed out by comparing the timestamp synchronized through the independent channels and determines whether the data is complete by calculating the CRC value of the received data and comparing it with the CRC value in the received data packet. However, this approach has the following drawbacks: 1. Separation of timeliness and integrity protection results in an incomplete security loop: Timeliness verification (timestamp comparison) and integrity verification (CRC check) are parallel and independent processes. An attacker might intercept a valid but outdated data packet (whose CRC check passes) and replay it to the receiver later. Due to potential tolerance windows or clock synchronization errors in timestamp verification, this outdated data might be mistakenly identified as valid and accepted, causing the system to make incorrect decisions based on outdated information, thus failing to effectively defend against replay attacks.
[0004] 2. Low coupling between error handling and security guidance mechanisms: When CRC check fails or timestamp expires, existing solutions typically discard data packets or trigger independent alarms or security procedures. This mechanism's response is not direct or deterministic enough; the system state may become unknown after data is discarded. Furthermore, the independent security procedures themselves may have design flaws or common-mode failures, failing to force the system's final output or state towards a predefined "security side" in a deterministic, direct, and strongly data-related manner.
[0005] Therefore, there is an urgent need for an intrinsic security method that can deeply couple data timeliness verification, integrity verification, and security-oriented mechanisms to solve the above problems.
[0006] The statements herein provide only background information in relation to the present invention and do not necessarily constitute prior art. Summary of the Invention
[0007] The purpose of this invention is to provide a method, medium, and device for redundancy code protection based on CRC and timestamps, which can solve the technical problems in the prior art where data timeliness protection and integrity protection are independent, error handling and security guidance mechanisms are poorly coupled, resulting in an inability to effectively defend against replay attacks, and the security guidance is not direct and uncertain.
[0008] To achieve the above objectives, this invention provides a redundancy protection method based on CRC and timestamps, applicable to an architecture with a first system and a second system. The protection method includes: The data transmission step is performed by the first system, and the data transmission step includes: Obtain the raw data to be sent; calculate the first cyclic redundancy check code of the raw data; obtain the first timestamp of the first system; perform a first logical operation on the first cyclic redundancy check code and the first timestamp to generate a sending check code; send a data packet containing the raw data and the sending check code; The data receiving and redundancy code generation steps are performed by the second system, and these steps include: Receive the data packet and parse out the original data and the sending verification code from it; obtain the second timestamp of the second system; perform a second logical operation on the sending verification code and the second timestamp to obtain the receiving verification code; Based on the received original data, a second cyclic redundancy check code is obtained by recalculation; based on the received check code and the second cyclic redundancy check code, a redundancy code is generated. Specifically, an expected redundancy code is generated if and only if the first timestamp is consistent with the second timestamp and the received verification code is equal to the second cyclic redundancy check code; otherwise, an unexpected redundancy code is generated to guide the security side.
[0009] Optionally, the second timestamp is synchronized with the first timestamp through a time channel independent of the data packet transmission path.
[0010] Optionally, the time channel is a serial communication channel, and the data packets are transmitted through a network communication channel.
[0011] Optionally, both the first logical operation and the second logical operation are XOR operations, and the second logical operation is the inverse operation of the first logical operation.
[0012] Optionally, the process of generating and sending the verification code through the first logical operation is as follows: CRC_send = CRC_orig ⊕ VSN_Tx; In the formula, CRC_send represents sending the checksum, CRC_orig represents the first cyclic redundancy check (CRC), VSN_Tx represents the first timestamp, and ⊕ represents the XOR operation.
[0013] Optionally, the process of obtaining the received verification code through the second logical operation is as follows: CRC_recv = CRC_send ⊕ VSN_Rx; In the formula, CRC_recv represents the received checksum, VSN_Rx represents the second timestamp, and ⊕ represents the XOR operation.
[0014] Optionally, when the second timestamp is consistent with the first timestamp, the received verification code can be obtained by a second logical operation to obtain a result consistent with the first cyclic redundancy check code.
[0015] Optionally, if the received original data is error-free, the second cyclic redundancy check code is consistent with the first cyclic redundancy check code, therefore the received check code is consistent with the second cyclic redundancy check code.
[0016] Optionally, the redundant code generation step specifically includes: The predefined security baseline code, the second cyclic redundancy check code, and the received check code are subjected to a third logical operation to obtain the redundancy code.
[0017] Optionally, when the first timestamp is consistent with the second timestamp and the received verification code is equal to the second cyclic redundancy check code, an expected redundancy code is generated, and the expected redundancy code is equal to the security baseline code. Otherwise, an unexpected redundant code is generated, and the unexpected redundant code is not equal to the security baseline code.
[0018] Optionally, the third logical operation is an XOR operation.
[0019] Optionally, the security reference code is a NISAL code.
[0020] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the protection method when executing the program.
[0021] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the protection method described above.
[0022] In summary, compared with the prior art, the present invention has the following beneficial effects: 1. This invention provides a method, medium, and device for redundancy protection based on CRC and timestamps. By using timestamp information as a perturbation factor and XORing it into the first cyclic redundancy check (CRC), the verification of data "freshness" becomes a prerequisite and intrinsic component of data integrity verification. Any time asynchrony will directly prevent the receiver from correctly descrambling the original CRC, thus inevitably causing subsequent integrity comparisons to fail. This fundamentally defends against replay attacks. Therefore, this invention achieves a deep integration and intrinsic security of timeliness protection and integrity protection.
[0023] 2. This invention provides a method, medium, and device for redundancy code protection based on CRC and timestamps. The dual verification results of timeliness and integrity (i.e., whether the received check code is equal to the second cyclic redundancy check code CRC) are directly used as input to a redundancy code generation algorithm (such as XOR operation). When the verification passes, the algorithm outputs the correct expected redundancy code; when the verification fails (data timeout or error), the algorithm automatically and without delay generates an unexpected redundancy code representing the security side using its mathematical properties (such as XOR operation). Therefore, this invention eliminates the intermediate step of "verification failure -> triggering an independent security process" in traditional schemes, making the security response more direct, more certain, and more reliable. Attached Figure Description
[0024] Figure 1 This is a schematic diagram illustrating normal data transmission according to the present invention. Figure 2 This is a schematic diagram illustrating the data delay transmission of the present invention; Figure 3 This is a schematic diagram illustrating a code point jump during data transmission in this invention. Detailed Implementation
[0025] The following will be combined with the appendix Figures 1-3 The present invention will be further described in detail through preferred embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of the present invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of the present invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention.
[0026] This invention provides a method for protecting redundant code points based on Cyclic Redundancy Check (CRC) and timestamps, applicable to an architecture with a first system and a second system. The method for protecting redundant code points includes: The data transmission step is performed by the first system, and the data transmission step includes: Obtain the raw data to be sent; calculate the first cyclic redundancy check code of the raw data; obtain the first timestamp of the first system; perform a first logical operation on the first cyclic redundancy check code and the first timestamp to generate a sending check code; send a data packet containing the raw data and the sending check code; The data receiving and redundancy code generation steps are performed by the second system, and these steps include: Receive the data packet and parse out the original data and the sending verification code from it; obtain the second timestamp of the second system; perform a second logical operation on the sending verification code and the second timestamp to obtain the receiving verification code; Based on the received original data, a second cyclic redundancy check code is obtained by recalculation; based on the received check code and the second cyclic redundancy check code, a redundancy code is generated. Specifically, the received check code is equal to the second cyclic redundancy check code if and only if the first timestamp is consistent with the second timestamp and the original data is transmitted without error, thereby generating the expected redundancy code; otherwise, an unexpected redundancy code is generated to guide the security side.
[0027] The following is for reference. Figure 1 Provide a specific implementation process: The redundancy protection method provided in this embodiment performs the following steps between the sender (i.e., the first system) and the receiver (i.e., the second system): S101, the sender performs the sending step, which includes: Retrieve the raw data to be sent.
[0028] Calculate the first cyclic redundancy check code of the original data Data, denoted as CRC_orig.
[0029] Get the sender's current system timestamp, i.e., the first timestamp, denoted as VSN_Tx.
[0030] Perform a first logical operation on CRC_orig and VSN_Tx to generate a send check code, denoted as CRC_send. Specifically, the first logical operation is an XOR operation, and the process of generating the send check code CRC_send can be expressed as: CRC_send = CRC_orig ⊕ VSN_Tx, where ⊕ represents the XOR operation.
[0031] The data packet containing the original data Data and the sending verification code CRC_send is transmitted to the receiver through the network communication channel.
[0032] S102, Time Synchronization: The sender and receiver synchronize the system timestamps of the first and second systems in real time through a time channel independent of the aforementioned data channel. Therefore, under ideal synchronization conditions, the second timestamp VSN_Rx held locally by the receiver should be consistent with the first timestamp VSN_Tx of the sender, i.e., VSN_Rx = VSN_Tx; wherein, the time channel is a dedicated serial communication channel, such as a serial port.
[0033] S103, the receiver receives and processes the data packet.
[0034] The receiver receives data packets through the network communication channel and parses out the original data (Data) and the CRC checksum (CRC_send).
[0035] The receiver synchronizes the second timestamp VSN_Rx through an independent time channel and updates it locally.
[0036] The receiver performs a second logical operation on the second timestamp VSN_Rx and the sent verification code CRC_send to generate a received verification code, denoted as CRC_recv. Specifically, the second logical operation is an XOR operation and is the inverse operation of the first logical operation. The process of generating the received verification code CRC_recv can be expressed as: CRC_recv = CRC_send ⊕ VSN_Rx, where ⊕ represents the XOR operation.
[0037] Furthermore, since VSN_Rx = VSN_Tx, CRC_recv = CRC_send ⊕ VSN_Rx = CRC_orig ⊕ VSN_Tx ⊕ VSN_Tx = CRC_orig. Therefore, through the second logical operation, the received check code CRC_recv is consistent with the first cyclic redundancy check code CRC_orig, that is, CRC_recv = CRC_orig.
[0038] Based on the received original data, the receiver recalculates to obtain the second cyclic redundancy check code, denoted as CRC_calc.
[0039] If the received original data is error-free, the obtained second cyclic redundancy check code CRC_calc is consistent with the first cyclic redundancy check code CRC_orig, that is, CRC_calc=CRC_orig. Therefore, in this data transmission case, the received check code CRC_recv is equal to the second cyclic redundancy check code CRC_calc.
[0040] S104, the receiver verifies the processed data and generates a redundancy code; specifically, if the verification is correct, the expected redundancy code is generated; if the verification is incorrect, an unexpected redundancy code is generated to guide the security test.
[0041] Specifically, the verification includes: The check for synchronization between the first and second timestamps, i.e., whether VSN_Rx equals VSN_Tx; and, Verification of whether the second cyclic redundancy check code CRC_calc and the received check code CRC_recv are equal.
[0042] An expected redundancy code is generated if and only if the first timestamp matches the second timestamp and the received verification code CRC_recv is equal to the second cyclic redundancy check code CRC_calc; otherwise, an unexpected redundancy code is generated to guide the security side.
[0043] More specifically, the process of generating the redundant code is as follows: The predefined security baseline code, the second cyclic redundancy check code CRC_calc, and the received check code CRC_recv are subjected to a third logical operation to obtain a redundancy code, denoted as Output_Code; wherein, the third logical operation is an XOR operation; the security baseline code is a NISAL code, which represents a normal security state.
[0044] The process of obtaining the redundant code is as follows: Output_Code = NISAL ⊕ CRC_recv ⊕ CRC_calc, where ⊕ represents the XOR operation.
[0045] Furthermore, when the first timestamp is consistent with the second timestamp, and the received verification code CRC_recv is equal to the second cyclic redundancy check code CRC_calc, an expected redundancy code equal to the security reference code is generated; otherwise, an unexpected redundancy code not equal to the security reference code is generated to guide the security side.
[0046] When an unexpected redundant code that is not equal to the security reference code is generated, it indicates that the time is out of sync (data timeout) or the data is corrupted during transmission (data is tampered with or code bit is skipped). In this case, the resulting redundant code Output_Code will be a code value of a non-security reference code NISAL. This code value is designed to directly drive the system into or maintain a predefined "security side" state (e.g., output security side control commands, trigger safety braking, etc.) without going through an additional, potentially erroneous security logic judgment process.
[0047] The following is combined with Figures 1 to 3 The effects of the invention are further illustrated through three typical scenarios: Figure 1 This represents a scenario where data is transmitted normally. In this scenario, the sender sends the original data at time T0 and generates a sending check code CRC_send using the first cyclic redundancy check code CRC_orig and the current first timestamp VSN(T0), i.e., CRC_send=CRC_orig⊕VSN(T0), where ⊕ represents the XOR operation.
[0048] The receiver receives the data packet containing the original data and the sending checksum at time T0 (or within a very short delay) and synchronizes the timestamp information locally, forming a second timestamp VSN_Rx, i.e., VSN_Rx = VSN(T0). Then, it parses the data packet and performs a logical operation between the parsed sending checksum CRC_send and the local second timestamp VSN(T0) to generate the receiving checksum CRC_recv, i.e., CRC_recv = CRC_send ⊕ VSN(T0), where ⊕ represents an XOR operation. This receiving checksum CRC_recv is the first cyclic redundancy check (CRC) code CRC_orig, i.e., CRC_recv = CRC_orig, indicating that the timestamp descrambling is correct. Next, the receiver recalculates the parsed original data to obtain the second cyclic redundancy check (CRC_calc). Since the original data is error-free, CRC_calc = CRC_orig, therefore CRC_calc = CRC_recv.
[0049] The receiver generates a redundancy code Output_Code based on the received checksum CRC_recv and the second cyclic redundancy checksum CRC_calc, and based on a predefined security baseline code. That is, Output_Code = NISAL ⊕ CRC_recv ⊕ CRC_calc, where ⊕ represents the XOR operation. Since CRC_calc = CRC_recv, Output_Code = NISAL. At this time, the output is the expected redundancy code equal to the security baseline code, and the system operates normally.
[0050] Figure 2This represents a scenario of delayed data transmission. In this scenario, the sender sends the original data at time T1 and generates a sending check code CRC_send using the first cyclic redundancy check code CRC_orig and the current first timestamp VSN(T1), i.e., CRC_send=CRC_orig⊕VSN(T1), where ⊕ represents the XOR operation.
[0051] Due to network latency, the receiver receives the data packet containing the original data and the sending checksum at time T10. At this time, its local second timestamp has been updated to VSN(T10), and VSN(T10) ≠ VSN(T1). The receiver then parses the data packet and performs a logical operation between the parsed sending checksum CRC_send and its local second timestamp VSN(T10) to generate the receiving checksum CRC_recv, i.e., CRC_recv = CRC_send ⊕ VSN(T10), where ⊕ represents an XOR operation. At this point, the receiving checksum CRC_recv is not equal to the first cyclic redundancy check (CRC_orig), i.e., CRC_recv ≠ CRC_orig. The receiver then recalculates the parsed original data to obtain the second cyclic redundancy check (CRC_calc). Again, since CRC_calc = CRC_orig, CRC_calc ≠ CRC_recv.
[0052] The receiver generates a redundancy code Output_Code based on the received checksum CRC_recv and the second cyclic redundancy checksum CRC_calc, and based on a predefined security baseline code. That is, Output_Code = NISAL ⊕ CRC_recv ⊕ CRC_calc, where ⊕ represents an XOR operation. Since CRC_calc ≠ CRC_recv, Output_Code ≠ NISAL. At this time, the output is an unexpected redundancy code that is not equal to the security baseline code, and the data delay drives the system to the security side.
[0053] Figure 3 This indicates a code bit transition during data transmission. In this scenario, the sender transmits the original data Data at time T0 and generates a transmission check code CRC_send using the first cyclic redundancy check code CRC_orig and the current first timestamp VSN(T0), i.e., CRC_send = CRC_orig ⊕ VSN(T0), where ⊕ represents the XOR operation.
[0054] During transmission to the receiver, a bit in the original data Data undergoes a bit shift. Therefore, the receiver receives a data packet containing the err data Data_err and a sending checksum at time T0. The receiver then synchronizes the timestamp information locally, forming a second timestamp VSN_Rx, i.e., VSN_Rx = VSN(T0). The data packet is then parsed, and the parsed sending checksum CRC_send is logically operated on with the local second timestamp VSN(T0) to generate the receiving checksum CRC_recv, i.e., CRC_recv = CRC_send ⊕ VSN(T0), where ⊕ represents an XOR operation. This receiving checksum CRC_recv is the first cyclic redundancy check (CRC_orig), i.e., CRC_recv = CRC_orig, indicating that the timestamp descrambling was successful. Next, the receiver calculates the parsed error data Data_err and obtains the second cyclic redundancy check code CRC_calc_err. At this time, CRC_calc_err ≠ CRC_orig, therefore CRC_calc_err ≠ CRC_recv.
[0055] The receiver generates a redundancy code Output_Code based on the received checksum CRC_recv and the second cyclic redundancy checksum CRC_calc_err, and based on a predefined security baseline code. That is, Output_Code = NISAL ⊕ CRC_recv ⊕ CRC_calc_err, where ⊕ represents an XOR operation. Since CRC_calc_err ≠ CRC_recv, Output_Code ≠ NISAL. At this time, the output is an unexpected redundancy code that is not equal to the security baseline code, and the system is redirected to the security side due to data errors.
[0056] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the redundancy code point protection method when executing the program.
[0057] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the aforementioned redundancy code point protection method.
[0058] In summary, the redundancy code protection method, medium, and device provided by this invention, based on CRC and timestamps, deeply integrates timestamp verification, CRC verification, and the final secure output code generation process through ingenious coding design. Therefore, regardless of whether the data fails due to timeout or error, the same set of deterministic mathematical operations will directly and automatically generate a secure output, achieving efficient and reliable intrinsic security protection.
[0059] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0060] In the description of this invention, it should be understood that the terms "center," "height," "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0061] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0062] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0063] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method for protecting redundant code points based on CRC and timestamp, characterized in that, The protection method, applied in an architecture having a first system and a second system, includes: The data transmission step is performed by the first system and includes: Obtain the raw data to be sent; calculate the first cyclic redundancy check code of the raw data; obtain the first timestamp of the first system; perform a first logical operation on the first cyclic redundancy check code and the first timestamp to generate a sending check code; send a data packet containing the raw data and the sending check code; The data receiving and redundancy code generation steps are performed by the second system, and these steps include: Receive the data packet and parse out the original data and the sending verification code from it; obtain the second timestamp of the second system; perform a second logical operation on the sending verification code and the second timestamp to obtain the receiving verification code; Based on the received original data, a second cyclic redundancy check code is obtained by recalculation; based on the received check code and the second cyclic redundancy check code, a redundancy code is generated. Specifically, an expected redundancy code is generated if and only if the first timestamp is consistent with the second timestamp and the received verification code is equal to the second cyclic redundancy check code; otherwise, an unexpected redundancy code is generated to guide the security side.
2. The protection method as described in claim 1, characterized in that, The second timestamp is synchronized with the first timestamp through a time channel independent of the data packet transmission path.
3. The protection method as described in claim 2, characterized in that, The time channel is a serial communication channel, and the data packets are transmitted through a network communication channel.
4. The protection method as described in claim 2, characterized in that, Both the first logical operation and the second logical operation are XOR operations, and the second logical operation is the inverse operation of the first logical operation.
5. The protection method as described in claim 4, characterized in that, The process of generating and sending the verification code through the first logical operation is as follows: CRC_send = CRC_orig ⊕ VSN_Tx; In the formula, CRC_send represents sending the checksum, CRC_orig represents the first cyclic redundancy check (CRC), VSN_Tx represents the first timestamp, and ⊕ represents the XOR operation.
6. The protection method as described in claim 5, characterized in that, The process of obtaining the received verification code through the second logical operation is as follows: CRC_recv = CRC_send ⊕ VSN_Rx; In the formula, CRC_recv represents the received checksum, VSN_Rx represents the second timestamp, and ⊕ represents the XOR operation.
7. The protection method as described in claim 6, characterized in that, When the second timestamp is consistent with the first timestamp, the received verification code can be obtained through the second logical operation to obtain a result consistent with the first cyclic redundancy check code.
8. The protection method as described in claim 7, characterized in that, If the received original data is error-free, the second cyclic redundancy check code is consistent with the first cyclic redundancy check code, therefore the received check code is consistent with the second cyclic redundancy check code.
9. The protection method as described in claim 8, characterized in that, The redundant code generation step specifically includes: The predefined security baseline code, the second cyclic redundancy check code, and the received check code are subjected to a third logical operation to obtain the redundancy code.
10. The protection method as described in claim 9, characterized in that, When the first timestamp is consistent with the second timestamp, and the received verification code is equal to the second cyclic redundancy check code, an expected redundancy code is generated, and the expected redundancy code is equal to the security baseline code. Otherwise, an unexpected redundant code is generated, and the unexpected redundant code is not equal to the security baseline code.
11. The protection method as described in claim 9, characterized in that, The third logical operation is the XOR operation.
12. The protection method as described in claim 9, characterized in that, The security baseline code is the NISAL code.
13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the protection method as described in any one of claims 1-12.
14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the protection method as described in any one of claims 1-12.