Circuit board and electronic equipment

Abstract

The embodiment of the invention discloses a circuit board and electronic equipment. The circuit board comprises a signal vertical interconnection structure group and a signal wiring group, two signal vertical interconnection structures of the signal vertical interconnection structure group are electrically connected with two signal wiring of the signal wiring group respectively, and a first signal path and a second signal path capable of transmitting signals in the same direction are constructed and formed; the first conductor part on the first signal path is adjacent to the second conductor part on the second transmission path, the signal transmission directions on the first conductor part and the second conductor part are opposite, and a crosstalk suppression structure is constructed. Therefore, reverse mutual inductance can be formed based on the first conductor part and the second conductor part, and compared with mutual inductance of crosstalk generated by same-direction transmission between the first signal path and the second signal path, the first conductor part and the second conductor part forming the reverse mutual inductance on the signal path are constructed into a crosstalk suppression structure; relative capacitive coupling and relative inductive coupling of the whole link can be adjusted, the crosstalk of the whole link is effectively reduced, and the signal quality is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of circuit boards, and in particular to a circuit board and an electronic device. BACKGROUND

[0002] With the continuous improvement of the signal rate of high-speed systems, the crosstalk between adjacent signals has a greater and greater impact when the signals propagate on the transmission line. Excessive crosstalk noise will lead to signal quality degradation, and even affect the implementation of system functions.

[0003] In order to reasonably control the crosstalk noise, the related technology usually uses optimization means to suppress the crosstalk at the node area with large crosstalk, so as to reduce the system crosstalk. For example, through a high signal-to-ground pin map scheme, the crosstalk influence between vias is improved; for another example, the thickness of the green oil layer of the surface microstrip line is adjusted to improve the crosstalk influence of the surface trace. However, the space available for arrangement in the node area with large crosstalk is limited, and the crosstalk suppression optimization means will limit the impedance optimization of the corresponding area, and cannot effectively solve the crosstalk bottleneck of the high-speed system architecture. SUMMARY

[0004] Embodiments of the present application provide a circuit board and an electronic device, which effectively improve the crosstalk influence of the signal transmission link through the structural optimization of the circuit board, and provide technical support for improving signal quality and rate.

[0005] A first aspect of embodiments of the present application provides a circuit board, which includes a signal vertical interconnection structure group and a signal trace group, the signal vertical interconnection structure group includes two signal vertical interconnection structures, and the signal trace group includes two signal traces; wherein the two signal vertical interconnection structures of the signal vertical interconnection structure group and the two signal traces of the signal trace group are respectively electrically connected, and form a first signal path and a second signal path that can transmit signals in the same direction; a first conductor part on the first signal path is arranged adjacent to a second conductor part on the second transmission path, the signal transmission directions on the first conductor part and the second conductor part are opposite, and the first conductor part and the second conductor part are constructed as a crosstalk suppression structure. In this way, the first conductor part and the second conductor part can form a reverse mutual inductance based on the first conductor part and the second conductor part, compared with the mutual inductance generated by the crosstalk between the first signal path and the second signal path transmitting in the same direction, the first conductor part and the second conductor part forming the reverse mutual inductance on the signal path are constructed as a crosstalk suppression structure, which can adjust the relative capacitive coupling and the relative inductive coupling of the whole link, effectively reduce the whole link crosstalk, and improve the signal quality. At the same time, it provides good technical support for the improvement of signal rate.

[0006] Exemplarily, the circuit board can be a chip packaging substrate, and can also be a carrier board or a carrier-like board used to realize electrical connection between electronic elements.

[0007] Based on the first aspect, the embodiments of the present application further provide a first implementation of the first aspect: the signal vertical interconnection structure group comprises a first vertical interconnection structure and a second vertical interconnection structure, the signal wire group comprises a first signal wire and a second signal wire, the first signal wire comprises a first connection wire segment and a first lead-out wire segment connected together, the first connection wire segment is electrically connected with the first vertical interconnection structure, the second signal wire comprises a second connection wire segment and a second lead-out wire segment connected together, the second connection wire segment is electrically connected with the second vertical interconnection structure; wherein the first conductor part is formed by the first connection wire segment or by the first lead-out wire segment; the second conductor part is formed by the second connection wire segment or by the second lead-out wire segment. Specifically, in different crosstalk scenarios, the arrangement position of the reverse suppression structure can be determined according to the overall design requirements of the product, and better adaptability is achieved.

[0008] In actual application, the signal wire group can be a surface signal wire, or can also be an inner layer signal wire.

[0009] Based on the first implementation of the first aspect, the embodiments of the present application further provide a second implementation of the first aspect: the signal vertical interconnection structure group is a signal via group, the signal via group comprises a first signal via and a second signal via, the first signal via and the second signal via are arranged at intervals in a first direction; the signal wire group comprises a first signal wire and a second signal wire, the first signal wire comprises a first connection wire segment and a first lead-out wire segment connected together, the first connection wire segment is electrically connected with the first signal via, the second signal wire comprises a second connection wire segment and a second lead-out wire segment connected together, the second connection wire segment is electrically connected with the second signal via. In this way, for the signal wire connected with the signal via to construct a signal path, a reverse mutual inductance can be formed by arranging a reverse suppression structure to reduce the full-link crosstalk. It has the characteristics of simple structure and low process implementation cost.

[0010] Based on the second implementation of the first aspect, the embodiments of the present application further provide a third implementation of the first aspect: the first connection wire segment and the second connection wire segment are located between the first signal via and the second signal via, the first connection wire segment is arranged to extend from the first signal via towards the second signal via, and the second connection wire segment is arranged to extend from the second signal via towards the first signal via; the first conductor part is formed by the first connection wire segment, and the second conductor part is formed by the second connection wire segment. In this way, the connection position of the signal via and the signal wire can be used to construct a reverse suppression structure, which can effectively reduce the full-link crosstalk without increasing the occupation of the board layout space.

[0011] Exemplarily, in the second direction, the first lead-out wire segment is arranged to extend towards one side of the circuit board, and the second lead-out wire segment is arranged to extend towards the other side of the circuit board. Here, the first direction and the second direction are two directions intersecting in the circuit board plane.

[0012] Exemplarily, in the second direction, the first lead-out wire segment is arranged to extend towards one side of the circuit board, and the second lead-out wire segment is arranged to extend towards the other side of the circuit board. Here, the first direction and the second direction are two directions intersecting in the circuit board plane.

[0013] Based on the second implementation manner of the first aspect, the embodiments of the present application further provide a fourth implementation manner of the first aspect: the first connection wire segment and the second connection wire segment are located on one side of the first signal via and the second signal via in the second direction, the first lead-out wire segment is located on the side of the second signal via away from the first signal via, the second lead-out wire segment is located between the first signal via and the second signal via, and the first lead-out wire segment and the second lead-out wire segment are arranged to extend towards the other side of the first signal via and the second signal via in the second direction; the first conductor part is formed by the first connection wire segment, and the second conductor part is formed by the second connection wire segment. In this way, the first lead-out wire segment and the second lead-out wire segment of the signal wire group are arranged to extend towards the same side, which is beneficial to realize the layout on the board.

[0014] Based on the second implementation manner of the first aspect, the embodiments of the present application further provide a fifth implementation manner of the first aspect: in the second direction, the first connection wire segment is arranged to extend from the first signal via towards one side, the first signal wire is bent and arranged to extend in the second direction towards the other side to form the first lead-out wire segment, and the first lead-out wire segment is located between the first signal via and the second signal via; in the second direction, the second connection wire segment is arranged to extend from the second signal via towards one side, the second signal wire is bent and arranged to extend in the second direction towards the other side to form the second lead-out wire segment, and the second lead-out wire segment is located on the side of the second signal via away from the first signal via; the first conductor part is formed by the first lead-out wire segment, and the second conductor part is formed by the second connection wire segment. In this way, the first lead-out wire segment and the second lead-out wire segment of the signal wire group are arranged to extend towards the same side, which is beneficial to realize the layout on the board.

[0015] Based on the second implementation manner of the first aspect, or the third implementation manner of the first aspect, or the fourth implementation manner of the first aspect, or the fifth implementation manner of the first aspect, the embodiments of the present application further provide a sixth implementation manner of the first aspect: the signal via group can be a blind via, a buried via or a through via. In this way, in different crosstalk scenarios, the reverse suppression structure can be applied according to the overall design requirements of the product to reduce the influence of crosstalk, which has good adaptability.

[0016] In the seventh implementation of the first aspect, a notch is formed in the dielectric layer between the wiring layer where the first conductor and the second conductor are located and the reference layer, and the notch is arranged opposite to the first conductor and the second conductor in the thickness direction of the circuit board. In this way, the mutual inductance value of the crosstalk suppression structure can be adjusted as needed based on the notch in the dielectric layer, and the crosstalk suppression effect is effectively improved by adjusting the reverse mutual inductance coupling.

[0017] For example, the projections of the first connection wiring segment and the second connection wiring segment on the board surface of the circuit board at least partially overlap with the projection of the notch on the board surface of the circuit board.

[0018] In actual applications, the thickness of the adjacent dielectric layer between the crosstalk suppression structure and the reference layer can also be reduced to adjust the coupling design according to the overall design needs of the product, and the inductance value of the introduced inductance term can also be adjusted to obtain a corresponding reverse suppression mutual inductance value, thereby optimizing the suppression effect.

[0019] In the eighth implementation of the first aspect, the circuit board is a high-density interconnection circuit board, the first signal via includes a first top via segment, a first intermediate layer wiring segment, and a first bottom via segment connected in sequence, the first top via segment and the first bottom via segment are arranged staggered, the second signal via includes a second top via segment, a second intermediate layer wiring segment, and a second bottom via segment connected in sequence, the second top via segment and the second bottom via segment are arranged staggered, in the intermediate wiring layer of the circuit board, the first intermediate layer wiring segment extends from the first top via segment towards the first bottom via segment, and the second intermediate layer wiring segment extends from the second top via segment towards the second bottom via segment, the first conductor is formed by the first intermediate layer wiring segment, and the second conductor is formed by the second intermediate layer wiring segment. In this way, the crosstalk suppression structure can be arranged in the thickness direction of the circuit board, which effectively reduces the full-link crosstalk without increasing the occupation of the board layout space, thereby meeting the design requirements of the high-density layout trend.

[0020] Based on the eighth implementation manner of the first aspect, the ninth implementation manner of the first aspect is provided in the embodiments of the present application: the first top via segment and the second bottom via segment are oppositely arranged in the plate thickness direction, and the second top via segment and the first bottom via segment are oppositely arranged in the plate thickness direction. In this way, on the basis of effectively reducing the full-link crosstalk, the layout density of the two sides of the circuit board is not affected.

[0021] Based on the first aspect, the tenth implementation manner of the first aspect is provided in the embodiments of the present application: the signal vertical interconnection structure group is a signal pad group, the signal pad group includes a first signal pad and a second signal pad, the signal trace group includes a first signal trace and a second signal trace, the first signal trace includes a first connection trace segment and a first lead-out trace segment connected in sequence, the first connection trace segment is electrically connected with the first signal pad, the second signal trace includes a second connection trace segment and a second lead-out trace segment connected in sequence, and the second connection trace segment is electrically connected with the second signal pad. In this way, for the signal trace connected with the signal pad to construct a signal path, the reverse mutual inductance can be formed by arranging the reverse suppression structure to reduce the full-link crosstalk. The structure is simple, and the process implementation cost is low.

[0022] Exemplarily, the signal trace group can be a surface layer signal trace; and other exemplarily, the signal trace group can also be an inner layer signal trace, the first connection trace segment and the first signal pad are electrically connected through a via, and the second connection trace segment and the second signal pad are electrically connected through a via.

[0023] Based on the tenth implementation manner of the first aspect, the eleventh implementation manner of the first aspect is provided in the embodiments of the present application: the first signal pad and the second signal pad of the signal pad group are arranged in a pad array, the first signal pad and the second signal pad are located in two adjacent rows of the pad array in the second direction and are staggered arranged in the first direction; the first connection trace segment is bent from the first signal pad towards the second signal pad, and the first lead-out trace segment is arranged in extension in the second direction; the first lead-out trace segment is located on one side of the second signal pad in the first direction, the second connection trace segment extends from the second signal pad towards the first signal pad, the second lead-out trace segment is arranged in extension in the second direction after being bent, and the second lead-out trace segment is located on the other side of the second signal pad in the first direction; the first conductor part is formed by the first lead-out trace segment, and the second conductor part is formed by the second connection trace segment. In this way, based on the pad array layout, the full-link crosstalk is effectively reduced without increasing the occupation of the board layout space, which meets the design requirements of the high-density layout trend.

[0024] In addition, based on the pad array layout, the ground pads can be arranged at intervals. In actual application, in the first direction, the signal pads and the ground pads arranged in rows are arranged at intervals in sequence, and in the second direction, the signal pads of the two adjacent rows of pads are staggered arranged to reduce the near-end crosstalk.

[0025] The second aspect of the embodiments of the present application provides an electronic device, which comprises a shell and a circuit board arranged in the shell, and the circuit board is as described above. Based on the circuit board, it is beneficial to improve the crosstalk noise when signals are transmitted at high speed, and to improve the crosstalk suppression effect of the whole link.

[0026] Exemplarily, the circuit board can be a chip packaging substrate, and can also be a carrier plate or a carrier plate-like plate used for electrical connection between electronic elements. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A schematic diagram of a circuit board packaging structure provided by the embodiments of the present application;

[0028] Figure 2 A schematic diagram of a circuit board provided by the embodiments of the present application;

[0029] Figure 3 A schematic diagram of a construction principle of a crosstalk suppression structure provided by the embodiments of the present application;

[0030] Figure 4 A partial schematic diagram of a positional relationship between a crosstalk suppression structure and a dielectric layer slot provided by the embodiments of the present application;

[0031] Figure 5 A schematic diagram of another circuit board provided by the embodiments of the present application;

[0032] Figure 6 A schematic diagram of another circuit board provided by the embodiments of the present application;

[0033] Figure 7 A schematic diagram of another circuit board provided by the embodiments of the present application;

[0034] Figure 8 A schematic diagram of another circuit board provided by the embodiments of the present application;

[0035] Figure 9 A schematic diagram of another circuit board provided by the embodiments of the present application;

[0036] Figure 10 A schematic diagram of a crosstalk suppression structure formed based on an HDI process provided by the embodiments of the present application;

[0037] Figure 11 A schematic diagram of another crosstalk suppression structure formed based on an HDI process provided by the embodiments of the present application;

[0038] Figure 12 A schematic diagram of an electronic device provided by the embodiments of the present application.

[0039] In the figure:

[0040] Processor 10, chip 101, package substrate 102, trace 1021, via 1022, solder ball 103, mainboard 20, trace 201, via 202, connector 30, memory stick 40, shell 50.

[0041] Circuit board 1, signal via group 2, first signal via 21, second signal via 22, signal trace group 3, first signal trace 31, first connection trace segment 311, first lead-out trace segment 312, second signal trace 32, second connection trace segment 321, second lead-out trace segment 322. DETAILED DESCRIPTION

[0042] The embodiment of the present application provides a circuit board implementation scheme for reducing system crosstalk, which optimizes the signal path on the board and reasonably controls the full-link crosstalk of signal transmission.

[0043] The circuit board is an important electronic component in an electronic device and is a carrier for electrical connection of electronic components. According to different functional applications, the circuit board can be classified into packaging substrates, carrier boards and carrier-like boards; according to the dielectric layer material and manufacturing process, the circuit board can be classified into printed circuit boards (PCB), low-temperature co-fired ceramic (LTCC) circuit boards, high-temperature co-fired ceramic (HTCC) and flexible printed circuit boards (FPC).

[0044] Taking a memory signal interconnection system in a computing server as an example, the mainboard is a typical carrier board form and is used to realize electrical connection between a processor and a memory stick. Please refer to Figure 1Fig. 1 is a schematic diagram of an interconnection link of a memory system architecture according to an embodiment of the present application. The memory system includes a processor (chip package) 10, a mainboard 20, a connector 30, and a memory stick (Dual-Inline-Memory-Modules, DIMM) 40. The chip 101 of the processor 10 is packaged on a packaging substrate 102 and can be soldered to an interface on the mainboard 20 through ball grid array (Ball Grid Array, BGA) solder balls 103. The chip 101 and the DIMM 40 are interconnected through structures such as wires, vias, solder balls, and connectors to form a signal transmission path. Among them, according to the arrangement direction of the interconnection structure, the wires 101 on the mainboard 10 and the wires 1021 on the packaging substrate 102 of the chip 101 are horizontal interconnection structures, and the vias 202 on the mainboard 10 and the vias 1022 on the packaging substrate 102 of the chip, the solder balls 103, and the connector 30 are vertical interconnection structures.

[0045] In order to reduce the crosstalk influence between adjacent signals, the related technology usually uses an optimization means to suppress crosstalk in a node area with large crosstalk. For example, the chip package uses a pin arrangement mode with high signal-to-ground ratio to improve the crosstalk influence between adjacent signal vias; for another example, the thickness of the green oil layer of the surface layer microstrip line of the board is adjusted to improve the crosstalk influence between adjacent surface layer wires. With the trend of product miniaturization, the arrangement space of the node area with large crosstalk is limited, which leads to a bottleneck in crosstalk suppression of the system architecture and cannot meet the evolution of signal rate.

[0046] Based on this, an embodiment of the present application provides a circuit board, which includes a signal vertical interconnection structure group and a signal wire group. The signal vertical interconnection structure group includes two signal vertical interconnection structures, and the signal wire group includes two signal wires. The two signal vertical interconnection structures of the signal vertical interconnection structure group and the two signal wires of the signal wire group are respectively electrically connected, and form a first signal path and a second signal path that can transmit signals in the same direction. A first conductor part on the first signal path is arranged adjacent to a second conductor part on the second transmission path, and the signal transmission directions on the first conductor part and the second conductor part are opposite. In this way, a reverse mutual inductance can be formed based on the first conductor part and the second conductor part. Compared with the mutual inductance generated by the crosstalk between the first signal path and the second signal path transmitting in the same direction, the first conductor part and the second conductor part forming the reverse mutual inductance on the signal path are constructed as a crosstalk suppression structure. The relative capacitive coupling and the relative inductive coupling of the whole link can be adjusted, the whole link crosstalk can be effectively reduced, and the signal quality is improved, which provides a good technical guarantee for the improvement of signal rate.

[0047] In order not to lose generality, specific embodiments will be described in detail below in conjunction with the drawings. Please refer to Figure 2 andFigure 3 wherein, Figure 2 a schematic diagram of a circuit board provided by an embodiment of the present application, Figure 3 a schematic diagram of a construction principle of a crosstalk suppression structure provided by an embodiment of the present application.

[0048] As Figure 2 shown, the circuit board 1 comprises a signal via group 2 and a signal trace group 3, the signal via group 2 comprises a first signal via 21 and a second signal via 22, and the signal trace group 3 comprises a first signal trace 31 and a second signal trace 32. In order to clearly show the adaptation principle of the crosstalk suppression structure, Figure 2 only partial signal paths connected with a group of signal vias are shown.

[0049] In the first direction X, the first signal via 21 and the second signal via 22 are arranged at intervals. One end of the first signal trace 31 is electrically connected with the first signal via 21, thereby constructing a first signal path; the second signal trace 32 is electrically connected with the second signal via 22, thereby constructing a second signal path. As Figure 3 shown, the first signal path P1 and the second signal path P2 can transmit signals in the same direction. Here, “transmit signals in the same direction” means that signals are transmitted in the same direction on the two signal paths, for example, data signals are transmitted from the processor chip side to the memory stick side. Exemplarily, in the node region S adjacent to the first signal path P1 and the second signal path P2, crosstalk is generated between the signals transmitted in the same direction based on mutual inductance.

[0050] As Figure 2 shown, the first signal trace 31 comprises a first connection trace segment 311 and a first lead-out trace segment 312 connected with each other, the first connection trace segment 311 is electrically connected with the first signal via 21, and the second signal trace 32 comprises a second connection trace segment 321 and a second lead-out trace segment 322 connected with each other, the second connection trace segment 321 is electrically connected with the second signal via 22; that is, the first signal trace 31 is electrically connected with the first signal via 21 through the first connection trace segment 311, and the second signal trace 32 is electrically connected with the second signal via 22 through the second connection trace segment 321, thereby leading out signals from the corresponding signal vias and distributing the signals to other parts (not shown in the figure) of the circuit board 1.

[0051] In the first direction X, the first connection trace segment 311 and the second connection trace segment 321 are located between the first signal via 21 and the second signal via 22, and the first connection trace segment 311 is arranged to extend from the first signal via 21 towards the second signal via 22, and the second connection trace segment 321 is arranged to extend from the second signal via 22 towards the first signal via 21. That is, the first connection trace segment 311 and the second connection trace segment 321 extend from the signal vias connected with each other towards each other, and they are arranged adjacent to each other in the second direction Y. AsFigure 2 As shown by the arrows, the signals on the first connection trace segment 311 and the second connection trace segment 321 are transmitted in opposite directions, thereby forming a reverse mutual inductance.

[0052] The first connection trace segment 311 is a structural form of the first conductor part, and the second connection trace segment 321 is another structural form of the second conductor part. In other words, the first conductor part is formed by the first connection trace segment 311, and the second conductor part is formed by the second connection trace segment 321. With respect to the mutual inductance that generates crosstalk effects at the node area S, the first connection trace segment 311 and the second connection trace segment 321 are constructed as a passive crosstalk suppression structure that can form a reverse mutual inductance. In this way, by adjusting the capacitive coupling and the inductive coupling of the entire link, the inductive term and the capacitive term in the link are made to be approximately equivalent, thereby effectively reducing the far-end crosstalk (FEXT) and further reducing the entire link crosstalk of the signal transmission path. It should be understood that the above technical advantages are more significant for an architecture that performs data transmission based on a parallel bus.

[0053] In the second direction Y, the first lead-out trace segment 312 is arranged to extend towards one side of the circuit board, and the second lead-out trace segment 322 is arranged to extend towards the other side of the circuit board, without affecting the connection wiring of the first signal via 21 and the second signal via 22 on the basis of constructing a reliable passive crosstalk suppression structure.

[0054] In specific implementations, the signal via group 2 can be a buried via, a blind via, or a through via. For the signal via group 2 in the form of a buried via, the signal trace group 3 can be an inner layer signal trace of the circuit board 1; for the signal via group 2 in the form of a blind via or a through via, the signal trace group 3 can be an inner layer signal trace of the circuit board 1 or a surface layer signal trace of the circuit board 1. The embodiments of the present application are not limited in this regard.

[0055] In the present embodiment, the signal trace connected to the signal via is arranged in a bent shape to construct a passive crosstalk suppression structure. As a preference, the crosstalk suppression structure on the circuit board trace structure in the link can be arranged in a relatively spacious area to avoid affecting the overall layout of the circuit board due to the introduction of the crosstalk suppression structure. In specific implementations, the inductance value of the inductive term formed by the crosstalk suppression structure can be adjusted by adjusting the length or cross-sectional dimension (trace width) of the first conductor part and the second conductor part, or the spacing between the first conductor part and the second conductor part, to match the inductive term of other nodes in the link, thereby effectively reducing the overall crosstalk of the link.

[0056] To further optimize the reverse mutual inductance suppression effect, in addition to adjusting the self structure and relative position relationship of the first conductor part and the second conductor part, for the corresponding wire segments (the first connection wire segment 311 and the second connection wire segment 321) of the signal wire group constructing the crosstalk suppression structure, a slotting manner can be used in the adjacent dielectric layer between the crosstalk suppression structure and the reference layer, please refer to Figure 4 , which is a partial schematic view of the position relationship between the crosstalk suppression structure and the dielectric layer slot of the embodiment of the application.

[0057] As Figure 4 shown, for the first connection wire segment 311 and the second connection wire segment 321 constructed as the passive crosstalk suppression structure, a slot 111 is provided in the adjacent dielectric layer 11 between the wiring layer where the first connection wire segment 311 and the second connection wire segment 321 are located and the reference layer, and the slot 111 is oppositely arranged in the thickness direction of the circuit board 1. In this way, based on the provision of the dielectric layer slot 111, the mutual inductance value formed by the crosstalk suppression structure is adjusted according to the overall design requirements of the product, the reverse mutual inductance coupling is adjusted, and the crosstalk suppression effect is effectively improved.

[0058] In specific implementation, the projection of the first connection wire segment 311 and the second connection wire segment 321 on the board surface of the circuit board at least partially coincides with the projection of the slot 111 on the board surface of the circuit board. The specific implementation can be determined according to actual needs, and the embodiment of the application is not limited.

[0059] In other specific implementations, the adjacent dielectric layer 11 (not shown in the figure) between the crosstalk suppression structure and the reference layer can also be thinned to adjust the coupling design according to the overall design needs of the product, adjust the inductance value of the introduced inductance term to obtain the corresponding reverse suppression mutual inductance value, and optimize the suppression effect.

[0060] In addition, in other possible implementation schemes, the dielectric constant of the adjacent dielectric layer between the crosstalk suppression structure and the reference layer can also be adjusted, for example but not limited to, by increasing or reducing the dielectric constant of the dielectric layer adjacent to the crosstalk suppression structure region, relative to the dielectric layer material of other regions, to adjust the mutual inductance value and further improve the crosstalk suppression effect.

[0061] For the signal wire, other bending wiring forms can also be used to construct the crosstalk suppression structure in other specific implementations. Please refer to Figure 5 , which is a schematic view of another circuit board provided by the embodiment of the application. In order to clearly show the differences and relationships between different embodiments, the same functions and structures are shown in the figure with Figure 1 .

[0062] As Figure 5As shown, the first signal trace 31 and the second signal trace 32 of the circuit board 1 employ different bending routing methods to construct a passive crosstalk suppression structure. In the first direction X, the first connection trace segment 311 and the second connection trace segment 321 are located between the first signal via 21 and the second signal via 22, and the first connection trace segment 311 and the second connection trace segment 321 are constructed to form a passive crosstalk suppression structure capable of generating reverse mutual inductance. Figure 2 Compared to the described solution, the difference in this implementation is that, after the second lead-out ...

[0063] Other components and connection methods can be the same as those in the aforementioned implementation scheme. They will not be repeated here.

[0064] Please see Figure 6 This figure is a schematic diagram of another type of circuit board provided in an embodiment of this application.

[0065] like Figure 6 As shown, the first signal trace 31 and the second signal trace 32 of the circuit board 1 also employ different bending routing methods to construct a passive crosstalk suppression structure. The first connecting trace segment 311 and the second connecting trace segment 321 of the first signal trace 31 are located on one side of the first signal via 21 and the second signal via 22 in the second direction Y. The first connecting trace segment 311 and the second connecting trace segment 321 are constructed to form a passive crosstalk suppression structure that can generate reverse mutual inductance. The first lead-out trace segment 312 of the first signal trace 31 is located on the side of the second signal via 22 away from the first signal via 21. The second lead-out trace segment 322 of the second signal trace 32 is located between the first signal via 21 and the second signal via 22. The first lead-out trace segment 312 and the second lead-out trace segment 322 extend toward the other side of the first signal via 21 and the second signal via 22 in the second direction Y.

[0066] Other components and connection methods can be the same as those in the aforementioned implementation scheme. They will not be repeated here.

[0067] Please see Figure 7 This figure is a schematic diagram of another circuit board provided in an embodiment of this application.

[0068] like Figure 7As shown, the first signal trace 31 and the second signal trace 32 of the circuit board 1 have the same bending layout. In the second direction Y, the first connection trace segment 311 of the first signal trace 31 extends from the first signal via 21 towards one side, and the first signal trace 31 is bent to extend in the second direction Y towards the other side to form the first lead-out trace segment 312, which is located between the first signal via 21 and the second signal via 22. In the second direction Y, the second connection trace segment 321 of the second signal trace 32 extends from the second signal via 22 towards one side, and the second signal trace 32 is bent to extend in the second direction Y towards the other side to form the second lead-out trace segment 322, which is located on the side of the second signal via 22 away from the first signal via 21.

[0069] In the embodiment, the first lead-out trace segment 312 and the second connection trace segment 321 are configured to form a passive crosstalk suppression structure with mutual inductance. In other words, the first conductor part is formed by the first lead-out trace segment 312, and the second conductor part is formed by the second connection trace segment 321.

[0070] Other configurations and connection manners can be the same as those in the foregoing embodiments, which will not be described herein.

[0071] In the foregoing embodiments, the signal traces are horizontal interconnection structures on the signal paths, and the signal vias are vertical interconnection structures on the signal paths. In other specific implementations, the vertical interconnection structures electrically connected to the signal trace group 3 can also be pad groups on the surface of the circuit board 1, such as interface pad groups for connecting to pins of a connector, or interface pad groups for connecting to solder balls of a chip package. Please refer to Figure 8 , which is a schematic diagram of another circuit board provided by an embodiment of the present application. In order to clearly show the differences and connections between the present embodiment and the foregoing embodiments, the configurations and structures with the same functions are schematically shown in the figure by Figure 1 .

[0072] Compared with the foregoing embodiments, the difference of the present embodiment is that the vertical interconnection structures electrically connected to the signal trace group 3 are the signal pad group 2a, the signal pad group 2a includes the first signal pad 21a and the second signal pad 22a, and the signal trace group 3 is the surface signal trace of the circuit board 1. The arrayed signal pads are arranged at intervals with the ground pads 23, as shown in Figure 8 , in the first direction X, the arrayed signal pads and the ground pads 23 are arranged at intervals in sequence, and in the second direction Y, the signal pads of adjacent two rows of pads are arranged at intervals to reduce the near-end crosstalk.

[0073] Exemplarily, Figure 8As an example, only the signal pad group 2a is taken into account, and the signal wire group 3 connected with the signal pad group 2a is shown. The first signal pad 21a and the second signal pad 22a of the signal pad group 2a are located in the two adjacent rows of the pad array in the second direction Y, and are staggered in the first direction X. Correspondingly, the first signal wire 31 is electrically connected with the first signal pad 21a, and the second signal wire 32 is electrically connected with the second signal pad 22a, and is led out to the same side in the second direction Y.

[0074] The first connection wire segment 311 of the first signal wire 31 is bent from the first signal pad 21a towards the second signal pad 22a, and the first leading-out wire segment 312 connected with the first connection wire segment 311 is arranged in extension in the second direction Y. The first leading-out wire segment 312 is located between the second signal pad 22a and the ground pad 23 adjacent to one side of the second signal pad 22a in the first direction X. The second connection wire segment 321 of the second signal wire 32 is arranged in extension from the second signal pad 22a towards the first signal pad 21a, and the second leading-out wire segment 322 connected with the second connection wire segment 321 is arranged in extension in the second direction Y after being bent. The second leading-out wire segment 322 is located between the second signal pad 22a and the ground pad 23 adjacent to the other side of the second signal pad 22a in the first direction X.

[0075] In the embodiment, the first leading-out wire segment 312 and the second connection wire segment 321 are configured as a passive crosstalk suppression structure capable of forming a reverse mutual inductance. In other words, the first conductor part is formed by the first leading-out wire segment 312, and the second conductor part is formed by the second connection wire segment 321. In a specific implementation, the signal pad group 2a of the circuit board 1 can be an interface pad for connector-on-board assembly. The embodiments of the present application are not limited thereto.

[0076] Other configurations and connection manners can be the same as those of the foregoing embodiments, and thus will not be described herein.

[0077] The foregoing Figure 8 The described circuit board signal pad can also lead out signals through a via. Please refer to Figure 9 , which is a schematic diagram of another circuit board provided by an embodiment of the present application. In order to clearly show the differences and connections between the Figure 8 described embodiments, the configurations and structures with the same functions are shown in the figure by Figure 1 .

[0078] As Figure 9 shown, the Figure 8In the described embodiment, the difference of the present embodiment is that the signal trace group 3 is an inner layer signal trace of the circuit board 1, and the first signal pad 21a and the second signal pad 22a of the signal pad group 2a are both electrically connected with the corresponding signal trace through the signal via 24. The ground pad 23 is electrically connected with the reference ground layer (not shown in the figure) through the ground via 25.

[0079] Similarly, the first lead-out trace segment 312 and the second connection trace segment 321 are constructed as a passive crosstalk suppression structure capable of forming a reverse mutual inductance. Other configurations and connections can be the same as those of the described embodiment. Here, no further description is given. Figure 8 The described embodiment is the same. Here, no further description is given.

[0080] For the circuit board with limited layout space of the horizontal trace layer, a passive crosstalk suppression structure can also be constructed based on a high-density interconnector (HDI) process using the layoutable layer inside the board. Please refer to Figure 10 , which is a schematic diagram of a crosstalk suppression structure constructed based on an HDI process according to an embodiment of the present application. In order to clearly show the structural configuration relationship of the crosstalk suppression structure, only a group of signal via groups inside the circuit board is shown in the figure.

[0081] As shown in Figure 10 , the first signal path P1 and the second signal path P2 can transmit signals in the same direction, and the main structure of the first signal path P1 and the second signal path P2 is a via, which can realize the interconnection between the top layer and the bottom layer of the circuit board. The first signal path P1 includes a first top via segment 11b, a first middle layer trace segment 12b, and a first bottom via segment 13b connected in sequence, and the second signal path P2 includes a second top via segment 21b, a second middle layer trace segment 22b, and a second bottom via segment 23b connected in sequence.

[0082] Among them, the first top via segment 11b and the second bottom via segment 23b can be oppositely arranged in the thickness direction of the board, and the second top via segment 21b and the first bottom via segment 13b can be oppositely arranged in the thickness direction of the board; in the middle trace layer of the circuit board, the first middle layer trace segment 12b is arranged to extend from the first top via segment 11b towards the first bottom via segment 13b, and the second middle layer trace segment 22b is arranged to extend from the second top via segment 21b towards the second bottom via segment 23b, both of which can be constructed as a crosstalk suppression structure capable of forming a reverse mutual inductance; in other words, the first conductor part is formed by the first middle layer trace segment 12b, and the second conductor part is formed by the second middle layer trace segment 22b. On the basis of reducing the total link crosstalk, the layout density of the two sides of the circuit board is not affected.

[0083] Here, in the plate thickness direction, the first top via segment 11b and the second bottom via segment 23b arranged oppositely, and the second top via segment 21b and the first bottom via segment 13b arranged oppositely, include the case that the corresponding via segments are completely aligned, and also include the case that the corresponding via segments are partially aligned. The embodiments of the present application are not limited.

[0084] Based on the characteristics of the HDI process, the first signal path P1 and the second signal path P2 exchange the opening positions in the middle layer of the circuit board, and construct the crosstalk suppression structure capable of forming mutual inductance through the traces located in the middle layer. In specific implementation, the circuit board can be one-order, two-order, three-order, four-order, five-order, etc. HDI, which can be configured according to the overall design requirements of the product, that is, the first middle layer trace segment and the second middle layer trace segment for constructing the crosstalk suppression structure can be arranged in the middle wiring layer between any two adjacent orders. The embodiments of the present application are not limited.

[0085] In order to obtain better crosstalk suppression effect, in specific implementation, the crosstalk suppression structure can also be arranged between the traces and the vias in the signal transmission link. Please refer to Figure 11 , which is a schematic diagram of another crosstalk suppression structure constructed based on the HDI process according to an embodiment of the present application. In order to clearly show the difference and connection between the embodiment and the Figure 10 described embodiment, the same function and structure are shown in the figure with Figure 1 .

[0086] Compared with the embodiment described in Figure 10 , the present embodiment further includes a signal trace group, which includes the first signal trace 14b and the second signal trace 24b. As shown in Figure 11 , the first signal path P1 includes the first signal trace 14b, the first top via segment 11b, the first middle layer trace segment 12b and the first bottom via segment 13b connected in sequence, and the second signal path P2 includes the second signal trace 24b, the second top via segment 21b, the second middle layer trace segment 22b and the second bottom via segment 23b connected in sequence.

[0087] Among them, the first signal trace 14b and the second signal trace 24b are surface signal traces of the circuit board, the first signal trace 14b is electrically connected with the first top via segment 11b through the first connection trace segment 141b, the second signal trace 24b is electrically connected with the second top via segment 21b through the second connection trace segment 241b, and the first connection trace segment 141b and the second connection trace segment 241b are constructed as the crosstalk suppression structure capable of forming mutual inductance. In specific implementation, the first signal trace 14b and the second signal trace 24b as the signal trace group can use the Figure 2 , Figures 4 to 7The crosstalk suppression structure is constructed in the form described in the foregoing embodiment.

[0088] Meanwhile, in the intermediate wiring layer, the first intermediate layer wiring segment 12b and the second intermediate layer wiring segment 22b are constructed into a crosstalk suppression structure capable of forming a mutual inductance. Overall, based on the crosstalk suppression structure between the signal wiring groups and the crosstalk suppression structure between the vias, the mutual inductance formed is cooperatively adjusted in value to further improve the crosstalk suppression effect of the entire link. Specifically, the arrangement position of the reverse suppression structure can be flexibly determined as needed in different crosstalk scenarios. The embodiments of the present application are not limited.

[0089] The circuit board 1 described in the foregoing embodiments can be widely applied to electronic devices in different application scenarios. Please refer to Figure 12 , which is a schematic diagram of an electronic device provided by an embodiment of the present application.

[0090] As Figure 12 shown, the electronic device 100 includes a housing 50 and the aforementioned circuit board 1 disposed in the housing 50. Based on the circuit board, it is beneficial to improve the crosstalk noise when signals are transmitted at high speed and to improve the crosstalk suppression effect of the entire link. In a specific implementation, the circuit board can be a chip packaging substrate, a carrier plate or a carrier-like plate used to realize electrical connection between electronic components, etc. The embodiments of the present application are not limited.

[0091] It should be understood that other functional components of the electronic device can be implemented using existing technologies, and therefore will not be described herein.

[0092] In addition, the ordinal numbers "first" and "second" used herein are only used to describe the same function or structure in the technical solutions. It can be understood that the use of the ordinal numbers does not limit the technical solutions claimed by the present application in terms of understanding.

[0093] The above is only a preferred embodiment of the present application, and it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A circuit board, characterized in that, The circuit board includes a signal vertical interconnect structure group and a signal trace group. The signal vertical interconnect structure group includes two signal vertical interconnect structures, and the signal trace group includes two signal traces. The two vertical interconnect structures of the signal vertical interconnect structure group are electrically connected to the two signal traces of the signal trace group, respectively, to form a first signal path and a second signal path that can transmit signals in the same direction; the first conductor portion on the first signal path is arranged adjacent to the second conductor portion on the second transmission path, the signal transmission directions on the first conductor portion and the second conductor portion are opposite, and a crosstalk suppression structure is constructed.

2. The circuit board according to claim 1, characterized in that, The signal vertical interconnect structure group includes a first vertical interconnect structure and a second vertical interconnect structure. The signal trace group includes a first signal trace and a second signal trace. The first signal trace includes a first connecting trace segment and a first lead-out trace segment connected together. The first connecting trace segment is electrically connected to the first vertical interconnect structure. The second signal trace includes a second connecting trace segment and a second lead-out trace segment connected together. The second connecting trace segment is electrically connected to the second vertical interconnect structure. The first conductor portion is formed by the first connecting trace segment, or by the first lead-out trace segment; The second conductor portion is formed by the second connecting trace segment or by the second lead-out trace segment.

3. The circuit board according to claim 2, characterized in that, The signal trace group is either a surface layer signal trace or an inner layer signal trace.

4. The circuit board according to claim 1, characterized in that, The signal vertical interconnect structure group is a signal via group, which includes a first signal via and a second signal via, and the first signal via and the second signal via are spaced apart in a first direction; the signal trace group includes a first signal trace and a second signal trace, the first signal trace includes a first connecting trace segment and a first lead-out trace segment connected together, the first connecting trace segment being electrically connected to the first signal via, and the second signal trace includes a second connecting trace segment and a second lead-out trace segment connected together, the second connecting trace segment being electrically connected to the second signal via.

5. The circuit board according to claim 4, characterized in that, The first connection trace segment and the second connection trace segment are located between the first signal via and the second signal via. The first connection trace segment extends from the first signal via toward the second signal via, and the second connection trace segment extends from the second signal via toward the first signal via. The first conductor portion is formed by the first connection trace segment, and the second conductor portion is formed by the second connection trace segment.

6. The circuit board according to claim 5, characterized in that, In the second direction, the first lead-out trace extends toward one side of the circuit board, and the second lead-out trace extends toward the other side of the circuit board.

7. The circuit board according to claim 5, characterized in that, In the second direction, the first lead-out trace extends toward one side of the circuit board; the second lead-out trace wraps around the first signal via and extends toward the same side in the second direction as the first lead-out trace.

8. The circuit board according to claim 4, characterized in that, The first connecting trace segment and the second connecting trace segment are located on one side of the first signal via and the second signal via in the second direction. The first lead-out trace segment is located on the side of the second signal via away from the first signal via. The second lead-out trace segment is located between the first signal via and the second signal via. The first lead-out trace segment and the second lead-out trace segment extend toward the other side of the first signal via and the second signal via in the second direction. The first conductor portion is formed by the first connecting trace segment, and the second conductor portion is formed by the second connecting trace segment.

9. The circuit board according to claim 4, characterized in that, In the second direction, the first connecting trace segment extends from the first signal via to one side, the first signal trace bends and extends to the other side in the second direction to form the first lead-out trace segment, and the first lead-out trace segment is located between the first signal via and the second signal via; in the second direction, the second connecting trace segment extends from the second signal via to one side, the second signal trace bends and extends to the other side in the second direction to form the second lead-out trace segment, and the second lead-out trace segment is located on the side of the second signal via away from the first signal via; the first conductor portion is formed by the first lead-out trace segment, and the second conductor portion is formed by the second connecting trace segment.

10. The circuit board according to any one of claims 4 to 9, characterized in that, The signal via group can be a blind via, a buried via, or a through via.

11. The circuit board according to any one of claims 2 to 9, characterized in that, A slot is formed on the dielectric layer between the wiring layer and the reference layer where the first conductor portion and the second conductor portion are located. The slot is disposed opposite to the first conductor portion and the second conductor portion in the thickness direction of the circuit board.

12. The circuit board according to any one of claims 4 to 10, characterized in that, The circuit board is a high-density interconnect circuit board. The first signal via includes a first top via segment, a first intermediate layer trace segment, and a first bottom via segment connected in sequence, with the first top via segment and the first bottom via segment being staggered. The second signal via includes a second top via segment, a second intermediate layer trace segment, and a second bottom via segment connected in sequence, with the second top via segment and the second bottom via segment being staggered. Within the intermediate trace layer of the circuit board, the first intermediate layer trace extends from the first top via segment toward the first bottom via segment, and the second intermediate layer trace extends from the second top via segment toward the second bottom via segment. The first conductor portion is formed by the first intermediate layer trace segment, and the second conductor portion is formed by the second intermediate layer trace segment.

13. The circuit board according to claim 12, characterized in that, The first top via section and the second bottom via section are arranged opposite to each other in the plate thickness direction.

14. The circuit board according to claim 1, characterized in that, The signal vertical interconnect structure group is a signal pad group, which includes a first signal pad and a second signal pad. The signal trace group includes a first signal trace and a second signal trace. The first signal trace includes a first connecting trace segment and a first lead-out trace segment connected to each other. The first connecting trace segment is electrically connected to the first signal pad. The second signal trace includes a second connecting trace segment and a second lead-out trace segment connected to each other. The second connecting trace segment is electrically connected to the second signal pad.

15. The circuit board according to claim 14, characterized in that, The signal trace group is a surface layer signal trace, or the signal trace group is an inner layer signal trace. The first connection trace segment is electrically connected to the first signal pad through a via, and the second connection trace segment is electrically connected to the second signal pad through a via.

16. The circuit board according to claim 14 or 15, characterized in that, The first signal pad and the second signal pad of the signal pad group are arranged in a pad array. The first signal pad and the second signal pad are located in two adjacent rows of the pad array in the second direction and are staggered in the first direction. The first connecting trace segment bends from the first signal pad toward the second signal pad, and the first lead-out trace segment extends in the second direction; the first lead-out trace segment is located on one side of the second signal pad in the first direction, the second connecting trace segment extends from the second signal pad toward the first signal pad, the second lead-out trace segment bends and extends in the second direction, and the second lead-out trace segment is located on the other side of the second signal pad in the first direction; the first conductor portion is formed by the first lead-out trace segment, and the second conductor portion is formed by the second connecting trace segment.

17. An electronic device, characterized in that, The electronic device includes a housing and a circuit board disposed within the housing, the circuit board being any one of claims 1 to 16.

18. The circuit board according to claim 17, characterized in that, The circuit board is a chip packaging substrate, a carrier board or carrier-like board used for electrical connections between electronic components.

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