Semiconductor device

Abstract

A semiconductor device includes: a cell vertical active pattern and a peripheral vertical active pattern at the same vertical height; an on-cell extension source / drain pattern and a cell contact plug sequentially stacked on the cell vertical active pattern; a peripheral upper extension source / drain pattern and a peripheral contact plug sequentially stacked on the peripheral vertical active pattern; a cell isolation pattern on a side surface of the on-cell extension source / drain pattern and a side surface of the cell contact plug; a peripheral isolation pattern on a side surface of the peripheral upper extended source / drain pattern and a side surface of the peripheral contact plug; and an upper interconnect on the peripheral contact plug and the peripheral isolation pattern. A first distance between a vertical height of an upper end of the cell contact plug and a vertical height of an upper end of the cell isolation pattern is different from a second distance between a vertical height of an upper end of the peripheral contact plug and a vertical height of an upper end of the peripheral isolation pattern.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] There have been ongoing researches to reduce the size of elements included in semiconductor devices and to improve their performance. For example, in DRAMs, researches to reliably and stably form a size-reduced component have been conducted, but as the size of the component is reduced, the dispersion properties of the semiconductor device deteriorate. SUMMARY

[0003] Aspects of the inventive concept provide a semiconductor device having increased integration density and improved performance.

[0004] Aspects of the inventive concept provide a method of manufacturing a semiconductor device.

[0005] According to example embodiments of the present disclosure, a semiconductor device includes: a cell vertical active pattern and a peripheral vertical active pattern disposed at a same vertical height; a cell upper extension source / drain pattern and a cell contact plug sequentially stacked on the cell vertical active pattern; a peripheral upper extension source / drain pattern and a peripheral contact plug sequentially stacked on the peripheral vertical active pattern; a cell isolation pattern on side surfaces of the cell upper extension source / drain pattern and the cell contact plug; a peripheral isolation pattern on side surfaces of the peripheral upper extension source / drain pattern and the peripheral contact plug; and an upper interconnect on the peripheral contact plug and the peripheral isolation pattern, wherein a first distance between a vertical height of an upper end of the cell contact plug and a vertical height of an upper end of the cell isolation pattern is different from a second distance between a vertical height of an upper end of the peripheral contact plug and a vertical height of an upper end of the peripheral isolation pattern.

[0006] According to an example embodiment of this disclosure, a semiconductor device includes: a cell vertical active pattern and a peripheral vertical active pattern, the cell vertical active pattern and the peripheral vertical active pattern being disposed at the same vertical height; cell-extended source / drain patterns and cell contact plugs, the cell-extended source / drain patterns and the cell contact plugs being sequentially stacked on the cell vertical active pattern; peripheral extended source / drain patterns and peripheral contact plugs, the peripheral extended source / drain patterns and peripheral contact plugs being sequentially stacked on the peripheral vertical active pattern; a cell isolation pattern, the cell isolation pattern being located on the side surface of the cell-extended source / drain pattern and the side surface of the cell contact plug; and a peripheral isolation pattern, the... The peripheral isolation pattern is located on the side surface of the extended source / drain pattern and the side surface of the peripheral contact plug; and the upper interconnect is located on the peripheral contact plug and the peripheral isolation pattern, wherein the cell contact plug includes a cell lower conductive layer and a cell upper conductive layer stacked sequentially, wherein the peripheral contact plug includes a peripheral lower conductive layer and a peripheral upper conductive layer stacked sequentially, wherein the cell lower conductive layer and the peripheral lower conductive layer include a first conductive material, wherein the cell upper conductive layer and the peripheral upper conductive layer include a second conductive material different from the first conductive material, and wherein the upper interconnect includes a third conductive material different from both the first and second conductive materials.

[0007] According to an example embodiment of this disclosure, a semiconductor device includes: a first structure including a storage region and a peripheral region; and a second structure perpendicularly overlapping the first structure and including peripheral circuitry, wherein the storage region includes: a cell vertical active pattern; a cell gate electrode having a side surface facing a side surface of the cell vertical active pattern; a cell source / drain pattern and a cell contact plug, the cell source / drain pattern and the cell contact plug being disposed on the cell vertical active pattern, the cell source / drain pattern being located on the cell vertical active pattern. Between the cell contact plug and the cell isolation pattern; a cell isolation pattern located on the side surface of the cell source / drain pattern and the side surface of the cell contact plug; and a data storage structure located on the cell contact plug and the cell isolation pattern, wherein the peripheral region includes: a peripheral vertical active pattern; a peripheral gate electrode having a side surface facing the side surface of the peripheral vertical active pattern; a peripheral source / drain pattern and a peripheral contact plug disposed on the peripheral vertical active pattern, the peripheral region... The upper source / drain pattern is located between the peripheral vertical active pattern and the peripheral contact plug; a peripheral isolation pattern is located on the side surface of the peripheral upper source / drain pattern and the side surface of the peripheral contact plug; and an upper interconnect is located on the peripheral contact plug and the peripheral isolation pattern, wherein the cell upper source / drain pattern includes a first cell source / drain layer and a second cell source / drain layer stacked sequentially, wherein the peripheral upper source / drain pattern includes a first peripheral source / drain layer and a second peripheral source / drain layer stacked sequentially, wherein the peripheral circuitry includes... The storage region comprises a first lower transistor and a second lower transistor that are vertically overlapped with the peripheral region. The cell contact plug includes a cell lower conductive layer and a cell upper conductive layer that are sequentially stacked. The peripheral contact plug includes a peripheral lower conductive layer and a peripheral upper conductive layer that are sequentially stacked. The cell lower conductive layer and the peripheral lower conductive layer include a first conductive material. The cell upper conductive layer and the peripheral upper conductive layer include a second conductive material different from the first conductive material. The upper interconnect includes a third conductive material different from the first conductive material and the second conductive material. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 2 This is a circuit diagram illustrating the memory region of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 6 This is a diagram illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 7 This is an enlarged view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 8 This is an enlarged view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 9 This is an enlarged view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 10 This is an enlarged view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 11 , Figure 12A and Figure 12B This is a diagram illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 13A This is a cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 13B This is a cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 13C This is a cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 13D This is a cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 13E This is a cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment of the present disclosure; Figures 14 to 23 This is a cross-sectional view illustrating a method for forming a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0009] In the following description, terms such as “upper,” “middle,” and “lower” may be replaced with other terms, such as “first,” “second,” and “third,” to describe the elements of the specification. Terms such as “first,” “second,” and “third” may be used to describe different elements, but these elements are not limited by these terms, and a “first element” may be referred to as a “second element.” In the specification, terms such as “lower,” “upper,” “upper end,” and “lower end” may be terms described with reference to the accompanying drawings.

[0010] An item, layer, or part of an item or layer is described as extending "longitudinally" in a particular direction, having a length in that particular direction and a width perpendicular to that direction, wherein the length is greater than the width.

[0011] It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected to or coupled to or directly on the other element, or there may be intermediate elements present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to or “in contact with” another element (or “in contact with” another element in any form), there are no intermediate elements at the point of contact.

[0012] Throughout this specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that, unless the context otherwise indicates, the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component. On the other hand, the term "composed of" indicates that the component is formed solely by the listed elements.

[0013] According to Figure 1 The example embodiments described herein are semiconductor devices. Figure 1 This is a perspective view showing a semiconductor device according to an example embodiment.

[0014] refer to Figure 1 According to an example embodiment, the semiconductor device 1 may include a first structure ST1 and a second structure ST2 perpendicularly overlapping the first structure ST1. The second structure ST2 may be disposed below the first structure ST1. In an example embodiment, the second structure ST2 may be disposed on the first structure ST1. In an example embodiment, the first structure ST1 may include a memory region (…). Figure 2 , Figure 3 and Figure 4 CR in the middle) and the outer region ( Figure 3 and Figure 4 The first chip structure ST1 (PR) can be a first chip structure, while the second chip structure ST2 can be a second chip structure including peripheral circuitry. The first structure ST1 and the second structure ST2 can be bonded to each other by a bonding process such as a wafer bonding process. Therefore, the first structure ST1 can contact and be bonded to the second structure ST2.

[0015] Semiconductor device 1 may include multiple memory cells BA and an external peripheral region PERI. The external peripheral region PERI may include a first peripheral region PERI1 in the first structure ST1 and a second peripheral region PERI2 in the second structure ST2. The external peripheral region PERI may be a peripheral region in which peripheral circuitry for inputting and outputting data or commands, or inputting power / ground, is provided. Each of the multiple memory cells BA may include a first memory cell region BA1 in the first structure ST1 and a second memory cell region BA2 in the second structure ST2. The first memory cell region BA1 in the first structure ST1 may include a memory cell MC (such as...). Figure 2 (As shown). The second memory region BA2 in the second structure ST2 may include peripheral circuitry such as a sense amplifier and a sub-word line driver.

[0016] In the following description, reference will be made to Figure 2 The circuit describes the memory region CR of the first structure ST1. Figure 2 This is a circuit diagram illustrating the storage region of a semiconductor device according to an example embodiment.

[0017] refer to Figure 2 The memory region CR may include memory cells MC. The memory region CR may include memory cells MC arranged in a grid pattern in a first direction X and a second direction Y, word lines WL connected to the memory cells MC and extending in the first direction X, and bit lines BL connected to the memory cells MC and extending in the second direction Y. The first direction X and the second direction Y may be perpendicular to each other. The word lines WL may intersect the memory region CR by extending in the first direction X. The bit lines BL may intersect the memory region CR by extending in the second direction Y. Each memory cell MC may include a data storage structure DS that functions as data storage and a cell transistor cTR electrically connected to the data storage structure DS. In a memory such as DRAM, the data storage structure DS may be a cell capacitor capable of storing information. The memory region CR may also include back gate lines BG. Each back gate line BG may be disposed between a pair of word lines WL that are adjacent to each other in the second direction Y. Each back gate line BG may be disposed between vertical channel regions of the cell transistor cTR.

[0018] Reference Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 6 as well as Figure 1 and Figure 2 An example is described for the first portion ST1_A of the first structure ST1 of a semiconductor device according to an example embodiment. Figure 3 , Figure 4 ,Figure 5A , Figure 5B and Figure 6 middle, Figure 3 This is a top view showing a semiconductor device according to an example embodiment. Figure 4 It shows along Figure 3 A cross-sectional view of the region intercepted by line I-I' in the diagram. Figure 5A It is shown by Figure 4 Enlarged cross-sectional views of the areas indicated by "A" and "B" in the diagram. Figure 5B It is shown by Figure 4 Enlarged cross-sectional view of the areas indicated by "C" and "D" in the diagram.

[0019] refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 6 The first structure ST1 of the semiconductor device 1 may include a storage region CR and a peripheral region PR. Hereinafter, the storage region CR and the peripheral region PR in the first portion ST1_A of the first structure ST1 of the semiconductor device 1 will be described.

[0020] The storage region CR may include a cell vertical active pattern 21c, a cell gate electrode 27c, an extended source / drain pattern 35c on the cell, a cell contact plug 57c, and a cell isolation pattern 52a. The peripheral region PR may include a first peripheral vertical active pattern 21n, a first peripheral gate electrode 27n, a first peripheral extended source / drain pattern 35n, a first peripheral contact plug 57n, and a first peripheral isolation pattern 52c. The peripheral region PR may also include a second peripheral vertical active pattern 21p, a second peripheral gate electrode 27p, a second peripheral extended source / drain pattern 35p, a second peripheral contact plug 57p, and a second peripheral isolation pattern 52b.

[0021] Each cell vertical active pattern 21c may include a cell lower source / drain region 21c_L, a cell vertical channel region 21c_CH located on the cell lower source / drain region 21c_L, and a cell upper source / drain region 21c_U located on the cell vertical channel region 21c_CH. Each first peripheral vertical active pattern 21n may include a first peripheral lower source / drain region 21n_L, a first peripheral vertical channel region 21n_CH located on the first peripheral lower source / drain region 21n_L, and a first peripheral upper source / drain region 21n_U located on the first peripheral vertical channel region 21n_CH. Each second peripheral vertical active pattern 21p may include a second peripheral lower source / drain region 21p_L, a second peripheral vertical channel region 21p_CH located on the second peripheral lower source / drain region 21p_L, and a second peripheral upper source / drain region 21p_U located on the second peripheral vertical channel region 21p_CH.

[0022] Unit gate electrode 27c can be a reference Figure 2 The word line WL is described. The cell gate electrode 27c may have a side surface facing the side surface of the cell perpendicular active pattern 21c. The first peripheral gate electrode 27n may have a side surface facing the side surface of the first peripheral perpendicular active pattern 21n. The second peripheral gate electrode 27p may have a side surface facing the side surface of the second peripheral perpendicular active pattern 21p.

[0023] Each extended source / drain pattern 35c on a cell may include sequentially stacked lower source / drain layers 36c and upper source / drain layers 42c. The vertically extending side surfaces of the lower source / drain layer 36c and the upper source / drain layer 42c may be aligned. Each extended source / drain pattern 35n on a first periphery may include sequentially stacked lower source / drain layers 36n and upper source / drain layers 42n on a first periphery. The vertically extending side surfaces of the lower source / drain layer 36n and the upper source / drain layer 42n on a first periphery may be aligned. Each extended source / drain pattern 35p on a second periphery may include sequentially stacked lower source / drain layers 36p and upper source / drain layers 48p on a second periphery. The vertically extending side surface of the second peripheral lower source / drain layer 36p and the vertically extending side surface of the second peripheral upper source / drain layer 48p can be aligned.

[0024] The extended source / drain pattern 35c on the cell can have N-type conductivity. The extended source / drain pattern 35n on the first periphery can have N-type conductivity. The extended source / drain pattern 35p on the second periphery can have P-type conductivity.

[0025] The impurity concentration in the upper source / drain layer 42c of the cell can be higher than the impurity concentration in the lower source / drain layer 36c of the cell. The impurity concentration in the lower source / drain layer 36c of the cell can be higher than the impurity concentration in the upper source / drain region 21c_U of the cell. The impurity concentration in the first peripheral upper source / drain layer 42n can be higher than the impurity concentration in the first peripheral lower source / drain layer 36n. The impurity concentration in the first peripheral lower source / drain layer 36n can be higher than the impurity concentration in the first peripheral upper source / drain region 21n_U. The impurity concentration in the second peripheral upper source / drain layer 48p can be higher than the impurity concentration in the second peripheral lower source / drain layer 36p. The impurity concentration in the second peripheral lower source / drain layer 36p can be higher than the impurity concentration in the second peripheral upper source / drain region 21p_U.

[0026] The vertical active patterns 21c, 21n, and 21p can be set at substantially the same vertical height. The upper extended source / drain patterns 35c, 35n, and 35p can be set at substantially the same vertical height. The upper extended source / drain patterns 35c, 35n, and 35p can overlap vertically with the vertical active patterns 21c, 21n, and 21p, respectively, and can contact the vertical active patterns 21c, 21n, and 21p, respectively. The width of each of the upper extended source / drain patterns 35c, 35n, and 35p in the first horizontal direction X can be greater than the width of each of the vertical active patterns 21c, 21n, and 21p in the first horizontal direction X. The storage region CR and the peripheral region PR may also include a dummy source / drain pattern 35D set at the same vertical height as the upper extended source / drain patterns 35c, 35n, and 35p. The dummy source / drain pattern 35D can be formed of the same material as the extended source / drain patterns 35c, 35n, and 35p, and can have the same structure as the extended source / drain patterns 35c, 35n, and 35p. The dummy source / drain pattern 35D can be spaced apart from the vertical active patterns 21c, 21n, and 21p.

[0027] Cell contact plugs 57c can be disposed on cell-extended source / drain patterns 35c. Each cell contact plug 57c may include a cell lower conductive layer 53c in contact with the upper surface of the cell-extended source / drain layer 42c and a cell upper conductive layer 56c located on the cell lower conductive layer 53c. The cell lower conductive layer 53c and cell upper conductive layer 56c can be sequentially stacked. The sequentially stacked cell lower conductive layer 53c and cell upper conductive layer 56c can have vertically extending side surfaces that are coplanar with each other. The sequentially stacked cell-extended source / drain patterns 35c and cell contact plugs 57c can have vertically extending side surfaces that are aligned with each other. The sequentially stacked cell-extended source / drain patterns 35c and cell contact plugs 57c can have vertically extending side surfaces that are coplanar with each other.

[0028] First peripheral upper contact plugs 57n may be disposed on first peripheral extended source / drain patterns 35n. Each first peripheral upper contact plug 57n may include a first peripheral lower conductive layer 53n in contact with the upper surface of the first peripheral upper source / drain layer 42n and a first peripheral upper conductive layer 56n located on the first peripheral lower conductive layer 53n. The first peripheral lower conductive layer 53n and the first peripheral upper conductive layer 56n may be sequentially stacked. The sequentially stacked first peripheral lower conductive layer 53n and the first peripheral upper conductive layer 56n may have vertically extending side surfaces that are coplanar with each other. The sequentially stacked first peripheral extended source / drain patterns 35n and the first peripheral upper contact plugs 57n may have vertically extending side surfaces that are aligned with each other. The sequentially stacked first peripheral extended source / drain patterns 35n and the first peripheral upper contact plugs 57n may have vertically extending side surfaces that are coplanar with each other.

[0029] Second peripheral upper contact plugs 57p may be disposed on the second peripheral extended source / drain pattern 35p. Each second peripheral upper contact plug 57p may include a second peripheral lower conductive layer 53p in contact with the upper surface of the second peripheral upper source / drain layer 48p and a second peripheral upper conductive layer 56p located on the second peripheral lower conductive layer 53p. The sequentially stacked second peripheral lower conductive layer 53p and second peripheral upper conductive layer 56p may have vertically extending side surfaces that are coplanar with each other. The sequentially stacked second peripheral extended source / drain pattern 35p and second peripheral upper contact plug 57p may have vertically extending side surfaces that are aligned with each other. The sequentially stacked second peripheral extended source / drain pattern 35p and second peripheral contact plug 57p may have vertically extending side surfaces that are coplanar with each other.

[0030] Contact plugs 57c, 57n, and 57p can be aligned and contacted with the extended source / drain patterns 35c, 35n, and 35p. The storage region CR and the peripheral region PR may also include a dummy contact plug 57D aligned and contacted with the dummy source / drain pattern 35D. The dummy contact plug 57D may be positioned at the same height as contact plugs 57c, 57n, and 57p, may be formed of the same material as contact plugs 57c, 57n, and 57p, and may have the same structure as contact plugs 57c, 57n, and 57p.

[0031] Cell isolation pattern 52a may define vertically extending side surfaces of sequentially stacked cells extending source / drain patterns 35c and cell contact plugs 57c. First peripheral isolation pattern 52c may define vertically extending side surfaces of sequentially stacked first peripheral extended source / drain patterns 35n and first peripheral contact plugs 57n. Second peripheral isolation pattern 52b may define vertically extending side surfaces of sequentially stacked second peripheral extended source / drain patterns 35p and second peripheral contact plugs 57p. Cell isolation pattern 52a may surround the side surfaces of sequentially stacked cell extended source / drain patterns 35c and cell contact plugs 57c, first peripheral isolation pattern 52c may surround the side surfaces of sequentially stacked first peripheral extended source / drain patterns 35n and first peripheral contact plugs 57n, and second peripheral isolation pattern 52b may surround the side surfaces of sequentially stacked second peripheral extended source / drain patterns 35p and second peripheral contact plugs 57p. The unit isolation pattern 52a, the first peripheral isolation pattern 52c, and the second peripheral isolation pattern 52b can be disposed at the same vertical height and can include the same insulating material. For example, the unit isolation pattern 52a, the first peripheral isolation pattern 52c, and the second peripheral isolation pattern 52b can include insulating materials of silicon nitride or silicon oxide.

[0032] In the example, the difference (e.g., distance) between the height of the upper end of the cell contact plug 57c and the height of the upper end of the cell isolation pattern 52a may be different from the difference (e.g., distance) between the height of the upper end of the first peripheral contact plug 57n and the height of the upper end of the first peripheral isolation pattern 52c.

[0033] In the example, the difference between the height of the highest point of the upper end of the unit contact plug 57c and the height of the highest point of the upper end of the unit isolation pattern 52a can be greater than the difference between the height of the highest point of the upper end of the first peripheral contact plug 57n and the height of the highest point of the upper end of the first peripheral isolation pattern 52c.

[0034] In the example, the highest point of the upper surface of the cell contact plug 57c can be set at a height lower than the highest point of the upper surface of the cell isolation pattern 52a.

[0035] In the example, the lower conductive layer 53c, the first peripheral lower conductive layer 53n, and the second peripheral lower conductive layer 53p can be set at the same vertical height and can have the same thickness.

[0036] In the example, the thickness of the conductive layer 56c on the cell may be different from the thickness of each of the first peripheral conductive layer 56n and the second peripheral conductive layer 56p.

[0037] For example, the thickness of the conductive layer 56c on the unit may be less than the thickness of each of the first peripheral conductive layer 56n and the second peripheral conductive layer 56p. For example, the thickness of the conductive layer 56c on the unit may vary along a first horizontal direction. For example, the minimum thickness of the conductive layer 56c on the unit may be less than the thickness of each of the first peripheral conductive layer 56n and the second peripheral conductive layer 56p.

[0038] In the example, the first peripheral conductive layer 56n and the second peripheral conductive layer 56p may have upper surfaces disposed at the same vertical height.

[0039] In the example, the lowest point of the upper surface of the conductive layer 56c on the cell can be set at a vertical height different from the vertical height of the upper surface of the conductive layer 56n on the first periphery.

[0040] In the example, the lowest point of the upper surface of the conductive layer 56c on the cell can be set at a height lower than the height of the upper surface of the first peripheral conductive layer 56n.

[0041] In the example, the upper surface of the conductive layer 56c on the cell may have a concave shape, and the first peripheral conductive layer 56n and the second peripheral conductive layer 56p may have substantially flat upper surfaces. For example, the end of the upper surface of the conductive layer 56c on the cell in the first horizontal direction X may be at a vertical height higher than the center of the upper surface of the conductive layer 56c on the first horizontal direction X.

[0042] In the example, the highest point at the top of the unit isolation pattern 52a, the highest point at the top of the first peripheral isolation pattern 52c, and the highest point at the top of the second peripheral isolation pattern 52b can be set at the same vertical height.

[0043] In the example, the upper surface of the unit isolation pattern 52a may have a convex shape. For example, the end of the upper surface of the unit isolation pattern 52a in the first horizontal direction X may be at a vertical height lower than the center of the upper surface of the unit isolation pattern 52a in the first horizontal direction X.

[0044] In an embodiment, the upper surface of the conductive layer 56c on the unit can be the upper surface of the unit contact plug 57c, the upper surface of the first peripheral conductive layer 56n can be the upper surface of the first peripheral contact plug 57n, and the upper surface of the second peripheral conductive layer 56p can be the upper surface of the second peripheral contact plug 57p.

[0045] The peripheral area PR may also include conductive patterns 63a, 63n and 63p set at the same vertical height and made of the same material.

[0046] The conductive patterns 63a, 63n and 63p may include pad pattern 63a, a first upper interconnect 63n and a second upper interconnect 63p.

[0047] The first upper interconnect 63n can be connected to the first peripheral upper contact plug 57n. The second upper interconnect 63p can be connected to the second peripheral contact plug 57p. The pad pattern 63a may not overlap perpendicularly with either the first peripheral upper contact plug 57n or the second peripheral upper contact plug 57p.

[0048] In the example, the lower conductive layer 53c, the first peripheral lower conductive layer 53n, and the second peripheral lower conductive layer 53p may include a first conductive material. The upper conductive layer 56c, the first peripheral upper conductive layer 56n, and the second peripheral upper conductive layer 56p may include a second conductive material different from the first conductive material.

[0049] In the example, the first conductive material may include a metal semiconductor compound layer, while the second conductive material may include a metal nitride or a metal. For example, each of the lower conductive layer 53c, the first peripheral lower conductive layer 53n, and the second peripheral lower conductive layer 53p may include TiSi, TiSiN, TaSi, TaSiN, MoSi, NiSi, or CoSi. Each of the upper conductive layer 56c, the first peripheral upper conductive layer 56n, and the second peripheral upper conductive layer 56p may include at least one of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, and RuTiN.

[0050] In the example, each of the conductive patterns 63a, 63n, and 63p may include a third conductive material different from the first and second conductive materials. For example, each of the conductive patterns 63a, 63n, and 63p may include at least one of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, and RuTiN. The second and third conductive materials may include different materials among Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, and RuTiN.

[0051] In the example, each of the conductive patterns 63a, 63n, and 63p may include a second conductive material. For example, conductive patterns 63a, 63n, and 63p may include the same material as the conductive layer 56c on the cell, the first peripheral conductive layer 56n, and the second peripheral conductive layer 56p.

[0052] In the example, each of the conductive patterns 63a, 63n, and 63p may include a second conductive material that is the same as the conductive layer 56c on the cell, the first peripheral conductive layer 56n, and the second peripheral conductive layer 56p, and a third conductive material that is different from the second conductive material.

[0053] In the example, each of the conductive patterns 63a, 63n, and 63p may include a first upper conductive layer 59 and a second upper conductive layer 62 stacked sequentially. The first upper conductive layer 59 may include a material different from the material of the first peripheral upper conductive layer 56n and the material of the second peripheral conductive layer 56p.

[0054] In the example, the second upper conductive layer 62 may include a material that is different from the material of the first upper conductive layer 59 and the same as the material of the first peripheral upper conductive layer 56n and the second peripheral upper conductive layer 56p.

[0055] In the example, the second upper conductive layer 62 may include a material that is different from the material of the first upper conductive layer 59 and different from the material of the first peripheral upper conductive layer 56n and the material of the second peripheral conductive layer 56p.

[0056] The storage region CR and the peripheral region PR may also include an insulating pad 66. The insulating pad 66 may be disposed on the cell contact plug 57c, the cell isolation pattern 52a, and the upper conductive patterns 63a, 63n, and 63p. The insulating pad 66 may cover the upper surface of the cell contact plug 57c and the cell isolation pattern 52a in the storage region CR, and may cover the upper and side surfaces of the upper conductive patterns 63a, 63n, and 63p in the peripheral region PR. The insulating pad 66 may include an insulating material, such as SiN, SiBN, SiCN, or a high-k dielectric.

[0057] The storage area CR and the peripheral area PR may also include the data storage structure DS and the insulating layer 70.

[0058] The data storage structure DS may include a first electrode 68a connected to a cell contact plug 57c in the storage region CR, penetrating an insulating pad 66 and extending in the vertical direction Z, a second electrode 68c located on each of the side and top surfaces of the first electrode 68a, and a dielectric layer 68b located between the first electrode 68a and the second electrode 68c. The data storage structure DS may be a cell capacitor of a memory such as DRAM.

[0059] The insulating layer 70 may cover the data storage structure DS in the storage region CR and cover the insulating pad 66 in the peripheral region PR. The insulating layer 70 may include at least one of silicon oxide or a low-k dielectric.

[0060] The storage region CR and the peripheral region PR may also include lower source / drain patterns 78c, 78n and 78p connected below the vertical active patterns 21c, 21n and 21p, and lower interconnect patterns 83c, 83n and 83p aligned with the lower source / drain patterns 78c, 78n and 78p below the lower source / drain patterns 78c, 78n and 78p.

[0061] The lower source / drain patterns 78c, 78n, and 78p may include a lower source / drain pattern 78c connected to the cell vertical active pattern 21c, a first peripheral lower source / drain pattern 78n connected to the first peripheral vertical active pattern 21n, and a second peripheral lower source / drain pattern 78p connected to the first peripheral vertical active pattern 21p.

[0062] The lower interconnect patterns 83c, 83n, and 83p may include a bit line 83c aligned and contacting the cell lower source / drain pattern 78c, a first lower interconnect 83n aligned and contacting the first peripheral lower source / drain pattern 78n, and a second lower interconnect 83p aligned and contacting the second peripheral lower source / drain pattern 78p. Each of the lower interconnect patterns 83c, 83n, and 83p may include a first lower conductive layer 81 and a second lower conductive layer 82 disposed below the first lower conductive layer 81. The bit line 83c may be a reference... Figure 2 The bit line BL is described. The memory region CR may also include a cell gate dielectric layer 24c, a cell back gate electrode 16c, a cell back gate dielectric layer 14c, and insulating layers 18, 33, 30, and 75. The peripheral region PR may also include a first peripheral gate dielectric layer 24n, a first peripheral back gate electrode 16n, a first peripheral back gate dielectric layer 14n, a second peripheral gate dielectric layer 24p, a second peripheral back gate electrode 16p, a second peripheral back gate dielectric layer 14p, insulating layers 18, 33, 30, and 75, and insulating structures 54 and 56.

[0063] The unit back gate electrode 16c can be a reference. Figure 2 The back gate line BG is described. Each cell gate electrode 27c may extend in a second horizontal direction Y. The cell gate electrodes 27c may be spaced apart from each other in a first horizontal direction X perpendicular to the second horizontal direction Y. Each cell back gate electrode 16c may have a line shape extending in the second horizontal direction Y.

[0064] For each pair of adjacent unit back gate electrodes 16c, a pair of unit gate electrodes 27c may be provided between them (see example). Figure 4 In the plane, each cell vertical active pattern 21c may have a strip shape extending in the second horizontal direction Y. Each cell vertical active pattern 21c may be disposed between the cell back gate electrode 16c and the cell gate electrode 27c adjacent to the cell back gate electrode 16c.

[0065] Each first peripheral gate electrode 27n may extend in a second horizontal direction Y. Each first peripheral back gate electrode 16n may have a line shape extending in the second horizontal direction Y. Among the first peripheral gate electrodes 27n, a pair of first peripheral gate electrodes 27n adjacent to each other in the first horizontal direction X may be disposed between a pair of first peripheral back gate electrodes 16n adjacent to each other in the first horizontal direction X. In the plane, each first peripheral vertical active pattern 21n may have a strip shape extending in the second horizontal direction Y. Each first peripheral vertical active pattern 21n may be disposed between the first peripheral back gate electrode 16n and the first peripheral gate electrode 27n and the first peripheral gate electrode 27n adjacent to the first peripheral back gate electrode 16n.

[0066] Each second peripheral gate electrode 27p may extend in a second horizontal direction Y. Each second peripheral back gate electrode 16p may have a line shape extending in the second horizontal direction Y. Among the second peripheral gate electrodes 27p, a pair of second peripheral gate electrodes 27p adjacent to each other in the first horizontal direction X may be disposed between a pair of second peripheral back gate electrodes 16p adjacent to each other in the first horizontal direction X. In the plane, each second peripheral vertical active pattern 21p may have a strip shape extending in the second horizontal direction Y. Each second peripheral vertical active pattern 21p may be disposed between the second peripheral back gate electrode 16p and the second peripheral gate electrode 27p and the second peripheral gate electrode 27p adjacent to the second peripheral back gate electrode 16p.

[0067] A cell gate dielectric layer 24c can be disposed between the side surface of the cell vertical active pattern 21c and the side surface of the cell gate electrode 27c. The cell gate dielectric layer 24c can extend to cover the lower surface of the cell gate electrode 27c. The cell gates 24c and 27c, including the cell gate dielectric layer 24c and the cell gate electrode 27c, can face the side surface of the cell vertical channel region 21c_CH. A first peripheral gate dielectric layer 24n can be disposed between the side surface of the first peripheral vertical active pattern 21n and the side surface of the first peripheral gate electrode 27n. The first peripheral gates 24n and 27n, including the first peripheral gate dielectric layer 24n and the first peripheral gate electrode 27n, can face the side surface of the first peripheral vertical channel region 21n_CH. The first peripheral gate dielectric layer 24n can extend to cover the lower surface of the first peripheral gate electrode 27n. A second peripheral gate dielectric layer 24p can be disposed between the side surface of the second peripheral vertical active pattern 21p and the side surface of the second peripheral gate electrode 27p. The second peripheral gate dielectric layer 24p may extend to cover the lower surface of the second peripheral gate electrode 27p. The second peripheral gates 24p and 27p, including the second peripheral gate dielectric layer 24p and the second peripheral gate electrode 27p, may face the side surface of the second peripheral vertical channel region 21p_CH.

[0068] The cell back gate dielectric layer 14c can be disposed between the cell vertical active pattern 21c and the cell back gate electrode 16c. The first peripheral back gate dielectric layer 14n can be disposed between the first peripheral vertical active pattern 21n and the first peripheral back gate electrode 16n. The second peripheral back gate dielectric layer 14p can be disposed between the second peripheral vertical active pattern 21p and the second peripheral back gate electrode 16p.

[0069] Insulating layer 18 may be disposed below the lower surfaces of back gate electrodes 16c, 16n, and 16p. Insulating layer 75 may be disposed on the upper surfaces of back gate electrodes 16c, 16n, and 16p. Insulating layer 33 may be disposed on the upper surfaces of gate electrodes 27c, 27n, and 27p. Each insulating layer 30 may be disposed between adjacent gate electrodes among gate electrodes 27c, 27n, and 27p, and between adjacent insulating layers among insulating layers 33. Insulating layer 22 may be disposed between the lower surfaces of gate dielectric layers 24c, 24n, and 24p and the lower source / drain patterns 78c, 78n, and 78p.

[0070] Each insulating structure 54 and 56 may be disposed between adjacent groups of a set of unit isolation patterns 52a, a set of first peripheral isolation patterns 52c, and a set of second peripheral isolation patterns 52b. Each insulating structure 54 and 56 may include an insulating pattern 56 and an insulating pad 54 covering the side and bottom surfaces of the insulating pattern 56. The insulating pattern 56 may include oxides, while the insulating pad 54 may include nitrides. A pad pattern 63a may be disposed on the upper surface of the insulating structures 54 and 56.

[0071] The storage region CR may also include a bit line shielding structure 88, and the storage region CR and the peripheral region PR may also include insulating structures 85 and 86 and an insulating layer 90.

[0072] Insulating structures 85 and 86 may include insulating pattern 86 and insulating pad 85. Insulating pad 85 may cover the side and top surfaces of insulating pattern 86, the side surfaces of lower source / drain patterns 78c, 78n and 78p, and the side and bottom surfaces of lower interconnect patterns 83c, 83n and 83p.

[0073] Bit line shielding structure 88 may include a vertical portion disposed between bit lines 83c and a plate portion extending from the vertical portion and overlapping the bit lines 83c perpendicularly. Bit line shielding structure 88 may be spaced apart from bit lines 83c by insulating gasket 85. Insulating layer 90 may be disposed below insulating structures 85 and 86 and bit line shielding structure 88.

[0074] The vertical active patterns 21c, 21n, and 21p may comprise monocrystalline silicon. The extended source / drain pattern 35c on the cell and the extended source / drain pattern 35n on the first periphery may comprise first polycrystalline silicon, for example, polycrystalline silicon with N-type conductivity. The extended source / drain pattern 35p on the second periphery may comprise second polycrystalline silicon, for example, polycrystalline silicon with P-type conductivity.

[0075] The lower source / drain pattern 78c and the first peripheral lower source / drain pattern 78n may include a third polysilicon, such as N-type polysilicon. The second peripheral lower source / drain pattern 78p may include a fourth polysilicon, such as P-type polysilicon.

[0076] The width of each of the extended source / drain patterns 35c, 35n, and 35p in the first horizontal direction X can be greater than the width of each of the vertical active patterns 21c, 21n, and 21p in the first horizontal direction X.

[0077] The upper source / drain SDcU may include an extended source / drain pattern 35c and an upper source / drain region 21c_U. The lower source / drain SDcL may include a lower source / drain pattern 78c and a lower source / drain region 21c_L. Both the upper source / drain SDcU and the lower source / drain SDcL may have N-type conductivity.

[0078] The unit transistor cTR may include the upper source / drain SDcU, the lower source / drain SDcL, the vertical channel region 21c_CH, the gate dielectric layer 24c, and the gate electrode 27c.

[0079] The first peripheral upper source / drain SDnU may include a first peripheral extended source / drain pattern 35n and a first peripheral upper source / drain region 21n_U. The first peripheral lower source / drain SDnL may include a first peripheral lower source / drain pattern 78n and a first peripheral lower source / drain region 21n_L. The first peripheral upper source / drain SDnU and the first peripheral lower source / drain SDnL may have N-type conductivity. The first peripheral transistor TRn may include a first peripheral upper source / drain SDnU, a first peripheral lower source / drain SDnL, a first peripheral vertical channel region 21n_CH, a first peripheral gate dielectric layer 24n, and a first peripheral gate electrode 27n. The first peripheral transistor TRn may be an NMOS transistor. Multiple first peripheral transistors TRn may be provided, and the multiple first peripheral transistors TRn may be provided, for example, in... Figure 3 The NMOS transistor region NMOS1 is shown in the diagram.

[0080] The second peripheral upper source / drain SDpU may include a second peripheral extended source / drain pattern 35p and a second peripheral upper source / drain region 21p_U. The second peripheral lower source / drain SDpL may include a second peripheral lower source / drain pattern 78p and a second peripheral lower source / drain region 21p_L. The second peripheral upper source / drain SDpU and the second peripheral lower source / drain SDpL may have P-type conductivity. The second peripheral transistor TRp may include a second peripheral upper source / drain SDpU, a second peripheral lower source / drain SDpL, a second peripheral vertical channel region 21p_CH, a second peripheral gate dielectric layer 24p, and a second peripheral gate electrode 27p. The second peripheral transistor TRp may be an NMOS transistor. Multiple second peripheral transistors TRp may be provided, and multiple second peripheral transistors TRp may be provided, for example, in... Figure 3 The PMOS transistor region PMOS1 is shown in the diagram.

[0081] Various example embodiments of the semiconductor device 1 will be described below. The various example embodiments described below and the example embodiments described above can be combined with each other to form example embodiments. In the following description, components described above may be directly referenced without detailed description, or may be omitted entirely. Additionally, the components described below may be modified or replaced with reference to the following drawings; however, components that can be modified, replaced, or added may be combined with each other or with the components described above to form a semiconductor device according to the example embodiments.

[0082] Reference Figure 7 An example of a semiconductor device according to an example embodiment. Figure 7 It is shown Figure 5A Area "E" and Figure 5B An enlarged view of region "F" to illustrate an example of a semiconductor device according to an example embodiment.

[0083] In the example embodiment, reference Figure 7 The conductive layer on the unit described above ( Figure 6 56c in the diagram can be replaced with a conductive layer 56c1 on the cell surface having a lower height, and the cell isolation pattern described above ( Figure 652a) in the diagram can be replaced with a cell isolation pattern 52a1 having a lower upper surface. Therefore, the upper surface of the cell upper conductive layer 56c1 and the upper surface of the cell isolation pattern 52a1 can be set at a height lower than the height of the upper surface of the first peripheral upper conductive layer 56n and the upper surface of the first peripheral isolation pattern 52c. Therefore, the upper surface of the cell contact plug 57c and the upper surface of the cell isolation pattern 52a1 can be set at a height lower than the height of the upper surface of the first peripheral upper contact plug 57n and the upper surface of the first peripheral isolation pattern 52c.

[0084] In the following description, reference will be made to Figure 8 An example of a semiconductor device according to an example embodiment. Figure 8 It is shown Figure 5A Area "E" and Figure 5B An enlarged view of region "F" to illustrate an example of a semiconductor device according to an example embodiment.

[0085] In the example embodiment, reference Figure 8 The conductive layer on the unit described above ( Figure 6 56c in the diagram can be replaced with a conductive layer 56c2 on the cell surface with a higher height, and the cell isolation pattern described above ( Figure 6 52a) in the diagram can be replaced with a unit isolation pattern 52a2 having a lower upper surface.

[0086] The upper surface of the conductive layer 56c2 on the unit can be positioned at a height higher than the upper surface of the unit isolation pattern 52a1. Therefore, the upper surface of the unit contact plug 57c can be positioned at a height higher than the upper surface of the unit isolation pattern 52a1. The conductive layer 56c2 on the unit can have a convex upper surface, and the unit isolation pattern 52a1 can have a concave upper surface. The upper surface of the unit isolation pattern 52a1 can be positioned at a height lower than the height of the upper surface of the first peripheral isolation pattern 52c and the upper surface of the first peripheral contact plug 57n. For example, the middle portion of the highest surface of the conductive layer 56c2 on the unit can be at a vertical height higher than the edge portion of the highest surface of the conductive layer 56c2 on the unit. For example, the middle portion of the highest surface of the unit isolation pattern 52a2 can be at a vertical height lower than the edge portion of the highest surface of the unit isolation pattern 52a2.

[0087] In the following description, reference will be made to Figure 9 An example of a semiconductor device according to an example embodiment. Figure 9 It is shown Figure 5A Area "E" and Figure 5B An enlarged view of region "F" to illustrate an example of a semiconductor device according to an example embodiment.

[0088] In the example embodiment, reference Figure 9 The conductive layer on the unit described above ( Figure 6 56c in the text can be replaced with a unit-top conductive layer 56c3 comprising a first unit conductive layer 56c3a and a second unit conductive layer 56c3b stacked sequentially, and the first peripheral conductive layer described above ( Figure 6 56n) in the text can be replaced with a first peripheral upper conductive layer 56n1 comprising a first peripheral conductive layer 56na and a second peripheral conductive layer 56nb stacked sequentially.

[0089] The first unit conductive layer 56c3a and the first peripheral conductive layer 56na may have the same thickness and may be formed of the same material. The second unit conductive layer 56c3b and the second peripheral conductive layer 56nb may have substantially the same thickness and may be formed of the same material.

[0090] The materials of the second unit conductive layer 56c3b and the second peripheral conductive layer 56nb may be different from the materials of the first unit conductive layer 56c3a and the first peripheral conductive layer 56na.

[0091] The materials of the second unit conductive layer 56c3b and the second peripheral conductive layer 56nb may be different from the material of the first upper interconnect adjacent to the second peripheral conductive layer 56nb.

[0092] The upper surface of the unit contact plug 57c may be disposed at substantially the same height as the upper surface of the first peripheral contact plug 57n. The upper surface of the unit contact plug 57c may be disposed at substantially the same height as the upper surface of the unit isolation pattern 52a3. The upper surface of the unit isolation pattern 52a3 may be disposed at substantially the same height as the upper surface of the first peripheral isolation pattern 52c.

[0093] In the following description, reference will be made to Figure 10 An example of a semiconductor device according to an example embodiment. Figure 10 The illustration is shown. Figure 5A Area "E" and Figure 5B A portion of region “F” is used to describe an enlarged view of an example semiconductor device according to an example embodiment.

[0094] In the example embodiment, reference Figure 10 The first electrode described above ( Figure 6 68a) can be replaced by penetrating the insulating gasket 66 and extending into the first electrode 68a1 in the unit contact plug 57c. The lower surface of the first electrode 68a1 can be positioned at a lower height than the upper surface of the unit contact plug 57c. For example, the first electrode 68a1 can penetrate the reference... Figure 9The second unit conductive layer 56c3b is described and can be in contact with the first unit conductive layer 56c3a.

[0095] Reference Figure 11 , Figure 12A and Figure 12B An example of a semiconductor device according to an example embodiment. Figure 11 It can be with Figure 4 Corresponding cross-sectional views are provided to illustrate examples of semiconductor devices according to exemplary embodiments. Figure 12A It can be shown Figure 11 Enlarged views of areas "A2" and "B2" are shown, and Figure 12B It is shown Figure 11 Enlarged views of areas "C2" and "D2" shown.

[0096] In the example embodiment, reference Figure 11 , Figure 12A and Figure 12B The first structure described above ( Figure 1 The first part of ST1) Figure 4 ST1_A in the text can be replaced with Figure 11 The first structure in ( Figure 1 The first part of ST1 in the reference is ST1_F. Figure 4 , Figure 5A and Figure 5B The described cell gate dielectric layer 24c, first peripheral gate dielectric layer 24n, second peripheral gate dielectric layer 24p, and insulating layers 18, 33, and 75 can be replaced as shown in Figure 11 , Figure 12A and Figure 12BThe back gate dielectric layer 24c', the first peripheral gate dielectric layer 24n', the second peripheral gate dielectric layer 24p', and insulating layers 18', 33', and 75' are included. The cell gate dielectric layer 24c' can be disposed between the side surface of the cell vertical active pattern 21c and the side surface of the cell gate electrode 27c, and can extend to cover the upper surface of the cell gate electrode 27c. The first peripheral gate dielectric layer 24n' can be disposed between the side surface of the first peripheral vertical active pattern 21n and the side surface of the first peripheral gate electrode 27n, and can extend to cover the upper surface of the first peripheral gate electrode 27n. The second peripheral gate dielectric layer 24p' can be disposed between the side surface of the second peripheral vertical active pattern 21p and the side surface of the second peripheral gate electrode 27p, and can extend to cover the upper surface of the second peripheral gate electrode 27p. The insulating layer 18' can be disposed on the upper surface of the back gate electrodes 16c, 16n, and 16p. Insulating layer 75' can be disposed below the lower surfaces of back gate electrodes 16c, 16n, and 16p. Insulating layer 33' can be disposed below the lower surfaces of gate electrodes 27c, 27n, and 27p. Insulating layer 22' can be disposed on the upper surface of gate dielectric layers 24c', 24n', and 24p'.

[0097] In the following description, reference will be made to Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E Description Reference Figure 1 Various examples of semiconductor device 1 are described. Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E It is a reference. Figure 1 Figures illustrating various examples of the described semiconductor device 1.

[0098] In the example embodiment, reference Figure 1 and Figure 13A Semiconductor device 1 may include and Figure 1 The first structure ST1a corresponding to the first structure ST1 in the first structure ST1 and the first structure ST1a with Figure 1 The second structure ST2a corresponds to the second structure ST2 in the first structure ST1a. The second structure ST2a can be disposed below the first structure ST1a and can be joined to and in contact with the first structure ST1a. The first structure ST1a may include a reference... Figures 4 to 12B The first part ST1_1 is the same as one of the first parts ST1_A and ST1_F. For example, the first part ST1_1 can be the same as... Figure 4The first part ST1_A is the same. The first structure ST1a may further include an insulating layer 74 located on the first part ST1_1 and an insulating layer 95 located below the first part ST1_1. The first structure ST1a may further include upper contact plugs 70a and 70c and an upper interconnect 72. Each upper contact plug 70a may include a conductive plug pattern 69b and a conductive pad 69a covering the side surface and lower surface of the conductive plug pattern 69b. The upper contact plugs 70a and 70c may include a unit contact plug 70c that penetrates the insulating layer 70 and is connected to the second electrode 68c, and a connection contact plug 70a that penetrates the insulating layer 70 and the insulating pad 66 and is connected to the pad pattern 63a. The upper interconnect 72 may be connected to the contact plugs 70a and 70c and the insulating layer 70. The insulating layer 74 may be disposed on the insulating layer 70 and the upper interconnect 72. The first structure ST1a may further include lower contact plugs 93b, 93a, 93n1, 93n2, 93p2, and 93p1 extending upward and penetrating the insulating layer 90. Each of the lower contact plugs 93b, 93a, 93n1, 93n2, 93p2, and 93p1 may include a conductive plug pattern 92 and a conductive pad 91 covering the lower and side surfaces of the conductive plug pattern 92. The lower contact plugs 93b, 93a, 93n1, 93n2, 93p2 and 93p1 may include a lower contact plug 93a connected to and in contact with bit line 83c, a lower contact plug 93b connected to and in contact with pad pattern 63a, a lower contact plug 93n1 connected to and in contact with first upper interconnect 63n, a lower contact plug 93n2 connected to and in contact with first lower interconnect 83n, a lower contact plug 93p2 connected to and in contact with second lower interconnect 83p, and a lower contact plug 93p1 connected to and in contact with second upper interconnect 63p. The first structure ST1a may form an insulating layer 95 disposed below the first part ST_1, a routing interconnect structure 97 electrically connected to the lower contact plugs 93b, 93a, 93n1, 93n2, 93p2 and 93p1, and a bonding pad 99 connected to the routing interconnect structure 97 in the insulating layer 95. The lower surface of the insulating layer 95 and the lower surface of the bonding pad 99 may be coplanar with each other.

[0099] The second structure ST2a may include a first peripheral circuit pTRa perpendicularly overlapping the memory region CR and a second peripheral circuit pTRb perpendicularly overlapping the peripheral region PR. The second structure ST2a may include a substrate 403 and a device isolation region 406 defining an active region 409 on the substrate 403. The substrate 403 may be a semiconductor substrate. The first peripheral circuit pTRa and the second peripheral circuit pTRb may be disposed on the substrate 403. Each of the first peripheral circuit pTRa and the second peripheral circuit pTRb may include peripheral gate structures pGO and pGE disposed on the active region 409, peripheral source / drain regions pSD disposed on both sides of the peripheral gate structures pGO and pGE in the active region 409, and a peripheral channel region pCH located between the peripheral source / drain regions pSD. The peripheral gate structures pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE stacked sequentially. The first peripheral circuit pTRa and the second peripheral circuit pTRb may include a first peripheral circuit transistor pTRa that overlaps perpendicularly to the storage region CR and a second peripheral circuit transistor pTRb that overlaps perpendicularly to the peripheral region PR. The second structure ST2a may further include a lower routing interconnect structure 420 disposed on the substrate 403 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb, a second bonding pad 425 disposed on the lower routing interconnect structure 420, and a lower insulating structure 415. The lower insulating structure 415 may be disposed on the substrate 403 and may have an upper surface coplanar with the upper surface of the second bonding pad 425. The upper surface of the second bonding pad 425 may be bonded to the lower surface of the first bonding pad 99, and the upper surface of the lower insulating structure 415 may be bonded to the lower surface of the insulating layer 95. The lower routing interconnect structure 420 may include a first lower routing interconnect structure 420a electrically connected to the second bonding pad 425 and a second lower routing interconnect structure 420b not directly connected to the second bonding pad 425. The second structure ST2a may further include an insulating layer 430 disposed below the substrate 403, a conductive through-path 440 penetrating the insulating layer 430 and the substrate 403 and connected to the second lower routing interconnect structure 420b, an insulating spacer 435 disposed on the side surface of the conductive through-path 440, and an input / output pad 450 connected to the conductive through-path 440 below the insulating layer 430.

[0100] In the example embodiment, reference Figure 1 and Figure 13B It is not necessary to provide Figure 13A The first bonding pad 99 in the first structure ST1a. Figure 13A The second structure ST2a in the text can be replaced with Figure 13B The second structure ST2b in the text.

[0101] The second structure ST2b may include a first peripheral circuit pTRa perpendicularly overlapping the memory region CR and a second peripheral circuit pTRb perpendicularly overlapping the peripheral region PR. The second structure ST2b may include a substrate 503 and a device isolation region 506 defining an active region 509 below the substrate 503. The substrate 503 may be a semiconductor substrate. The first peripheral circuit pTRa and the second peripheral circuit pTRb may be disposed below the substrate 503. Each of the first peripheral circuit pTRa and the second peripheral circuit pTRb may include peripheral gate structures pGO and pGE disposed below the active region 509, peripheral source / drain regions pSD disposed in the active region 509 on both sides of the peripheral gate structures pGO and pGE, and a peripheral channel region pCH located between the peripheral source / drain regions pSD. The peripheral gate structures pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE stacked sequentially downwards.

[0102] The second structure ST2b may further include a lower routing interconnect structure 520 disposed below the substrate 503 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb, and a lower insulating structure 515 covering the lower routing interconnect structure 520 below the lower routing interconnect structure 520.

[0103] The lower routing interconnect structure 520 may include a first lower routing interconnect structure 520a and a second lower routing interconnect structure 520b. The second structure ST2b may also include input / output pads 550 disposed below the lower insulating structure 515 and electrically connected to the second lower routing interconnect structure 520b, and an insulating layer 530 disposed between the substrate 503 and the first structure ST1a. The insulating layer 530 and the insulating layer 95 may be bonded to each other.

[0104] The first structure ST1a and the second structure ST2b may further include a conductive through-path 535 electrically connected to the first lower routing interconnect structure 520a, extending in the vertical direction Z, penetrating the substrate 503 and the insulating layer 530 and contacting the routing interconnect structure 97, and an insulating spacer 534 located on the side surface of the conductive through-path 535. The conductive through-path 535 may include a conductive pillar 535a and a conductive pad layer 535b covering the side surface and the top surface of the conductive pillar 535a. Therefore, a semiconductor device 1b including the first structure ST1a and the second structure ST2b can be provided.

[0105] In the example embodiment, reference Figure 1 and Figure 13C The semiconductor device 1d according to the example embodiment may include, with Figure 1 The first structure ST1a corresponding to the first structure ST1 in the first structure ST1 and the first structure ST1a with Figure 1The second structure ST2c corresponds to the second structure ST2 in the first structure ST1a. The second structure ST2c can be disposed on the first structure ST1a and joined to and in contact with the first structure ST1a. The first structure ST1a may include a reference... Figures 4 to 12B The first part ST1_A and ST1_F described are the same as the first part ST1_3. For example, the first part ST1_3 can be the same as... Figure 4 The first part ST1_A is the same. The first structure ST1a may also include an insulating layer 662 located on the first part ST1_1 and a first bonding pad 625 electrically connected to the routing interconnect structure 660 in the insulating layer 662. The upper surface of the first bonding pad 625 may be coplanar with the upper surface of the insulating layer 662. The pad pattern 63a described above may include a first pad pattern 63a1 that overlaps perpendicularly to the bit line 83c, a second pad pattern 63a2 that overlaps perpendicularly to the first lower interconnect 83n, and a third pad pattern 63a3 that overlaps perpendicularly to the second lower interconnect 83p.

[0106] The first structure ST1a may further include lower contact plugs 693a, 693n2, and 693p2, and upper contact plugs 670c, 670a, 670n2, 670n1, 670p1, and 670p2. The lower contact plugs 693a, 693n2, and 693p2 may include a lower contact plug 693a extending between bit line 83c and the first pad pattern 63a1 and electrically connecting bit line 83c to the first pad pattern 63a1; a lower contact plug 693n2 extending between the first lower interconnect 83n and the second pad pattern 63a2 and electrically connecting the first lower interconnect 83n to the second pad pattern 63a2; and a lower contact plug 693p2 extending between the second lower interconnect 83p and the third pad pattern 63a3 and electrically connecting the second lower interconnect 83p to the third pad pattern 63a3. Each of the lower contact plugs 693a, 693n2, and 693p2 may include a plug pattern 692 and a conductive pad 691 covering the side and lower surfaces of the plug pattern 692. The upper contact plugs 670c, 670a, 670n2, 670n1, 670p1, and 670p2 may include an upper contact plug 670c connected to the second electrode 68c, an upper contact plug 670a connected to the first pad pattern 63a1, an upper contact plug 670n2 connected to the second pad pattern 63a2, an upper contact plug 670p2 connected to the third pad pattern 63a3, an upper contact plug 670n1 connected to the first upper interconnect 63n1, and an upper contact plug 670p1 connected to the second upper interconnect 63p1. Upper contact plugs 670a, 670n2, 670n1, 670p1, and 670p2 can penetrate the insulating layer 70 and the insulating gasket 66. Upper contact plug 670c can penetrate the insulating layer 70. Upper contact plugs 670c, 670a, 670n2, 670n1, 670p1, and 670p2 can be electrically connected to the routing interconnect structure 660.

[0107] The second structure ST2c may include a first peripheral circuit pTRa perpendicularly overlapping the memory region CR and a second peripheral circuit pTRb perpendicularly overlapping the peripheral region PR. The second structure ST2c may include a substrate 603 and a device isolation region 606 defining an active region 609 below the substrate 603. The substrate 603 may be a semiconductor substrate. The first peripheral circuit pTRa and the second peripheral circuit pTRb may be disposed below the substrate 603. Each of the first peripheral circuit pTRa and the second peripheral circuit pTRb may include peripheral gate structures pGO and pGE disposed below the active region 609, peripheral source / drain regions pSD disposed in the active region 609 on both sides of the peripheral gate structures pGO and pGE, and a peripheral channel region pCH located between the peripheral source / drain regions pSD. The peripheral gate structures pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE stacked sequentially downwards. The second structure ST2c may further include a lower routing interconnect structure 620 disposed below the substrate 603 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb, a lower insulating structure 615 covering the lower routing interconnect structure 620 below it, and a second bonding pad 699 having a lower surface coplanar with the lower surface of the lower insulating structure 615. The second bonding pad 699 may be bonded to the first bonding pad 625, and the lower insulating structure 615 may be bonded to the insulating layer 662. The lower routing interconnect structure 620 may include a first lower routing interconnect structure 620a and a second lower routing interconnect structure 620b. The second structure ST2c may further include an insulating layer 630 on the substrate 603, input / output pads 650 on the insulating layer 630, a conductive pass-through 640 extending between the input / output pads 650 and the second lower routing interconnect structure 620b and electrically connecting the input / output pads 650 to the second lower routing interconnect structure 620b, and insulating spacers 635 on the side surface of the conductive pass-through 640. The conductive pass-through 640 may penetrate the insulating layer 630 and the substrate 603.

[0108] In the example embodiment, reference Figure 1 and Figure 13D It is not necessary to provide Figure 13C The first bonding pad 625 in the first structure ST1a. Figure 13C The second structure ST2c in the text can be replaced with Figure 13DThe second structure ST2d may include a first peripheral circuit pTRa perpendicularly overlapping the storage region CR and a second peripheral circuit pTRb perpendicularly overlapping the peripheral region PR. The second structure ST2d may include a substrate 703 and a device isolation region 706 defining an active region 709 on the substrate 703. The substrate 703 may be a semiconductor substrate. The first peripheral circuit pTRa and the second peripheral circuit pTRb may be disposed on the substrate 703.

[0109] Each of the first peripheral circuit pTRa and the second peripheral circuit pTRb may include peripheral gate structures pGO and pGE disposed on the active region 709, peripheral source / drain regions pSD disposed on both sides of the peripheral gate structures pGO and pGE in the active region 709, and a peripheral channel region pCH disposed between the peripheral source / drain regions pSD. The peripheral gate structures pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE stacked sequentially.

[0110] The second structure ST2d may further include a lower routing interconnect structure 720 disposed on the substrate 703 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb, and a lower insulating structure 715 covering the lower routing interconnect structure 720.

[0111] The lower routing interconnect structure 720 may include a first lower routing interconnect structure 720a and a second lower routing interconnect structure 720b. The second structure ST2d may further include input / output pads 750 disposed on the lower insulating structure 715 and electrically connected to the second lower routing interconnect structure 720b, and an insulating layer 730 disposed between the substrate 703 and the first structure ST1b. The insulating layers 730 and 795 may be bonded to each other. The first structure ST1b and the second structure ST2d may further include a conductive through-path 735 electrically connected to the first lower routing interconnect structure 720a, extending downward, penetrating the substrate 703 and the insulating layer 730, and contacting and connecting to the routing interconnect structure 797, and an insulating spacer 734 located on the side surface of the conductive through-path 735. The conductive through-path 735 may include a conductive pillar 735b and a conductive pad layer 735a covering the side and lower surfaces of the conductive pillar 735b. Therefore, a semiconductor device 1e including the first structure ST1b and the second structure ST2d can be provided.

[0112] In the example embodiment, reference Figure 1 and Figure 13E ,exist Figure 13A In the second structure ST2a, a conductive path may not be provided. Figure 13A 440 in the middle), insulating spacer (Figure 13A 435 in the middle) and input / output pads ( Figure 13A (450 in the middle). Therefore, it can be as follows: Figure 13E Modify it like that Figure 13A The second structure ST2a is included. The first structure ST1a may further include input and output lower contact plugs 93io formed simultaneously with lower contact plugs 93b, 93a, 93n1, 93n2, 93p2, and 93p1. The first structure ST1a may further include input and output conductive patterns 63io formed simultaneously with conductive patterns 63a, 63n, and 63p. The first structure ST1a may further include input and output connecting contact plugs 70io formed simultaneously with connecting contact plugs 70a, input and output interconnects 72io formed simultaneously with upper interconnects 72, contact plugs 440a located on input and output interconnects 72io, and input and output pads 450a located on contact plugs 440a. The input and output lower contact plugs 93io, input and output conductive patterns 63io, input and output connecting contact plugs 70io, input and output interconnects 72io, contact plugs 440a, and input and output pads 450a may be electrically connected to each other.

[0113] In the following description, reference will be made to Figures 14 to 23 An example describing a method for forming a semiconductor device according to an exemplary embodiment. Figures 14 to 23 It shows along Figure 3 The cross-sectional view of the region intercepted by line I-I' is used to illustrate an example of a method for forming a semiconductor device according to an exemplary embodiment.

[0114] refer to Figure 3 and Figure 14 A sacrificial substrate 3, a sacrificial insulating layer 6, and a semiconductor layer 9 can be formed sequentially. The semiconductor layer 9 can be formed from a semiconductor material such as single-crystal silicon. Trench 12 can be formed penetrating the semiconductor layer 9 and the sacrificial insulating layer 6. The trench 12 can be formed in the memory region CR and the peripheral region PR. When viewed in a cross-section in the XZ plane (see example...), Figure 14 Each trench 12 may have a line shape extending in the vertical direction Z. The semiconductor layer 9 may be divided by trenches, and the divided regions of the semiconductor layer 9 may be spaced apart from each other in the first horizontal direction X. The method may include: forming a back gate dielectric layer 14 conformally covering the inner wall of the trench 12; forming a back gate conductive layer on the back gate dielectric layer 14; forming a preliminary back gate electrode 16 partially filling the trench 12 by etching a portion of the back gate conductive layer using an etch-back process; and forming a back gate cover insulating layer 18 filling the remaining portion of the trench 12 on the preliminary back gate electrode 16. The back gate cover insulating layer 18 may be formed of an insulating material.

[0115] refer toFigure 3 and Figure 15 It can be achieved by modifying the semiconductor layer ( Figure 14 In step 9), patterning is performed to form vertical active patterns 21c, 21n, and 21p, and simultaneously, the sacrificial insulating layer 6 can be exposed. The vertical active patterns 21c, 21n, and 21p can include a cell vertical active pattern 21c formed in the storage region CR and a first peripheral active pattern 21n and a second peripheral active pattern 21p formed in the peripheral region PR. Among the vertical active patterns 21c, 21n, and 21c, a pair of adjacent vertical active patterns can be formed on both sides of one of the initial back gate electrodes 16. An insulating layer 22 can be formed on the exposed sacrificial insulating layer 6. The upper surface of the insulating layer 22 can be set at a height lower than the height of the upper surface of the initial back gate electrode 16.

[0116] refer to Figure 3 and Figure 16 Dielectric layers 24c, 24, 24n, and 24p, and gate electrodes 27c, 27n, and 27p, can be formed. Forming dielectric layers 24c, 24, 24n, and 24p, and gate electrodes 27c, 27n, and 27p, may include: forming dielectric layers 24c, 24, 24n, and 24p that conformally cover the upper surface of the insulating layer 22 and the exposed side surfaces of the active patterns 21c, 21n, and 21c; forming a preliminary gate conductive layer that conformally covers the gate dielectric layers 24c, 24, 24n, and 24p; forming a gate conductive layer by anisotropically etching the preliminary gate conductive layer; forming an isolation insulating layer 30 on the gate conductive layer; forming gate electrodes 27c, 27n, and 27p by partially etching the gate conductive layer; and forming a gate covering insulating layer 33 on the gate electrodes 27c, 27n, and 27p.

[0117] Dielectric layers 24c, 24, 24n, and 24p may include a cell gate dielectric layer 24c, a first peripheral gate dielectric layer 24n, a second peripheral gate dielectric layer 24p, and dielectric layer 24. The cell gate dielectric layer 24c may contact the side surface of the cell vertical active pattern 21c. The first peripheral gate dielectric layer 24n may contact the side surface of the first peripheral vertical active pattern 21n. The second peripheral gate dielectric layer 24p may contact the side surface of the second peripheral vertical active pattern 21p. Dielectric layer 24 may be disposed between adjacent groups of a set of cell vertical active patterns 21c, a set of first peripheral vertical active patterns 21n, and a set of second peripheral vertical active patterns 21p.

[0118] An isolation insulating layer 30 can be disposed between adjacent unit gate electrodes 27c, adjacent first peripheral gate electrodes 27n, adjacent second peripheral gate electrodes 27p, and on the dielectric layer 24. The upper surfaces of the vertical active patterns 21c, 21n, and 21p, the upper surface of the isolation insulating layer 30, and the upper surface of the gate covering insulating layer 33 can be coplanar. A first semiconductor layer 36 can be formed on the vertical active patterns 21c, 21n, and 21p, the isolation insulating layer 30, and the gate covering insulating layer 33. The lower surface of the first semiconductor layer 36 can contact the upper surfaces of the vertical active patterns 21c, 21n, and 21p. The vertical active patterns 21c, 21n, and 21p can be formed of monocrystalline silicon. For example, the vertical active patterns 21c, 21n, and 21p can be formed of undoped monocrystalline silicon.

[0119] In this example, the first semiconductor layer 36 may be formed of polysilicon. For instance, the first semiconductor layer 36 may be formed of undoped polysilicon.

[0120] In the example, the first semiconductor layer 36 can be formed from epitaxial silicon.

[0121] refer to Figure 3 and Figure 17 A third semiconductor pattern 48a (e.g., a third semiconductor layer) and a second semiconductor pattern 42a (e.g., a second semiconductor layer) with different conductivity types can be formed on the first semiconductor layer 36. The third semiconductor pattern 48a and the second semiconductor pattern 42a can have substantially the same thickness. The second semiconductor pattern 42a can be perpendicularly overlapped with the cell vertical active pattern 21c and the first peripheral vertical active pattern 21n. The third semiconductor pattern 48a can be perpendicularly overlapped with the second peripheral vertical active pattern 21p. The second semiconductor pattern 42a can have N-type conductivity, while the third semiconductor pattern 48a can have P-type conductivity. A first impurity in the second semiconductor pattern 42a can diffuse into the first semiconductor layer (…). Figure 16 The upper region of the third semiconductor pattern 48a (36), the upper region of the unit vertical active pattern 21c, and the upper region of the first peripheral vertical active pattern 21n. Therefore, the impurity concentration in the second semiconductor pattern 42a can be higher than the impurity concentration in the first semiconductor layer 36, and the impurity concentration in the first semiconductor layer 36 can be higher than the impurity concentration in the upper region of the unit vertical active pattern 21c and the upper region of the first peripheral vertical active pattern 21n. The first impurity can be a group V element of the periodic table, such as P or As. The second impurity in the third semiconductor pattern 48a can diffuse into the first semiconductor layer (36). Figure 16The first semiconductor layer 36 is located in the upper region of the third semiconductor pattern 42a and the upper region of the second peripheral vertical active pattern 21p. Therefore, the concentration of impurities in the third semiconductor pattern 48a can be higher than the concentration of impurities in the first semiconductor layer 36, and the concentration of impurities in the first semiconductor layer 36 can be higher than the concentration of impurities in the upper region of the second peripheral vertical active pattern 21p. The first impurity can be a group III element of the periodic table, such as B or Al. The first semiconductor layer 36 can be formed of polycrystalline silicon doped with group V and group III elements. The first semiconductor layer 36 located below the second semiconductor pattern 42a can be formed of a first semiconductor layer 36a doped with the first impurity, and the first semiconductor layer 36 located below the third semiconductor pattern 48a can be formed of a first semiconductor layer 36b doped with the second impurity. The first conductive layer 53 and the second conductive layer 56 can be sequentially stacked on the second semiconductor pattern 42a and the third semiconductor pattern 48a. The first conductive layer 53 can include a first conductive material, while the second conductive layer 56 can include a second conductive material different from the first conductive material.

[0122] refer to Figure 3 and Figure 18 Isolation patterns 52a, 52b, and 52c can be formed. Isolation patterns 52a, 52b, and 52c can be formed from an insulating nitride (e.g., silicon nitride). Isolation patterns 52a, 52b, and 52c can include a cell isolation pattern 52a, a first peripheral isolation pattern 52c, and a second peripheral isolation pattern 52b. Isolation patterns 52a, 52b, and 52c can be spaced apart from vertical active patterns 21c, 21n, and 21p. Cell isolation pattern 52a can be formed in the memory region CR and can penetrate the first conductive layer 53, the second conductive layer 56, the second semiconductor pattern 42a, and the first semiconductor layer 36a. The first peripheral isolation pattern 52c can be formed in the peripheral region PR and can penetrate the first conductive layer 53, the second conductive layer 56, the second semiconductor pattern 42a, and the first semiconductor layer 36a. The second peripheral isolation pattern 52b can be formed in the peripheral region PR and can penetrate the first conductive layer 53, the second conductive layer 56, the third semiconductor pattern 48a and the first semiconductor layer 36b.

[0123] refer to Figure 3 and Figure 19Insulating structures 54 and 56 can be formed. Each insulating structure 54 and 56 can be disposed between adjacent groups of a set of cell isolation patterns 52a, a set of first peripheral isolation patterns 52c, and a set of second peripheral isolation patterns 52b. Insulating structures 54 and 56 can penetrate the first conductive layer 53, the second conductive layer 56, the second semiconductor pattern 42a, the third semiconductor pattern 48a, and the first semiconductor layers 36a and 36b. Each insulating structure 54 and 56 may include an insulating pattern 56 and an insulating pad 54 covering the side and bottom surfaces of the insulating pattern 56. The insulating pattern 56 may include an oxide, and the insulating pad 54 may include a nitride. The first semiconductor layer 36a and the second semiconductor pattern 42a defined by the cell isolation pattern 52a can form a lower source / drain layer 36c and an upper source / drain layer 42c. A first semiconductor layer 36a defined by a first peripheral isolation pattern 52c and a second semiconductor pattern 42a can form a first peripheral lower source / drain layer 36n and a first peripheral upper source / drain layer 42n. A first semiconductor layer 36b defined by a second peripheral isolation pattern 52b and a third semiconductor pattern 48a can form a second peripheral lower source / drain layer 36p and a second peripheral upper source / drain layer 42p. Sequentially stacked lower source / drain layers 36c and upper source / drain layers 42c can form an upper extended source / drain pattern 35c. Sequentially stacked lower source / drain layers 36n and upper source / drain layers 42n can form an upper extended source / drain pattern 35n. Sequentially stacked lower source / drain layers 36p and upper source / drain layers 48p can form an upper extended source / drain pattern 35p. The first conductive layer 53 and the second conductive layer 56 defined by the isolation patterns 52a, 52b and 52c can respectively form contact plugs 57c, 57n and 57p. Contact plugs 57c, 57n and 57p may include a cell contact plug 57c formed on the upper surface of the cell source / drain layer 42c, a first peripheral contact plug 57n formed on the upper surface of the first peripheral source / drain layer 42n, and a second peripheral contact plug 57p formed on the upper surface of the second peripheral source / drain layer 42p.

[0124] Each cell contact plug 57c may include a lower cell conductive layer 53c in contact with the upper surface of the cell upper source / drain layer 42c and an upper cell conductive layer 56c located on the lower cell conductive layer 53c. Each first peripheral upper contact plug 57n may include a first peripheral lower conductive layer 53n in contact with the upper surface of the first peripheral upper source / drain layer 42n and a first peripheral upper conductive layer 56n located on the first peripheral lower conductive layer 53n. Each second peripheral upper contact plug 57p may include a second peripheral lower conductive layer 53p in contact with the upper surface of the second peripheral upper source / drain layer 48p and a second peripheral lower conductive layer 53p located on the second peripheral upper conductive layer 56p.

[0125] refer to Figure 3 and Figure 20 Conductive structures 59 and 62 may be formed on contact plugs 57c, 57n and 57p, insulating structures 54 and 56, and isolation patterns 52a, 52b and 52c. Conductive structures 59 and 62 may include a first upper conductive layer 59 and a second upper conductive layer 62 stacked sequentially.

[0126] refer to Figure 3 and Figure 21 Conductive patterns 63a, 63n, and 63p can be formed by patterning conductive structures 59 and 62. Conductive patterns 63a, 63n, and 63p may include pad pattern 63a, a first upper interconnect 63n, and a second upper interconnect 63p. The first upper interconnect 63n can be connected to a first peripheral upper contact plug 57n. The first upper interconnect 63n can contact the upper surface of the first peripheral upper contact plug 57n and the upper surface of the first peripheral isolation pattern 52c. The second upper interconnect 63p can be connected to a second peripheral upper contact plug 57p. The second upper interconnect 63p can contact the upper surface of the second peripheral upper contact plug 57p and the upper surface of the second peripheral isolation pattern 52b. Pad pattern 63a can be disposed on insulating structures 54 and 56. An insulating pad 66 can be formed covering the upper and side surfaces of conductive patterns 63a, 63n, and 63p in the peripheral region PR and covering the upper surface of the cell contact plug 57c and the upper surface of the cell isolation pattern 52a in the storage region CR.

[0127] In the example embodiment, the conductive material of the upper region of the unit contact plug 57c may be different from the material of the conductive structures 59 and 62 adjacent to the peripheral contact plugs 57n and 57p. Therefore, the unit contact plug 57c can be prevented from being over-etched while the conductive structures 59 and 62 are patterned.

[0128] refer to Figure 3 and Figure 22A data storage structure DS can be formed. The data storage structure DS may include a cell contact plug 57c connected to a cell contact plug 57c, a first electrode 68a extending in the vertical direction Z through an insulating pad 66, a second electrode 68c located on each of the side and top surfaces of the first electrode 68a, and a dielectric layer 68b located between the first electrode 68a and the second electrode 68c. An insulating layer 70 may be formed covering the data storage structure DS in the storage region CR and covering the insulating pad 66 in the peripheral region PR. The insulating pad 66 may include a material different from the material of the insulating layer 70. Contact plugs 70a and 70c may be formed. Each contact plug 70a may include a conductive plug pattern 69b and conductive pads 69a covering the side and bottom surfaces of the conductive plug pattern 69b. Contact plugs 70a and 70c may include a cell contact plug 70c that penetrates the insulating layer 70 and is connected to the second electrode 68c, and a connection contact plug 70a that penetrates the insulating layer 70 and the insulating pad 66 and is connected to a pad pattern 63a. An upper interconnect 72 may be formed on the insulating layer 70 to connect to the contact plugs 70a and 70c. An insulating layer 74 may be formed on the insulating layer 70 and the upper interconnect 72.

[0129] refer to Figure 3 and Figure 23 The insulating layer 74 can be positioned in the downward direction, and the sacrificial substrate 3 and the sacrificial insulating layer 6 can be removed. The back gate electrodes 16c, 16n, and 16p can be formed by partially etching the initial back gate electrode 16, and the insulating layer 75 can be formed on the back gate electrodes 16c, 16n, and 16p. The insulating layer 22 and the vertical active patterns 21c, 21n, and 21p can be exposed.

[0130] Refer again Figure 3 and Figure 4Vertically aligned lower source / drain patterns 78c, 78n, and 78p, as well as lower interconnect patterns 83c, 83n, and 83p, can be formed. The lower source / drain patterns 78c, 78n, and 78p may include a cell lower source / drain pattern 78c connected to the cell vertical active pattern 21c, a first peripheral lower source / drain pattern 78n connected to the first peripheral vertical active pattern 21n, and a second peripheral lower source / drain pattern 78p connected to the first peripheral vertical active pattern 21p. Impurities in the cell lower source / drain pattern 78c can diffuse into the cell vertical active pattern 21c, thereby forming a source / drain region in the cell vertical active pattern 21c. Impurities in the first peripheral lower source / drain pattern 78n can diffuse into the first peripheral vertical active pattern 21n, thereby forming a source / drain region in the first peripheral vertical active pattern 21n. Impurities in the second peripheral lower source / drain pattern 78p can diffuse into the second peripheral vertical active pattern 21p, thereby forming a source / drain region in the second peripheral vertical active pattern 21p. Lower interconnect patterns 83c, 83n, and 83p may include a bit line 83c that contacts and self-aligns with the cell lower source / drain pattern 78c, a first lower interconnect 83n that contacts and self-aligns with the first peripheral lower source / drain pattern 78n, and a second lower interconnect 83p that contacts and self-aligns with the second peripheral lower source / drain pattern 78p. Insulating structures 85 and 86 and a bit line shielding structure 88 may be formed. Insulating structures 85 and 86 may include insulating pads 85 covering the side and top surfaces of insulating pattern 86, the side surfaces of lower source / drain patterns 78c, 78n, and 78p, and the side and bottom surfaces of lower interconnect patterns 83c, 83n, and 83p. The bit line shielding structure 88 may be disposed between and below the bit lines 83c. The bit line shielding structure 88 may be spaced apart from the bit line 83c by an insulating pad 85. An insulating layer 90 may be formed on the insulating structures 85 and 86 and the bit line shielding structure 88.

[0131] According to the foregoing example embodiments, a transistor may include a vertically aligned lower source / drain, a vertical channel region, and an upper source / drain. The upper source / drain may include an upper source / drain region disposed in the upper region of the vertical active pattern and an extended upper source / drain pattern disposed on the vertical active pattern. The lower source / drain may include a lower source / drain region disposed in the lower region of the vertical active pattern and an extended lower source / drain pattern disposed below the vertical active pattern. Each of the extended lower source / drain pattern and the extended upper source / drain pattern can improve the leakage current characteristics of the transistor. By including both a lower source / drain pattern and an upper source / drain pattern in the transistor, the performance of the transistor can be improved.

[0132] Additionally, contact plugs aligned perpendicularly to the extended source / drain pattern and lower interconnects aligned perpendicularly to the lower source / drain can be provided. This allows for increased integration density in semiconductor devices.

[0133] Furthermore, the conductive material of the region of the contact plug adjacent to the upper interconnect and the conductive material of the upper interconnect adjacent to the contact plug can be different from each other. Therefore, over-etching of the contact plug can be prevented during the patterning process used to form the upper interconnect. This improves the reliability and performance of the semiconductor device.

[0134] In addition, by including transistors, contact plugs, upper interconnects and lower interconnects, semiconductor devices can have improved performance and increased integration density.

[0135] The various advantages and effects of the present invention are not limited to those described above, and will be more readily understood in the process of explaining specific embodiments of the present invention.

[0136] Although exemplary embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: The unit vertical active pattern and the peripheral vertical active pattern are set at the same vertical height. The cell has an extended source / drain pattern and a cell contact plug, which are sequentially stacked on the vertical active pattern of the cell. The peripheral extended source / drain pattern and peripheral contact plug are stacked sequentially on the peripheral vertical active pattern; A cell isolation pattern, wherein the cell isolation pattern is located on the side surface of the extended source / drain pattern on the cell and on the side surface of the cell contact plug; A peripheral isolation pattern, wherein the peripheral isolation pattern is located on the side surface of the extended source / drain pattern on the periphery and on the side surface of the peripheral contact plug; as well as Upper interconnect, the upper interconnect being located on the peripheral contact plug and the peripheral isolation pattern, The first distance between the vertical height of the upper end of the unit contact plug and the vertical height of the upper end of the unit isolation pattern is different from the second distance between the vertical height of the upper end of the peripheral contact plug and the vertical height of the upper end of the peripheral isolation pattern.

2. The semiconductor device according to claim 1, wherein, The first distance is greater than the second distance.

3. The semiconductor device according to claim 1, wherein, The upper surface of the unit contact plug is positioned at a higher vertical height than the upper surface of the unit isolation pattern.

4. The semiconductor device according to claim 1, wherein, The upper surface of the unit contact plug is positioned at a lower vertical height than the upper surface of the unit isolation pattern.

5. The semiconductor device according to claim 1, in, The unit contact plug comprises a lower conductive layer and an upper conductive layer of the unit stacked sequentially. The peripheral contact plug comprises a lower peripheral conductive layer and an upper peripheral conductive layer stacked sequentially. Wherein, the lower conductive layer of the unit and the lower conductive layer of the periphery have the same thickness and include the same first material, and The conductive layer on the unit and the conductive layer on the periphery both comprise the same second material.

6. The semiconductor device according to claim 5, wherein, The thickness of the conductive layer on the periphery is greater than the thickness of the conductive layer on the unit.

7. The semiconductor device according to claim 1, wherein, The upper surface of the unit isolation pattern is set at a lower vertical height than the upper surface of the outer isolation pattern.

8. The semiconductor device according to claim 1, further comprising: An insulating pad covers the upper surface of the unit isolation pattern, the upper surface of the unit contact plug, the side surface of the upper interconnect, and the upper surface of the upper interconnect; as well as The data storage structure includes a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode. The first electrode is connected to the unit contact plug, penetrates the insulating gasket, and extends upward.

9. The semiconductor device according to claim 1, in, The extended source / drain pattern on the cell includes a lower source / drain layer and an upper source / drain layer located on the lower source / drain layer. The peripheral extended source / drain pattern includes a peripheral lower source / drain layer and a peripheral upper source / drain layer located on the peripheral lower source / drain layer.

10. The semiconductor device according to claim 9, in, The impurity concentration in the upper source / drain layer of the cell is higher than the impurity concentration in the lower source / drain layer of the cell, and The concentration of impurities in the outer upper source / drain layer is higher than the concentration of impurities in the outer lower source / drain layer.

11. The semiconductor device according to claim 1, in, The vertical active pattern of the unit includes a first unit source / drain region, a second unit source / drain region located on the first unit source / drain region, and a unit channel region located between the first unit source / drain region and the second unit source / drain region. The peripheral vertical active pattern includes a first peripheral source / drain region, a second peripheral source / drain region located on the first peripheral source / drain region, and a peripheral channel region located between the first peripheral source / drain region and the second peripheral source / drain region.

12. The semiconductor device of claim 11, further comprising: The cell-level extended source / drain pattern is disposed below the cell-level vertical active pattern and connected to the first cell-level source / drain region. as well as The peripheral extended source / drain pattern is disposed below the peripheral vertical active pattern and connected to the first peripheral source / drain region.

13. The semiconductor device of claim 12, further comprising: Bit lines are aligned vertically with the lower extended source / drain pattern of the cell and located below the lower extended source / drain pattern of the cell; as well as The lower interconnect is aligned with the peripheral lower extended source / drain pattern along the vertical direction and is located below the peripheral lower extended source / drain pattern.

14. The semiconductor device of claim 13, further comprising: A cell gate, the side surface of which faces the cell channel region; as well as A peripheral gate, the side surface of which faces the peripheral channel region.

15. A semiconductor device, the semiconductor device comprising: The unit vertical active pattern and the peripheral vertical active pattern are set at the same vertical height. The cell has an extended source / drain pattern and a cell contact plug, which are sequentially stacked on the vertical active pattern of the cell. The peripheral extended source / drain pattern and peripheral contact plug are stacked sequentially on the peripheral vertical active pattern; A cell isolation pattern, wherein the cell isolation pattern is located on the side surface of the extended source / drain pattern on the cell and on the side surface of the cell contact plug; A peripheral isolation pattern, wherein the peripheral isolation pattern is located on the side surface of the extended source / drain pattern on the periphery and on the side surface of the peripheral contact plug; as well as Upper interconnect, the upper interconnect being located on the peripheral contact plug and the peripheral isolation pattern, The unit contact plug comprises a lower conductive layer and an upper conductive layer of the unit stacked sequentially. The peripheral contact plug comprises a lower peripheral conductive layer and an upper peripheral conductive layer stacked sequentially. The lower conductive layer of the unit and the lower conductive layer of the periphery include a first conductive material. Wherein, the conductive layer on the unit and the conductive layer on the periphery include a second conductive material different from the first conductive material, and The upper interconnect includes a third conductive material that is different from the first conductive material and different from the second conductive material.

16. The semiconductor device of claim 15, further comprising: An insulating pad covers the upper surface of the unit isolation pattern, the upper surface of the unit contact plug, the side surface of the upper interconnect, and the upper surface of the upper interconnect; as well as The data storage structure includes a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode. The first electrode is connected to the unit contact plug, penetrates the insulating gasket, and extends upward.

17. The semiconductor device according to claim 15, in, The extended source / drain pattern on the cell includes a lower source / drain layer and an upper source / drain layer located on the lower source / drain layer. The peripheral extended source / drain pattern includes a peripheral lower source / drain layer and a peripheral upper source / drain layer located on the peripheral lower source / drain layer. Wherein, the impurity concentration of the upper source / drain layer of the unit is higher than the impurity concentration of the lower source / drain layer of the unit, and The concentration of impurities in the outer upper source / drain layer is higher than the concentration of impurities in the outer lower source / drain layer.

18. A semiconductor device, said semiconductor device comprising: A first structure, the first structure including a storage area and a peripheral area; as well as A second structure, which overlaps perpendicularly with the first structure and includes peripheral circuitry, The storage area includes: Vertical active pattern of the unit; A unit gate electrode, the unit gate electrode having a side surface facing the side surface of the active pattern perpendicular to the unit; The cell has a source / drain pattern and a cell contact plug, wherein the source / drain pattern and the cell contact plug are disposed on the vertical active pattern of the cell, and the source / drain pattern is located between the vertical active pattern of the cell and the cell contact plug; Cell isolation patterns, the cell isolation patterns being located on the side surfaces of the source / drain patterns on the cell and the side surfaces of the cell contact plugs; and A data storage structure is located on the unit contact plug and the unit isolation pattern. The peripheral area includes: Peripheral vertical active pattern; A peripheral gate electrode having a side surface facing the side surface of the peripheral active pattern perpendicular to the periphery; The peripheral source / drain pattern and the peripheral contact plug are disposed on the peripheral vertical active pattern, and the peripheral source / drain pattern is located between the peripheral vertical active pattern and the peripheral contact plug; A peripheral isolation pattern, wherein the peripheral isolation pattern is located on the side surface of the peripheral source / drain pattern and the side surface of the peripheral contact plug; and Upper interconnect, the upper interconnect being located on the peripheral contact plug and the peripheral isolation pattern, The source / drain pattern on the unit includes a first unit source / drain layer and a second unit source / drain layer stacked sequentially. The peripheral source / drain pattern includes a first peripheral source / drain layer and a second peripheral source / drain layer stacked sequentially. The peripheral circuit includes a first lower transistor that overlaps perpendicularly to the storage region and a second lower transistor that overlaps perpendicularly to the peripheral region. The unit contact plug comprises a lower conductive layer and an upper conductive layer of the unit stacked sequentially. The peripheral contact plug comprises a lower peripheral conductive layer and an upper peripheral conductive layer stacked sequentially. The lower conductive layer of the unit and the lower conductive layer of the periphery include a first conductive material. Wherein, the conductive layer on the unit and the conductive layer on the periphery include a second conductive material different from the first conductive material, and The upper interconnect includes a third conductive material that is different from the first conductive material and the second conductive material.

19. The semiconductor device of claim 18, further comprising: An insulating gasket covers the upper surface of the unit isolation pattern, the upper surface of the unit contact plug, the side surface of the upper interconnect, and the upper surface of the upper interconnect. The data storage structure includes a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode. The first electrode is connected to the unit contact plug, penetrates the insulating gasket, and extends upward.

20. The semiconductor device according to claim 18, in, The unit vertical active pattern and the peripheral vertical active pattern comprise monocrystalline silicon. Wherein, each of the first unit source / drain layer and the first peripheral source / drain layer includes a first polysilicon layer, and Each of the second unit source / drain layer and the second peripheral source / drain layer includes a second polysilicon layer.

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