A micro-current and voltage measuring device

Abstract

The application provides a micro-current and voltage measuring device, belonging to the field of semiconductor devices, comprising a collector region, a base region, a central emitter region, a guard ring surrounding the central emitter region, a high-resistance region between the central emitter region and the guard ring, and a quenching resistor; the central emitter region and the collector region can be silicon materials, and the base region can be a germanium-silicon material; the central emitter region and the base region form an emitter junction, the guard ring and the base region form a guard ring junction, and the collector region and the base region form a collector junction; the central emitter region and the guard ring are homotypically heavily doped, the high-resistance region is a homotypically lightly doped region of the central emitter region, or the high-resistance region is a homotypically heavily doped region of the central emitter region and is relatively thin; during operation of the device, the emitter junction is forward biased, the guard ring junction is reverse biased, and the base region under the guard ring is partially or completely depleted; the collector junction is reverse biased, and the working voltage of the collector junction is greater than the avalanche breakdown voltage thereof. Compared with existing devices, the device of the application can accurately measure smaller electrical signals.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology for measuring minute currents and voltages. Background Technology

[0002] In the fields of electroencephalography (EEG), electrocardiography (ECG), electromyography (EMG), and terahertz signals, extremely weak current / voltage signals (such as single-electron-level electrical signals) are often submerged in noise backgrounds (down to picoampere-level currents or nanovolt-level voltages). Measuring these signals is a core foundational capability supporting cutting-edge scientific exploration and key engineering technologies. The measurement of extremely weak current / voltage signals relies on high-precision, low-noise, and wide dynamic range detection techniques. For example, signal detection can be achieved by counting individual electron events. Although this method can be implemented using a single-electron transistor (SET), it requires highly complex device fabrication techniques and is currently difficult to widely apply.

[0003] US Patent Publication No. US20100013458A1 and the article "Electron counting at room temperature in an avalanche bipolar transistor" by Lany et al. (APPLIEDPHYSICS LETTERS, Vol. 92, no. 022111, January 14, 2008) disclose a single-electron bipolar avalanche transistor (SEBAT), which is a weak signal measurement device that combines the advantages of a single-electron transistor (SET) and a Geiger-mode avalanche bipolar transistor for measuring ultra-small currents (such as single-electron level). SEBAT devices have a base, emitter, collector, and avalanche quenching resistor. The base is drawn from the base region, the emitter from the emitter region, and the collector from the collector region. A collector junction is formed between the base and collector regions, and an emitter junction is formed between the base and emitter regions. Both the collector and emitter junctions are PN junctions. The avalanche quenching resistor is connected in series with the collector junction and is used for quenching and recovering from avalanche breakdown. The collector junction is designed to operate in reverse bias as an avalanche diode, operating above the avalanche breakdown voltage. The collector junction operates similarly to a single-photon avalanche diode (SPAD). Figure 1The diagram shows the circuit schematic of an NPN-type SEBAT device. Unlike SPAD devices, which are triggered by a single photon, SEBAT devices are triggered by a single electron. For single-electron detection operation, the bias voltage Vcc on the collector C is set higher than the collector junction breakdown voltage. If a negative voltage is applied to the emitter E, the emitter junction is forward biased, and minority carriers (such as electrons) are injected from the emitter region into the base region, resulting in an emitter current. I E The emitter current I E Part of this includes emitter electrons that overcome the potential barrier between the emitter and base regions to reach the collector junction. That is, minority carriers injected into the base region diffuse to the strongly reverse-biased collector junction, triggering the avalanche multiplication process and generating significant, detectable avalanche current pulses. I A By counting the number of pulses per unit time using an external counting circuit, the ultra-small current or voltage signal introduced through the emitter can be quantized into an electronic pulse count at the collector, thus achieving single-electron-level current or voltage measurement. Quenching resistor R Q The combination of the collector junction and the collector junction creates an avalanche quenching circuit that generates an output voltage pulse. V OUT It is used to reset SEBAT after breakdown. Figure 1 middle, The inherent capacitance of the PN junction formed by the collector and base regions. I R This indicates that after the avalanche ends, the collector passes through the avalanche quenching circuit to the capacitor. The charging current during recharging. V CB This represents the voltage between the collector (C) and base (B). The ability of the SEBAT device concept to detect single electrons in real time at room temperature has been demonstrated by Lany et al. However, a key issue with existing SEBAT devices is the ratio of the collector output pulse count to the number of electrons injected at the emitter (i.e., the common-base current gain coefficient). Extremely low (approximately 0.01% or The extremely low common-base current gain coefficient limits the device's ability to reliably detect the smallest electrical signal (such as a single electron charge) because the emitter current in a SEBAT device does not come from a macroscopic current source, but may come from a photocurrent generated by a single photon, a single electron tunneling event, or other extremely small charges to be measured. This severely limits the practical application of SEBAT devices and the smallest electrical signal size that can actually be measured.

[0004] Therefore, there is an urgent need for a novel SEBAT structure that can improve the common-base current gain coefficient in order to improve the detection limit of SEBAT devices. Summary of the Invention

[0005] Therefore, embodiments of the present invention provide a micro current and voltage measurement device that improves the common-base current gain coefficient by modifying the emitter structure of existing SEBAT devices. This improves the detection limit of the SEBAT device.

[0006] One aspect of the present invention provides a small current and voltage measuring device, which is an improved single-electron bipolar avalanche transistor (SEBAT) device. The SEBAT device includes: an emitter structure, a collector region, a base region, an emitter, a base, a collector, and a quenching resistor connected in series with the collector junction. The emitter structure includes a central emitter region, a guard ring surrounding the central emitter region, and a high-resistance region located between the central emitter region and the guard ring. The emitter is led out from the central emitter region, and the guard ring has a guard ring terminal. The guard ring is connected to the central emitter region through the high-resistance region.

[0007] An emitter junction is formed between the center emitter region and the base region, a collector junction is formed between the collector region and the base region, and a guard ring junction is formed between the guard ring and the base region. The center emitter region and the guard ring are heavily doped regions of the same type. The sheet resistance of the high-resistance region is higher than that of the center emitter region and the guard ring, which is used to reduce the bias current between the center emitter region and the guard ring.

[0008] When a SEBAT device is in operation, its base is grounded, its emitter junction is forward biased, its guard ring junction is reverse biased, its collector junction is reverse biased, and the reverse bias voltage of the collector junction is greater than its avalanche breakdown voltage.

[0009] In some embodiments of the present invention, the bias voltage of the guard ring junction is set such that the base region under the reverse-biased guard ring junction is completely depleted; or, the bias voltage of the guard ring junction is set such that the base region under the reverse-biased guard ring junction is partially depleted.

[0010] In some embodiments of the present invention, the SEBAT device is an NPN structure, the central emitter region and guard ring are N-type heavily doped monocrystalline silicon structures or polycrystalline silicon structures, and the high-resistance region is an N-type monocrystalline silicon structure or polycrystalline silicon structure.

[0011] In some embodiments of the present invention, the central emitter region, the guard ring, and the high-resistance region are monocrystalline silicon structures, the base region is a monocrystalline germanium-silicon structure, and the collector region is a monocrystalline silicon structure.

[0012] In some embodiments of the present invention, the avalanche quenching resistor is a polysilicon strip resistor located on the surface of the device; or the avalanche quenching resistor is an epitaxial layer resistor of the collector region directly below the electric field enhancement region; or the avalanche quenching resistor is a lateral resistor of the base region below the guard ring junction that does not belong to the depletion region, and the magnitude of the avalanche quenching resistor is adjusted by the reverse bias voltage of the guard ring junction.

[0013] In some embodiments of the present invention, the SEBAT device further includes a field limiting ring, a field plate, or a junction termination extension structure disposed at the collector junction to prevent the edge of the collector junction from being prematurely broken down.

[0014] In some embodiments of the present invention, the horizontal cross-section of the central emission region is circular, and the diameter of the central emission region is 0.1~100μm;

[0015] The horizontal cross-section of the protective ring is circular, and the minimum ring width of the protective ring is 0.1 μm;

[0016] The minimum distance between the central launch area and the inner contour line of the protective ring is 2 μm.

[0017] In some embodiments of the present invention, the high-resistance region is a lightly doped region of the same type as the central emitter region, and the thickness of the high-resistance region is not greater than that of the central emitter region; or

[0018] The high-resistivity region is a heavily doped region of the same type as the central emitter region, and the thickness of the high-resistivity region is smaller than that of the central emitter region.

[0019] In some embodiments of the present invention, the SEBAT device further includes one or more electric field enhancement regions located in the collector region directly below the central emitter region, and the doping concentration of the electric field enhancement regions is higher than that of the main body of the collector region; for multiple electric field enhancement regions, similar to epitaxial resistance quenching silicon photomultipliers (GQ Zhang et al., “Demonstration of a silicon photomultiplier with bulk integrated quenching resistors on epitaxial silicon”, Nuclear Instruments and Methods in Physics Research A, A, 621 (2010) 116–120), the intrinsic bulk resistance of the epitaxial layer is used as the avalanche quenching resistor, and when there are three or more electric field enhancement regions, adjacent electric field enhancement regions are equally spaced, and all electric field enhancement regions are completely covered by the central emitter region.

[0020] This invention proposes a device for measuring minute current and voltage. By creatively incorporating a guard ring into the emitter structure of the SEBAT device, surface recombination current at the emitter junction edge can be effectively suppressed, overcoming the limitations of existing SEBAT technology in measuring ultra-small current / voltage signals. The problem of excessively low values ​​increases the detection limit of SEBAT devices.

[0021] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows, and will also become apparent in part to those skilled in the art upon studying the description, or may be learned by practice of the invention. The objects and other advantages of the invention can be realized and obtained by means of the structures specifically pointed out in the description and drawings.

[0022] Those skilled in the art will understand that the objectives and advantages achievable with the present invention are not limited to those specifically described above, and that the above and other objectives achievable with the present invention will become clearer from the following detailed description. Attached Figure Description

[0023] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, are not intended to limit the scope of the invention. The components in the drawings are not drawn to scale but are merely illustrative of the principles of the invention. For ease of illustration and description of certain parts of the invention, corresponding portions in the drawings may be enlarged, i.e., may appear larger relative to other components in an exemplary device actually manufactured according to the invention. In the drawings:

[0024] Figure 1 This is the circuit schematic for the SEBAT device.

[0025] Figure 2A This is a schematic cross-sectional view of a SEBAT device in one embodiment of the present invention, in which a Si-GeSi heterojunction is used between the emitter structure and the base region, the high-resistivity region and the central emitter region have the same doping concentration but are thinner, and the lateral resistance of the base region under the guard ring junction is an avalanche quenching resistance.

[0026] Figure 2B This is a schematic cross-sectional view of a SEBAT device comprising a polycrystalline silicon emitter structure, a monocrystalline silicon base region, and a monocrystalline silicon collector region in one embodiment of the present invention; the doping concentration of the high-resistance region is lower than that of the central emitter region and the guard ring region, and the thickness of the high-resistance region is the same as that of the central emitter region; and the polycrystalline silicon strip resistor on the surface serves as an avalanche quenching resistor.

[0027] Figure 2C This is a schematic cross-sectional view of a SEBAT device in one embodiment of the present invention, which includes a multi-unit avalanche enhancement region distributed at equal intervals, uses the bulk resistance of a single-crystal silicon epitaxial layer as the avalanche quenching resistance, has a high resistance region with a lower doping concentration than the central emitter region and the guard ring region, and has the same thickness as the central emitter region. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.

[0029] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.

[0030] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, element, step, or component, but does not exclude the presence or addition of one or more other features, elements, steps, or components.

[0031] It should also be noted that, unless otherwise specified, the term "connection" in this article can refer not only to a direct connection, but also to an indirect connection involving an intermediary.

[0032] In the following description, embodiments of the invention will be illustrated with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar parts, or the same or similar steps.

[0033] SEBAT devices, used for measuring minute currents and voltages, differ significantly from traditional bipolar junction transistors (BJTs) in their operating principles. The core of a BJT is linear amplification achieved through a "minority carrier + diffusion + collection" mechanism. Operating in a non-breakdown state of the collector junction, minority carriers injected into the emitter junction diffuse across the base region, with most reaching the collector junction to form the collector current, and a small portion recombinating in the emitter junction and base region to form the base current. This base current linearly amplifies and modulates the output current. In contrast, the collector junction of a SEBAT device is biased above the breakdown voltage. It utilizes a single-electron event as a "seed" to trigger a controlled, quenchable avalanche current pulse in a carefully biased avalanche region. SEBAT devices have extremely low operating currents (i.e., emitter currents). In conventional SEBAT device structures, minority carriers at the emitter junction can generate recombination currents, especially at the emitter junction edge, where the recombination current accounts for a very high proportion of the emitter current. In other words, when the emitter current generated by electron injection into the forward-biased emitter junction is very small, the common-base current gain coefficient is very low. The current decreases significantly, mainly because when the emitter current is very small, most of the minority carriers (e.g., electrons) injected from the emitter region into the base region are recombinated in the emitter junction depletion region, especially recombination at the surface depletion region of the emitter junction edge. This results in very few carriers effectively injected into the base region and diffused into the collector region, thus causing... The value is extremely low.

[0034] To address the limitation on the detection limit of ultra-small current or voltage signals caused by the extremely low common-base current gain coefficient in SEBAT devices, which differ from traditional BJTs, the inventors of this application have conducted extensive research. The inventors believe that the limitation caused by the extremely low common-base current gain coefficient in SEBAT devices... The fundamental reason for the low value is that the SEBAT device operates in an ultra-low current mode. Therefore, this application improves the common-base current gain coefficient for ultra-low current and voltage signal measurements by modifying the emitter structure of the SEBAT device. .

[0035] Specifically, this application innovatively incorporates a protective ring surrounding the emitter region to significantly improve the common-base current gain coefficient under ultra-low current conditions. According to semiconductor PN junction theory, minority carrier recombination only occurs in the depletion region of a forward-biased PN junction, while it does not occur in a reverse-biased PN junction. Therefore, during operation, the SEBAT device maintains a forward bias in the emitter junction formed by the central emitter region and the base region to ensure carrier injection and flow towards the base region, while the guard ring junction formed by the outer guard ring of the central emitter region and the base region remains reverse-biased. This effectively reduces the surface recombination current at the emitter junction edge, improving performance during low-current measurements. Furthermore, the bias voltage applied to the guard ring can be set such that the reverse-biased guard ring can completely or partially deplete its lower base region, blocking the current path between the center emitter region and the base, and minimizing the surface recombination current at the emitter junction edge.

[0036] The SEBAT device proposed in this application includes: an emitter structure, a collector region, a base region, an emitter electrode, a base electrode, a collector electrode, a guard ring terminal, and a quench resistor connected in series with the collector junction. The emitter structure includes a central emitter region, a guard ring surrounding the central emitter region, and a high-resistance region located between the central emitter region and the guard ring. The sheet resistance of the high-resistance region is higher than the sheet resistance of the central emitter region and the sheet resistance of the guard ring. The emitter electrode is led out from the central emitter region, and the guard ring terminal is led out from the guard ring. The guard ring is connected to the central emitter region through the high-resistance region. An emitter junction is formed between the central emitter region and the base region, a collector junction is formed between the collector region and the base region, and a guard ring junction is formed between the guard ring and the base region. The central emitter region and the guard ring are homogeneous heavily doped regions, and the high-resistance region is used to reduce the bias current between the central emitter region and the guard ring.

[0037] When the SEBAT device is in operation, the base is grounded, the emitter junction is forward biased, the guard ring junction and the collector junction are reverse biased, and the reverse bias voltage of the collector junction is greater than its avalanche breakdown voltage.

[0038] Figures 2A to 2C The following are cross-sectional schematic diagrams of the SEBAT device in different embodiments of the present invention. Please refer to... Figures 2A to 2CIn SEBAT devices, the central emitter region is used to inject minority carriers into the base region, and the doping concentration of the central emitter region is higher than that of the base and collector regions. To prevent short circuit between the central emitter region and the guard ring, the central emitter region and the guard ring in this application are arranged in a non-direct contact manner, and the region between the central emitter region and the guard ring has a high sheet resistance (high sheet resistance is relative to the sheet resistance of the central emitter region and the guard ring), so as to reduce the bias current flowing through the region between the central emitter region and the guard ring (the bias current is formed based on the potential difference between the central emitter region and the guard ring when the SEBAT device is operating). In this application, the region between the central emitter region and the guard ring can be called a high-resistance region. The high-resistance region can be defined as the region formed by the inner surface of the guard ring (the surface near the central emitter region) and the outer surface of the central emitter region. The high-resistance region can have a high sheet resistance relative to the central emitter region and the guard ring by selecting ion implantation or adding etching processes.

[0039] In some embodiments of this application, in order to improve The guard ring is designed to suppress carrier injection into the base region from the edge surface of the emitter junction; therefore, the guard ring is placed around the center emitter region.

[0040] In this embodiment, the structure of the central emitter region, the region between the central emitter region and the guard ring (i.e., the high-resistance region), and the guard ring combination serves as the emitter structure. The size of the emitter structure in this SEBAT device can be no smaller than the emitter region size in existing SEBAT devices. Similarly, the sizes of the collector region and base region can be no smaller than the collector region and base region sizes in existing SEBAT devices, respectively.

[0041] As an example, the various regions in the emitter structure can be designed as follows: the horizontal cross-section of the central emitter region is circular, and the diameter of the central emitter region is 0.1~100μm; the horizontal cross-section of the guard ring is annular, and the minimum ring width of the guard ring is 0.1μm; the minimum distance between the outer surface of the central emitter region and the inner surface of the guard ring is 2μm. This application does not specifically limit the shape and size of the central emitter region and the guard ring, as long as it can ensure that the guard ring surrounds the central emitter region and can suppress the recombination current on the emitter junction surface. For example, the central emitter region can be designed to be smaller in size to improve the signal-to-noise ratio.

[0042] In this application's SEBAT device, the emitter structure, base region, and collector region can be arranged in the same positions as in existing SEBAT devices. For example, the base region and the central emitter region can be designed side-by-side or form a ring-finger structure, and the collector region can be led out through a deep well / buried layer or located on the periphery of the base region. In this application, the central emitter region, guard ring, and collector region all have contact interfaces with the base region. Therefore, an emitter junction is formed between the central emitter region and the base region in the SEBAT device, a collector junction is formed between the collector region and the base region, and a guard ring junction is formed between the guard ring and the base region. In this application, the emitter junction, collector junction, and guard ring junction are all PN junctions.

[0043] In some embodiments of this application, to achieve the functions of the central emitter region and the guard ring, a selective doping process can be employed. The central emitter region is prepared as a heavily doped region, the guard ring is a heavily doped region with the same doping type as the central emitter region, and the high-resistivity region is a lightly doped or heavily doped region with the same doping type as the central emitter region. The doping concentrations of the central emitter region, the high-resistivity region, and the guard ring are relative. More specifically, the high-resistivity region is a lightly doped region with the same doping type as the central emitter region, and the thickness of the high-resistivity region is no greater than that of the central emitter region. Figure 2B and Figure 2C As shown, the thickness of the high-resistivity region is equal to that of the central emitter region; or the high-resistivity region is a heavily doped region of the same doping type as the central emitter region, but the high-resistivity region is thinner, that is, the thickness of the high-resistivity region is smaller than that of the central emitter region, such as... Figure 2A As shown. Figures 2A to 2C This is merely an example and is not limited to it. Other variations are possible as long as the sheet resistance of the high-resistance region is higher than that of the sheet resistance of the central emitter region and the sheet resistance of the guard ring.

[0044] The improved SEBAT device provided in this application effectively suppresses surface recombination current at the emitter junction edge due to the guard ring design, thereby improving the base transport factor and emitter efficiency, and consequently significantly increasing the common-base current gain coefficient. The higher common-base current gain coefficient directly increases the ratio of collector output pulse count to emitter injected electron count, thus improving the detection limit and sensitivity of single-electron detection.

[0045] In some embodiments of this application, single-crystal silicon material can be used to fabricate the emitter structure in the SEBAT device, such as... Figure 2A and Figure 2C As shown. Alternatively, the emission structure can also be fabricated using polycrystalline silicon material, such as... Figure 2BAs shown. As an example, when the SEBAT device is an NPN structure, the central emitter region and guard ring can be N+ type monocrystalline silicon or polycrystalline silicon structures, and the high-resistance region can be N+ or N- type monocrystalline silicon or polycrystalline silicon structures. Compared to monocrystalline silicon, SEBAT devices with emitter structures made of polycrystalline silicon have a higher common-base current gain coefficient, and when the doping concentration is the same in all regions of the emitter structure, the high-resistance region made of polycrystalline silicon has a higher sheet resistance.

[0046] As an example, this application can also use germanium-silicon technology to fabricate SEBAT devices. For instance, when the SEBAT device is an NPN structure, the central emitter region, guard ring, and high-resistance region can be single-crystal silicon structures, the base region can be a single-crystal germanium-silicon alloy structure, and the collector region can be a single-crystal silicon structure. That is, the central emitter region, guard ring, and high-resistance region are fabricated using single-crystal silicon material, the base region is fabricated using single-crystal germanium-silicon material, and the collector region is fabricated using single-crystal silicon material. In this way, the silicon-germanium-silicon (Si-GeSi) heterojunction has a lower barrier height and higher carrier injection efficiency. At the same time, it can use a lower doping concentration in the central emitter region, a lower doping concentration in the high-resistance region, and a higher doping concentration in the base region, which is beneficial for reducing power consumption and heat generation in the high-resistance region and improving low-current efficiency. The value reduces the dark count rate.

[0047] In a SEBAT device, the emitter, extending from the central emitter region, receives the electrical signal under test and forms a current loop between the central emitter region and an external path (such as a voltage supply device), thereby forward-biasing the emitter junction and injecting charge carriers. The SEBAT device also includes a guard ring terminal connected to a guard ring. This guard ring terminal can be biased with a voltage to form a current loop between the guard ring and the external path (such as a voltage supply device), ensuring the guard junction is reverse-biased during SEBAT device operation. The emitter and guard ring terminal are non-contact to prevent short circuits. The SEBAT device may also include a collector extending from the collector region and a base extending from the base region; the collector collects charge carriers from the collector region, forming a collector current that is output to an external counter circuit. In this application, the emitter, guard ring terminal, collector, and base can be metal electrodes, etc., and this application does not limit their material types.

[0048] In some embodiments of this application, a quenching resistor connected in series with the collector junction is used to quench and terminate the avalanche breakdown process. That is, after a single electron event injecting into the central emitter region causes an avalanche breakdown, the voltage drop across the quenching resistor increases rapidly due to the rapid increase in the avalanche current, causing the voltage applied to the collector junction to drop rapidly below the avalanche breakdown voltage, thus quenching and terminating the avalanche breakdown process. Furthermore, after quenching is complete, as the current flowing through the quenching resistor decreases, the voltage drop across the quenching resistor decreases, causing the voltage applied to the collector junction to return to the initial operating voltage (greater than the avalanche breakdown voltage of the collector junction). The SEBAT device then re-enters electron counting mode to detect the next injected electron. The quenching resistor can be a channel resistor located in the base region below the reverse bias guard ring junction (i.e., the lateral resistance of the base region below the guard ring junction that is not part of the depletion region, the magnitude of which can be adjusted using the reverse bias voltage of the guard ring junction), or the epitaxial layer resistance of the collector region directly below the electric field enhancement region, or a polysilicon strip resistor on the device surface. The first two quenching resistor schemes disclosed in this invention do not require additional fabrication steps, thus reducing the manufacturing cost of SEBAT devices. The quenching resistor is connected in series with the collector junction, and its value can be selected from 50 to 500 kΩ to optimize the amplitude, width, and recovery time of the avalanche pulse.

[0049] In some embodiments of this application, the SEBAT device may further include a field limiting ring, field plate, or junction termination extension (JTE) disposed at the collector junction to prevent premature breakdown at the edge of the collector junction. Furthermore, the operation of the collector junction in existing SEBAT technology is similar to that of a single-photon avalanche photodiode, with a limited single-electron count rate, restricting the dynamic range. To overcome this deficiency, during the fabrication of the SEBAT device, the region directly below the central emitter region in the collector region can be selectively heavily doped to increase its doping concentration, thereby increasing its electric field strength. This ensures that avalanche breakdown always occurs in the region directly below the central emitter region in the collector region. This selectively heavily doped region directly below the central emitter region can be referred to as the electric field enhancement region. In this case, the collector region may include a main collector region and an electric field enhancement region. The SEBAT device proposed in this application may include one or more electric field enhancement regions that can be completely covered by the central emitter region. When there are three or more electric field enhancement regions, adjacent electric field enhancement regions are equally spaced. By increasing the number of electric field enhancement regions in existing SEBAT devices, the total single-electron count rate can be improved.

[0050] In some embodiments of this application, when the SEBAT device is in operating mode, the center emitter region is forward biased relative to the base region, and the guard ring is reverse biased relative to the base region; that is, the emitter junction is forward biased, and the guard ring junction is reverse biased. Furthermore, when the SEBAT device is operating, the emitter junction is forward biased to inject carriers into the base region when electrons to be counted (i.e., the electrical signal to be measured) are injected, the collector junction is reverse biased, and the operating voltage of the collector junction is greater than its avalanche breakdown voltage (for example, the avalanche breakdown voltage of the collector junction can be designed to be 15~30V to ensure that the SEBAT device operates in a stable avalanche multiplication region). This application does not specifically limit the magnitude of the bias voltage applied to the center emitter region, guard ring, and collector region; as long as they are in a specific bias state, that is sufficient.

[0051] When the SEBAT device is operating, the base is grounded and the guard ring junction is reverse biased. The bias voltage applied to the guard ring terminals can induce the formation of a partial or complete depletion region in the base region beneath the guard ring junction. This depletion region effectively prevents carriers at the emitter junction edge from being injected into the base region, eliminating edge surface recombination paths. The depletion region formed by the emitter structure and the base region is as follows: Figures 2A to 2C As shown.

[0052] Avalanche quenching resistors can be polycrystalline silicon strip resistors located on the surface of the device, such as... Figure 2B As shown, or, the avalanche quenching resistance can be the epitaxial layer resistance of the main body of the collector region directly below the central emitter region, such as... Figure 2C As shown, alternatively, the avalanche quenching resistor can be the transverse resistance of the neutral base region below the protection loop junction that is not part of the depletion region, such as... Figure 2A As shown.

[0053] In some embodiments of this application, the specific process of performing electrical signal measurement using the SEBAT device described in any of the above embodiments can be as follows:

[0054] Signal input: The minute current generated by the minute current signal or the minute voltage signal to be measured (such as a single-electron-level current or voltage signal) is injected into the center emitter region through the emitter (input terminal).

[0055] Central emitter injection: After receiving the electrical signal to be measured, the central emitter region injects minority carriers (electrons) into the base region.

[0056] Carrier transport: Carriers (electrons) injected from the central emitter region diffuse in the base region and reach the collector junction, which is in a reverse bias state and has an operating voltage higher than the avalanche breakdown voltage.

[0057] Avalanche multiplication, avalanche breakdown quenching, and pulse generation: When one or more electrons reach the depletion region of a high-field collector junction, the avalanche breakdown process is triggered by the avalanche multiplication effect, generating a significantly amplified current pulse (avalanche current) that can be easily detected by external circuitry (such as an external counter circuit). The quenching resistor senses the rapid increase in the avalanche current, causing the voltage applied to the collector junction to drop. When the voltage drops below the avalanche breakdown voltage, the avalanche breakdown process is quenched and terminated, during which a pulsed electrical signal is formed and output. The avalanche current pulses output from the collector are counted by an external counter circuit (e.g., counting the number of pulses per unit time), thereby achieving the measurement of the electrical signal under test. Each avalanche current pulse corresponds to an electron event. Furthermore, after quenching is complete, the quenching mechanism can perform a recharging process, restoring the voltage applied to the collector junction to the initial operating voltage (i.e., greater than the collector junction avalanche breakdown voltage), preparing for the detection of the next injected electron.

[0058] SEBAT devices measure signals by converting weak signals into electronic pulse counts. The process of calculating the measured electrical signal using electronic pulse counting is as follows:

[0059] Electronic count value (i.e., the number of avalanche current pulses obtained by counting with an external counter circuit) The number of electrons injected into the emitter The relationship is By precise counting The minute current or voltage signal to be measured can then be accurately deduced using the following formula (the voltage signal to be measured can be converted into an electrical signal to be measured through a known impedance):

[0060] ;

[0061] in, The elementary charge is the amount of charge carried by one electron. , This represents the current signal to be measured.

[0062] In some embodiments of the present invention, Figure 2A Taking the NPN structure SEBAT device shown as an example, the exemplary fabrication process of this SEBAT device is as follows:

[0063] 1. Epitaxial wafer preparation and silicon layer growth:

[0064] An N-type single-crystal silicon epitaxial wafer (the epitaxial wafer is a bilayer structure containing N- and N+) is selected, and the N- part is used as the collector region; a P-type germanium silicon layer (single-crystal germanium silicon) is grown on it using molecular beam epitaxy (MBE) technology, and an N+ single-crystal silicon layer is grown on the P-type germanium silicon layer.

[0065] 2. Define the active region

[0066] Defining the active region refers to marking out the "core area" where the transistor actually works on the epitaxial wafer after the above growth. The active region is defined by photolithography and mesa selective etching, and a thick layer of silicon dioxide is deposited by PECVD for passivation protection.

[0067] 3. Preparation of the base contact region

[0068] A base contact window is opened at a predetermined position on the P-type germanium-silicon layer, and a P+ contact region is selectively formed in the germanium-silicon layer by photolithography, selective boron ion implantation, and annealing processes.

[0069] 4. Fabrication of the emission structure

[0070] High-resistance region windows are opened at predetermined high-resistance region locations on the N+ single-crystal silicon layer using photolithography and etching processes, and the thickness is reduced by dry etching and other methods.

[0071] The central emitter contact window and the guard ring contact window are opened at specific locations on the N+ single crystal silicon layer using processes such as photolithography and etching.

[0072] Figure 2A In the example shown, the doping concentrations of the central emitter region, the high-resistivity region, and the guard ring are the same. The thickness of the high-resistivity region is less than that of the central emitter region, and the sheet resistance of the high-resistivity region is higher than that of the central emitter region and the guard ring.

[0073] 5. Avalanche enhancement and electric field modulation

[0074] In the collector region opposite the central emitter region, N-type buried layer doping is performed by phosphorus or arsenic implantation to form an electric field enhancement region with a higher doping concentration than the main part of the collector region, so that the avalanche region is concentrated below the central emitter region.

[0075] 6. Electrode generation

[0076] A metal layer (such as aluminum, copper, or TiN composite layer, with a thickness of about 1000-2000 nm) is deposited, and then photolithography and etching are used to form metal terminals that connect the base region, guard ring, and central emitter region, thus forming the base, guard ring terminal, and emitter.

[0077] The epitaxial wafer is thinned on the back side, and a collector electrode is formed on the back side by means of methods such as vapor deposition of metal layers.

[0078] In the above-prepared structure, the channel resistance (connected in series with the collector junction) in the base region below the protection ring junction is used as a quenching resistor to quench avalanche breakdown.

[0079] In addition, a field plate structure can be fabricated in the edge region of the collector junction, specifically including: depositing a 200nm SiO2 dielectric layer above the collector region, and covering the dielectric layer with a metal field plate at the same potential as the collector region, extending more than 0.5μm beyond the base region.

[0080] against Figure 2B The exemplary fabrication process of the SEBAT device shown is as follows:

[0081] 1. Substrate preparation:

[0082] For example, a P-type single-crystal silicon substrate with a resistivity of about 10-20 Ω·cm can be used.

[0083] 2. Buried layer formation

[0084] A selected area on the prepared P-type single-crystal silicon substrate is subjected to high-energy, high-dose phosphorus ion implantation and annealing to form an N+ buried layer. The N+ buried layer can reduce the collector series resistance.

[0085] 3. Define the active region

[0086] and Figure 2A The corresponding processes are similar, the difference being that selective ion implantation is used instead of selective mesa etching.

[0087] 4. Fabrication of collector and base regions

[0088] An N-type collector region is formed by performing operations such as phosphorus ion implantation and annealing on selected collector regions in the substrate.

[0089] A P-type base region (highly doped single-crystal silicon) can be formed above the collector region through photolithography, selective boron ion implantation, and annealing processes.

[0090] 5. Fabrication of the emission structure

[0091] First, a layer of polysilicon (such as about 200-300nm thick, but not limited to) is deposited at the pre-defined emission structure position above the base region.

[0092] High-resistivity windows are formed at predetermined low-dose doping sites on a polycrystalline silicon layer through processes such as photolithography and etching. N-type high-resistivity regions (low-doped polycrystalline silicon) are formed through photolithography and low-dose phosphorus or arsenic implantation.

[0093] A central emitter window and a guard ring window are formed at predetermined high-dose doping sites on a polycrystalline silicon layer using photolithography and etching processes. An N+ type central emitter region (highly doped polycrystalline silicon) and a guard ring region (highly doped polycrystalline silicon) located at the edge of the emitter region are formed by photolithography and high-dose phosphorus (or arsenic) implantation.

[0094] Figure 2BIn the example shown, the doping concentration of the high-resistivity region is lower than that of the central emitter region and the guard ring region, and the thickness of the high-resistivity region is equal to that of the central emitter region.

[0095] 6. Avalanche enhancement and electric field modulation

[0096] In the collector region directly below the central emitter region, N-type buried layer doping is performed by phosphorus or arsenic implantation to form an electric field enhancement region with a higher doping concentration than the main body of the collector region.

[0097] 7. Electrode generation

[0098] High-concentration N-type ion implantation (N+) is performed at predetermined N- positions in the active region to form a low-resistance channel and ohmic contact region connecting the N+ buried layer. High-concentration P-type ion implantation (P+) is performed at predetermined positions in the base region to form a low-resistance ohmic contact region. A SiO2 insulating layer is deposited on the upper surface of the fabricated device to achieve electrical isolation. Metal deposition windows are formed above the corresponding low-resistance ohmic contact regions, central emitter region, and guard ring in the collector and base regions by photolithography etching of the SiO2 insulating layer, and metal layers (such as aluminum, copper, or TiN composite layers, with a thickness of about 100-200 nm) are deposited to form metal terminals connecting the collector region, base region, guard ring, and central emitter region, respectively, thus forming the collector, base, guard ring terminal (ring electrode), and emitter.

[0099] In addition, a polycrystalline silicon layer can be deposited on the SiO2 insulating layer, and polycrystalline silicon strip resistors can be formed by ion implantation doping, annealing, photolithography, and etching, and used as avalanche quenching resistors.

[0100] against Figure 2C The exemplary fabrication process of the SEBAT device shown is as follows:

[0101] 1. Epitaxial wafer preparation

[0102] N-type single-crystal silicon epitaxial wafers are selected (the epitaxial wafer is a double-layer structure containing N- and N+).

[0103] 2. Define the active region

[0104] and Figure 2B The corresponding process is the same.

[0105] 3. Preparation of the base region

[0106] A P-type base region is formed at a selected base region location using photolithography, selective boron ion implantation, and annealing processes.

[0107] 4. Fabrication of the emission structure

[0108] By using photolithography and low-dose phosphorus or arsenic implantation, an N-type high-resistivity region (low-doped single-crystal silicon) is formed at a selected high-resistivity region location, and an N+ type central emitter region and an N+ type guard ring (high-doped single-crystal silicon) are formed at a selected central emitter region location and a selected guard ring location.

[0109] Figure 2C In the example shown, there is no need to perform a thinning process on the high-resistance region. The doping concentration of the high-resistance region is lower than that of the central emitter region and the guard ring region, and the thickness of the high-resistance region is equal to that of the central emitter region, so that the sheet resistance of the high-resistance region is higher than that of the central emitter region and the sheet resistance of the guard ring.

[0110] 5. Avalanche enhancement and electric field modulation

[0111] In the N-epitaxial wafer located directly below the central emitter region and below the base region, N-type doping is performed by phosphorus or arsenic implantation to form three equally spaced electric field enhancement regions (the doping concentration of the electric field enhancement regions is higher than that of the main part of the collector region).

[0112] When the device is working, the N-type epitaxial wafer below the electric field enhancement region can serve as the main part of the collector region to collect charge carriers, while the N- part of the epitaxial wafer that does not belong to the collector region, base region and central emitter region is the depletion region. Furthermore, the inherent bulk resistance of the epitaxial layer that forms the collector region can serve as a quenching resistor for quenching avalanche breakdown.

[0113] 6. Electrode generation

[0114] The fabrication process of the SiO2 insulating layer, collector, base, guard ring terminal, and emitter is the same as that of the collector. Figure 2A The example shown.

[0115] The main improvement of this application lies in overcoming the limitations of existing SEBAT technology in measuring ultra-small current / voltage signals by configuring the emitter structure containing a central emitter region, a high-resistance region, and a guard ring, as well as configuring the PN junction bias state. The problem of excessively low values ​​increases the detection limit of the SEBAT device. Therefore, the fabrication process will not be described in detail. The SEBAT device of this application can be easily fabricated using existing processes. More specifically, the SEBAT device structure proposed in this application is compatible with standard BCD (Bipolar-CMOS-DMOS) processes, requiring no special process steps, and is suitable for large-scale, low-cost manufacturing.

[0116] In some specific embodiments of this application, the common-base current gain coefficient of the proposed SEBAT device is determined by referring to the current transport characteristics of a bipolar transistor. Perform theoretical estimation.

[0117] In the SEBAT device proposed in this application, the guard ring structure can suppress the minority carrier recombination current on the outer surface of the emitter junction. The minority carrier injection current density formed by the forward bias emitter junction, the minority carrier recombination current density inside the emitter junction, and the common-base current gain coefficient approximately satisfy the following formula (refer to Sze, SM (2002). Semiconductor devices: Physics and technology (2nd ed.). John Wiley & Sons.):

[0118] ;

[0119] ;

[0120] ;

[0121] in,

[0122] ;

[0123] ;

[0124] in, This represents the current density formed when minority carriers injected into the emitter junction are finally collected by the collector junction. This represents the minority carrier recombination current density within the emitter junction. Represents the emitter current density. Indicates the electron diffusion coefficient. Indicates intrinsic carrier concentration. Indicates the applied voltage. Represents Boltzmann's constant. Represents absolute temperature. Indicates carrier lifetime. Represents the dielectric constant. Indicates the built-in potential. Represents the elementary charge. Indicates the base area width. Indicates the acceptor doping concentration in the base region. Indicates the donor doping concentration. This indicates that the width has been exhausted.

[0125] The following assumptions are made in the theoretical estimation: , , , , , , ,at this time The theoretical estimation results of the value are shown in Table 1. From Table 1, it can be seen that... = to Within the range, The minimum loss is 0.59%, compared to the experimental results of the SEBAT device without a guard ring (0.01%). The SEBAT device proposed in this application can achieve this. The value increased by more than 59 times.

[0126] Table 1 Theoretical estimation results of the value

[0127]

[0128] The SEBAT device proposed in this application is suitable for current measurements from the femtoampere (fA) to the microampere (μA) level, or voltage measurements from the nanovolt (nV) to the millivolt (mV) level. The improved SEBAT structure provided in this application has the following significant advantages:

[0129] ① Significantly improved Value: The guard ring design effectively eliminates surface recombination current at the emitter junction edge, improving both the base transport factor and emitter efficiency. Theoretical calculations and simulations show that the SEBAT device proposed in this application can improve the common-base current gain coefficient under ultra-low current operation. The improvement rate has increased from approximately 0.01% in existing technologies to a range of 0.59% to 4%, and even higher. The value can directly reduce the equivalent input noise current, improve the signal-to-noise ratio, and increase the detection limit and sensitivity of single-electron detection.

[0130] ② Extremely low power consumption design: The high resistance region ensures that there is only a very small leakage current between the center emitter region and the protection ring terminal.

[0131] ③ Improve performance stability: Low power consumption can effectively reduce device temperature rise, thereby improving the temperature stability and long-term reliability of the device.

[0132] ④ Excellent process compatibility: The SEBAT device structure proposed in this application is compatible with standard BCD (Bipolar-CMOS-DMOS) process, requiring no special process steps, and is suitable for large-scale, low-cost manufacturing.

[0133] The SEBAT device proposed in this application has a simple structure and high efficiency. It boasts high compatibility with mainstream CMOS / BCD manufacturing processes. It provides an ideal solution for high-precision, high-sensitivity, and room-temperature real-time measurement of ultra-small currents (such as fA-level currents) and weak voltages at the single-electron level. This contributes to the development of cutting-edge fields such as quantum computing readout, single-molecule detection, nanoscale electrical characterization, high-energy physics, and ultrasensitive sensing, demonstrating significant technological advantages and broad application prospects.

[0134] Those skilled in the art will understand that the exemplary components, systems, and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software, or a combination of both. Whether implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention. When implemented in hardware, it can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this invention are programs or code segments used to perform the desired tasks. The programs or code segments can be stored in a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried in a carrier wave.

[0135] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention.

[0136] In this invention, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or in place of features of other embodiments.

[0137] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations of the embodiments of the present invention are possible. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A microcurrent and voltage measuring device, said measuring device being an improved single-electron bipolar avalanche transistor (SEBAT) device, the SEBAT device comprising: The emitter structure, collector region, base region, emitter, base, collector electrode, and quenching resistor connected in series with the collector junction are characterized in that the emitter structure includes a central emitter region, a protective ring surrounding the central emitter region, and a high-resistance region located between the central emitter region and the protective ring; the emitter is led out from the central emitter region, the protective ring has a protective ring terminal, and the protective ring is connected to the central emitter region through the high-resistance region; An emitter junction is formed between the central emitter region and the base region, a collector junction is formed between the collector region and the base region, and a guard ring junction is formed between the guard ring and the base region; the central emitter region and the guard ring are heavily doped regions of the same type, and the sheet resistance of the high-resistance region is higher than the sheet resistance of the central emitter region and the sheet resistance of the guard ring, which is used to reduce the bias current between the central emitter region and the guard ring. When the SEBAT device is in operation, the base is grounded, the emitter junction is forward biased, the guard ring junction is reverse biased, the collector junction is reverse biased, and the reverse bias voltage of the collector junction is greater than its avalanche breakdown voltage. Wherein, the high-resistance region is a lightly doped region of the same type as the central emitter region, and the thickness of the high-resistance region is not greater than that of the central emitter region; or The high-resistance region is a heavily doped region of the same type as the central emitter region, and the thickness of the high-resistance region is smaller than that of the central emitter region.

2. The device according to claim 1, characterized in that, The guard ring terminal is used to apply a bias voltage so that the guard ring junction can be reverse biased.

3. The device according to claim 2, characterized in that, The bias voltage is set such that the base region beneath the reverse-biased guard ring junction is partially or completely depleted.

4. The device according to claim 1, characterized in that, The SEBAT device has an NPN structure, the central emitter region and the guard ring are N-type heavily doped monocrystalline silicon or polycrystalline silicon structures, and the high-resistance region is an N-type monocrystalline silicon or polycrystalline silicon structure.

5. The device according to claim 1, characterized in that, The central emitter region, guard ring, and high-resistance region are monocrystalline silicon structures, the base region is a monocrystalline germanium-silicon structure, and the collector region is a monocrystalline silicon structure.

6. The device according to claim 1, characterized in that, The SEBAT device further includes at least one electric field enhancement region located in the collector region directly below the central emitter region, and the doping concentration of the electric field enhancement region is higher than that of the main body of the collector region. When there are three or more electric field enhancement regions, adjacent electric field enhancement regions are distributed at equal intervals and are completely covered by the central emission region.

7. The device according to claim 1, characterized in that, The quenching resistor is used to quench and terminate the avalanche breakdown process. The quenching resistor is a channel resistor located in the base region below the reverse bias protection ring junction, or a polysilicon strip resistor on the device surface, or an epitaxial layer resistor in the collector region directly below the electric field enhancement region.

8. The device according to claim 1, characterized in that, The SEBAT device also includes a field limiting ring, a field plate, or a junction termination extension structure disposed at the collector junction to prevent the edge of the collector junction from being prematurely broken down.

9. The device according to claim 1, characterized in that, The horizontal cross-section of the central emission region is circular, and the diameter of the central emission region is 0.1~100μm; The horizontal cross-section of the protective ring is circular, and the minimum ring width of the protective ring is 0.1 μm; The minimum distance between the central launch area and the inner contour line of the protective ring is 2 μm.

10. The device according to claim 7, characterized in that, The quenching resistor located in the base region below the reverse bias protection ring junction is adjusted by the reverse bias voltage of the protection ring junction.

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