Shield gate trench type MOSFET manufacturing method for controlling IPO thickness

Abstract

The invention discloses a shield gate trench type MOSFET manufacturing method for controlling IPO thickness, and relates to the technical field of semiconductors. Etching a groove on the epitaxial wafer, then filling photoresist, and exposing to the top of the groove; then performing wet etching on the side wall oxide layer to a specified depth; removing the photoresist; then, 100 to 400 thermal oxide layers are grown; the preparation method comprises the following steps of: depositing 100 to 400 percent of Nitride (Si3N4); depositing a thin oxide layer; depositing polycrystalline silicon; etching the polycrystalline silicon to a specified depth; carrying out thermal oxidation on the polycrystalline silicon to a specified thickness; performing wet etching on the thin oxide layer on the side wall of the groove; performing hot phosphoric acid etching on the thin Nitride on the side wall of the groove; performing wet etching on the thin oxide layer on the side wall of the groove; growing a gate oxide layer, and depositing gate polycrystalline silicon to form a gate electrode; and then completing subsequent processes such as body region injection and trap pushing, source electrode injection and annealing, interlayer dielectric deposition and the like according to a traditional process, and finally forming a complete structure of the shield gate type trench MOSFET. By means of the manufacturing method, the shield gate type trench MOSFET capable of accurately controlling the IPO thickness is formed, the technological parameter variables are few, the technology is simple, and the manufacturing cost is low.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a manufacturing method of a shield gate trench MOSFET for controlling IPO thickness. BACKGROUND

[0002] As a kind of high-performance power semiconductor device, shield gate trench MOSFET (SGT-MOSFET for short) is widely used in new energy vehicles, smart grid, industrial control, consumer electronics and other core fields due to its low on-resistance, low switching loss, high voltage resistance and other advantages. With the increasing requirements of downstream applications on the energy efficiency, integration and reliability of power devices, the manufacturing process precision and performance stability of SGT-MOSFET are required to be more stringent.

[0003] The mainstream manufacturing process of existing SGT-MOSFET is based on epitaxial silicon substrate, and its core process can be summarized as follows: first, an N-type lightly doped epitaxial layer is grown on an N-type heavily doped substrate as a drift region; then a deep trench structure is formed in the epitaxial layer by defining a trench pattern through lithography and using a dry etching process, and the depth and sidewall perpendicularity of the deep trench directly affect the voltage resistance and current density of the device; then a thick oxide layer is grown on the inner wall of the deep trench and the surface of the epitaxial layer, which is used to preliminarily isolate the subsequent conductive polysilicon; then the polysilicon is filled by using a chemical vapor deposition (CVD) process to cover the deep trench and the surface of the epitaxial layer; the excess polysilicon on the surface of the epitaxial layer is removed by chemical mechanical polishing (CMP) and dry etching process, and the polysilicon in the deep trench is etched and thinned to form a shield gate at the lower part of the deep trench; then a wet etching process is used to remove the remaining thick oxide layer above the shield gate in the deep trench to reserve space for the preparation of the subsequent gate structure; the key step is to grow an isolation oxide layer (IPO for short) between the gate and the shield gate, which is the core structure to ensure the electrical isolation between the shield gate and the gate; then a gate oxide layer is grown on the inner wall of the deep trench and the surface of the epitaxial layer, and a gate polysilicon is filled by a CVD process, and the gate polysilicon is made flush with the surface of the silicon wafer by lithography, etching and CMP process to form a gate at the upper part of the deep trench; finally, subsequent processes such as P-type body region ion implantation and high-temperature push-well annealing, N-type source ion implantation and activation annealing, interlayer dielectric (ILD) deposition, contact hole etching, metallization and passivation are performed in sequence, and finally a complete SGT-MOSFET device is formed.

[0004] In the aforementioned manufacturing process, the quality of the IPO layer is one of the key factors determining the electrical characteristics of the SGT-MOSFET. Existing technologies commonly employ a "one-step" IPO growth scheme, where the IPO layer is grown in a single step via thermal oxidation or CVD. However, this scheme suffers from insurmountable technical bottlenecks: after the deep trench undergoes polysilicon etching of the shielding gate and wet etching of the thick oxide layer, the width of the polysilicon at the top of the shielding gate within the trench exhibits process deviations. Furthermore, the morphology of the trench sidewalls and the top of the shielding gate after wet etching easily forms irregular chamfers or residues, resulting in an uneven substrate surface state during IPO layer growth. Specifically, the growth environment varies in different regions within the trench (such as the top edge of the shielding gate and the middle of the trench sidewalls), making it impossible to maintain a consistent IPO layer growth rate. This ultimately leads to significant non-uniformity in the thickness of the resulting IPO layer—the IPO layer tends to be thinner at trench corners and thicker in straight areas of the trench sidewalls, with a large overall variation in IPO layer thickness, making precise control impossible.

[0005] The uncontrollable nature of the IPO layer thickness and morphology has a fatal impact on the core electrical characteristics of SGT-MOSFETs, severely restricting the improvement of device performance and industrial application. Firstly, uneven IPO layer thickness leads to significant dispersion in the parasitic capacitances (Cgs, Cgd) between the gate and the shield gate. Fluctuations in Cgs affect the switching response speed of the device, while instability in Cgd increases switching losses and reduces the device's energy efficiency. Secondly, the thin areas of the IPO layer are prone to electric field concentration, which leads to a significant increase in leakage current (IGSS, IGSSR) between the gate and the shield gate. In severe cases, it can cause gate insulation breakdown, which greatly reduces the reliability and lifespan of the device. Third, morphological defects in the IPO layer will further exacerbate the uneven growth of the gate oxide layer, forming a chain reaction that leads to problems such as threshold voltage (Vth) drift and increased on-resistance (Rdson) of the device. Fourth, in order to compensate for the performance fluctuations caused by the uncontrollable thickness of the IPO layer, the existing technology can only reserve a safety margin by increasing the design thickness of the IPO layer. This will not only further increase the parasitic capacitance and sacrifice the switching performance of the device, but also increase the process complexity and manufacturing cost, which is contrary to the development trend of "high efficiency and low cost" of power devices.

[0006] In summary, the uncontrollable thickness and morphology of the IPO layer in the existing SGT-MOSFET manufacturing process, particularly the one-step forming technology, has become a key technical bottleneck restricting the stability of device electrical characteristics, performance improvement, and industrial competitiveness. Currently, no effective solution has been proposed in the industry to overcome this bottleneck. Achieving precise control over the IPO layer thickness and uniformity of its morphology, thereby optimizing core electrical parameters such as Cgs / Cgd / IGSS / IGSSR, improving device energy efficiency and reliability, and reducing manufacturing costs, is a pressing technical challenge for those skilled in the art and a core requirement driving the iterative upgrade of SGT-MOSFET technology. Summary of the Invention

[0007] To address the above problems, this invention provides a method for manufacturing shielded gate trench MOSFETs that controls the IPO layer thickness to achieve precise control over the thickness, thereby optimizing the core electrical parameters of the device and improving the performance stability of the device.

[0008] The technical solution of this invention is: A method for manufacturing a shielded gate trench MOSFET with controlled IPO thickness includes the following steps: Step 1: Substrate preparation and epitaxial growth; Step 2: Trench etching; Step 3: Growth of the first oxide layer within the trench; Step 4: Remove residual photoresist after etching the first oxide layer on the trench sidewalls; Step 5: Growth of the second thermal oxide layer; Step 6: Deposit silicon nitride layers on the surface of the second oxide layer and the surface of the first oxide layer; Step 7: Deposit a third oxide layer on the surface of the silicon nitride layer; Step 8: Fill and etch the shielding gate polysilicon in the trench and on the surface of the epitaxial layer; Step 9: Thermal oxidation of the polysilicon on top of the shielding gate to grow a fourth oxide layer of a predetermined thickness; Step 10: Wet etching of the thin oxide layer on the trench sidewalls; Step 11: Etching the silicon nitride layer on the trench sidewalls; Step 12: Etching the remaining oxide layer on the trench sidewalls; Step 13: Growing a gate oxide layer on the inner wall of the trench and the surface of the epitaxial layer; Step 14: Gate polysilicon deposition and etching; Gate polysilicon is filled in the trench and on the surface of the epitaxial layer. After the gate pattern is defined by photolithography, the excess gate polysilicon is etched by dry etching process. Then, the gate polysilicon is flush with the surface of the silicon wafer through a process to form the gate located on the upper part of the deep trench.

[0009] Specifically, in step 5, a second oxide layer with a thickness of 100 Å to 400 Å is grown on the inner wall of the trench using a thermal oxidation process.

[0010] Specifically, in step 6, the silicon nitride thickness is 100 Å to 400 Å.

[0011] Specifically, in step 7, the thickness of the third oxide layer is no greater than 1000 Å.

[0012] Specifically, in step 12, a wet etching process is used to etch the residual oxide layer on the sidewall of the deep trench, so that a smooth and uniform insulating interface is formed on the inner wall of the trench.

[0013] Specifically, after step 14 is completed, P-type body region ion implantation is performed sequentially, followed by a high-temperature push-in annealing process to fully diffuse and activate the implanted P-type impurities and form a body region. Then, N-type source ion implantation is performed, followed by activation annealing to activate the N-type impurities and form the source. The interlayer dielectric is deposited using CVD technology to cover the silicon wafer surface; the interlayer dielectric is etched using photolithography and dry etching processes to form contact holes; a metal layer is deposited using sputtering technology, and a metal interconnect structure is formed using photolithography and etching; finally, a passivation process is performed to deposit a passivation layer on the surface of the metal layer, completing the final fabrication of the device and forming a structurally complete shielded gate trench MOSFET.

[0014] This invention employs conventional processes to etch trenches on an epitaxial wafer, fill them with photoresist, and expose the top of the trench. Then, the sidewall oxide layer is wet-etched to a specified depth; the photoresist is removed; a 100Å~400Å thermal oxide layer is grown; a 100Å~400Å Nitride (Si3N4) layer is deposited; a thin oxide layer is deposited; polysilicon is deposited; the polysilicon is etched to a specified depth; the polysilicon is thermally oxidized to a specified thickness; the thin oxide layer on the trench sidewalls is wet-etched; the thin Nitride layer on the trench sidewalls is etched with thermal phosphoric acid; the thin oxide layer on the trench sidewalls is wet-etched again; a gate oxide layer is grown; and then gate polysilicon is deposited to form the gate. Subsequent processes, including body implantation and push-in, source implantation and annealing, and interlayer dielectric deposition, are then completed according to conventional processes, finally forming the complete structure of a shielded gate trench MOSFET. This manufacturing method produces a shielded gate trench MOSFET with precisely controllable IPO thickness, few process parameter variables, simple process, and low manufacturing cost. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure in which the first oxide layer grows within the trench; Figure 2 This is a schematic diagram of the structure for removing the photoresist at the top of the trench; Figure 3This is a schematic diagram of the structure after wet etching of the sidewall oxide layer to a specified depth; Figure 4 This is a schematic diagram of the structure after the photoresist has been removed; Figure 5 This is a schematic diagram of the growth structure of the second oxide layer; Figure 6 This is a schematic diagram of the structure after the silicon carbide layer is deposited; Figure 7 This is a schematic diagram of the structure of the deposited third oxide layer; Figure 8 This is a schematic diagram of the structure after filling with polycrystalline silicon; Figure 9 This is a schematic diagram of the structure after polysilicon has been etched to a set position; Figure 10 This is a schematic diagram of the structure of polycrystalline silicon after thermal oxidation to a specified thickness; Figure 11 This is a schematic diagram of the structure after etching the sidewall oxide layer; Figure 12 This is a schematic diagram of the silicon nitride layer structure on the sidewall of the etched trench; Figure 13 This is a schematic diagram of the structure for etching the second oxide layer on the sidewall; Figure 14 This is a schematic diagram of the structure after the growth of the gate oxide layer; Figure 15 This is a schematic diagram of the deposited and etched gate polysilicon structure; Figure 16 This is a schematic diagram of the structure after the present invention has been prepared. Detailed Implementation

[0016] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0017] To address the problems of large fluctuations in electrical parameters and yield loss caused by the inability to precisely control the IPO thickness in existing technologies, this application mainly provides a shielded gate trench MOSFET manufacturing process that allows for precise control of IPO thickness. This process has fewer variable process parameters, is simpler, and has lower manufacturing costs. The specific solution is as follows: A method for manufacturing a shielded gate trench MOSFET with controlled IPO thickness. Step 1: Substrate preparation and epitaxial growth; An N-type heavily doped silicon substrate is selected, and an N-type lightly doped epitaxial layer is epitaxially grown on the substrate surface using chemical vapor deposition (CVD) to form the drift region of the device. Step 2: Trench etching; The trench pattern is defined by photolithography, and a deep trench structure with a preset depth and width is formed by dry etching in the epitaxial layer. After etching, the sidewalls of the trench are cleaned to remove etching residue. Step 3: Growth of the first oxide layer within the trench; A first oxide layer is grown on the inner wall of the trench and the surface of the epitaxial layer using a thermal oxidation process. This first oxide layer is used to initially isolate the polysilicon that will be filled later, thus ensuring the insulation performance of the shielded gate. Then, a spin-coating process is used to uniformly coat the silicon wafer surface, trenches, and upper part with photoresist, such as... Figure 1 As shown, the pattern is then transferred to the photoresist using a photolithography process, leaving the photoresist within the trenches (exposed to the top of the trenches), while the photoresist in the remaining areas is removed by exposure; as... Figure 2 As shown; Step 4: Remove residual photoresist after wet etching of the first oxide layer on the trench sidewall; Using the retained photoresist as a mask, a wet etching process is employed to etch the thick oxide layer in the areas of the deep trench sidewalls not covered by the photoresist, continuing until a preset depth is reached, thus achieving precise thinning of the sidewall oxide layer. Then, a plasma ashing combined with wet cleaning process is used to thoroughly remove residual photoresist from the silicon wafer surface and within the trenches. Figures 3-4 As shown; Step 5: Growth of the second thermal oxide layer; like Figure 5 As shown, a second oxide layer with a thickness of approximately 100 Å to 400 Å is grown on the inner wall of the trench and the surface of the epitaxial layer using a thermal oxidation process, providing a flat substrate surface for the subsequent deposition of silicon nitride (Si3N4, Nitride) layers; Step 6: Nitride layer deposition; like Figure 6 As shown, silicon nitride (Si3N4, Nitride) layers with a thickness of approximately 100Å to 400Å are deposited on the surface of the second oxide layer and the surface of the first oxide layer using a CVD process. This layer is used to help achieve precise control of the thickness of the IPO layer. Step 7: Deposition of a thin oxide layer; like Figure 7 As shown, a third oxide layer is deposited on the surface of the silicon nitride layer using a CVD process to further optimize the interface state of subsequent polysilicon filling; the thickness of the third oxide layer in this case is less than 1000 Å. Step 8: Filling and etching the shielding gate with polysilicon; like Figures 8-9As shown, polysilicon is filled in the trench and on the surface of the epitaxial layer using CVD process. Then, chemical mechanical polishing (CMP) is used to remove excess polysilicon from the surface of the epitaxial layer, making the polysilicon surface flush with the surface of the epitaxial layer. Then, photolithography and dry etching processes are used to etch and thin the polysilicon in the deep trench to a preset depth, forming a shielding gate located at the bottom of the deep trench. Step 9: Thermal oxidation of the polysilicon on top of the shielding gate; like Figure 10 As shown, the polysilicon on top of the etched shielding gate is subjected to thermal oxidation to grow a fourth oxide layer of a predetermined thickness. This oxide layer is a core component of the IPO layer and achieves preliminary isolation between the shielding gate and the subsequent gate. Step 10: Wet etching of the thin oxide layer on the trench sidewalls; like Figure 11 As shown, a wet etching process is used to etch the oxide layer located on the sidewall of the trench above the fourth oxide layer; Step 11: Etching the silicon nitride layer on the trench sidewalls; like Figure 12 As shown, a hot phosphoric acid etching process is used to etch the silicon nitride layer located on the trench sidewall above the fourth oxide layer, precisely removing this layer to expose the underlying fourth oxide layer and ensuring the insulation consistency of the IPO layer. Step 12: Etching the remaining oxide layer on the trench sidewalls; like Figure 13 As shown, a wet etching process is used again to etch the residual oxide layer on the sidewall of the deep trench, so that a smooth and uniform insulating interface is formed on the inner wall of the trench. Step 13: Gate oxide layer growth; like Figure 14 As shown, a gate oxide layer is grown on the inner wall of the deep trench and the surface of the epitaxial layer using a thermal oxidation process. This layer serves as an insulating layer between the gate and the semiconductor substrate, ensuring the switching control performance of the gate. Step 14: Gate polysilicon deposition and etching; like Figure 15 As shown, gate polysilicon is filled in the deep trench and on the surface of the epitaxial layer by CVD process. After the gate pattern is defined by photolithography, the excess gate polysilicon is etched by dry etching process. Then, the gate polysilicon is flush with the silicon wafer surface by CMP process to form the gate located on the upper part of the deep trench. The process involves sequentially implanting P-type body ions, followed by a high-temperature push-in annealing process to fully diffuse and activate the implanted P-type impurities, forming the body region. Next, N-type source ion implantation is performed, followed by activation annealing to activate the N-type impurities and form the source. Interlayer dielectric (ILD) is deposited using CVD to cover the silicon wafer surface. The interlayer dielectric is then etched using photolithography and dry etching to form contact holes. A metal layer is deposited using sputtering, and the metal interconnect structure is formed using photolithography and etching. Finally, a passivation process is performed to deposit a passivation layer on the metal layer surface, completing the final fabrication of the device and forming a structurally complete shielded gate trench MOSFET.

[0018] This invention, following conventional processes, completes trench etching and thick oxide layer growth within the trench, fills the trench with photoresist, and exposes it to the top of the trench. Then, it wet-etches the sidewall oxide layer to a specified depth; removes the photoresist; re-grows a 100Å~400Å thermal oxide layer; deposits a 100Å~400Å Nitride (Si3N4); deposits a thin oxide layer; deposits polysilicon; etches the polysilicon to a specified depth; thermally oxidizes the polysilicon to a specified thickness; wet-etches the thin oxide layer on the trench sidewalls; thermally etches the thin Nitride layer on the trench sidewalls; wet-etches the thin oxide layer on the trench sidewalls; grows a gate oxide layer; and then deposits gate polysilicon to form the gate. Subsequent processes, including body implantation and push-in, source implantation and annealing, and interlayer dielectric deposition, are then completed according to conventional processes, finally forming a complete structure of a shielded gate trench MOSFET.

[0019] The manufacturing method described in this case forms a shielded gate trench MOSFET structure with precisely controllable IPO thickness, significantly improving the controllability of adjusting gate leakage current and device capacitance. With fewer process parameter variables and a simpler process, compared to traditional one-step molding processes, it not only retains the high-quality thermal oxide layer of traditional one-step molding processes but also significantly increases the IPO thickness for better isolation of the gate polysilicon and shielding of the gate polysilicon, while precisely controlling the IPO thickness to achieve stable and controllable gate-source leakage current and gate capacitance. Compared to traditional HDP processes, it can precisely control the IPO thickness while avoiding high-cost processes such as Oxide HDP CVD and Oxide CMP. It also avoids the risks of large-scale fluctuations in gate capacitance and gate-source isolation leakage caused by the superposition of process fluctuations during the IPO formation process of rough processes such as Oxide HDP CVD, Oxide CMP, and wet etching of the oxide layer.

[0020] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method for manufacturing a shielded gate trench MOSFET with controlled IPO thickness, characterized in that, Includes the following steps: Step 1: Substrate preparation and epitaxial growth; Step 2: Trench etching; Step 3: Growth of the first oxide layer within the trench; Step 4: Remove residual photoresist after etching the first oxide layer on the trench sidewalls; Step 5: Growth of the second thermal oxide layer; Step 6: Deposit silicon nitride layers on the surface of the second oxide layer and the surface of the first oxide layer; Step 7: Deposit a third oxide layer on the surface of the silicon nitride layer; Step 8: Fill and etch the shielding gate polysilicon in the trench and on the surface of the epitaxial layer; Step 9: Thermal oxidation of the polysilicon on top of the shielding gate to grow a fourth oxide layer of a predetermined thickness; Step 10: Wet etching of the thin oxide layer on the trench sidewalls; Step 11: Etching the silicon nitride layer on the trench sidewalls; Step 12: Etching the remaining oxide layer on the trench sidewalls; Step 13: Growing a gate oxide layer on the inner wall of the trench and the surface of the epitaxial layer; Step 14: Gate polysilicon deposition and etching; Gate polysilicon is filled in the trench and on the surface of the epitaxial layer. After the gate pattern is defined by photolithography, the excess gate polysilicon is etched by dry etching process so that the gate polysilicon is flush with the surface of the silicon wafer, forming the gate located on the upper part of the deep trench.

2. The method for manufacturing a shielded gate trench MOSFET with controlled IPO thickness according to claim 1, characterized in that, Step 5 involves using a thermal oxidation process to grow a second oxide layer with a thickness of 100 Å to 400 Å on the inner wall of the trench.

3. The method for manufacturing a shielded gate trench MOSFET with controlled IPO thickness according to claim 1, characterized in that, In step 6, the thickness of silicon nitride is 100 Å to 400 Å.

4. The method for manufacturing a shielded gate trench MOSFET with controlled IPO thickness according to claim 1, characterized in that, In step 7, the thickness of the third oxide layer is no greater than 1000 Å.

5. The method for manufacturing a shielded gate trench MOSFET with controlled IPO thickness according to claim 1, characterized in that, In step 12, a wet etching process is used to etch the residual oxide layer on the sidewall of the deep trench, so that a smooth and uniform insulating interface is formed on the inner wall of the trench.

6. The method for manufacturing a shielded gate trench MOSFET with controlled IPO thickness according to claim 1, characterized in that, After step 14 is completed, P-type body region ion implantation is performed sequentially, followed by high-temperature push-in annealing process to fully diffuse and activate the implanted P-type impurities and form a body region. Then, N-type source ion implantation is performed, followed by activation annealing to activate the N-type impurities and form the source. Interlayer dielectrics are deposited using CVD technology to cover the silicon wafer surface; Contact holes are formed by etching the interlayer dielectric through photolithography and dry etching processes; A metal layer is deposited using a sputtering process, and a metal interconnect structure is formed through photolithography and etching. Finally, a passivation process is performed to deposit a passivation layer on the surface of the metal layer, completing the final fabrication of the device and forming a structurally complete shielded trench MOSFET.

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