GaN HEMT all-dielectric suspension field plate device and preparation method thereof

Abstract

The invention discloses a GaN HEMT (High Electron Mobility Transistor) all-dielectric suspension field plate device and a preparation method thereof. The device comprises a GaN buffer layer, a GaN channel layer and a nitride barrier layer which are sequentially epitaxially grown on a substrate, the source electrode, the drain electrode, the grid electrode and the passivation layer are formed above the nitride barrier layer; the gradient aperture metasurface is formed above the passivation layer; the gradient aperture metasurface forms an all-dielectric suspension field plate, is formed between a grid electrode and a drain electrode in an electrical suspension state, and comprises dielectric microstructure units which are arranged periodically, the arrangement period of the units is 100-600 nm, and the characteristic size of the units is in monotonic gradient change in the direction from the grid electrode to the drain electrode. The monotonic gradient change comprises linear, exponential and Gaussian gradient change. The gradient aperture metasurface is adopted as the all-dielectric suspension field plate, electric field optimization is achieved through the space gradient design of the dielectric metasurface, stray capacitance can be eliminated, and electromagnetic wave regulation and control and heat management are achieved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of wide bandgap semiconductor power electronic devices, and particularly relates to a GaN HEMT full dielectric floating field plate device and a preparation method thereof. BACKGROUND

[0002] GaN HEMT (Gallium Nitride High Electron Mobility Transistor) is widely used in 5G base stations, electric vehicles, radars and satellite communications due to its high breakdown electric field (> 3 MV / cm), high electron saturation velocity and high power density. However, it has a problem of electric field concentration in the gate-drain region under high voltage bias, which easily causes premature breakdown, current collapse and dynamic on-resistance degradation.

[0003] Traditional solutions include metal field plates and dielectric field plates. The metal field plate can effectively modulate the electric field, but introduces significant gate-drain parasitic capacitance (Cgd), limiting high-frequency performance; the dielectric field plate reduces parasitic effects, but lacks the ability to actively regulate the electric field distribution. In recent years, metasurface technology has made breakthroughs in electromagnetic wave regulation, and its subwavelength artificial micro-nano structure can achieve local field modulation. However, the concept of metasurface has not been introduced into radio frequency power semiconductor devices, especially the construction of gradient aperture, full dielectric, electrically floating field plate structures, which has not been reported. In addition, existing field plates often ignore the need for thermal management, making it difficult to address local hot spot problems under high power density. SUMMARY

[0004] The purpose of the present application is to provide a GaN HEMT full dielectric floating field plate device and a preparation method thereof, which uses a gradient aperture metasurface as a full dielectric floating field plate, realizes electric field optimization through the spatial gradient design of the dielectric metasurface, and can eliminate parasitic capacitance, achieve electromagnetic wave regulation and thermal management.

[0005] To achieve the above-mentioned purpose, one aspect of the present application provides a GaN HEMT full dielectric floating field plate device, comprising: a GaN buffer layer, a GaN channel layer and a nitride barrier layer epitaxially grown in sequence on a substrate; a source, a drain, a gate and a passivation layer formed above the nitride barrier layer; and a gradient aperture metasurface formed above the passivation layer. The gradient aperture metasurface constitutes a full dielectric floating field plate and is formed in an electrically floating state between the gate and the drain, and includes periodically arranged dielectric microstructure units, the arrangement period of the microstructure units is 100-600 nm, the characteristic size of the microstructure units is 50-500 nm, and the microstructure units monotonically change along the direction from the gate to the drain, and the monotonous gradient change includes linear, exponential and Gaussian type gradient changes.

[0006] Another aspect of the present application provides a preparation method of the above-mentioned GaN HEMT full dielectric floating field plate device, comprising: Step S1, sequentially epitaxially growing a GaN buffer layer, a GaN channel layer and a nitride barrier layer on a substrate; Step S2, preparing a source and a drain ohmic contact and a gate Schottky contact of the device on the nitride barrier layer; Step S3, depositing a passivation layer on the entire surface of the device by chemical vapor deposition; Step S4, depositing a dielectric layer above the passivation layer, and forming a gradient-aperture metasurface structure as a full-dielectric floating field plate in the dielectric layer by a nano-patterning process, the nano-patterning process including electron beam lithography, nano-imprinting and self-assembly.

[0007] According to the GaN HEMT full-dielectric floating field plate device and the preparation method thereof of the above aspect of the present application, the gradient-aperture metasurface is used as the full-dielectric floating field plate, the electric field is optimized by the spatial gradient design of the dielectric metasurface, and the parasitic capacitance can be eliminated, so that the electromagnetic wave regulation and control and the thermal management are realized. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings: Figure 1 is a cross-sectional structure schematic diagram of the GaN HEMT full-dielectric floating field plate device of the embodiment 1 of the present application; Figure 2 is a top surface schematic diagram of the GaN HEMT full-dielectric floating field plate device of the embodiment 1 of the present application; Figure 3 is a cross-sectional structure schematic diagram of the GaN HEMT full-dielectric floating field plate device of the embodiment 2 of the present application; Figure 4 is a top surface schematic diagram of the GaN HEMT full-dielectric floating field plate device of the embodiment 2 of the present application; Figure 5 is a cross-sectional structure schematic diagram of the GaN HEMT full-dielectric floating field plate device of the embodiment 3 of the present application; Figure 6 is a top surface schematic diagram of the GaN HEMT full-dielectric floating field plate device of the embodiment 3 of the present application. DETAILED DESCRIPTION

[0009] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below in conjunction with the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0010] The embodiment of the present application provides a GaN HEMT full dielectric suspended field plate device, which comprises a GaN buffer layer, a GaN channel layer, an AlGaN (or AlN, InAlN, ScAlN, etc. nitride barrier layer, and the typical thickness is 5-25 nm), a source electrode, a drain ohmic contact, a gate Schottky contact, a passivation layer (SiN x , SiO2, etc.), and a full dielectric suspended field plate which is composed of a gradient aperture super surface, the material is a dielectric with a dielectric constant ≥4 or a thermal conductivity ≥50 W / m·K, the microstructure unit period is 100-600 nm, and the characteristic size (aperture or column diameter or width) is monotonically gradient changed (linear / exponential / Gaussian type) along the gate to the drain direction. The suspended field plate is not connected with any electrode and is in an electrically floating state. The device can further comprise a GaN or in-situ SiNx cap layer above the nitride barrier layer.

[0011] The dielectric material of the full dielectric suspended field plate can be a composite of dielectric materials with different dielectric constants or thermal conductivities, and the composite mode includes filling, coating or embedding, etc. The formed microstructure unit is a nano hole or a nano column, and the material is a high dielectric constant dielectric material with a dielectric constant ≥4 or a high thermal conductivity dielectric material with a thermal conductivity ≥100 or a composite material of the two. The high dielectric constant dielectric material includes SiN x , HfO2, Al2O3, HfSiON and ZrO2, and the high thermal conductivity dielectric material includes AlN, BN, SiC and diamond. The gradient change function of the gradient aperture is a linear function, an exponential function or a Gaussian function, the period is 100-600 nm, and the aperture is 50-500 nm. The gradient characteristic size super surface has functions of electric field regulation, parasitic capacitance regulation, super surface electromagnetic wave regulation, thermal diffusion enhancement or stress regulation, etc.

[0012] The embodiment of the present application further provides a preparation method of a GaN HEMT full dielectric suspended field plate device, which comprises the following steps. Step S1, sequentially epitaxially growing a GaN buffer layer, a GaN channel layer and a nitride barrier layer on a substrate; Step S2, preparing a source electrode and a drain ohmic contact and a gate Schottky contact of the device on the nitride barrier layer; Step S3, depositing a passivation layer on the whole device surface by plasma-enhanced chemical vapor deposition. Step S4: Deposit a dielectric layer above the passivation layer, and form a gradient aperture metasurface structure in the dielectric layer as an all-dielectric suspended field plate through a nanopatterning process. The nanopatterning process includes electron beam lithography, nanoimprinting, self-assembly and other processes.

[0013] The following three embodiments detail the GaN HEMT all-dielectric suspended field plate device and its fabrication method according to the present invention.

[0014] Example 1: GaN HEMT device based on gradient aperture metasurface all-dielectric suspended field plate Step S1: Substrate and Epitaxial Structure Fabrication like Figure 1 and Figure 2 As shown, SiC single-crystal substrate 101 was selected due to its combination of high thermal conductivity (~370 W / m·K) and good lattice matching. The following layers were epitaxially grown sequentially using a metal-organic chemical vapor deposition (MOCVD) system: GaN buffer layer 102: 1.5 μm thick, Fe-doped for high resistivity; GaN channel layer 103: 200 nm thick, unintentionally doped; Al₂O₃... 25 Ga0. 75 N barrier layer 104: 20 nm thick, undoped; GaN cap layer 105: 1-2 nm thick, surface passivated with NH3 to reduce interface defects.

[0015] Step S2: Preparation of Ohmic and Schottky Contacts Source 201 / Drain 202 Ohmic Contact: A multilayer metal of Ti (20 nm) / Al (100 nm) / Ni (40 nm) / Au (60 nm) was sequentially deposited by electron beam evaporation, followed by rapid thermal annealing (RTA) at 850°C for 30 seconds in a N2 atmosphere to form a low-resistance ohmic contact (specific contact resistance <0.5 Ω·mm) for source 201 / drain 202.

[0016] Gate 203 Schottky contact: Ni (30 nm) / Au (200 nm) T-type or Y-type gate structure is prepared by stripping process, with gate length Lg = 0.2 μm and gate-drain spacing Lgd = 3 μm.

[0017] Device isolation: Photolithography defines the active region, and dry etching or ion implantation defines the mesa region, preferably using multiple multi-energy ion implantation methods, with N-type ions selected for implantation. + (Nitrogen ions), energy 50~250 keV, resistivity of the injected region increased to >10 9 Ω·cm, to achieve electrical isolation.

[0018] Step S3: Passivation layer deposition A layer of SiN is deposited on the entire device surface by plasma enhanced chemical vapor deposition (PECVD) x A passivation layer 106 with thickness of 20-150 nm is used to suppress surface states and provide a support platform for the subsequent field plate.

[0019] Step S4: Gradient-aperture all-dielectric suspended field plate construction: The field plate is located on the SiN x Above the passivation layer 106, covering the high electric field region between the gate 203 and the drain 202.

[0020] First, a dielectric layer 301 of high-k dielectric material (such as SiNx, HfO2, Al2O3, HfSiON, ZrO2) or high-thermal-conductivity dielectric material (such as AlN, BN, SiC, diamond) is deposited above the passivation layer by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other techniques, with a thickness of about 100 nm.

[0021] Next, ZEP520A electron beam resist is spin-coated on the dielectric layer 301, and an electron beam lithography (EBL) is used to define a gradient-aperture metasurface pattern that linearly increases from 50 nm near the gate to 300 nm near the drain, with a period of 400 nm and a shape of circular holes or columnar structures. The feature size (aperture or column diameter) changes linearly, exponentially, or in a Gaussian manner from the gate to the drain.

[0022] Finally, the designed gradient-aperture metasurface structure 302 is precisely etched using reactive ion etching (RIE), inductively coupled plasma etching (ICP), or atomic layer etching (ALE). After etching, N2 plasma surface treatment or wet etching is performed to repair the surface dangling bonds on the etched dielectric surface, improving dielectric stability. In this embodiment, for the dielectric microstructure unit, a dielectric material 301 with high dielectric constant (≥4) or high thermal conductivity (≥100 W / m·K) is preferred, such as AlN, BN, diamond, etc., to meet the needs of electric field optimization and thermal management.

[0023] The design of the gradient-aperture metasurface structure 302 allows flexible adjustment of the electric field distribution according to actual needs, while also supporting the integration of other functions such as electromagnetic wave regulation and stress management. The entire structure does not require additional metal connections, maintaining all-dielectric and electrically suspended characteristics.

[0024] Example 2: All-dielectric suspended field plate GaNHEMT device based on HfSiON-diamond inlaid composite gradient aperture metasurface Step S1: Substrate and Epitaxial Structure Fabrication like Figure 3 and Figure 4 As shown, SiC single-crystal substrate 101 was selected due to its combination of high thermal conductivity (~370 W / m·K) and good lattice matching. The following layers were epitaxially grown sequentially using a metal-organic chemical vapor deposition (MOCVD) system: GaN buffer layer 102: 1.5 μm thick, Fe-doped for high resistivity, resistivity > 1 × 10⁻⁶. 5 Ω·cm; GaN channel layer 103: 200nm thick, unintentionally doped; Al0. 25 Ga0. 75 N barrier layer 104: 20 nm thick, undoped; GaN cap layer 105: 1-2 nm thick, surface passivated with NH3 to reduce interface defects.

[0025] Step S2: Preparation of Ohmic and Schottky Contacts Source 201 / Drain 202 Ohmic Contact: A multilayer metal of Ti (20 nm) / Al (100 nm) / Ni (40 nm) / Au (60 nm) was sequentially deposited by electron beam evaporation, followed by rapid thermal annealing (RTA) at 850°C for 30 seconds in a N2 atmosphere to form a low-resistance ohmic contact (specific contact resistance <0.5 Ω·mm) for source 201 / drain 202.

[0026] Gate 203 Schottky contact: After photolithography and etching to form gate trenches, Ni (30 nm) / Au (200 nm) T-type or Y-type gate structures are prepared by lift-off process, with gate length Lg = 0.2 μm and gate-drain spacing Lgd = 3 μm.

[0027] Device isolation: Photolithography defines the active region, and dry etching or ion implantation defines the mesa region, preferably using multiple multi-energy ion implantation methods, with N-type ions selected for implantation. + (Nitrogen ions), energy 50~250 keV, resistivity of the injected region increased to >10 9 Ω·cm, to achieve electrical isolation.

[0028] Step S3: Passivation layer deposition A SiN layer was deposited on the entire device surface using plasma-enhanced chemical vapor deposition (PECVD). x The passivation layer 106, with a thickness of 20nm~150nm, is used to suppress surface states and provide a support platform for subsequent field plates.

[0029] Step S4: Construction of Hafnium Oxide Silicon (HfSiON)-Diamond Inlaid Composite All-Dielectric Suspended Field Plate The plate is located in SiN x Above the passivation layer 106, a critical high electric field region is covered between the gate 203 and the drain 202.

[0030] A dense HfSiON dielectric layer 401 with a thickness of 100 nm was deposited on the device surface above the passivation layer using plasma-enhanced atomic layer deposition (PE-ALD).

[0031] ZEP520A electron beam lithography (EBL) was used to spin-coat a ZfSiON dielectric layer 401 to define a circular window array with a linear gradient distribution along the gate-drain direction. The period P = 400 nm, and the aperture increases linearly from 80 nm near the gate to 280 nm on the drain side, forming a total of 8 gradient unit regions. Reactive ion etching (RIE) was used to etch the windows into the interior of the ZfSiON dielectric layer or to the next SiN layer. x The interface of the passivation layer forms anchor points. After etching, N2 plasma surface treatment is performed to repair the dangling bonds on the HfSiON surface and improve dielectric stability. The above-mentioned etching window was filled with nanocrystalline diamond 402 using microwave plasma chemical vapor deposition (MPCVD), and a nanocrystalline diamond film 403 was formed on the surface of the HfSiON dielectric layer. The diamond particle size was controlled between 50 and 250 nm to match the pore size.

[0032] Optionally, the surface of the nanocrystalline diamond film 403 is planarized using chemical mechanical polishing (CMP); the final structure is SiN. x Diamond nanopillars with a gradient distribution are embedded in the matrix to form a composite dielectric metasurface SiN. x Encapsulation and planarization; optionally, another layer of SiN is deposited via PECVD. x A thin film (200 nm thick) completely covers the diamond islands and fills the gaps to form a continuous dielectric layer.

[0033] Example 3: GaN HEMT device based on HfO2 / AlN stacked exponential gradient high-k metasurface Step S1: Substrate and Epitaxial Structure Fabrication like Figure 5 and Figure 6 As shown, SiC single-crystal substrate 101 was selected due to its combination of high thermal conductivity (~370 W / m·K) and good lattice matching. The following layers were epitaxially grown sequentially using a metal-organic chemical vapor deposition (MOCVD) system: GaN buffer layer 102: 1.5 μm thick, Fe-doped for high resistivity, resistivity > 1 × 10⁻⁶.5 Ω·cm; GaN channel layer 103: 200nm thick, unintentionally doped; Al0. 25 Ga0. 75 N barrier layer 104: 20 nm thick, undoped; GaN cap layer 105: 1-2 nm thick, surface passivated with NH3 to reduce interface defects.

[0034] Step S2: Preparation of Ohmic and Schottky Contacts Source 201 / Drain 202 Ohmic Contact: A multilayer metal of Ti (20 nm) / Al (100 nm) / Ni (40 nm) / Au (60 nm) was sequentially deposited by electron beam evaporation, followed by rapid thermal annealing (RTA) at 850°C for 30 seconds in a N2 atmosphere to form a low-resistance ohmic contact (specific contact resistance <0.5 Ω·mm) for source 201 / drain 202.

[0035] Gate Schottky contact: After photolithography and etching to form gate trenches, Ni (30nm) / Au (200nm) T-type or Y-type gate structures are prepared using a lift-off process, with gate length Lg = 0.2μm and gate-drain spacing Lgd = 3μm.

[0036] Device isolation: Photolithography defines the active region, and dry etching or ion implantation defines the mesa region, preferably using multiple multi-energy ion implantation methods, with N-type ions selected for implantation. + (Nitrogen ions), energy 50~250 keV, resistivity of the injected region increased to >10 9 Ω·cm, to achieve electrical isolation.

[0037] Step S3: Passivation layer deposition A SiN layer was deposited on the entire device surface using plasma-enhanced chemical vapor deposition (PECVD). x The passivation layer 106, with a thickness of 20nm~150nm, is used to suppress surface states and provide a support platform for subsequent field plates.

[0038] Step S4: Construction of an all-dielectric suspended field plate of HfO2 / AlN stacked exponential gradient high-k metasurface The suspended field plate, located above the passivation layer 106, covers the high-voltage region between the gate 203 and the drain 202. It consists of a periodic stacked structure 502 array composed of HfO2 5021 and AlN 5022, whose feature size monotonically increases exponentially along the gate-drain direction, achieving synergistic optimization of high dielectric constant (high k) gradient control and efficient thermal conduction. AlN combines high thermal conductivity, high breakdown strength (>10 MV / cm), and good interface passivation capability, providing a thermal-electric synergy foundation for subsequent high-k field plates.

[0039] Atomic layer deposition (ALD) was used to alternately deposit HfO2 and AlN films, forming a multilayer stacked structure of [HfO2 (5 nm) / AlN (10 nm)] × 6, with a total thickness of 90 nm. HfO2: dielectric constant ε ≈ 22~25, used to enhance local capacitive coupling to modulate the electric field; AlN: thermal conductivity 100~260 W / (m·K), serving as a thermal diffusion channel and improving the mechanical stability of the structure; all depositions are performed at 400°C to ensure compatibility with GaN processes and to prevent thermal damage.

[0040] ZEP520A electron beam lithography was spin-coated onto the surface of the stacked thin film, and a circular nanopillar pattern was defined using high-precision electron beam lithography (EBL). The feature size of the nanopillar pattern varied exponentially from the gate to the drain: the array period P = 500 nm, which met the subwavelength condition (<λ / 3 @ 10 GHz).

[0041] Anisotropic dry etching was used to etch HfO2 / AlN stacks to form a 90nm high stacked nanostructure 502 array with steep sidewalls (tilt angle >85°) and no obvious interlayer peeling or undercutting.

[0042] After etching, a N2 / O2 mixed plasma surface treatment (50 W, 60 s) is performed to repair surface defects and improve dielectric stability. The entire metasurface structure is not connected to any electrodes and is in a completely electrically floating state, ensuring that no additional parasitic capacitance is introduced.

[0043] A SiN layer was deposited on the entire device surface using plasma-enhanced chemical vapor deposition (PECVD). x The passivation layer 501, with a thickness of 50nm~250nm, is used for surface passivation and protection.

[0044] The device performance and electro-thermal synergistic mechanism in this embodiment include: High-k electric field modulation: The high dielectric constant of HfO2 significantly enhances local capacitive coupling, reduces the peak electric field of the gate-drain region, increases the breakdown voltage, and suppresses the current collapse effect.

[0045] Synergistic thermal management: The AlN layer forms a vertical heat conduction path, reducing hotspot temperature; High-frequency characteristics are maintained: Due to the all-dielectric design, the gate-drain parasitic capacitance C is minimized. gd The increase is relatively small, but compared to traditional metal field plates, it significantly improves the f of the device. T / f max .

[0046] Functional expansion potential: Introducing oxygen vacancies or doping Zr into HfO2 (forming HfZrO2) can endow the field plate with ferropolar polarization control capability and realize dynamic electric field reconstruction; the stacked structure can also be used for multi-band electromagnetic response design, supporting sensing or communication integration in future smart power chips.

[0047] In summary, the GaN HEMT all-dielectric levitation field plate device and its fabrication method based on gradient aperture metasurfaces of this invention achieve the following by constructing a gradient aperture metasurface composed of high k (dielectric constant) or high thermal conductivity dielectric material above the passivation layer as an electrical levitation field plate: uniform surface electric field along the channel direction, improving breakdown voltage; zero metal introduction, eliminating parasitic capacitance and maintaining high-frequency characteristics; selection of high thermal conductivity materials (such as AlN, BN, diamond, etc.) to achieve electro-thermal synergistic management; process compatibility with GaN processes, possessing mass production potential; and suitability for high-frequency, high-voltage, high-power, and intelligent power chip applications.

[0048] The all-dielectric gradient aperture metasurface field plate of this invention is fundamentally different from traditional metal field plates or floating metal field plates: Traditional metal field plates or floating metal field plates: By introducing metal plates, the electric field lines at the gate edge are redistributed, "smoothing" the peak electric field and pushing it towards the drain, thereby improving the breakdown voltage. Multiple floating metal field plates are equivalent to introducing multiple "buffer steps," further smoothing the electric field distribution and suppressing electric field peaks more effectively than a single field plate, especially at high voltages. The all-dielectric gradient aperture metasurface field plate of this invention: Structurally, the metal field plate is completely removed, and a two-dimensional structure composed of nanoscale dielectric units (such as pores or columnar structures) is constructed in the passivation layer. The size (aperture) of these units varies gradient along the source-drain direction. It is essentially a local electric field modulator. The gradient aperture structure is equivalent to creating an equivalent refractive index gradient, which can "guide" and "reconstruct" the electric field lines in a very precise way, like an "optical lens" manipulating light waves, achieving unprecedented control over the electric field distribution.

[0049] Compared with floating metal field plates (whether single or multiple), the all-dielectric gradient aperture metasurface field plate of this invention has comprehensive advantages in a systematic and multi-dimensional way: (1) Eliminate parasitic capacitance from the root and improve frequency performance. Because it completely eliminates the use of metal, the parasitic capacitance introduced by the metal field plate is eliminated at its source. This allows the device to maintain higher intrinsic frequency characteristics, which is crucial for RF applications that require higher operating frequencies. However, regardless of the number of floating metal field plates, additional gate-drain parasitic capacitance (Cgd) is inevitably introduced. This is because a strong capacitive coupling, similar to a MOS structure, is formed between the metal and the underlying two-dimensional electron gas channel. When multiple metal field plates are used, the parasitic capacitance can even superimpose, severely dragging down the device's cutoff frequency (fT) and maximum oscillation frequency (fmax). This is an inherent drawback that metal field plate technology cannot avoid.

[0050] (2) More refined and proactive electric field shaping capabilities Each subwavelength unit of a metasurface can be designed to fine-tune the local electric field. By designing gradient-variable apertures, a smooth, continuous, and nearly ideal linear distribution of the electric field from the gate edge to the drain can be achieved. This "engineered" electric field distribution can more efficiently improve the breakdown voltage while avoiding local electric field concentration. In contrast, the control of the electric field by a metal field plate is "passive" and "macroscopic." It can only push the electric field peak further away as a whole, but the shape of the electric field distribution is relatively fixed, and new, smaller electric field peaks may still appear at the edges of multiple field plates.

[0051] (3) Better thermal stability and reliability Thanks to the optimized electric field distribution mentioned above, it can reduce the peak electric field at the gate edge to a lower level, thereby significantly improving the breakdown voltage of the device; the all-dielectric structure naturally has better thermal and chemical stability, and since there are no free electrons in the all-dielectric structure, there is no electromigration problem. The materials used (such as AlN, SiN) x It exhibits stable chemical properties, high temperature resistance, and radiation resistance, along with a low interface state density, effectively suppressing dynamic on-resistance degradation. It can be tightly integrated with standard dielectric deposition processes and nanopatterning processes (such as electron beam lithography), simplifying the process flow and avoiding potential problems at the metal-dielectric interface. In contrast, metal field plates face inherent risks such as electromigration, high-temperature diffusion, and interface degradation. Especially under high electric field and high-temperature operating conditions, metal atoms may migrate into GaN, leading to threshold voltage drift or increased leakage current.

[0052] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A GaN HEMT all-dielectric suspended field plate device, characterized in that, include: A GaN buffer layer, a GaN channel layer, and a nitride barrier layer are epitaxially grown sequentially on the substrate; a source, drain, gate, and passivation layer are formed above the nitride barrier layer. And a gradient aperture metasurface formed above the passivation layer; The gradient aperture metasurface forms a fully dielectric levitation field plate, which is electrically levitation between the gate and the drain. It includes periodically arranged dielectric microstructure units with an arrangement period of 100~600 nm and a feature size of 50~500 nm. The microstructure units exhibit a monotonically varying gradient along the direction from the gate to the drain. The monotonically varying gradient includes linear, exponential, and Gaussian gradients.

2. The device as described in claim 1, characterized in that, The dielectric microstructure unit is a nanopore or a nanopillar, with the characteristic size being the pore diameter or the pillar diameter. The material is a high dielectric constant dielectric material with a dielectric constant ≥ 4, a high thermal conductivity dielectric material with a thermal conductivity ≥ 50 W / m·K, or a composite material of both.

3. The device as described in claim 2, characterized in that, The high dielectric constant dielectric material includes SiN. x High thermal conductivity dielectric materials include AlN, BN, SiC, and diamond, such as HfO2, Al2O3, HfSiON, and ZrO2.

4. The device as described in any one of claims 1-3, characterized in that, The thickness of the nitride barrier layer is 5–25 nm, and the materials include AlGaN, AlN, InAlN, and ScAlN; the thickness of the passivation layer is 20 nm–150 nm, and the materials include SiN. x And SiO2.

5. A method for preparing the device according to any one of claims 1-4, characterized in that, include: Step S1: Epitaxially grow a GaN buffer layer, a GaN channel layer, and a nitride barrier layer sequentially on the substrate; Step S2: Fabricate the source and drain ohmic contacts and the gate Schottky contact of the device on the nitride barrier layer; Step S3: Deposit a passivation layer on the entire device surface by chemical vapor deposition; Step S4: Deposit a dielectric layer above the passivation layer, and form a gradient aperture metasurface structure in the dielectric layer as an all-dielectric suspended field plate through a nanopatterning process. The nanopatterning process includes electron beam lithography, nanoimprinting and self-assembly.

6. The method as described in claim 5, characterized in that, In step S4, a dielectric material with high dielectric constant or high thermal conductivity is deposited above the passivation layer to form a dielectric layer; a gradient aperture metasurface pattern with a linear gradient distribution along the gate to drain direction is defined using a nanopatterning process; and the gradient aperture metasurface structure is etched using an etching process.

7. The method as described in claim 5, characterized in that, In step S4, a high dielectric constant dielectric material is deposited above the passivation layer as a dielectric layer; A circular window array with a linear gradient distribution along the gate-to-drain direction is defined using a nanopatterning process; An etching process is used to etch a window into the interior of the dielectric layer or the interface with the passivation layer. The etched window is filled with a high thermal conductivity dielectric material, and a high thermal conductivity dielectric material film is formed on the surface of the dielectric layer.

8. The method as described in claim 7, characterized in that, The high dielectric constant dielectric material is HfSiON, and the high thermal conductivity dielectric material is nanocrystalline diamond. The surface of the nanocrystalline diamond film is planarized by chemical mechanical polishing.

9. The method as described in claim 5, characterized in that, In step S4, high dielectric constant dielectric material and high thermal conductivity dielectric material are alternately deposited to form a multilayer stacked structure as a dielectric layer; Electron beam photoresist is spin-coated onto the surface of the dielectric layer, and a circular nanopillar pattern is defined by high-precision electron beam lithography. The feature size of the nanopillar pattern varies exponentially along the direction from the gate to the drain. Anisotropic dry etching is used to etch the multilayer stacked structure to form a stacked nanostructure array; Plasma-enhanced chemical vapor deposition is used to deposit a passivation layer on the entire device surface.

10. The method according to any one of claims 6-9, characterized in that, After etching, N2 plasma surface treatment is performed to repair surface defects on the etched surface of the dielectric layer and improve dielectric stability.

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