High-voltage anti-radiation transverse device and manufacturing method thereof
By designing specific doped regions and dielectric layer structures in high-voltage LDMOS devices, the performance degradation and burn-out problems of the devices under total dose and single-event radiation were solved, enhancing their application capability in radiation environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-05
- Publication Date
- 2026-03-24
AI Technical Summary
The performance degradation and burn-out of high-voltage LDMOS devices under total dose radiation and single-event radiation environments limit their application in space radiation environments.
A high-voltage radiation-hardened lateral device was designed, including a specific doped region and a dielectric layer structure, which enhances the radiation resistance of the device by providing additional hole extraction paths and blocking parasitic leakage channels.
This improves the device's resistance to total dose radiation and single-particle burn-off, and reduces the risk of performance degradation in radiation environments.
Smart Images
Figure CN121728801A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a high-voltage radiation-resistant lateral device and its manufacturing method. Background Technology
[0002] High-voltage lateral double-diffused MOSFETs (LDMOS) are critical components, playing a vital role in analog switches and high-voltage driver chips in spacecraft, satellites, and other space and electronic systems. However, LDMOS devices are highly sensitive to total dose radiation and single-event radiation effects. The charge generated by total dose radiation can lead to stable defects in the dielectric materials used during manufacturing, resulting in threshold voltage drift, strong leakage current, and the formation of parasitic conductive paths. Under heavy ion radiation, electron-hole pairs are generated within the device, leading to single-event burn-out and single-event gate breakdown under strong electric fields. Particularly for high-voltage LDMOS devices, the impact of radiation effects increases with increasing operating voltage, limiting their application in space radiation environments. Therefore, radiation hardening of high-voltage LDMOS devices is essential to ensure their proper functioning in harsh radiation environments.
[0003] Therefore, this invention urgently needs to propose a high-voltage radiation-resistant transverse device to avoid performance degradation under total dose radiation environment and device burnout under single-particle radiation environment, so as to improve the radiation resistance of the device. Summary of the Invention
[0004] The purpose of this invention is to provide a high-voltage radiation-resistant transverse device and its manufacturing method to solve the above-mentioned problem of radiation-resistant hardening of high-voltage devices.
[0005] To solve the above-mentioned technical problems, the present invention provides a high-voltage radiation-resistant lateral device, comprising: A substrate having a second P-type doped region, a fourth P-type doped region, and a first N-type doped region spaced apart on its surface; The first P-type doped region is located below and adjacent to the second P-type doped region; The third P-type doped region is located inside the second P-type doped region and is connected to the first P-type doped region; The fifth P-type doped region, the sixth P-type doped region, and the third N-type doped region are respectively disposed on the surface of the third P-type doped region, the fourth P-type doped region, and the first N-type doped region; The second N-type doped region is disposed on the surface of the second P-type doped region and is adjacent to the fifth P-type doped region; The first dielectric layer and the second dielectric layer are disposed sequentially from bottom to top on the surface of the drift region; The third dielectric layer is disposed on the surface of the active region; A polysilicon gate electrode is disposed on the surface of the third dielectric layer below the first source metal; A first source metal and a first drain metal are respectively disposed on a fourth dielectric layer, and the fourth dielectric layer covers the surfaces of the second dielectric layer and the third dielectric layer; wherein the sixth P-type doped region is connected to the fifth P-type doped region and the second N-type doped region through the first source metal; the first drain metal is connected to the third N-type doped region.
[0006] Preferably, the substrate is an SOI material sheet; wherein the SOI material sheet consists of a P-type substrate, a buried oxide layer, a P-type buried layer, and a first N-type epitaxial layer arranged sequentially from bottom to top.
[0007] Preferably, the substrate is an SOI material sheet; wherein the SOI material sheet consists of a P-type substrate, a buried oxide layer, and an N-type top silicon layer arranged sequentially from bottom to top.
[0008] Preferably, the substrate is a bulk silicon material sheet; the bulk silicon material sheet is a P-type substrate and a second N-type epitaxial layer arranged sequentially from bottom to top.
[0009] Preferably, the first source metal and the first drain metal are F-shaped and L-shaped, respectively, and both partially cover the second dielectric layer.
[0010] Preferably, it further includes a second source metal and a second drain metal, both L-shaped, disposed on the fourth dielectric layer; wherein the second source metal is connected to and covers the first source metal; and the second drain metal is connected to and covers the first drain metal.
[0011] Preferably, the thickness of the first dielectric layer is 40nm~100nm, the thickness of the second dielectric layer is 0.4μm~1.2μm, and the thickness of the third dielectric layer is 40nm~150nm.
[0012] Preferably, the implantation dose of the first P-type doped region and the third P-type doped region is 1E14cm. -2 ~1E15cm -2 The implantation dose of the fourth P-type doped region is 1E12cm. -2 ~1E13cm -2 The implantation dose of the first N-type doped region is 5E12cm. -2 ~1E14cm -2 .
[0013] Preferably, the first dielectric layer and the third dielectric layer are formed by an oxidation process, and the second dielectric layer is formed by a deposition process, which improves the interface quality of the field oxide layer and enhances the device's resistance to total dose radiation.
[0014] The present invention also provides a method for manufacturing a high-voltage radiation-hardened lateral device, to prepare a high-voltage radiation-hardened lateral device as described above, comprising: A substrate is provided, and a P-type impurity is implanted on the substrate surface using an ion implantation process to form the first P-type doped region; P-type impurities are implanted onto the substrate surface using photolithography and ion implantation processes, and a second P-type doped region is formed through an annealing process. N-type impurities are implanted into the substrate surface using photolithography and ion implantation processes, and the first N-type doped region is formed by annealing. The second P-type doped region is implanted with P-type impurities using an ion implantation process, and the third P-type doped region is formed by an annealing process. P-type impurities are implanted into the substrate surface using an ion implantation process, and a fourth P-type doped region is formed through an annealing process. An oxidation process is used to grow a first dielectric layer on the substrate surface, and a deposition process is used to deposit a second dielectric layer on the surface of the first dielectric layer. The first and second dielectric layers on the surface of the active region are removed by photolithography and etching processes. An oxidation process is used to grow a third dielectric layer on the surface of the active region; Polysilicon is deposited on the surface of the device, and polysilicon gate electrodes are formed through photolithography and etching processes; Using photolithography and ion implantation processes, N-type impurities are implanted into the second P-type doped region and the first N-type doped region to form the second N-type doped region and the third N-type doped region, respectively. Using photolithography and ion implantation processes, P-type impurities are implanted into the third and fourth P-type doped regions to form the fifth and sixth P-type doped regions, respectively. A fourth dielectric layer is deposited on the device surface, and photolithography and etching processes are used to form the first contact hole, the second contact hole and the third contact hole; The first source metal and the first drain metal are formed by deposition and etching processes.
[0015] Compared with the prior art, the present invention has the following beneficial effects: The high-voltage radiation-hardened lateral device provided by this invention has a first P-type doped region, a third P-type doped region, a fourth P-type doped region, and a sixth P-type doped region. The fourth and sixth P-type doped regions provide additional extraction paths for holes generated by heavy-ion radiation, reducing the hole current in the second P-type doped region and the hole density at the lower interface of the third dielectric layer, thereby improving the device's resistance to single-event burn-out and single-event gate breakdown. The sixth P-type doped region is directly connected to the second N-type doped region through a first source metal, i.e., connected to the source and body electrodes of the device through the first source metal, protecting the third dielectric layer from the potential of the third N-type doped region and preventing damage or even breakdown of the third dielectric layer in a heavy-ion environment. A P-type buried layer is set at the upper interface of the buried oxide layer. Under total dose radiation, the high concentration of buried layer injection cuts off the parasitic leakage current channel between the source and drain, preventing field leakage problems and improving the device's resistance to total dose radiation. The manufacturing methods of the first, second, and third dielectric layers can reduce the impact of total dose radiation on the device's drift region, thereby ensuring the device's radiation resistance. Attached Figure Description
[0016] Figure 1 This is a schematic cross-sectional view of a high-voltage radiation-resistant lateral device structure provided in Embodiment 1 of the present invention.
[0017] Figure 2 This is a schematic cross-sectional view of a high-voltage radiation-resistant lateral device structure provided in Embodiment 2 of the present invention.
[0018] Figure 3 This is a schematic cross-sectional view of a high-voltage radiation-resistant lateral device structure provided in Embodiment 3 of the present invention.
[0019] Figure 4 This is a schematic cross-sectional view of a high-voltage radiation-resistant lateral device structure provided in Embodiment 4 of the present invention.
[0020] Figure 5 This is a schematic diagram of the first step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0021] Figure 6 This is a schematic diagram of the second step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0022] Figure 7 This is a schematic diagram of the third step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0023] Figure 8 This is a schematic diagram of the fourth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0024] Figure 9 This is a schematic diagram of the fifth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0025] Figure 10 This is a schematic diagram of the sixth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0026] Figure 11 This is a schematic diagram of the seventh step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0027] Figure 12 This is a schematic diagram of the eighth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0028] Figure 13 This is a schematic diagram of the ninth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0029] Figure 14 This is a schematic diagram of the tenth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0030] Figure 15 This is a schematic diagram of the eleventh step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0031] Figure 16 This is a schematic diagram of the twelfth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0032] Figure 17 This is a schematic diagram of the thirteenth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0033] Figure 18 This is a schematic diagram of the fourteenth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0034] Figure 19 This is a schematic diagram of the sixteenth step of the device manufacturing method provided in Embodiment 5 of the present invention.
[0035] In the figure: 11-P-type substrate; 12-buried oxide layer; 13-P-type buried layer; 14-first N-type epitaxial layer; 15-N-type top silicon layer; 16-second N-type epitaxial layer; 21-first dielectric layer; 22-second dielectric layer; 23-third dielectric layer; 24-fourth dielectric layer; 31-first P-type doped region; 32-second P-type doped region; 33-third P-type doped region; 34-fourth P-type doped region; 35-fifth P-type doped region; 36-sixth P-type doped region; 41-first N-type doped region; 42-second N-type doped region; 43-third N-type doped region; 51-polysilicon gate electrode; 61-first source metal; 62-first drain metal; 63-second source metal; 64-second drain metal; 71-first contact hole; 72-second contact hole; 73-third contact hole; 74-fourth contact hole; 75-fifth contact hole. Detailed Implementation
[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0037] Example 1 like Figure 1 As shown, this embodiment provides a high-voltage radiation-hardened lateral device, the structure of which includes a P-type substrate 11, a buried oxide layer 12, a P-type buried layer 13, a first N-type epitaxial layer 14, a first dielectric layer 21, a second dielectric layer 22, a third dielectric layer 23, a fourth dielectric layer 24, a first P-type doped region 31, a second P-type doped region 32, a third P-type doped region 33, a fourth P-type doped region 34, a fifth P-type doped region 35, a sixth P-type doped region 36, a first N-type doped region 41, a second N-type doped region 42, a third N-type doped region 43, a polysilicon gate electrode 51, a first source metal 61, a second source metal 63, and a first drain metal 62. The second drain metal 64, the first N-type epitaxial layer 14 is disposed on the upper surface of the P-type buried layer 13, the first P-type doped region 31 is disposed on the lower surface of the second P-type doped region 32, the third P-type doped region 33 is disposed inside the second P-type doped region 32 and connected to the first P-type doped region 31, the fifth P-type doped region 35 and the sixth P-type doped region 36 are respectively disposed on the surface of the third P-type doped region 33 and the fourth P-type doped region 34, the first source metal 61 and the first drain metal 62 both partially cover the first dielectric layer 21 and the second dielectric layer 22, the second source metal 63 covers the first source metal 61, and the second drain metal 64 covers the first drain metal 62.
[0038] The fourth P-type doped region 34 is disposed on the surface of the first N-type epitaxial layer 14. It can recombine electrons induced on the surface of the drift region under total dose radiation, thereby avoiding the influence of total dose radiation effect on the output current and breakdown voltage characteristics of the device.
[0039] The P-type buried layer 13 is set on the upper interface of the buried oxide layer 12 to avoid back gate punch-through leakage caused by total dose radiation effect, thereby improving the device's resistance to total dose radiation.
[0040] The first P-type doped region 31 is located below the second P-type doped region 32, and the third P-type doped region 33 is located inside the second P-type doped region 32. This is used to reduce the parasitic resistance of the second P-type doped region 32 and avoid the device from prematurely burning out due to single-event radiation.
[0041] The fourth P-type doped region 34 contains a sixth P-type doped region 36. The sixth P-type doped region 36 is connected to the fifth P-type doped region 35 and the second N-type doped region 42 through the first source metal 61, providing an additional extraction path for holes generated by single-event radiation, improving the device's resistance to single-event burn-out, and also preventing holes from accumulating on the lower surface of the third dielectric layer 23, reducing the electric field acting on the third dielectric layer 23, thereby improving the resistance to single-event gate penetration.
[0042] The thickness of the first dielectric layer 21 is 40nm~100nm, the thickness of the second dielectric layer 22 is 0.4μm~1.2μm, and the thickness of the third dielectric layer 23 is 40nm~150nm.
[0043] The implantation dose of the first P-type doped region 31 and the third P-type doped region 33 is 1E14cm. -2 ~1E15cm -2 The implantation dose of the fourth P-type doped region 34 is 1E12cm. -2 ~1E13cm -2 The implantation dose of the first N-type doped region 41 is 5E12cm. -2 ~1E14cm -2 .
[0044] The first dielectric layer 21 is formed by an oxidation process, and the second dielectric layer 22 is formed by a deposition process. This improves the quality of the field oxide layer interface and enhances the device's resistance to total dose radiation.
[0045] The overall technical solution of this invention is as follows: A high-voltage radiation-resistant lateral device is disposed on an SOI substrate, having a first P-type doped region 31, a third P-type doped region 33, a fourth P-type doped region 34, and a sixth P-type doped region 36. The fourth P-type doped region 34 and the sixth P-type doped region 36 provide additional extraction paths for holes generated by heavy-ion radiation, reducing the hole current in the second P-type doped region 32 and preventing the parasitic transistor from turning on. The first P-type doped region 31 and the third P-type doped region 33 increase the concentration of the second P-type doped region 32, reducing the base resistance of the parasitic transistor and further preventing the parasitic transistor from turning on. The sixth P-type doped region 36 is directly connected to the second N-type doped region 42 through a first source metal 61, protecting the third dielectric layer 23 from the influence of the potential of the third N-type doped region 43 and preventing damage or even breakdown of the third dielectric layer 23 in a heavy-ion environment. A P-type buried layer 13 is set on the upper interface of the buried oxide layer 12. Under total dose radiation, the high concentration of buried layer injection cuts off the parasitic leakage current channel between the source and drain, avoids field leakage current problem of the device, and improves the device's resistance to total dose radiation.
[0046] Example 2 like Figure 2The image shows another high-voltage radiation-resistant lateral device provided in this embodiment, comprising a P-type substrate 11, a buried oxide layer 12, a P-type buried layer 13, a first N-type epitaxial layer 14, a first dielectric layer 21, a second dielectric layer 22, a third dielectric layer 23, a fourth dielectric layer 24, a first P-type doped region 31, a second P-type doped region 32, a third P-type doped region 33, a fourth P-type doped region 34, a fifth P-type doped region 35, a sixth P-type doped region 36, a first N-type doped region 41, a second N-type doped region 42, a third N-type doped region 43, a polysilicon gate electrode 51, a first source metal 61, and a first drain metal 62. In this device design and manufacturing process, for different operating voltage requirements, only the first source metal 61 and the first drain metal 62 can be formed, without the need to form the second source metal 63 and the second drain metal 64, thus reducing photolithography and mask requirements and lowering manufacturing costs.
[0047] Example 3 like Figure 3 The image shows another high-voltage radiation-resistant lateral device provided in this embodiment, comprising a P-type substrate 11, a buried oxide layer 12, an N-type top silicon layer 15, a first dielectric layer 21, a second dielectric layer 22, a third dielectric layer 23, a fourth dielectric layer 24, a first P-type doped region 31, a second P-type doped region 32, a third P-type doped region 33, a fourth P-type doped region 34, a fifth P-type doped region 35, a sixth P-type doped region 36, a first N-type doped region 41, a second N-type doped region 42, a third N-type doped region 43, a polysilicon gate electrode 51, a first source metal 61, a second source metal 63, a first drain metal 62, and a second drain metal 64. To meet different radiation capability requirements, during device design and process integration, the P-type buried layer 13 can be formed without implantation, reducing photolithography and mask requirements and lowering manufacturing costs. At the same time, by directly using SOI material wafers, there is no need for material epitaxy (i.e., instead of using the first N-type epitaxial layer 14, the N-type top silicon layer 15 is used to replace it and is directly formed on the second N-type top silicon layer 15), and no additional epitaxial process is required, further reducing manufacturing costs.
[0048] Example 4 like Figure 4As shown, this embodiment provides another high-voltage radiation-hardened lateral device, comprising a P-type substrate 11, a second N-type epitaxial layer 16, a first dielectric layer 21, a second dielectric layer 22, a third dielectric layer 23, a fourth dielectric layer 24, a first P-type doped region 31, a second P-type doped region 32, a third P-type doped region 33, a fourth P-type doped region 34, a fifth P-type doped region 35, a sixth P-type doped region 36, a first N-type doped region 41, a second N-type doped region 42, a third N-type doped region 43, a polysilicon gate electrode 51, a first source metal 61, a second source metal 63, a first drain metal 62, and a second drain metal 64. In this embodiment, to meet different radiation capability requirements, during device design and process integration, a P-type buried layer 13 can be formed without implantation, reducing photolithography and mask requirements and lowering manufacturing costs. Meanwhile, by directly using bulk silicon epitaxial material wafers (i.e., P-type substrate 11 and second N-type epitaxial layer 16), material epitaxy is not required (i.e., there is no need to use buried oxide layer 12, which can be directly placed on bulk silicon material), further reducing manufacturing costs.
[0049] Example 5 This embodiment provides a method for manufacturing a high-voltage radiation-resistant lateral device, which specifically includes the following steps: Step 1: As Figure 5 Prepare SOI materials, including a P-type substrate 11, a buried oxide layer 12, and a P-type buried layer 13; Step 2: As Figure 6 The first N-type epitaxial layer 14 is formed by epitaxial growth on the upper surface of the P-type buried layer 13. Step 3: As Figure 7 Using an ion implantation process, P-type impurities are implanted into the first N-type epitaxial layer 14 to form the first P-type doped region 31. Step 4: As Figure 8 Using photolithography and ion implantation processes, P-type impurities are implanted into the first N-type epitaxial layer 14, and the second P-type doped region 32 is formed by annealing. Step 5: As Figure 9 The first N-type epitaxial layer 14 is implanted with N-type impurities using photolithography and ion implantation processes, and the first N-type doped region 41 is formed by annealing. Step 6: As Figure 10 The second P-type doped region 32 is implanted with P-type impurities using an ion implantation process, and the third P-type doped region 33 is formed by an annealing process. Step 7: As Figure 11 The first N-type epitaxial layer 14 is implanted with P-type impurities using an ion implantation process, and the fourth P-type doped region 34 is formed by an annealing process. Step 8: As Figure 12An oxidation process is used to grow a first dielectric layer 21 on the surface of the first N-type epitaxial layer 14, and then a deposition process is used to deposit a second dielectric layer 22 on the surface of the first dielectric layer 21. Step 9: As Figure 13 The first dielectric layer 21 and the second dielectric layer 22 on the surface of the active region are removed by photolithography and etching processes. Step 10: As Figure 14 An oxidation process is used to grow a third dielectric layer 23 on the surface of the active region. Step 11: As Figure 15 Polysilicon is deposited on the surface of the device, and a polysilicon gate electrode 51 is formed by photolithography and etching. Step 12: As Figure 16 Using photolithography and ion implantation processes, N-type impurities are implanted into the second P-type doped region 32 and the first N-type doped region 41 to form the second N-type doped region 42 and the third N-type doped region 43, respectively. Step 13: As Figure 17 Using photolithography and ion implantation processes, P-type impurities are implanted into the third P-type doped region 33 and the fourth P-type doped region 34 to form the fifth P-type doped region 35 and the sixth P-type doped region 36, respectively. Step 14: As Figure 18 A fourth dielectric layer 24 is deposited on the surface of the transverse device, and then photolithography and etching processes are used to form the first contact hole 71, the second contact hole 72 and the third contact hole 73. Step 15: Using deposition and etching processes, the first source metal 61 and the first drain metal 62 are formed, completing the process as follows: Figure 2 The device structure fabrication disclosed in Example 2 above is shown; Step 16: As Figure 19 A fourth dielectric layer 24 is deposited on the surface of the lateral device, and then photolithography and etching processes are used to form a fourth contact hole 74 and a fifth contact hole 75. Step 17: Using deposition and etching processes, the second source metal 63 and the second drain metal 64 are formed, ultimately completing the process as shown in the figure. Figure 1 The device structure fabrication disclosed in Example 1 above is shown.
[0050] In summary, the high-voltage radiation-hardened lateral device and its manufacturing method of the present invention are applied in radiation-hardening processes. A fourth P-type doped region 34 and a sixth P-type doped region 36 are implanted inside the device, providing additional extraction paths for non-equilibrium carriers under single-event radiation conditions, accelerating hole current collection, preventing premature turn-on of parasitic transistors, and improving single-event capability. The fourth P-type doped region 34 is connected to the second N-type doped region 42 and the fifth P-type doped region 35 through the first source metal 61. Under single-event radiation conditions, it clamps the gate potential, preventing the drain potential from affecting the gate electric field and improving the device's resistance to single-event gate penetration. The P-type buried layer 13 is disposed at the interface of the buried oxide layer 12, preventing total dose radiation from inducing electron leakage channels at the interface and solving the problem of parasitic back-gate leakage caused by total dose radiation. During process integration, the first dielectric layer 21, the second dielectric layer 22, and the third dielectric layer 23 effectively reduce oxide layer trap charges and interface traps caused by total dose radiation, thereby reducing the impact of total dose radiation effects on the device's electrical performance.
[0051] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A high-voltage radiation-resistant lateral device, characterized in that, include: The substrate has a second P-type doped region (32), a fourth P-type doped region (34) and a first N-type doped region (41) spaced apart on its surface. The first P-type doped region (31) is located below and connected to the second P-type doped region (32); The third P-type doped region (33) is located inside the second P-type doped region (32) and is connected to the first P-type doped region (31); The fifth P-type doped region (35), the sixth P-type doped region (36), and the third N-type doped region (43) are respectively disposed on the surface of the third P-type doped region (33), the fourth P-type doped region (34), and the first N-type doped region (41); The second N-type doped region (42) is disposed on the surface of the second P-type doped region (32) and is adjacent to the fifth P-type doped region (35); The first dielectric layer (21) and the second dielectric layer (22) are disposed sequentially from bottom to top on the surface of the drift region; The third dielectric layer (23) is disposed on the surface of the active region; A polysilicon gate electrode (51) is disposed on the surface of the third dielectric layer (23) located below the first source metal (61); The first source metal (61) and the first drain metal (62) are respectively disposed on the fourth dielectric layer (24), and the fourth dielectric layer (24) covers the surfaces of the second dielectric layer (22) and the third dielectric layer (23); wherein the sixth P-type doped region (36) is connected to the fifth P-type doped region (35) and the second N-type doped region (42) through the first source metal (61); the first drain metal (62) is connected to the third N-type doped region (43).
2. The high-voltage radiation-resistant lateral device as described in claim 1, characterized in that, The substrate is an SOI material sheet; wherein the SOI material sheet is a P-type substrate (11), a buried oxide layer (12), a P-type buried layer (13), and a first N-type epitaxial layer (14) arranged sequentially from bottom to top.
3. The high-voltage radiation-resistant lateral device as described in claim 1, characterized in that, The substrate is an SOI material sheet; wherein the SOI material sheet is a P-type substrate (11), a buried oxide layer (12), and an N-type top silicon layer (15) arranged sequentially from bottom to top.
4. The high-voltage radiation-resistant lateral device as described in claim 1, characterized in that, The substrate is a bulk silicon material sheet; the bulk silicon material sheet consists of a P-type substrate (11) and a second N-type epitaxial layer (16) arranged sequentially from bottom to top.
5. A high-voltage radiation-resistant lateral device as described in claim 1, characterized in that, The first source metal (61) and the first drain metal (62) are F-shaped and L-shaped, respectively, and both partially cover the second dielectric layer (22).
6. The high-voltage radiation-resistant lateral device as described in claim 5, characterized in that, It also includes a second source metal (63) and a second drain metal (64) that are both L-shaped and disposed on the fourth dielectric layer (24); wherein the second source metal (63) is connected to the first source metal (61) and covers the first source metal (61); the second drain metal (64) is connected to the first drain metal (62) and covers the first drain metal (62).
7. A high-voltage radiation-resistant lateral device as described in claim 1, characterized in that, The thickness of the first dielectric layer (21) is 40nm~100nm, the thickness of the second dielectric layer (22) is 0.4μm~1.2μm, and the thickness of the third dielectric layer (23) is 40nm~150nm.
8. A high-voltage radiation-resistant lateral device as described in claim 1, characterized in that, The implantation dose of the first P-type doped region (31) and the third P-type doped region (33) is 1E14cm. -2 ~1E15cm -2 The implantation dose of the fourth P-type doped region (34) is 1E12cm. -2 ~1E13cm -2 The implantation dose of the first N-type doped region (41) is 5E12cm. -2 ~1E14cm -2 .
9. A high-voltage radiation-resistant lateral device as described in claim 1, characterized in that, The first dielectric layer (21) and the third dielectric layer (23) are formed by an oxidation process, and the second dielectric layer (22) is formed by a deposition process, which improves the quality of the field oxide layer interface and enhances the device's resistance to total dose radiation.
10. A method for manufacturing a high-voltage radiation-hardened lateral device, to prepare a high-voltage radiation-hardened lateral device as described in any one of claims 1 to 9, characterized in that, include: A substrate is provided, and a P-type impurity is implanted on the substrate surface using an ion implantation process to form a first P-type doped region (31). P-type impurities are implanted on the substrate surface using photolithography and ion implantation processes, and a second P-type doped region is formed by annealing (32). N-type impurities are implanted on the substrate surface using photolithography and ion implantation processes, and the first N-type doped region is formed by annealing (41). P-type impurities are implanted into the second P-type doped region (32) using an ion implantation process, and a third P-type doped region (33) is formed by an annealing process. P-type impurities were implanted on the substrate surface using an ion implantation process, and a fourth P-type doped region was formed by an annealing process (34). An oxidation process is used to grow a first dielectric layer (21) on the substrate surface, and a deposition process is used to deposit a second dielectric layer (22) on the surface of the first dielectric layer (21). The first dielectric layer (21) and the second dielectric layer (22) on the surface of the active region are removed by photolithography and etching processes. An oxidation process is used to grow a third dielectric layer on the surface of the active region (23). Polysilicon is deposited on the surface of the device, and a polysilicon gate electrode is formed by photolithography and etching processes (51). Using photolithography and ion implantation processes, N-type impurities are implanted into the second P-type doped region (32) and the first N-type doped region (41) to form the second N-type doped region (42) and the third N-type doped region (43), respectively. Using photolithography and ion implantation processes, P-type impurities are implanted in the third P-type doped region (33) and the fourth P-type doped region (34) to form the fifth P-type doped region (35) and the sixth P-type doped region (36), respectively. A fourth dielectric layer (24) is deposited on the surface of the device, and a first contact hole (71), a second contact hole (72) and a third contact hole (73) are formed by photolithography and etching processes. A first source metal (61) and a first drain metal (62) are formed by deposition and etching processes.