Semiconductor power device and forming method thereof

Abstract

The invention provides a semiconductor power device and a forming method thereof, the semiconductor power device comprises a substrate and a nucleating layer, a buffer layer and a dislocation regulation and control layer which are sequentially formed on the substrate, the dislocation regulation and control layer comprises a first high-resistance layer, a patterned lattice mismatch layer and a second high-resistance layer, the first high-resistance layer is formed on the buffer layer, and the second high-resistance layer is formed on the patterned lattice mismatch layer. The patterned lattice mismatch layer is formed on the first high-resistance layer and exposes a part of the first high-resistance layer, the second high-resistance layer covers the exposed first high-resistance layer and extends to cover the patterned lattice mismatch layer, and the second high-resistance layer has blade type dislocation. Due to the existence of the blade type dislocation, continuously distributed hole traps can be induced around the blade type dislocation and are coupled with the original traps in the buffer layer, a channel for hole transmission can be formed, hole redistribution is realized through the channel, electron accumulation in the buffer layer can be effectively relieved, and the dynamic performance degradation of the device can be inhibited.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor power device and a method for forming the same. Background Technology

[0002] Dynamic on-resistance is a key parameter for evaluating the performance of gallium nitride (GaN) power devices in practical power supply applications. An increase in its value directly leads to additional conduction losses, thus affecting the conversion efficiency, temperature rise control, and long-term operational reliability of the entire power system. When the device is in high-frequency switching operation, the degradation of dynamic on-resistance is mainly due to the charge trapping effect in the epitaxial layer. Specifically, numerous defects in the device structure (including surface states, interface states, and the buffer layer) trap or release charge carriers during switching, creating dynamic electrostatic modulation of the channel, causing the on-resistance to increase with the number of switching cycles or stress time. Therefore, it is necessary to reduce the degradation of dynamic on-resistance to effectively suppress the dynamic performance degradation of the device. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor power device and a method for forming the same, so as to suppress the dynamic performance degradation of the device.

[0004] To achieve the above objectives, the present invention provides a semiconductor power device, comprising:

[0005] Substrate;

[0006] A nucleation layer is formed on the substrate;

[0007] A buffer layer is formed on the nucleation layer;

[0008] The dislocation control layer includes a first high-resistivity layer, a patterned lattice mismatch layer, and a second high-resistivity layer. The first high-resistivity layer is formed on the buffer layer. The patterned lattice mismatch layer is formed on the first high-resistivity layer and exposes a portion of the first high-resistivity layer. The second high-resistivity layer covers the exposed first high-resistivity layer and extends to cover the patterned lattice mismatch layer. The second high-resistivity layer contains edge dislocations. Optionally, in the semiconductor power device, the material of the lattice mismatch layer is Al. x Ga 1-x N or In x Ga 1-x N, where 0.1 <x≤1。

[0009] Optionally, in the semiconductor power device, the patterned lattice mismatch layer has at least one opening, and the second high-resistivity layer fills the opening and extends to cover the top surface of the patterned lattice mismatch layer.

[0010] Optionally, in the semiconductor power device, both the first high-resistivity layer and the second high-resistivity layer are made of carbon-doped gallium nitride.

[0011] Optionally, in the semiconductor power device, the semiconductor power device further includes:

[0012] The channel layer is formed on the second high-resistivity layer;

[0013] A barrier layer is formed on the channel layer;

[0014] A cap layer is formed on the barrier layer.

[0015] Based on the same inventive concept, the present invention also provides a method for forming a semiconductor power device, comprising:

[0016] Provide substrate;

[0017] A nucleation layer is formed on the substrate;

[0018] A buffer layer is formed on the nucleation layer;

[0019] A dislocation control layer is formed, comprising a first high-resistivity layer, a patterned lattice mismatch layer, and a second high-resistivity layer. The first high-resistivity layer is formed on the buffer layer, the patterned lattice mismatch layer is formed on the first high-resistivity layer and exposes a portion of the first high-resistivity layer, and the second high-resistivity layer covers the exposed first high-resistivity layer and extends to cover the patterned lattice mismatch layer. The second high-resistivity layer has edge dislocations.

[0020] Optionally, in the method for forming the semiconductor power device, the patterned lattice mismatch layer has at least one opening, and the second high-resistivity layer fills the opening and extends to cover the top surface of the patterned lattice mismatch layer.

[0021] Optionally, in the method for forming the semiconductor power device, the method for forming the patterned lattice mismatch layer includes:

[0022] A lattice mismatch layer is formed on the first high-resistivity layer, and the lattice mismatch layer covers the first high-resistivity layer;

[0023] A patterned photoresist layer is formed on the first high-resistivity layer, the patterned photoresist layer exposing a portion of the lattice mismatch layer;

[0024] Using the patterned photoresist layer as a mask, the exposed lattice mismatch layer is etched using a dry etching process to form the patterned lattice mismatch layer.

[0025] Optionally, in the method for forming the semiconductor power device, the lattice mismatch layer is formed at a temperature of 600°C-900°C.

[0026] Optionally, in the method for forming the semiconductor power device, after forming the dislocation modulation layer, the method further includes:

[0027] A channel layer is formed on the second high-resistivity layer;

[0028] A barrier layer is formed on the channel layer;

[0029] A cap layer is formed on the barrier layer.

[0030] In the semiconductor power device and its formation method provided by this invention, a nucleation layer is formed on a substrate to provide pre-compressive stress, a buffer layer is formed on the nucleation layer to store compressive stress and thus compensate for tensile stress, and a dislocation control layer is formed on the buffer layer. The dislocation control layer includes a first high-resistivity layer, a patterned lattice mismatch layer, and a second high-resistivity layer. The first high-resistivity layer is formed on the buffer layer, the patterned lattice mismatch layer is formed on the first high-resistivity layer and exposes part of the first high-resistivity layer, and the second high-resistivity layer covers the exposed first high-resistivity layer and extends to cover the patterned lattice mismatch layer, and the second high-resistivity layer has edge dislocations. Due to the presence of edge dislocations, continuously distributed hole traps can be induced around them and coupled with the original traps in the buffer layer to form a channel for hole transport (i.e., a hole channel). Hole redistribution is achieved through this channel, which can effectively alleviate electron accumulation in the buffer layer and thus suppress the dynamic performance degradation of the device. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of a semiconductor power device provided in an embodiment of the present invention.

[0032] Figure 2 This is a schematic flowchart of a method for forming a semiconductor power device provided in an embodiment of the present invention.

[0033] Figures 3 to 8 This is a schematic diagram of the structure formed in the method for forming a semiconductor power device provided in an embodiment of the present invention.

[0034] The reference numerals in the attached figures are explained as follows:

[0035] 100 - Substrate; 110 - Nucleation layer; 120 - Buffer layer; 130 - Dislocation control layer; 131 - First high-resistivity layer; 132 - Lattice mismatch layer; 132a - Patterned lattice mismatch layer; 132b - Opening; 133 - Second high-resistivity layer; 133a - Edge dislocation; 140 - Patterned photoresist layer; 150 - Channel layer; 160 - Barrier layer; 170 - Cap layer. Detailed implementation manners

[0036] The following further elaborates on the semiconductor power device and its forming method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. Specifically, the emphases to be shown in each accompanying drawing are different, and sometimes different scales are used.

[0037] Figure 1 is a schematic structural diagram of the semiconductor power device provided by an embodiment of the present invention. As Figure 1 shown, the semiconductor power device provided in this embodiment includes a substrate 100, and a nucleation layer 110, a buffer layer 120, and a dislocation control layer 130 formed on the substrate 100 in sequence.

[0038] In this embodiment, the substrate 100 can be a silicon substrate 100.

[0039] As Figure 1 shown, the nucleation layer 110 is formed on the substrate 100, and the material of the nucleation layer 110 can be aluminum nitride (AlN), which can act as a wetting layer and can provide pre-compressive stress. Among them, the thickness of the nucleation layer 110 can be 100 nm to 250 nm.

[0040] As Figure 1 shown, the buffer layer 120 is formed on the nucleation layer 110, and the buffer layer 120 can cover the top surface of the nucleation layer 110. Among them, the buffer layer 120 is used to store compressive stress to compensate for the tensile stress suffered by the dislocation control layer 130 during the device cooling process.

[0041] In some embodiments, the material of the buffer layer 120 can include AlN and / or AlGaN.

[0042] In some embodiments, the buffer layer 120 can be a superlattice structure in which Al(Ga)N layers and AlGaN layers are alternately stacked.

[0043] In a further method, the buffer layer 120 includes a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer stacked in sequence from bottom to top to store compressive stress, so as to better compensate for the tensile stress suffered by the dislocation control layer 130 during the device cooling process. Specifically, the material of the first buffer layer can be Al x Ga 1-x N, where 0.6 < x < 0.8; the material of the second buffer layer can be Al x Ga1-x N, where 0.4 < x < 0.6; the material of the third buffer layer can be Al x Ga 1-x N, where 0.2 < x < 0.4; the material of the fourth buffer layer can be Al x Ga 1-x N, where 0.1 < x < 0.3. The thickness of the first buffer layer can be 100 nm to 300 nm; the thickness of the second buffer layer can be 100 nm to 600 nm; the thickness of the third buffer layer can be 100 nm to 800 nm; the thickness of the fourth buffer layer can be 100 nm to 2000 nm. In this embodiment, the thickness of the buffer layer 120 can be set according to the breakdown voltage level of the device. For example, the thickness of the buffer layer 120 can be 500 nm to 2 μm.

[0044] In this embodiment, as Figure 1 shown, the dislocation control layer 130 is formed on the buffer layer 120, and the dislocation control layer 130 includes a first high-resistance layer 131, a patterned lattice mismatch layer 132a, and a second high-resistance layer 133.

[0045] Specifically, the material of the first high-resistance layer 131 can be gallium nitride doped with carbon, and the thickness of the first high-resistance layer 131 can be 100 nm to 300 nm.

[0046] As Figure 1 shown, the patterned lattice mismatch layer 132a is formed on the first high-resistance layer 131 and exposes part of the first high-resistance layer 131. The second high-resistance layer 133 covers the exposed first high-resistance layer 131 and extends to cover the patterned lattice mismatch layer 132a, and there are edge dislocations 133a in the second high-resistance layer 133. Among them, there are edge dislocations 133a in the second high-resistance layer 133 induced by lattice mismatch and caused by the three-dimensional island merging process of the second high-resistance layer.

[0047] It has been found through research that edge dislocations in the GaN epitaxial layer can act as independent transport paths for holes. Edge dislocations induce the formation of a continuously distributed hole trap around them, and these traps are coupled with the C N type defects in the carbon-doped buffer layer to form a "hole channel". The hole redistribution assisted by edge dislocations helps to relieve the electron accumulation in the buffer layer, thereby reducing the dynamic performance degradation. Due to the existence of edge dislocations 133a in the second high-resistance layer 133, a continuously distributed hole trap can be induced around it and coupled with the original traps in the buffer layer (such as C N traps), and a channel for hole transport (i.e., a hole channel) can be formed. Through this channel, hole redistribution can be achieved, which can effectively relieve the electron accumulation in the buffer layer 120 and thus suppress the dynamic performance degradation of the device.

[0048] Specifically, refer to Figure 1 and combined Figure 7 As shown, the patterned lattice mismatch layer 132a has at least one opening 132b, which exposes a portion of the first high-resistivity layer 131. More specifically, the cross-sectional shape of the patterned lattice mismatch layer 132a in the horizontal direction of the substrate 100 can be strip-shaped, circular, or grid-like. The thickness of the patterned lattice mismatch layer 132a can be 10 nm to 100 nm.

[0049] In a further embodiment, the patterning period of the patterned lattice mismatch layer 132a and the size of the opening 132b can be designed accordingly by matching different device sizes.

[0050] In some embodiments, the lattice mismatch layer 132 is made of Al. x Ga 1-x N, where 0.1 <x≤1。

[0051] In some embodiments, the lattice mismatch layer 132 is made of In. x Ga 1-x N, where 0.1 <x≤1。

[0052] Continue to refer to Figure 1 As shown, the second high-resistivity layer 133 fills the opening 132b and extends to cover the top surface of the patterned lattice mismatch layer 132a. The material of the second high-resistivity layer 133 is carbon-doped gallium nitride (GaN).

[0053] In this embodiment, due to the presence of the patterned lattice mismatch layer 132a, the second high-resistivity layer 133 preferentially grows in a three-dimensional island shape within the opening 132b during its growth process. Specifically, the second high-resistivity layer 133 first nucleates in the opening 132b and grows vertically to form multiple independent three-dimensional island structures (i.e., GaN islands) with specific crystallographic faces on their sides. As the second high-resistivity layer 133 continues to grow, adjacent GaN islands extend laterally to the top surface of the patterned lattice mismatch layer 132a until they contact and merge. At the vertical interface where GaN islands merge, if the crystal orientations of adjacent GaN islands have a slight tilt or rotation, they cannot be completely spliced ​​into a single crystal. To reconcile the lattice mismatch, edge dislocations 133a are spontaneously formed. The Burgers vector of the edge dislocation 133a is usually located within the interface plane to compensate for the lattice mismatch and crystal orientation difference.

[0054] Further, since the merging interface of the GaN islands is determined by the pattern of the patterned lattice mismatch layer 132a, the edge dislocations 133a in the second high-resistance layer 133 also exhibit a periodic array corresponding to the pattern of the patterned lattice mismatch layer 132a, that is, the edge dislocations 133a in the second high-resistance layer 133 are arranged periodically. Further, since the distribution of the edge dislocations 133a in the second high-resistance layer 133 is periodic and controllable, the device has better consistency and repeatability.

[0055] In this embodiment, as Figure 1 shown, the semiconductor power device further includes a channel layer 150, the channel layer 150 is formed on the second high-resistance layer 133, and the channel layer 150 may cover the second high-resistance layer 133. Among them, the material of the channel layer 150 may be undoped gallium nitride, and the thickness of the channel layer 150 may be 100 nm - 500 nm.

[0056] As Figure 1 shown, the semiconductor power device further includes a barrier layer 160, the barrier layer 160 is formed on the channel layer 150, and the barrier layer 160 may cover the channel layer 150. Among them, the material of the barrier layer 160 includes AlN (aluminum nitride) and / or Al x Ga 1-x N (aluminum gallium nitride), 0.15 < x ≤ 0.25, and the thickness of the barrier layer 160 may be 10 nm - 25 nm.

[0057] As Figure 1 shown, the semiconductor power device further includes a cap layer 170, the cap layer 170 is formed on the barrier layer 160, and the cap layer 170 may cover the barrier layer 160. Among them, the material of the cap layer 170 may be gallium nitride. Further, if the semiconductor power device is a depletion-type device (normally on), the material of the barrier layer 160 is undoped gallium nitride, and the thickness of the cap layer 170 is 1 nm - 3 nm; if the semiconductor power device is an enhancement-type device (normally off), the material of the barrier layer 160 is P-type doped gallium nitride, and the thickness of the cap layer 170 is 70 nm - 100 nm.

[0058] In this embodiment, the semiconductor power device may be a gallium nitride high electron mobility transistor (GaN HEMT, High Electron Mobility Transistor).

[0059] Figure 2 is a schematic flow chart of the method for forming the semiconductor power device provided by the present invention. As Figure 2 shown, this embodiment further provides a method for forming a semiconductor power device, including:

[0060] Step S1: Provide a substrate;

[0061] Step S2: Forming a nucleation layer on the substrate;

[0062] Step S3: Form a buffer layer on the nucleation layer;

[0063] Step S4: Form a dislocation control layer, the dislocation control layer including a first high-resistivity layer, a patterned lattice mismatch layer and a second high-resistivity layer, the first high-resistivity layer is formed on the buffer layer, the patterned lattice mismatch layer is formed on the first high-resistivity layer and exposes part of the first high-resistivity layer, the second high-resistivity layer covers the exposed first high-resistivity layer and extends to cover the patterned lattice mismatch layer, the second high-resistivity layer has edge dislocations.

[0064] Figures 3 to 8 This is a schematic diagram of the structure formed in the method for forming a semiconductor power device provided in an embodiment of the present invention. The following will refer to the accompanying drawings. Figures 3 to 8 The method for forming the semiconductor power device provided in this embodiment will be described in more detail.

[0065] First, such as Figure 3 As shown, step S1 is performed to provide a substrate 100. The material of the substrate 100 can be any suitable material known to those skilled in the art, for example, the substrate 100 can be a silicon substrate 100, and the crystal orientation of the substrate 100 is... <111> .

[0066] Next, as Figure 3 As shown, step S2 is performed to form a nucleation layer 110, which is formed on the substrate 100. The material of the nucleation layer 110 can be aluminum nitride (AlN), which can act as a wetting layer and provide pre-stress.

[0067] Next, as Figure 3 As shown, step S3 is performed to form a buffer layer 120, which is formed on the nucleation layer 110. The buffer layer 120 can cover the top surface of the nucleation layer 110. The buffer layer 120 is used to store compressive stress to compensate for the tensile stress experienced by the dislocation modulation layer 130 during device cooling.

[0068] In some embodiments, the material of the buffer layer 120 may include AlN and / or AlGaN.

[0069] In some embodiments, the buffer layer 120 may be a superlattice structure consisting of alternating stacks of Al(Ga)N and AlGaN layers.

[0070] Next, as Figure 1As shown, step S4 is performed to form a dislocation control layer 130. The dislocation control layer 130 includes a first high-resistivity layer 131, a patterned lattice mismatch layer 132a, and a second high-resistivity layer 133. The first high-resistivity layer 131 is formed on the buffer layer 120. The patterned lattice mismatch layer 132a is formed on the first high-resistivity layer 131 and exposes a portion of the first high-resistivity layer 131. The second high-resistivity layer 133 covers the exposed first high-resistivity layer 131 and extends to cover the patterned lattice mismatch layer 132a. The second high-resistivity layer 133 contains edge dislocations 133a. Specifically, the edge dislocations 133a in the second high-resistivity layer 133 are induced by lattice mismatch and caused by the three-dimensional island merging process of the second high-resistivity layer. Due to the presence of the edge dislocation 133a in the second high-resistivity layer 133, a continuously distributed hole trap can be induced around it and coupled with the original trap in the buffer layer 120 to form a channel for hole transport (i.e., a hole channel). Hole redistribution can be achieved through this channel, which can effectively relieve the accumulation of electrons in the stress-relieving buffer layer and thus suppress the dynamic performance degradation of the device.

[0071] In this embodiment, as Figure 4 As shown, a first high-resistivity layer 131 is formed on the buffer layer 120. The first high-resistivity layer 131 can cover the buffer layer 120 and is used to improve the leakage current of the buffer layer 120. The material of the first high-resistivity layer 131 can be doped gallium nitride.

[0072] For example, the first high-resistivity layer 131 can be formed by metal-organic chemical vapor deposition (MOCVD). C2H4 can be used as the carbon doping source to form carbon-doped gallium nitride, thereby forming the first high-resistivity layer 131.

[0073] like Figure 7 As shown, after the formation of the first high-resistivity layer 131, a patterned lattice mismatch layer 132a is formed on the first high-resistivity layer 131 and exposes a portion of the first high-resistivity layer 131.

[0074] In this embodiment, the pattern of the patterned lattice mismatch layer 132a can be strip-shaped, circular, or grid-shaped in the horizontal direction of the substrate 100.

[0075] In a further embodiment, the patterning period of the patterned lattice mismatch layer 132a and the size of the opening 132b can be designed accordingly by matching different device sizes.

[0076] Specifically, the method for forming the patterned lattice mismatch layer 132a includes: such as Figure 5 As shown, a lattice mismatch layer 132 is formed on the first high-resistivity layer 131. The lattice mismatch layer 132 can cover the first high-resistivity layer 131, and the lattice mismatch layer 132 has misfit dislocations.

[0077] In some embodiments, the lattice mismatch layer 132 is made of Al. x Ga 1-x N, where 0.1 <x≤1。

[0078] In some embodiments, the lattice mismatch layer 132 is made of In. x Ga 1-x N, where 0.1 <x≤1。

[0079] For example, the lattice mismatch layer 132 can be formed by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The lattice mismatch layer 132 is formed at a temperature of 600℃-900℃, such as 650℃, 700℃, 750℃ or 800℃, and the thickness of the lattice mismatch layer 132 can be 10nm-100nm.

[0080] Next, as Figure 6 As shown, a patterned photoresist layer 140 is formed on the first high-resistivity layer 131, and the patterned photoresist layer 140 exposes a portion of the lattice mismatch layer 132.

[0081] Next, as Figure 7 As shown, using the patterned photoresist layer 140 as a mask, the exposed lattice mismatch layer 132 is etched using a dry etching process to form the patterned lattice mismatch layer 132a. The patterned lattice mismatch layer 132a has at least one opening 132b, for example, three or five openings 132b, and each opening 132b exposes a portion of the first high-resistivity layer 131.

[0082] Next, the patterned photoresist layer 140 is removed. Afterwards, as... Figure 8 As shown, a second high-resistivity layer 133 is formed, which fills the opening 132b and extends to cover the top surface of the patterned lattice mismatch layer 132a. The material of the second high-resistivity layer 133 is carbon-doped gallium nitride (GaN).

[0083] In this embodiment, the second high-resistivity layer 133 can be formed by metal-organic chemical vapor deposition (MOCVD). C2H4 can be used as the carbon doping source to form carbon-doped gallium nitride, which in turn forms the second high-resistivity layer 133. Due to the presence of the patterned lattice mismatch layer 132a, the second high-resistivity layer 133 preferentially grows in a three-dimensional island shape within the opening 132b during its growth process.

[0084] Specifically, the second high-resistivity layer 133 first nucleates in the opening 132b and grows vertically to form multiple independent three-dimensional island structures (i.e., GaN islands) with specific crystallographic planes on their sides. As the second high-resistivity layer 133 continues to grow, adjacent GaN islands extend laterally to the top surface of the patterned lattice mismatch layer 132a until the adjacent GaN islands contact and merge (i.e., form a continuous GaN thin film). At the vertical interface where GaN islands merge, if there is a slight tilt or rotation in the crystal orientation of adjacent GaN islands, they cannot be completely spliced ​​into a single crystal. To reconcile the lattice mismatch, edge dislocations 133a are spontaneously formed. The Burgers vector of the edge dislocation 133a is usually located in the interface plane to compensate for the lattice mismatch and crystal orientation difference.

[0085] Furthermore, since the merging interface of the GaN islands is determined by the pattern of the patterned lattice mismatch layer 132a, the arrangement of the edge dislocations 133a in the second high-resistivity layer 133 corresponds to the arrangement of the patterned lattice mismatch layer 132a, thereby enabling the edge dislocations 133a in the second high-resistivity layer 133 to be periodically arranged on the patterned lattice mismatch layer 132a.

[0086] Furthermore, since the distribution of the edge dislocations 133a in the second high-resistivity layer 133 is periodic and controllable, the device exhibits better consistency and repeatability.

[0087] like Figure 1 As shown, after forming the second high-resistivity layer 133, a channel layer 150 is formed on the second high-resistivity layer 133, and the channel layer 150 can cover the second high-resistivity layer 133. The material of the channel layer 150 can be undoped gallium nitride, and the thickness of the channel layer 150 can be 100nm-500nm.

[0088] Next, as Figure 1As shown, a barrier layer 160 is formed on the channel layer 150, and the barrier layer 160 can cover the channel layer 150. The material of the barrier layer 160 includes AlN (aluminum nitride) and / or Al. x Ga 1-x N (aluminum gallium nitride), 0.15 <x≤0.25。

[0089] In this embodiment, the thickness of the barrier layer 160 can be 10nm-25nm.

[0090] After that, as Figure 1 As shown, a cap layer 170 is formed on the barrier layer 160, and the cap layer 170 can cover the barrier layer 160. The material of the cap layer 170 can be gallium nitride. Further, if the semiconductor power device is a depletion-mode device (normally on), then the material of the barrier layer 160 is undoped gallium nitride, and the thickness of the cap layer 170 is 1nm-3nm; if the semiconductor power device is an enhancement-mode device (normally off), then the material of the barrier layer 160 is p-type doped gallium nitride, and the thickness of the cap layer 170 is 70nm-100nm.

[0091] In summary, in the semiconductor power device and its formation method provided by this invention, a nucleation layer is formed on a substrate to provide pre-compressive stress, a buffer layer is formed on the nucleation layer to store compressive stress, thereby compensating for tensile stress, and a dislocation control layer is formed on the buffer layer. The dislocation control layer includes a first high-resistivity layer, a patterned lattice mismatch layer, and a second high-resistivity layer. The patterned lattice mismatch layer is formed on the first high-resistivity layer and exposes part of the first high-resistivity layer. The second high-resistivity layer covers the exposed first high-resistivity layer and extends to cover the patterned lattice mismatch layer, and the second high-resistivity layer contains edge dislocations. Due to the presence of edge dislocations, continuously distributed hole traps can be induced around them and coupled with the original traps in the buffer layer to form a channel for hole transport (i.e., a hole channel). Hole redistribution is achieved through this channel, which can effectively alleviate electron accumulation in the buffer layer and thus suppress the dynamic performance degradation of the device.

[0092] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0093] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor power device, characterized in that, include: Substrate; A nucleation layer is formed on the substrate; A buffer layer is formed on the nucleation layer; The dislocation control layer includes a first high-resistivity layer, a patterned lattice mismatch layer, and a second high-resistivity layer. The first high-resistivity layer is formed on the buffer layer. The patterned lattice mismatch layer is formed on the first high-resistivity layer and exposes a portion of the first high-resistivity layer. The second high-resistivity layer covers the exposed first high-resistivity layer and extends to cover the patterned lattice mismatch layer. The second high-resistivity layer has edge dislocations.

2. The semiconductor power device as described in claim 1, characterized in that, The lattice mismatch layer is made of Al. x Ga 1- x N or In x Ga 1-x N, where 0.1 <x≤1。 3. The semiconductor power device as described in claim 1, characterized in that, The patterned lattice mismatch layer has at least one opening, and the second high-resistivity layer fills the opening and extends to cover the top surface of the patterned lattice mismatch layer.

4. The semiconductor power device as described in claim 1, characterized in that, Both the first high-resistivity layer and the second high-resistivity layer are made of gallium nitride doped with carbon.

5. The semiconductor power device as described in claim 1, characterized in that, The semiconductor power device further includes: The channel layer is formed on the second high-resistivity layer; A barrier layer is formed on the channel layer; A cap layer is formed on the barrier layer.

6. A method for forming a semiconductor power device, characterized in that, include: Provide substrate; A nucleation layer is formed on the substrate; A buffer layer is formed on the nucleation layer; A dislocation control layer is formed, comprising a first high-resistivity layer, a patterned lattice mismatch layer, and a second high-resistivity layer. The first high-resistivity layer is formed on the buffer layer, the patterned lattice mismatch layer is formed on the first high-resistivity layer and exposes a portion of the first high-resistivity layer, and the second high-resistivity layer covers the exposed first high-resistivity layer and extends to cover the patterned lattice mismatch layer. The second high-resistivity layer has edge dislocations.

7. The method for forming a semiconductor power device as described in claim 6, characterized in that, The patterned lattice mismatch layer has at least one opening, and the second high-resistivity layer fills the opening and extends to cover the top surface of the patterned lattice mismatch layer.

8. The method for forming a semiconductor power device as described in claim 7, characterized in that, The method for forming the patterned lattice mismatch layer includes: A lattice mismatch layer is formed on the first high-resistivity layer, and the lattice mismatch layer covers the first high-resistivity layer; A patterned photoresist layer is formed on the first high-resistivity layer, the patterned photoresist layer exposing a portion of the lattice mismatch layer; Using the patterned photoresist layer as a mask, the exposed lattice mismatch layer is etched using a dry etching process to form the patterned lattice mismatch layer.

9. The method for forming a semiconductor power device as described in claim 8, characterized in that, The lattice mismatch layer is formed at a temperature of 600℃-900℃.

10. The method for forming a semiconductor power device as described in claim 6, characterized in that, After forming the dislocation control layer, the method further includes: A channel layer is formed on the second high-resistivity layer; A barrier layer is formed on the channel layer; A cap layer is formed on the barrier layer.

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