Preparation method of indium arsenide colloidal quantum dot infrared imaging chip and chip
By employing an indium arsenide colloidal quantum dot infrared imaging chip fabrication method in a short-wave infrared image sensor, spatial separation of charge collection and light absorption functions was achieved, solving the problems of insufficient response rate and detection uniformity in existing technologies and improving imaging performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-03-24
AI Technical Summary
Existing shortwave infrared image sensors suffer from numerous intrinsic defects and low electron mobility, resulting in high dark current, low detectivity, poor imaging performance, and insufficient response rate and detection uniformity.
The fabrication method of indium arsenide colloidal quantum dot infrared imaging chip involves sequentially depositing a top incident transparent electrode layer, a hole transport layer, a first and second InAs quantum dot thin layer, an electron transport layer, and a metal bottom electrode on a silicon substrate, and connecting them with a CMOS chip to form a double-layer quantum dot structure to achieve spatial separation of charge collection and light absorption.
It improves the response rate and detection uniformity of shortwave infrared image sensors, reduces dark current, and enhances imaging performance.
Smart Images
Figure CN121728951A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of photoelectric detection technology, and specifically relates to a method for preparing an indium arsenide colloidal quantum dot infrared imaging chip and the chip itself. Background Technology
[0002] With the development of short-wave infrared (SWIR) imaging technology, it has been widely applied in night vision surveillance, aerial remote sensing, industrial inspection, biomedicine, and intelligent security. Short-wave infrared image sensors and CMOS readout circuit integrated circuits are the mainstream approach for constructing high-performance short-wave infrared imaging systems. The CMOS readout circuit integrated circuit can be a complementary metal-oxide-semiconductor readout integrated circuit (CMOS ROIC), and the short-wave infrared image sensor includes a photodiode detector array.
[0003] In the existing technology, the short-wave infrared image sensors used in short-wave infrared imaging technology are made of materials such as Ag2Te and CuInSe2. Due to the large number of intrinsic defects and low electron mobility, the devices have high dark current, low detectivity, and poor imaging effect, resulting in problems such as low response rate and poor detection uniformity of short-wave infrared image sensors.
[0004] In summary, there is an urgent need for a short-wave infrared image sensor with high response rate and strong detection uniformity. Summary of the Invention
[0005] To address the aforementioned technical problems, this invention provides a method for fabricating an indium arsenide colloidal quantum dot infrared imaging chip and the chip itself. The short-wave infrared image sensor fabricated by this method has the advantages of high response rate and strong detection uniformity.
[0006] In a first aspect, this application provides a method for fabricating an indium arsenide (InAs) colloidal quantum dot infrared imaging chip, comprising the following steps: The chip silicon substrate is preprocessed, and wafer-level CMOS wiring has been completed on the chip silicon substrate; A top incident transparent electrode layer and a hole transport layer are sequentially deposited on the silicon substrate of the chip by physical vapor deposition (PVD) or solution method. A first thin layer of InAs quantum dots and a second thick layer of InAs quantum dots are sequentially deposited on the hole transport layer. An electron transport layer is formed on the second InAs quantum dot thick layer by spin coating or vapor deposition. A metal bottom electrode is formed on the electron transport layer; The metal bottom electrode is connected to the readout terminal of the CMOS chip to form an interconnect structure; The pixel ports of the interconnect structure are exposed using a photolithography mask and wet etching, and then sealed with nitrogen gas.
[0007] In one embodiment, the pretreatment of the chip silicon substrate includes: Plasma is used to treat the silicon substrate of the chip to enhance the adhesion of the layers formed on the silicon substrate of the chip.
[0008] In one embodiment, the step of sequentially depositing a top incident transparent electrode layer and a hole transport layer on the chip silicon substrate by physical vapor deposition (PVD) or solution method includes: The top incident transparent electrode layer is obtained by treating the silicon substrate of the chip with doped oxide or thin metal mesh layer; The NiOx nano-sol target material was coated onto the top incident transparent electrode layer by spin coating at 2000 rpm for 30 s to obtain the hole transport layer, and then annealed in air at 150°C for 10 min.
[0009] In one embodiment, the sequential deposition of a first thin layer of InAs quantum dots and a second thick layer of InAs quantum dots on the hole transport layer includes: A 20 mg / mL indium arsenide colloidal quantum dot (InAs) CQD solution was spin-coated onto the hole transport layer to a thickness of approximately 40 nm using n-octane as a solvent. Ligand exchange was performed using a combination solution of 1% ethylene dithiol and methanol EDT / MeOH. This process was repeated twice to obtain the first InAs quantum dot thin layer. A 20 mg / mL indium arsenide colloidal quantum dot (InAs) CQD solution was spin-coated onto a first InAs quantum dot layer to a thickness of approximately 300 nm using n-octane as the solvent. Ligand exchange was performed using a 0.1 mol / L indium bromide (InBr3) solution with DMF as the solvent, and the exchange was repeated four times to obtain a second InAs quantum dot layer.
[0010] In one embodiment, forming an electron transport layer on the second InAs quantum dot thick layer by spin coating or vapor deposition includes: A 10 nm C60 thin film was evaporated on the second InAs quantum dot thick layer; SnO2 solution was spin-coated onto a C60 film at 2000 rpm for 40 s to a thickness of about 40 nm, and then annealed at 100°C for 10 min to form an electron transport layer.
[0011] In one embodiment, forming a metal bottom electrode on the electron transport layer includes: A metal bottom electrode is formed on the electron transport layer by thermal evaporation or magnetron sputtering. The step of connecting the metal bottom electrode to the readout terminal of the CMOS chip to form an interconnect structure includes: The metal bottom electrode is used as the lower electrode and connected to the metal via of the CMOS chip to form the interconnect structure.
[0012] Secondly, this application provides an infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots, comprising, in sequence: a top incident transparent electrode layer, a hole transport layer, a first InAs quantum dot thin layer, a second InAs quantum dot thick layer, an electron transport layer, a metal bottom electrode, and a CMOS readout integrated circuit substrate. The top incident transparent electrode layer is used to transmit incident short-wave infrared light and simultaneously serves as the anode of the photodiode. The hole transport layer is used to adjust energy level alignment and improve hole injection efficiency, and to suppress carrier reverse leakage. The first InAs quantum dot thin layer is used as a collection region for photogenerated carriers; The second InAs quantum dot thick layer is used to absorb incident SWIR light and generate photogenerated electrons; The electron transport layer is used to transport electrons and block holes; The metal bottom electrode is used to connect to the readout terminal of the CMOS readout integrated circuit base plate; The CMOS readout integrated circuit base plate is used for the capacitor array and readout amplification of image readout.
[0013] In one embodiment, the hole transport layer is NiOx or MoOx.
[0014] In one embodiment, the thickness of the first InAs quantum dot thin layer is between 10 and 40 nm; and the thickness of the second InAs quantum dot thick layer is between 150 and 300 nm.
[0015] In one embodiment, the electron transport layer is C60, ZnO, or SnO2.
[0016] This application provides a method for fabricating an indium arsenide (InAs) colloidal quantum dot infrared imaging chip. First, a silicon substrate is pretreated. Then, a top incident transparent electrode layer and a hole transport layer are sequentially deposited on the silicon substrate using physical vapor deposition (PVD) or solution deposition. Next, a first thin InAs quantum dot layer and a second thick InAs quantum dot layer are sequentially deposited on the hole transport layer. Then, an electron transport layer is formed on the second thick InAs quantum dot layer using spin coating or evaporation. A metal bottom electrode is formed on the electron transport layer. The metal bottom electrode is then connected to the readout terminals of a CMOS chip to form an interconnect structure. Finally, the pixel ports of the interconnect structure are exposed using a photolithography mask and wet etching, and then sealed with nitrogen gas. This embodiment, by employing a dual-layer quantum dot structure—a first thin InAs quantum dot layer and a second thick InAs quantum dot layer—achieves spatial separation of charge collection and light absorption functions, thereby improving the device's response rate and detection uniformity. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic flowchart of the fabrication method of the indium arsenide (InAs) colloidal quantum dot infrared imaging chip disclosed in this invention. Figure 2 This is a schematic diagram of the structure of an embodiment of the infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots disclosed in this application; Figure 3 This is a schematic diagram of an embodiment of the indium arsenide (InAs) colloidal quantum dot integrated structure disclosed in this application; Figure 4 This is a schematic diagram of the structure of an embodiment of the infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots disclosed in this application. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] To make the technical problems, technical solutions, and beneficial effects of this invention clearer and more understandable, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0021] See Figure 1 , Figure 1 This is a schematic flowchart of the fabrication method of the indium arsenide (InAs) colloidal quantum dot infrared imaging chip disclosed in this invention. The fabrication method of the indium arsenide (InAs) colloidal quantum dot infrared imaging chip of this invention includes the following steps: Step 101: Pre-process the silicon substrate of the chip.
[0022] In this embodiment, plasma is used to treat the chip silicon substrate to enhance the adhesion of the layer fabricated on the chip silicon substrate. The chip silicon substrate has already undergone wafer-level CMOS wiring, and the chip silicon substrate material can be a 6-inch Complementary Metal Oxide Semiconductor (CMOS) readout integrated circuit (ROIC) chip (640 × 512 pixel array, pixel size 15μm).
[0023] Step 102: Deposit the top incident transparent electrode layer and the hole transport layer sequentially on the silicon substrate of the chip by physical vapor deposition (PVD) or solution method. Specifically, the top incident transparent electrode layer is obtained by treating the silicon substrate of the chip with doped oxide or thin metal mesh layer; The NiOx nano-sol target material was coated onto the top incident transparent electrode layer by spin coating at 2000 rpm for 30 s to obtain the hole transport layer, and then annealed in air at 150°C for 10 min.
[0024] In this embodiment, the hole transport layer (HTL) is preferably NiOx or MoOx, which is used to adjust the energy level alignment and improve the hole injection efficiency, while suppressing carrier reverse leakage.
[0025] Preferably, the hole transport layer can be a NiOx magnetron sputtered thin film.
[0026] This embodiment improves optical coupling efficiency and short-wavelength response efficiency by setting a top-incident transparent electrode layer and adopting a top-incident structure, so that the incident light does not need to penetrate the metal bottom electrode.
[0027] Step 103: Sequentially deposit a first InAs quantum dot thin layer and a second InAs quantum dot thick layer on the hole transport layer; In this embodiment, an indium arsenide colloidal quantum dot (InAs) CQD solution with a concentration of 20 mg / mL was spin-coated onto the hole transport layer to a thickness of approximately 40 nm using n-octane as the solvent. Ligand exchange was performed using a combination solution of 1% ethylene dithiol and methanol EDT / MeOH, repeated twice to obtain the first InAs quantum dot thin layer. The InAs CQD precursor solution in this embodiment was an n-octane solution containing InAs cores with a particle size of 5.2 ± 0.4 nm, and the original ligand was oleic acid.
[0028] Furthermore, in this embodiment, an indium arsenide colloidal quantum dot (InAs) CQD solution with a concentration of 20 mg / mL was spin-coated onto a first InAs quantum dot thin layer with a thickness of approximately 300 nm using n-octane as the solvent. Ligand exchange was performed using an indium bromide (InBr3) solution with a concentration of 0.1 mol / L and DMF as the solvent, and the exchange was performed four times to obtain a second InAs quantum dot thick layer.
[0029] Preferably, the first InAs quantum dot thin layer has a thickness between 10 and 40 nm, serving as a collection region for photogenerated carriers and improving the device response speed. The second InAs quantum dot thick layer has a thickness between 150 and 300 nm, mainly used to absorb incident SWIR light and generate photogenerated electrons.
[0030] This embodiment employs a dual-layer quantum dot structure, consisting of a thin InAs quantum dot layer and a thick InAs quantum dot layer, to achieve spatial separation of charge collection and light absorption functions, thereby improving the device's response rate and detection uniformity.
[0031] Step 104: An electron transport layer is formed on the second InAs quantum dot thick layer by spin coating or vapor deposition. Specifically, a 10 nm C60 thin film is evaporated onto the second InAs quantum dot thick layer; a SnO2 solution is spin-coated onto the C60 film at 2000 rpm for 40 s to a thickness of approximately 40 nm, and then annealed at 100°C for 10 min to form an electron transport layer. For example, the electron transport layer material is a 15% (w / w) tin dioxide (SnO2) colloidal solution, and pure C60 is deposited.
[0032] In this embodiment, the electron transport layer (ETL) is preferably made of C60, ZnO, or SnO2, which is used to transport electrons and block holes, thereby improving the overall rectification characteristics of the machine.
[0033] Step 105: Form a metal bottom electrode on the electron transport layer; In this embodiment, a transparent metal oxide is deposited on the electron transport layer to form a metal bottom electrode using thermal evaporation or magnetron sputtering. The metal bottom electrode (cathode) can be a low work function metal such as Al, Ag, or Au, and is directly connected to the readout terminal of the underlying CMOS chip. Preferably, the metal bottom electrode is a transparent metal oxide electrode with a thickness ranging from 20 to 100 nm.
[0034] Step 106: Connect the metal bottom electrode to the readout terminal of the CMOS chip to form an interconnect structure; In this embodiment, a transparent metal oxide is deposited as the lower electrode using thermal evaporation or magnetron sputtering methods, and then connected to the metal via of the CMOS chip to form an interconnect. Specifically, the metal bottom electrode is used as the lower electrode and connected to the metal via of the CMOS chip to form the interconnect structure. In other words, the CMOS readout integrated circuit (ROIC) substrate is manufactured using conventional silicon processes and embeds a capacitor array and a readout amplification module for image readout.
[0035] Step 107: Using a photolithography mask and wet etching, expose the pixel ports of the interconnect structure and perform nitrogen-sealed encapsulation.
[0036] In this embodiment, the pixel array is patterned using photolithography and wet etching or stripping processes; the pixel ports are exposed using a photolithographic mask and wet etching, the chip array is separated by dry etching, and then sealed and packaged with nitrogen gas.
[0037] Based on the above embodiments, the module is finally packaged into an imaging module and connected to the control circuit via low-temperature bonding.
[0038] This embodiment employs CMOS-compatible materials and processes, enabling the entire device to be fabricated at temperatures below 100°C, thus achieving the manufacturing of large-area, high-resolution image sensor arrays. Furthermore, the packaged imaging module exhibits excellent operational stability, capable of continuous operation for several weeks in a nitrogen atmosphere at room temperature, maintaining stable detection performance. Compared to traditional PbS and InGaAs detectors, this invention uses non-toxic, low-cost InAs quantum dot materials, solving the problems of Pb toxicity and the high cost of InGaAs manufacturing processes, while simultaneously achieving superior detection performance.
[0039] In this embodiment, the silicon substrate is pre-processed to ensure wafer-level CMOS wiring is completed. A top incident transparent electrode layer and a hole transport layer are sequentially deposited on the silicon substrate using physical vapor deposition (PVD) or solution deposition. A first thin InAs quantum dot layer and a second thick InAs quantum dot layer are sequentially deposited on the hole transport layer. An electron transport layer is formed on the second thick InAs quantum dot layer using spin coating or vapor deposition. A metal bottom electrode is formed on the electron transport layer. The metal bottom electrode is connected to the readout terminals of the CMOS chip to form an interconnect structure. The pixel ports of the interconnect structure are exposed using a photolithography mask and wet etching, and then sealed with nitrogen. By employing a dual-layer quantum dot structure—a first thin InAs quantum dot layer and a second thick InAs quantum dot layer—spatial separation of charge collection and light absorption functions is achieved, improving the device's response rate and detection uniformity.
[0040] In summary, this invention innovatively proposes a scalable InAs CQD infrared imaging chip solution from multiple perspectives, including device structure, integration method, material system, and fabrication process. This fills the technological gap between high integration and low-cost manufacturing in existing short-wave infrared lead-free image sensors and has broad engineering application and commercialization potential.
[0041] See Figure 2 , Figure 3 Figure 4 , Figure 2 This is a schematic diagram of the structure of an embodiment of the infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots disclosed in this application. Figure 3 This is a schematic diagram of an embodiment of the indium arsenide (InAs) colloidal quantum dot integrated structure disclosed in this application. Figure 4 This is a schematic diagram of the structure of an embodiment of the infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots disclosed in this application. The infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots provided in this embodiment includes, in sequence: a top incident transparent electrode layer, a hole transport layer, a first thin InAs quantum dot layer, a second thick InAs quantum dot layer, an electron transport layer, a metal bottom electrode, and a CMOS readout integrated circuit substrate; wherein... The top incident transparent electrode layer is used to transmit incident short-wave infrared light and simultaneously serves as the anode of the photodiode. The hole transport layer is used to adjust energy level alignment and improve hole injection efficiency, and to suppress carrier reverse leakage; preferably, the hole transport layer is NiOx or MoOx.
[0042] The first InAs quantum dot thin layer is used as the collection region for photogenerated carriers; the thickness of the first InAs quantum dot thin layer is between 10 and 40 nm. The second InAs quantum dot layer is used to absorb incident SWIR light and generate photogenerated electrons; the thickness of the second InAs quantum dot layer is between 150 and 300 nm.
[0043] The electron transport layer is used to transport electrons and block holes; in this embodiment, the electron transport layer is C60, ZnO, or SnO2.
[0044] The metal bottom electrode is used to connect to the readout terminal of the CMOS readout integrated circuit base plate; The CMOS readout integrated circuit base plate is used for the capacitor array and readout amplification of image readout.
[0045] In this embodiment, the infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots sequentially includes: a top incident transparent electrode layer, a hole transport layer, a first thin InAs quantum dot layer, a second thick InAs quantum dot layer, an electron transport layer, a metal bottom electrode, and a CMOS readout integrated circuit substrate. The top incident transparent electrode layer transmits incident short-wave infrared light and simultaneously serves as the anode of a photodiode. The hole transport layer adjusts energy level alignment, improves hole injection efficiency, and suppresses reverse carrier leakage. The first thin InAs quantum dot layer serves as a collection region for photogenerated carriers. The second thick InAs quantum dot layer absorbs incident SWIR light to generate photogenerated electrons. The electron transport layer transports electrons and blocks holes. The metal bottom electrode connects to the readout terminals of the CMOS readout integrated circuit substrate. The CMOS readout integrated circuit substrate serves as a capacitor array for image readout and for readout amplification. By employing a double-layer quantum dot structure, namely a thin layer of InAs quantum dots and a thick layer of InAs quantum dots, spatial separation of charge collection and light absorption functions is achieved, thereby improving the device's response rate and detection uniformity.
[0046] Furthermore, the specific performance testing methods and data for the aforementioned infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots are as follows: Dark current test At room temperature, the dark current of the BDT-InAs device was measured to be 33.5 nA / cm² at a bias voltage of –0.1 V, and 168 nA / cm² for the Control group (without intermediate processing).
[0047] Optical response and bandwidth testing The device rise time was measured to be 0.253 μs under 980 nm LED illumination, with a –3 dB bandwidth of 105 kHz and a responsivity of 0.089 A / W.
[0048] Detection (D) Measurement* The noise current was measured to be 17.8 fA / Hz^1 / 2 using the SR570 low-noise preamplifier and current spectrum, and D* = 2.97×10¹² Jones @1100 nm was calculated.
[0049] Imaging system performance evaluation (640×512 pixels) Average noise voltage: 0.72 mV; Effective pixel ratio: 99.7%; Dynamic range (DR): 50 dB (full resolution of 12 gray levels); Spatial resolution: MTF50 = 50 lp / mm (ISO 12233 test image, image software analysis); Stability: After encapsulation, the image showed no significant degradation after 300 days of continuous operation in a nitrogen atmosphere.
[0050] This application provides a method for fabricating an indium arsenide (InAs) colloidal quantum dot infrared imaging chip. First, a silicon substrate is pretreated. Then, a top incident transparent electrode layer and a hole transport layer are sequentially deposited on the silicon substrate using physical vapor deposition (PVD) or solution deposition. Next, a first thin InAs quantum dot layer and a second thick InAs quantum dot layer are sequentially deposited on the hole transport layer. Then, an electron transport layer is formed on the second thick InAs quantum dot layer using spin coating or evaporation. A metal bottom electrode is formed on the electron transport layer. The metal bottom electrode is then connected to the readout terminals of a CMOS chip to form an interconnect structure. Finally, the pixel ports of the interconnect structure are exposed using a photolithography mask and wet etching, and then sealed with nitrogen gas. This embodiment, by employing a dual-layer quantum dot structure—a first thin InAs quantum dot layer and a second thick InAs quantum dot layer—achieves spatial separation of charge collection and light absorption functions, thereby improving the device's response rate and detection uniformity.
[0051] The above description discloses only one preferred embodiment of the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art will understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.
Claims
1. A method for fabricating an indium arsenide (InAs) colloidal quantum dot infrared imaging chip, characterized in that, Includes the following steps: The chip silicon substrate is preprocessed, and wafer-level CMOS wiring has been completed on the chip silicon substrate; A top incident transparent electrode layer and a hole transport layer are sequentially deposited on the silicon substrate of the chip by physical vapor deposition (PVD) or solution method. A first thin layer of InAs quantum dots and a second thick layer of InAs quantum dots are sequentially deposited on the hole transport layer. An electron transport layer is formed on the second InAs quantum dot thick layer by spin coating or vapor deposition. A metal bottom electrode is formed on the electron transport layer; The metal bottom electrode is connected to the readout terminal of the CMOS chip to form an interconnect structure; The pixel ports of the interconnect structure are exposed using a photolithography mask and wet etching, and then sealed with nitrogen gas.
2. The method for preparing the indium arsenide (InAs) colloidal quantum dot infrared imaging chip according to claim 1, characterized in that, The pretreatment of the chip silicon substrate includes: Plasma is used to treat the silicon substrate of the chip to enhance the adhesion of the layers formed on the silicon substrate of the chip.
3. The method for preparing the indium arsenide (InAs) colloidal quantum dot infrared imaging chip according to claim 2, characterized in that, The process of sequentially depositing a top incident transparent electrode layer and a hole transport layer on the silicon substrate of the chip via physical vapor deposition (PVD) or solution method includes: The top incident transparent electrode layer is obtained by treating the silicon substrate of the chip with doped oxide or thin metal mesh layer; The NiOx nano-sol target material was coated onto the top incident transparent electrode layer by spin coating at 2000 rpm for 30 s to obtain the hole transport layer, and then annealed in air at 150°C for 10 min.
4. The method for preparing the indium arsenide (InAs) colloidal quantum dot infrared imaging chip according to claim 3, characterized in that, The process of sequentially depositing a first thin layer of InAs quantum dots and a second thick layer of InAs quantum dots on the hole transport layer includes: A 20 mg / mL indium arsenide colloidal quantum dot (InAs) CQD solution was spin-coated onto the hole transport layer to a thickness of approximately 40 nm using n-octane as a solvent. Ligand exchange was performed using a combination solution of 1% ethylene dithiol and methanol EDT / MeOH. This process was repeated twice to obtain the first InAs quantum dot thin layer. A 20 mg / mL indium arsenide colloidal quantum dot (InAs) CQD solution was spin-coated onto a first InAs quantum dot layer to a thickness of approximately 300 nm using n-octane as the solvent. Ligand exchange was performed using a 0.1 mol / L indium bromide (InBr3) solution with DMF as the solvent, and the exchange was repeated four times to obtain a second InAs quantum dot layer.
5. The method for preparing the indium arsenide (InAs) colloidal quantum dot infrared imaging chip according to claim 4, characterized in that, The formation of an electron transport layer on the second InAs quantum dot thick layer by spin coating or vapor deposition includes: A 10 nm C60 thin film was evaporated on the second InAs quantum dot thick layer; SnO2 solution was spin-coated onto a C60 film at 2000 rpm for 40 s to a thickness of about 40 nm, and then annealed at 100°C for 10 min to form an electron transport layer.
6. The method for preparing the indium arsenide (InAs) colloidal quantum dot infrared imaging chip according to claim 5, characterized in that, The formation of a metal bottom electrode on the electron transport layer includes: A metal bottom electrode is formed on the electron transport layer by thermal evaporation or magnetron sputtering. The step of connecting the metal bottom electrode to the readout terminal of the CMOS chip to form an interconnect structure includes: The metal bottom electrode is used as the lower electrode and connected to the metal via of the CMOS chip to form the interconnect structure.
7. An infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots, characterized in that, In order, they include: Top incident transparent electrode layer, hole transport layer, first InAs quantum dot thin layer, second InAs quantum dot thick layer, electron transport layer, metal bottom electrode, CMOS readout integrated circuit substrate; The top incident transparent electrode layer is used to transmit incident short-wave infrared light and simultaneously serves as the anode of the photodiode. The hole transport layer is used to adjust energy level alignment and improve hole injection efficiency, and to suppress carrier reverse leakage. The first InAs quantum dot thin layer is used as a collection region for photogenerated carriers; The second InAs quantum dot thick layer is used to absorb incident SWIR light and generate photogenerated electrons; The electron transport layer is used to transport electrons and block holes; The metal bottom electrode is used to connect to the readout terminal of the CMOS readout integrated circuit base plate; The CMOS readout integrated circuit base plate is used for the capacitor array and readout amplification of image readout.
8. The infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots according to claim 7, characterized in that, The hole transport layer is NiOx or MoOx.
9. The infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots according to claim 7, characterized in that, The thickness of the first InAs quantum dot thin layer is between 10 and 40 nm; the thickness of the second InAs quantum dot thick layer is between 150 and 300 nm.
10. The infrared imaging chip based on indium arsenide (InAs) colloidal quantum dots according to claim 7, characterized in that, The electron transport layer is C60, ZnO, or SnO2.