Method for forming N-type work function layer in grid electrode

Abstract

The invention relates to a method for forming an N-type work function layer in a grid electrode, and the method comprises the steps: enabling material atoms of the N-type work function layer to form the N-type work function layer in the grid electrode of a semiconductor substrate through employing first physical vapor deposition with lower bias voltage when the N-type work function layer is formed; then, second physical vapor deposition with high bias voltage is adopted to enable material atoms of the N-type work function layer to bombard the N-type work function layer at a higher speed, so that the atoms can fully fill a gap formed by the N-type work function layer in a grid electrode, and the N-type work function layer with a flat surface is formed; and therefore, the problem that a subsequent layer cannot be plated or a subsequent plating layer is relatively thin can be avoided.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuits, and more specifically, to a method for forming an N-type work function layer in a gate. Background Technology

[0002] As the size of semiconductor integrated circuits continues to shrink to below 45nm, the thickness of the gate dielectric layer also decreases to below 2nm. Using traditional transistor structures to make gates is prone to leakage current. In order to improve the above problems, high-K dielectric materials are often used to replace SiON as the gate oxide layer, and metal gates are used to replace traditional polysilicon gates. The process of forming the above semiconductor devices is called HKMG process technology.

[0003] In existing HKMG process technology, a work function layer needs to be placed near the semiconductor substrate to reduce the threshold voltage of N-type semiconductor devices. N-type semiconductor devices typically use physical vapor deposition to form the N-type work function layer. However, due to the narrow gate width, when forming the N-type work function layer within the gate using physical vapor deposition, the surface of the N-type work function layer is uneven, often resulting in protrusions. This can cause problems such as subsequent layers being unable to be deposited or subsequent deposited layers being too thin. Summary of the Invention

[0004] The purpose of this disclosure is to provide a method for forming an N-type work function layer in a gate to solve the problem of poor flatness of N-type work function layers in the prior art.

[0005] To achieve the above objectives, this disclosure provides a method for forming an N-type work function layer in a gate, the method comprising: S1. A semiconductor substrate with the P-type work function layer removed from the NMOS gate structure formation region is provided; S2. An N-type work function layer is formed on the surface of the semiconductor substrate by sequentially performing a first physical vapor deposition and a second physical vapor deposition. The bias voltage of the second physical vapor deposition is greater than that of the first physical vapor deposition.

[0006] Optionally, the material of the N-type work function layer is TiAl; the thickness of the N-type work function layer is 50~150 angstroms.

[0007] Optionally, the first physical vapor deposition and the second physical vapor deposition respectively include vacuum sputtering deposition or ion plating deposition.

[0008] Optionally, the reaction conditions for the first physical vapor deposition include: a substrate temperature of 20~300℃, a deposition material of a TiAl alloy target, and a molar ratio of Ti to Al in the TiAl alloy target of 1:1; the reaction conditions for the second physical vapor deposition include: a substrate temperature of 20~300℃, a deposition material of a TiAl alloy target, and a molar ratio of Ti to Al in the TiAl alloy target of 1:1.

[0009] Optionally, the ratio of the bias voltage of the first physical vapor deposition to the bias voltage of the second physical vapor deposition is (0.05~0.9):1.

[0010] Optionally, the semiconductor substrate includes a PMOS gate structure formation region and an NMOS gate structure formation region, wherein a P-type work function layer is formed in the PMOS gate structure formation region; The N-type work function layer is formed simultaneously in the NMOS gate structure formation region and the PMOS gate structure formation region; in the PMOS gate structure formation region, the N-type work function layer is superimposed on the surface of the P-type work function layer.

[0011] Optionally, the method further includes: S3. An anti-diffusion layer is formed on the surface of the N-type work function layer; S4. A metal gate is formed on the surface of the anti-diffusion layer.

[0012] Optionally, the anti-diffusion layer includes a first anti-diffusion layer and a second anti-diffusion layer; the second anti-diffusion layer is located above the first anti-diffusion layer. The material of the first anti-diffusion layer is TiN; The material of the second anti-diffusion layer is Ti.

[0013] Optionally, the material of the metal gate is Al.

[0014] Optionally, this method is used in 28nm and 22nm HKMG processes.

[0015] Through the above technical solution, when forming the N-type work function layer, a first physical vapor deposition with a lower bias voltage is first used to form the N-type work function layer material atoms in the gate of the semiconductor substrate to form the N-type work function layer. Then, a second physical vapor deposition with a higher bias voltage is used to bombard the N-type work function layer material atoms at a faster speed. This allows the atoms to fully fill the gaps formed between the N-type work function layer and the gate, forming a flat N-type work function layer. This avoids the problems of subsequent layers not being able to be deposited or subsequent deposited layers being too thin.

[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of a method for forming an N-type work function layer in a gate.

[0018] Figure 2 This is a flowchart of an HKMG process disclosed in this paper.

[0019] Figure 3 This is a schematic diagram of a semiconductor substrate with the P-type work function layer removed from the NMOS gate structure formation region disclosed herein.

[0020] Figure 4 This is a schematic diagram of a metal grid structure manufactured using the HKMG process disclosed herein.

[0021] Explanation of reference numerals in the attached figures 1. Silicon substrate; 2. Sidewall; 3. Oxide layer; 4. High-k dielectric layer; 5. Transition layer; 6. Lower anti-diffusion layer; 7. P-type work function layer; 8. N-type work function layer; 9. First anti-diffusion layer; 10. Second anti-diffusion layer; 11. Metal gate; 12. PMOS gate structure formation region; 13. NMOS gate structure formation region. Detailed Implementation

[0022] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0023] like Figure 1 As shown, this disclosure provides a method for forming an N-type work function layer in a gate, the method comprising: S1. A semiconductor substrate with the P-type work function layer removed from the NMOS gate structure formation region 13 is provided; S2. An N-type work function layer is formed on the surface of the semiconductor substrate by sequentially performing a first physical vapor deposition and a second physical vapor deposition. The bias voltage of the second physical vapor deposition is greater than that of the first physical vapor deposition.

[0024] Through the above technical solution, when forming the N-type work function layer, a first physical vapor deposition with a lower bias voltage is first used to form the N-type work function layer material atoms in the gate of the semiconductor substrate to form the N-type work function layer. Then, a second physical vapor deposition with a higher bias voltage is used to bombard the N-type work function layer material atoms at a faster speed. This allows the atoms to fully fill the gaps formed between the N-type work function layer and the gate, forming a flat N-type work function layer. This avoids the problems of subsequent layers not being able to be deposited or subsequent deposited layers being too thin.

[0025] In one implementation, such as Figure 3 As shown, the semiconductor substrate in step S1 contains sidewalls 2 in both the NMOS gate structure formation region 13 and the PMOS gate structure formation region 12. The sidewalls 2 of the NMOS gate structure formation region 13 and the PMOS gate structure formation region 12 form a trench between the sidewalls 2 and the silicon substrate 1 that can be filled with a metal gate.

[0026] The sidewall 2 is made of silicon nitride and / or silicon oxide.

[0027] In one embodiment, the silicon substrate 1 used in this disclosure is a conventional choice in the art, and this application does not make any special requirements. For example, the silicon substrate 1 can be an SOI substrate.

[0028] In one embodiment, the semiconductor substrate includes a PMOS gate structure formation region 12 and an NMOS gate structure formation region 13, wherein a P-type work function layer is formed in the PMOS gate structure formation region 12; the N-type work function layer is formed simultaneously in the NMOS gate structure formation region 13 and the PMOS gate structure formation region 12; in the PMOS gate structure formation region 12, the N-type work function layer is superimposed on the surface of the P-type work function layer.

[0029] In one specific embodiment, the semiconductor substrate in step S1 consists of an oxide layer 3, a high-k dielectric layer 4, a transition layer 5, and a lower anti-diffusion layer 6, arranged sequentially from bottom to top at the bottom of the trench in the NMOS gate structure formation region 13; the semiconductor substrate in step S1 consists of an oxide layer 3, a high-k dielectric layer 4, a transition layer 5, a lower anti-diffusion layer 6, and a P-type work function layer 7, arranged sequentially from bottom to top at the bottom of the trench in the PMOS gate structure formation region 12.

[0030] In one embodiment, the oxide layer 3 used in this disclosure is made of SiO2 and / or SiON. In this embodiment, the oxide layer 3 is disposed between the high-k dielectric layer 4 and the silicon substrate 1, which can eliminate the problems caused by the high-k dielectric layer 4 being directly disposed on the silicon substrate 1, and can obtain an ideal interface between SiON and Si and / or SiO2 and Si, thereby improving the influence of dipole vibration on carrier mobility.

[0031] In one embodiment, the high-k dielectric layer 4 used in this disclosure is selected from one or more of hafnium silicate oxide (HfSiO4), hafnium dioxide (HfO2), lanthanum oxide (La2O3), HfZrO2, zirconium dioxide (ZrO2), strontium titanate (SrTiO3), and zirconium silicate oxide (ZrSiO4). In this embodiment, the high-k dielectric layer 4 is disposed above the oxide layer 3, which can increase the physical thickness of the gate dielectric layer with the same equivalent thickness, reducing the risk of high power consumption due to gate leakage.

[0032] In one embodiment, the transition layer 5 used in this disclosure is made of TiN. In this embodiment, by providing the transition layer 5 above the high-k dielectric layer 4, the risk of ions from the functional layer disposed above it entering the high-k dielectric layer 4 and reacting, thus affecting the functional value, can be reduced.

[0033] In one embodiment, the material of the lower anti-diffusion layer 6 used in this disclosure is TaN. In this embodiment, the lower anti-diffusion layer 6 is disposed above the transition layer 5, which not only prevents ions located above the lower anti-diffusion layer 6 from entering the high-k dielectric layer 4, but also allows subsequent etching processes to stop at the tantalum nitride layer.

[0034] In one embodiment, the material of the P-type work function layer 7 used in this disclosure is TiN.

[0035] In one implementation, such as Figure 2 As shown, step S1 includes: S11. An oxide layer 3, a high-k dielectric layer 4 and a transition layer 5 are sequentially formed on the silicon substrate 1. S12. Perform a pseudo-polysilicon gate process on the NMOS gate structure formation region 13 and the PMOS gate structure formation region 12 to form a pseudo-polysilicon gate. S13. Perform pseudo-polysilicon gate removal processing on the pseudo-polysilicon gate above the transition layer 5 to form a trench for filling the metal gate above the transition layer 5; wherein, the trench includes an N-type metal gate trench corresponding to the position of the NMOS gate structure forming region 13 and a P-type metal gate trench corresponding to the position of the PMOS gate structure forming region 12. S14. A lower anti-diffusion layer 6 is formed on the surface of the NMOS gate structure formation region 13 and the PMOS gate structure formation region 12. S15. A P-type work function layer 7 is formed on the surface of the lower anti-diffusion layer 6; S16. Perform P-type work function layer removal processing on the trench of the NMOS gate structure forming region 13.

[0036] In one embodiment, the method for removing the P-type work function layer in step S16 is a conventional choice in the art, and this application does not make special requirements. For example, this application uses wet etching and / or dry etching to remove it; preferably, this application uses wet etching. In this embodiment, the etching solution used for wet etching can be SC1 etching solution and / or SC2 etching solution. Both SC1 and SC2 etching solutions are conventional choices in the art, and this application does not make special requirements.

[0037] In one embodiment, step S2 further includes depositing an N-type work function layer 8 on the surface of the semiconductor substrate obtained in step S16 using a first physical vapor deposition method, such that the N-type work function layer 8 covers the sides and bottom of each trench and extends outside the trench. A second physical vapor deposition method is then used to continue deposition on the surface of the layer formed by the first physical vapor deposition, with the deposition location similarly covering the sides and bottom of each trench and extending outside the trench.

[0038] In one embodiment, the N-type work function layer 8 is made of TiAl. In this embodiment, using TiAl as the N-type work function layer 8 can reduce the threshold voltage of the N-type semiconductor device and improve the performance of the semiconductor device.

[0039] In one embodiment, the thickness of the N-type work function layer 8 is 50-150 angstroms. In this embodiment, since the trajectory of TiAl molecules cannot be controlled during physical vapor deposition, uneven thickness may occur. Selecting a very thin N-type work function layer 8 can reduce the problems caused by uneven thickness.

[0040] In one embodiment, the first physical vapor deposition and the second physical vapor deposition described herein each include any one of vacuum evaporation deposition, vacuum sputtering deposition, arc plasma deposition, ion plating deposition, and molecular beam epitaxy deposition, preferably vacuum sputtering deposition or ion plating deposition.

[0041] In one embodiment, during the switching from the first physical vapor deposition to the second physical vapor deposition, the bias voltage is adjusted while the substrate remains unchanged.

[0042] In one embodiment, the reaction conditions for the first and second physical vapor depositions include substrate temperature, deposition material, deposition material concentration, deposition time, and bias voltage. In this embodiment, physical vapor deposition (PVD) refers to a technique that uses physical methods under vacuum conditions to vaporize the surface of a material source into gaseous atoms or molecules, or partially ionize them into ions, and then deposits a thin film with a specific function on the substrate surface.

[0043] In this disclosure, the substrate temperatures for the first and second physical vapor deposition processes are 20~300℃, respectively. In this embodiment, using a suitable substrate temperature allows gaseous atoms or molecules to be generated on the surface of the target material. The substrate temperature can be flexibly set according to actual production needs; for example, the substrate temperature can be 100℃, 120℃, 140℃, 160℃, 180℃, 200℃, 220℃, 240℃, 260℃, 280℃, and 300℃.

[0044] In this disclosure, the deposition material for the first physical vapor deposition and the second physical vapor deposition is a TiAl alloy target, wherein the molar ratio of Ti to Al in the TiAl alloy target is 1:1.

[0045] The concentration of the deposition material, deposition time, and bias voltage of the first physical vapor deposition and the second physical vapor deposition described in this disclosure can be flexibly set according to actual production needs, which will not be elaborated here.

[0046] In one embodiment, the ratio of the bias voltage of the first physical vapor deposition to the bias voltage of the second physical vapor deposition is (0.05~0.9):1, preferably (0.1~0.6):1. In this embodiment, when the ratio of the bias voltage of the first physical vapor deposition to the bias voltage of the second physical vapor deposition is appropriate, the second physical vapor deposition can fully fill the periphery formed by the two sidewalls of the N-type work function layer protrusion and the gate trench, thereby forming a smooth N-type work function layer. The ratio of the bias voltage of the first physical vapor deposition to the bias voltage of the second physical vapor deposition can be flexibly set according to actual production needs. For example, the ratio of the bias voltage of the first physical vapor deposition to the bias voltage of the second physical vapor deposition can be 0.1:1, 0.2:1, 0.3:1, 0.4:1, 0.5:1, 0.6:1, 0.7:1, 0.8:1, and 0.9:1.

[0047] In one embodiment, the method further includes: S3. An anti-diffusion layer is formed on the surface of the N-type work function layer; S4. A metal gate is formed on the surface of the anti-diffusion layer.

[0048] In one embodiment, the anti-diffusion layer includes a first anti-diffusion layer 9 and a second anti-diffusion layer 10; the second anti-diffusion layer 10 is located above the first anti-diffusion layer 9.

[0049] In one embodiment, the first anti-diffusion layer 9 is made of TiN, and the second anti-diffusion layer 10 is made of Ti; the first anti-diffusion layer 9 and the second anti-diffusion layer 10 can be formed by physical vapor deposition.

[0050] In one embodiment, the metal gate is made of Al.

[0051] In one embodiment, the method provided in this disclosure is used in 28nm and 22nm HKMG processes.

[0052] In one implementation, such as Figure 4 As shown, the semiconductor device fabricated using the method of this disclosure includes a PMOS gate structure formation region 12 and an NMOS gate structure formation region 13; wherein, the structure in the NMOS gate structure formation region 13 is, from bottom to top, an oxide layer 3, a high-k dielectric layer 4, a transition layer 5, a lower anti-diffusion layer 6, an N-type work function layer 8, a first anti-diffusion layer 9, a second anti-diffusion layer 10, and a metal gate 11; the structure in the PMOS gate structure formation region 12 is, from bottom to top, an oxide layer 3, a high-k dielectric layer 4, a transition layer 5, a lower anti-diffusion layer 6, a P-type work function layer 7, an N-type work function layer 8, a first anti-diffusion layer 9, a second anti-diffusion layer 10, and a metal gate 11.

[0053] In this embodiment, since the N-type work function layer 8 prepared by the method of this disclosure has good flatness, it can avoid the plating effect of the subsequent first anti-diffusion layer 9, second anti-diffusion layer 10 and metal gate 11, and fully guarantee the effect of the N-type work function layer 8, first anti-diffusion layer 9, second anti-diffusion layer 10 and metal gate 11, thereby improving the WAT parameters, yield and reliability of the prepared semiconductor.

[0054] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0055] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0056] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A method for forming an N-type work function layer in a gate, characterized in that, The method includes: S1. A semiconductor substrate with the P-type work function layer removed from the NMOS gate structure formation region is provided; S2. An N-type work function layer is formed on the surface of the semiconductor substrate by sequentially performing a first physical vapor deposition and a second physical vapor deposition. The bias voltage of the second physical vapor deposition is greater than that of the first physical vapor deposition.

2. The method according to claim 1, characterized in that, The material of the N-type work function layer is TiAl; the thickness of the N-type work function layer is 50~150 angstroms.

3. The method according to claim 1, characterized in that, The first physical vapor deposition and the second physical vapor deposition respectively include vacuum sputtering deposition or ion plating deposition.

4. The method according to claim 1, characterized in that, The reaction conditions for the first physical vapor deposition include: a substrate temperature of 20~300℃, a deposition material of TiAl alloy target, and a molar ratio of Ti to Al in the TiAl alloy target of 1:1; The reaction conditions for the second physical vapor deposition include: a substrate temperature of 20~300℃, a TiAl alloy target as the deposition material, and a Ti to Al molar ratio of 1:1 in the TiAl alloy target.

5. The method according to claim 1, characterized in that, The ratio of the bias voltage of the first physical vapor deposition to the bias voltage of the second physical vapor deposition is (0.05~0.9):

1.

6. The method according to claim 1, characterized in that, The semiconductor substrate includes a PMOS gate structure formation region and an NMOS gate structure formation region, wherein a P-type work function layer is formed in the PMOS gate structure formation region. The N-type work function layer is formed simultaneously in the NMOS gate structure formation region and the PMOS gate structure formation region; in the PMOS gate structure formation region, the N-type work function layer is superimposed on the surface of the P-type work function layer.

7. The method according to claim 1, characterized in that, The method also includes: S3. An anti-diffusion layer is formed on the surface of the N-type work function layer; S4. A metal gate is formed on the surface of the anti-diffusion layer.

8. The method according to claim 7, characterized in that, The anti-diffusion layer includes a first anti-diffusion layer and a second anti-diffusion layer; the second anti-diffusion layer is located above the first anti-diffusion layer. The material of the first anti-diffusion layer is TiN; The material of the second anti-diffusion layer is Ti.

9. The method according to claim 7, characterized in that, The material of the metal gate is Al.

10. The method according to claim 1, characterized in that, This method is used in 28nm and 22nm HKMG processes.

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