Semiconductor structure and forming method thereof
By forming an infrared sensing material layer inside the wafer and using infrared light alignment technology, the problem of positioning deviation in the traditional through-hole fabrication process was solved, achieving high-precision through-hole penetration and improving structural reliability, simplifying the process flow and improving current transmission capability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-03-24
AI Technical Summary
In semiconductor manufacturing, traditional through-hole fabrication processes rely on front-side alignment marks, which leads to positioning deviations in back-side photolithography and etching, making it difficult to achieve high-precision through-hole connections. This affects the uniformity of resistance and current transmission capability of the interconnect structure, thus limiting device performance and reliability.
After forming the first via in the wafer, an infrared sensing material layer is covered and a conductive material layer is filled. The wafer is then aligned on the second surface using infrared light alignment technology to form a second via that communicates with the first via. This simplifies the process and reduces the difficulty of alignment. The infrared sensing material layer acts as a buffer layer to alleviate thermal mismatch stress.
It achieves high-precision through-hole penetration without relying on front alignment marks, simplifies the process flow, improves the resistance uniformity and current transmission capability of the interconnect structure, and enhances the overall performance and reliability of the device.
Smart Images
Figure CN121729068A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the rapid development of integrated circuit technology, using via arrays to achieve wafer conductivity has become one of the key technologies for realizing high-density interconnects and improving chip performance and integration. In semiconductor manufacturing processes, as chip feature sizes continue to shrink to the nanometer level, transistor density increases exponentially. Traditional single-layer or simple multi-layer interconnect structures can no longer meet the stringent requirements of complex circuits for wiring resources and electrical performance. Therefore, back-end processes are commonly used to construct up to ten or more metal interconnect layers, and vias that penetrate vertically through dielectric layers are used to achieve electrical connections between conductors in different layers.
[0003] In through-hole (TH) fabrication, the alignment accuracy of the back-side photolithography and etching stages depends on the alignment mark on the front side. This process requires first forming the TH on the front side of the wafer through photolithography and etching, then applying a protective layer to the front side and flipping it over. Next, the back side is thinned, and infrared alignment technology is used to capture the front-side alignment mark. Through mirror photolithography and etching, high-precision interconnection of the TH within the wafer is achieved. However, since the mark is located on the front side of the wafer, the infrared signal is easily affected by the wafer material and the uniformity of thinning during wafer penetration, leading to difficulties in mark recognition and poor positioning stability. This makes the back-side photolithography and etching prone to positioning deviations, hindering the high-precision interconnection of the TH structure, affecting the uniformity of interconnect resistance and current transmission capability, and ultimately limiting the overall performance and long-term reliability of the device. Summary of the Invention
[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same.
[0005] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: providing a wafer having a first surface and a second surface opposite to each other along the thickness direction of the wafer; forming a first via in the wafer, the first via extending from the first surface of the wafer toward the second surface but not penetrating the second surface of the wafer; forming an infrared sensing material layer covering the sidewalls and bottom wall of the first via; filling the first via with a conductive material layer, the conductive material layer covering the infrared sensing material layer; providing incident light to irradiate the second surface of the wafer, the infrared sensing material layer generating infrared light under the irradiation of the incident light; aligning the infrared light generated from the second surface through the infrared sensing material layer to form a second via in the wafer, the second via extending from the second surface of the wafer toward the first surface, the first via communicating with the second via.
[0006] In some embodiments, the method further includes: forming a reflective material layer covering the sidewall and bottom wall of the first through hole before forming an infrared sensing material layer covering the sidewall and bottom wall of the first through hole; the forming of the infrared sensing material layer covering the sidewall and bottom wall of the first through hole includes: forming the infrared sensing material layer on the sidewall and bottom wall of the first through hole where the reflective material layer is formed, wherein the infrared sensing material layer covers the reflective material layer.
[0007] In some embodiments, the reflective material layer includes at least one of titanium dioxide, silicon, silicon dioxide, indium tin oxide, zinc gallium oxide, tantalum nitride, tantalum oxide, gallium arsenide, aluminum arsenide, aluminum oxide, and gallium arsenide.
[0008] In some embodiments, the thickness of the reflective material layer is less than 1000 nm.
[0009] In some embodiments, after a second via is formed in the wafer, the reflective material layer and the infrared sensing material layer covering the bottom wall of the first via are removed through the second via.
[0010] In some embodiments, the infrared sensing material layer includes at least one of the following: neodymium-doped titanium dioxide stacked material, ytterbium-doped titanium dioxide stacked material, silicon dioxide and nitrogen-doped titanium dioxide stacked material, tungsten-doped vanadium dioxide, gold core titanium dioxide shell structure, lead sulfide quantum dot modified titanium dioxide material, perovskite quantum dot modified titanium dioxide material, lead selenide quantum dot modified titanium dioxide material, ytterbium ion-doped silicon dioxide, ytterbium ion-doped silicon nitride, erbium ion-doped silicon dioxide, and erbium ion-doped silicon nitride.
[0011] In some embodiments, the thickness of the infrared sensing material layer is less than 500 nm.
[0012] In some embodiments, the conductive material layer includes at least one of copper, tungsten, and cobalt.
[0013] In one embodiment, the wavelength of the incident light is greater than 1 μm.
[0014] In another aspect of this disclosure, a semiconductor structure is provided, comprising: a wafer having a first surface and a second surface disposed opposite to each other along the thickness direction of the wafer; a conductive via structure penetrating the wafer along the thickness direction, the conductive via structure including a first conductive via structure and a second conductive via structure arranged and contacting each other along the thickness direction of the wafer; the first conductive via structure extending from the first surface of the wafer toward the second surface; the second conductive via structure extending from the second surface of the wafer toward the first surface; the first conductive via structure including an infrared sensing material layer and a conductive material layer, the conductive material layer extending along the thickness direction of the wafer, the infrared sensing material layer covering the sidewalls of the conductive material layer and surrounding the conductive material layer.
[0015] In some embodiments, the first conductive via structure further includes a reflective material layer that covers the sidewalls of the infrared sensing material layer and surrounds the infrared sensing material layer.
[0016] In some embodiments, the infrared sensing material layer includes at least one of the following: neodymium-doped titanium dioxide stacked material, ytterbium-doped titanium dioxide stacked material, silicon dioxide and nitrogen-doped titanium dioxide stacked material, tungsten-doped vanadium dioxide, gold core titanium dioxide shell structure, lead sulfide quantum dot modified titanium dioxide material, perovskite quantum dot modified titanium dioxide material, lead selenide quantum dot modified titanium dioxide material, ytterbium ion-doped silicon dioxide, ytterbium ion-doped silicon nitride, erbium ion-doped silicon dioxide, and erbium ion-doped silicon nitride.
[0017] In some embodiments, the reflective material layer includes at least one of titanium dioxide, silicon, silicon dioxide, indium tin oxide, gallium zinc oxide, tantalum nitride, tantalum oxide, gallium arsenide, aluminum arsenide, aluminum oxide, and gallium arsenide aluminum.
[0018] In this embodiment, a first via is formed within the wafer, extending from the first surface to the second surface but not penetrating it. An infrared sensing material layer is formed covering the sidewalls and bottom wall of the first via. A conductive material layer covering the infrared sensing material layer is filled within the first via. An incident light source is provided to irradiate the second surface of the wafer. The infrared sensing material generates infrared light under the irradiation of the incident light source. Alignment is achieved from the second surface of the wafer using infrared light, forming a second via communicating with the first via within the wafer. In terms of manufacturing process, when forming the second via within the wafer, alignment is achieved using infrared light generated by the infrared sensing material layer on the sidewalls and bottom wall of the first via. This allows for direct alignment of the second surface without relying on alignment marks formed on the first surface, simplifying the process and reducing alignment difficulty. Structurally, the infrared sensing material layer, located between the wafer and the conductive material layer, acts as a buffer layer throughout the process, mitigating stress caused by thermal mismatch and improving structural reliability. Attached Figure Description
[0019] Figure 1 A flowchart of a semiconductor structure formation method provided in this disclosure embodiment; Figure 2 A schematic diagram of the manufacturing process of a semiconductor structure provided in this disclosure embodiment. Figure 1 ; Figure 3 A schematic diagram of the manufacturing process of a semiconductor structure provided in this disclosure embodiment. Figure 2 ; Figure 4 A schematic diagram of the manufacturing process of a semiconductor structure provided in this disclosure embodiment. Figure 3 ; Figure 5 A schematic diagram of the manufacturing process of a semiconductor structure provided in this disclosure embodiment. Figure 4 ; Figure 6 A schematic diagram of the manufacturing process of a semiconductor structure provided in this disclosure embodiment. Figure 5 ; Figure 7 A schematic diagram of the manufacturing process of a semiconductor structure provided in this disclosure embodiment. Figure 6 ; Figure 8 A schematic diagram of the manufacturing process of a semiconductor structure provided in this disclosure embodiment. Figure 7 ; Figure 9 A schematic diagram of the manufacturing process of a semiconductor structure provided in this disclosure embodiment. Figure 8 ; Figure 10 A schematic diagram of the manufacturing process of a semiconductor structure provided in another embodiment of this disclosure. Figure 9 ; Figure 11 A schematic diagram of the manufacturing process of a semiconductor structure provided in this disclosure embodiment. Figure 10 ; Figure 12 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation
[0020] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0021] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0022] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0024] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0026] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.
[0027] In 2D / 3D integration, via arrays, with their high interconnect density, uniform current distribution, and good compatibility with advanced micro-nano manufacturing processes, have become the core technology supporting the realization of efficient vertical interconnection and ensuring the overall performance and reliability of chips.
[0028] In through-hole (TH) fabrication, the alignment accuracy of the back-side photolithography and etching stages depends on the alignment mark on the front side. This process requires first forming the TH on the front side of the wafer through photolithography and etching, then applying a protective layer to the front side and flipping it over. Next, the back side is thinned, and infrared alignment technology is used to capture the front-side alignment mark. Through mirror photolithography and etching, high-precision interconnection of the TH within the wafer is achieved. However, since the mark is located on the front side of the wafer, the infrared signal is easily affected by the wafer material and the uniformity of thinning during wafer penetration, leading to difficulties in mark recognition and poor positioning stability. This makes the back-side photolithography and etching prone to positioning deviations, hindering the high-precision interconnection of the TH structure, affecting the uniformity of interconnect resistance and current transmission capability, and ultimately limiting the overall performance and long-term reliability of the device.
[0029] In view of this, embodiments of the present disclosure provide a method for forming a semiconductor structure. Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure, such as... Figure 1 As shown, the method for forming this semiconductor structure includes: Step S101: Provide a wafer having a first surface and a second surface opposite each other along the thickness direction of the wafer; Step S102: A first through-hole is formed in the wafer, the first through-hole extending from the first surface of the wafer toward the second surface but not penetrating the second surface of the wafer; Step S103: Form an infrared sensing material layer covering the sidewall and bottom wall of the first through hole; Step S104: Fill the first through hole with a conductive material layer, the conductive material layer covering the infrared sensing material layer; Step S105: Provide incident light to irradiate the second surface of the wafer, and the infrared sensing material layer generates infrared light under the irradiation of the incident light; Step S106: Alignment is performed using infrared light generated by the infrared sensing material layer from the second surface to form a second via in the wafer. The second via extends from the second surface of the wafer toward the first surface, and the first via communicates with the second via.
[0030] In this embodiment, a first via is formed within the wafer, extending from the first surface to the second surface but not penetrating it. An infrared sensing material layer is formed covering the sidewalls and bottom wall of the first via. A conductive material layer covering the infrared sensing material layer is filled within the first via. An incident light source is provided to irradiate the second surface of the wafer. The infrared sensing material generates infrared light under the irradiation of the incident light source. Alignment is achieved from the second surface of the wafer using infrared light, forming a second via communicating with the first via within the wafer. In terms of manufacturing process, when forming the second via within the wafer, alignment is achieved using infrared light generated by the infrared sensing material layer on the sidewalls and bottom wall of the first via. This allows for direct alignment of the second surface without relying on alignment marks formed on the first surface, simplifying the process and reducing alignment difficulty. Structurally, the infrared sensing material layer, located between the wafer and the conductive material layer, acts as a buffer layer throughout the process, mitigating stress caused by thermal mismatch and improving structural reliability.
[0031] Figures 2 to 11 This is a schematic diagram of the formation process of a semiconductor structure provided in an embodiment of this disclosure. The following will be combined with... Figure 1 , Figures 2 to 11 The present disclosure provides an illustrative description of a method for manufacturing a semiconductor structure according to embodiments thereof.
[0032] like Figure 2 As shown, in step S101, a wafer 101 is provided, the wafer 101 having a first surface 102 and a second surface 103 opposite to each other along the thickness direction of the wafer 101.
[0033] Here, wafer 101 refers to wafer 101 in a broad sense, which can include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, at least one silicon-on-insulator / germanium-on-insulator, or other semiconductor materials known in the art. For example, wafer 101 can be silicon (Si), germanium (Ge), silicon germanide (GeSi), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), etc. In this embodiment, wafer 101 is a silicon wafer.
[0034] like Figure 3 As shown, in step S102, a first through hole 110 is formed in the wafer 101. The first through hole 110 extends from the first surface 102 of the wafer 101 toward the second surface 103 but does not penetrate the second surface 103 of the wafer 101.
[0035] For example, a first mask layer (not shown) is formed on the first surface 102 of wafer 101, and then a patterned first photoresist layer (not shown) is formed on the first mask layer. The patterned first photoresist layer is used to etch the first mask layer on the first surface 102 of wafer 101 to form a first opening (not shown) in the first mask layer, exposing the first surface 102 of wafer 101. A dry etching process is used to etch wafer 101 from the first surface 102 along the wafer thickness direction based on the first opening formed in the first mask layer, to form a first via 110 with a certain depth in wafer 101.
[0036] In this embodiment, by controlling the time of the dry etching process, the depth of the first via 110 in the wafer 101 along the thickness direction of the wafer 101 is limited, so that the first via 110 does not penetrate the second surface 103 of the wafer 101.
[0037] like Figure 4 As shown, in step S103, an infrared sensing material layer 111 is formed covering the sidewalls and bottom wall of the first through-hole 110. The infrared sensing material layer 111 is formed on the sidewalls and bottom wall of the first through-hole 110 using a thin film deposition process. The thin film deposition process described in this embodiment and hereinafter includes at least one of: atomic layer deposition (ALD), physical vapor deposition (PVD), solution method, electrochemical deposition (ECD), and electron beam evaporation (EBE).
[0038] The infrared sensing material layer 111 includes, but is not limited to, doped titanium dioxide nanolayer materials, tungsten-doped vanadium dioxide and other phase change layer materials, high-quality core-shell structure materials, quantum dot materials with modification properties, ytterbium ion doped materials, erbium ion doped materials, etc.
[0039] In this embodiment, the infrared sensing material layer 111 includes at least one of the following: neodymium-doped titanium dioxide stacked material, ytterbium-doped titanium dioxide stacked material, silicon dioxide and nitrogen-doped titanium dioxide stacked material, tungsten-doped vanadium dioxide, gold core titanium dioxide shell structure, lead sulfide quantum dot modified titanium dioxide material, perovskite quantum dot modified titanium dioxide material, lead selenide quantum dot modified titanium dioxide material, ytterbium ion-doped silicon dioxide, ytterbium ion-doped silicon nitride, erbium ion-doped silicon dioxide, and erbium ion-doped silicon nitride.
[0040] The infrared sensing material layer in this embodiment not only has infrared luminescence properties, but can also be stress-matched with the conductive material layer and wafer involved in subsequent processes.
[0041] In this embodiment, the thickness of the infrared sensing material layer 111 is less than 500 nm. For example, 5 nm, 10 nm, 50 nm, 100 nm, 300 nm, 450 nm, etc. In practical applications, the thickness can be set according to the size of the first through-hole 110 and the application field.
[0042] like Figure 5 As shown, in step S104, a conductive material layer 112 is filled into the first through-hole 110, and the conductive material layer 112 covers the infrared sensing material layer 111. A conductive material layer 112, filling and covering the infrared sensing material layer 111, is formed within the first through-hole 110 using a thin-film deposition process to form a first conductive through-hole structure. An exemplary deposition process here is electroplating deposition.
[0043] In this embodiment, the material of the conductive material layer 112 includes, but is not limited to, metallic materials, including, but not limited to, at least one of copper, tungsten, and cobalt.
[0044] It is understandable that the filling of the first via 110 and subsequent processes will undergo multiple temperature changes. The difference in thermal expansion coefficients between the wafer and the conductive material layer 112 is significant. During temperature changes, the stress mismatch between the two can cause problems such as the conductive material layer 112 protruding, delamination and cracking at the contact interface between the wafer material and the conductive material layer 112 on the sidewalls and bottom wall of the first via 110, and wafer warping. In this embodiment, the infrared sensing material layer 111 covers the bottom and sidewalls of the first via 110, and the conductive material layer 112 covers the infrared sensing material layer 111. During temperature changes, the infrared sensing material layer 111 can act as a buffer layer, absorbing or decomposing the stress generated by the wafer and the conductive material layer 112, achieving stress adaptation and improving the reliability of the conductive via structure.
[0045] like Figure 6 and Figure 7 As shown, in some embodiments, before step S103, the method further includes: forming a reflective material layer 113 covering the sidewalls and bottom wall of the first through hole 110 before forming an infrared sensing material layer 111 covering the sidewalls and bottom wall of the first through hole 110; the formation of the infrared sensing material layer 111 covering the sidewalls and bottom wall of the first through hole 110 includes: forming the infrared sensing material layer 111 on the sidewalls and bottom wall of the first through hole 110 where the reflective material layer 113 is formed, wherein the infrared sensing material layer 111 covers the reflective material layer 113.
[0046] For example, a reflective material layer 113 is first formed on the sidewall and bottom wall of the first via 110 using a thin-film deposition process. After forming the reflective material layer 113, an infrared sensing material layer 111 covering the reflective material layer 113 is then formed using a thin-film deposition process. In this embodiment, the thin-film deposition processes for forming the reflective material layer 113 and the infrared sensing material layer 111 can be the same or different.
[0047] In this embodiment, the reflective material layer 113 includes, but is not limited to, at least one of titanium dioxide, silicon, silicon dioxide, indium tin oxide, zinc gallium oxide, tantalum nitride, tantalum oxide, gallium arsenide, aluminum arsenide, aluminum oxide, and gallium arsenide.
[0048] In this embodiment, the thickness of the reflective material layer 113 is less than 1000 nm. For example, 50 nm, 300 nm, 700 nm, 950 nm, etc. In practical applications, the thickness can be set according to the size of the first through-hole 110 and the application field.
[0049] After forming a first conductive via structure within wafer 101 via its first surface 102, the first surface 102 of wafer 101 is bonded to a carrier substrate (not shown). Then, wafer 101 is thinned from its second surface. Specifically, a carrier substrate with a carrier surface is provided. The first surface 102 of wafer 101 is bonded to the carrier surface of the carrier substrate using a bonding material. Then, wafer 101 is thinned from its second surface 103 using at least one of chemical mechanical polishing or etching processes. Once the target thickness is reached, a second via 120 is formed within wafer 101 via its second surface 103. In this embodiment, the carrier substrate is a silicon wafer; in other embodiments, the carrier substrate may also be a glass substrate.
[0050] In this embodiment, during the thinning process of wafer 101 from its second surface, the carrier substrate provides support; furthermore, the bonding between the first surface 102 of wafer 101 and the carrier surface of the carrier substrate protects the circuit structure of the first surface 102 of wafer 101 from contamination. The carrier substrate can be removed after the back-side processing of the wafer is completed in subsequent steps.
[0051] like Figure 8 and Figure 9 As shown, in step S105, an incident light source is provided to irradiate the second surface 103 of the wafer 101, and the infrared sensing material layer 111 generates infrared light under the irradiation of the incident light.
[0052] For example, a beam of incident light of a specific wavelength is provided and illuminates the second surface 103 of wafer 101 at a specific angle. The incident light passes through wafer 101 and reflective material layer 113 to reach infrared sensing material layer 111. Infrared sensing material layer 111 absorbs the energy in the incident light and generates infrared light in the opposite direction to the incident light, forming an infrared light source 130 on the second surface 103 of wafer 101. At this time, an infrared camera (IR camera) located above wafer 101 will identify and capture the infrared light source 130 formed on the second surface of wafer 101 to determine the position of the first via 110 in wafer 101.
[0053] In this embodiment, the infrared light generated by the infrared sensing material layer 111 forms an infrared light source 130 on the second surface 103 of the wafer 101, directly marking the position of the first via 110 in the wafer 101 on the second surface 103. When the second via 120 is formed in the wafer 101 through the second surface 103, there is no need to form an alignment mark on the first surface 102 of the wafer 101, reducing the difficulty of alignment.
[0054] In this embodiment, the infrared sensing material layer 111 and the reflective material layer 113 form a distributed Bragg reflector (DBR). On the one hand, when the infrared light generated by the infrared sensing material layer 111 is incident on the surface of the reflective material layer 113 in the form of a light source, the DBR reflective material layer will suppress the diffusion of the infrared light and only allow light perpendicular to the interface to pass through, transforming the divergent light source into a directional vertical beam propagation, thus confining the direction of light propagation. On the other hand, non-perpendicularly propagating light is reflected back to the infrared emitting material layer by the reflective layer, forming a back-and-forth resonance between the infrared emitting material layer and the reflective layer, which enhances the output of light perpendicular to the second surface of the wafer, reduces losses, and improves the utilization rate of the light source. At the same time, the highly collimated propagation direction enhances the convergence of the infrared light source, forming a sharp surface light source with clear boundaries and concentrated intensity on the second surface 103 of the wafer 101, which facilitates the IR camera to capture and identify the infrared light source on the second surface for alignment and positioning of the first via 110. The infrared light generated by the infrared sensing material layer 111 forms a surface light source on the second surface of the wafer. During the manufacturing process, even if the wafer is slightly warped, the location of the first via in the wafer can still be effectively identified.
[0055] In some embodiments, the wavelength of the incident light is greater than 1 μm, such as YAG lasers, CO2 lasers, Yb-based lasers, etc. In practical applications, the appropriate laser can be selected based on the infrared sensing material layer used in the application.
[0056] In this embodiment, the conductive material layer 112 has almost zero absorption for light sources with wavelengths greater than 1µm, and can serve as another DBR reflective layer to confine the propagation direction of the incident light source and the infrared light generated by the infrared sensing material layer. The non-perpendicularly propagating light source is reflected back to the infrared sensing material layer by the conductive material layer, and is reabsorbed by the infrared sensing material layer to participate in the light emission process again, thereby improving the light source collection efficiency.
[0057] like Figure 10 As shown, in step S106, infrared light generated from the second surface 103 through the infrared sensing material layer 111 is used for alignment to form a second through hole 120 in the wafer 101. The second through hole 120 extends from the second surface of the wafer 101 toward the first surface 102, and the first through hole 110 communicates with the second through hole 120.
[0058] For example, a second mask layer (not shown) is formed on the second surface 103 of wafer 101, and then a second photoresist layer (not shown) is formed on the second mask layer. The second photoresist layer on the second surface 103 of wafer 101 is subjected to photolithography to form a patterned second photoresist layer. The second mask layer is etched through the patterned second photoresist layer to form a second opening (not shown) in the second mask layer, exposing a portion of the second surface 103 of wafer 101. A dry etching process is used to etch wafer 101 from the second surface 103 along the thickness direction of wafer 101 based on the second opening formed in the second mask layer, to form a second via 120 with a certain depth within wafer 101. In this embodiment, the dry etching process stops when the formed second via 120 communicates with the first via, exposing the reflective material layer 113 of the bottom wall of the first via.
[0059] In this embodiment, before or during photolithography, the position of the first via 110 within the wafer 101 is determined by an infrared light source 130 formed on the second surface of the wafer 101 based on an IR camer, thereby determining the position of the second opening to be formed, so as to achieve precise docking between the subsequently formed second via 120 and the first via.
[0060] In this embodiment, the first opening and the second opening are basically the same in size and shape.
[0061] In some embodiments, after the second via 120 is formed in the wafer 101, the reflective material layer 113 and the infrared sensing material layer 111 covering the bottom wall of the first via 110 are removed through the second via 120.
[0062] like Figure 11As shown, after removing the reflective material layer 113 and the infrared sensing material layer 111 covering the bottom wall of the first through hole 110 through the second through hole 120, a conductive material layer 121 filling the second through hole 120 is formed by thin film deposition process to form a second conductive through hole structure. In this embodiment, the reflective material layer 113 and the infrared sensing material layer 111 on the bottom wall of the first through hole 110 are removed, and the conductive material layer 112 in the first through hole 110 and the conductive material layer 121 in the second through hole 120 can directly contact each other, which reduces the contact resistance, reduces potential contact interface defects, and thus reduces signal transmission delay.
[0063] In this embodiment, the material of the conductive material layer 121 in the second through hole 120 includes, but is not limited to, a metal material, including, but not limited to, at least one of copper, tungsten, and cobalt.
[0064] In this embodiment, the conductive material layer 112 in the first through hole 110 and the conductive material layer 121 in the second through hole 120 may be made of the same or different materials.
[0065] In some embodiments, the reflective material layer 113 is a non-conductive material. After the second through-hole 120 is formed in the wafer 101, the reflective material layer 113 covering the bottom wall of the first through-hole 110 is removed through the second through-hole 120.
[0066] In some embodiments, when both the reflective material layer 113 and the infrared sensing material layer 111 are conductive materials, the reflective material layer 113 and the infrared sensing material layer 111 can be directly retained in the first through hole 110, and the conductive material layer 121 can be directly filled in the second through hole 120.
[0067] Based on the above-described method for forming a semiconductor structure, this disclosure provides a semiconductor structure that can be manufactured using the methods described in any of the above embodiments.
[0068] like Figure 12 As shown, the semiconductor structure 200 includes: Wafer 101, the wafer 101 having a first surface 102 and a second surface 103 disposed opposite to each other along the thickness direction of the wafer 101; A conductive via structure 210 penetrates the wafer 101 along its thickness direction. The conductive via structure 210 includes a first conductive via structure 211 and a second conductive via structure 212 arranged and contacting each other along the thickness direction of the wafer 101. The first conductive via structure 211 extends from a first surface 102 of the wafer 101 towards a second surface 103; the second conductive via structure 212 extends from a second surface 103 of the wafer 101 towards a first surface 102. The first conductive via structure 211 includes an infrared sensing material layer 111 and a conductive material layer 112. The conductive material layer 112 extends along the thickness direction of the wafer 101, and the infrared sensing material layer 111 covers the sidewall of the conductive material layer 112 and surrounds the conductive material layer 112.
[0069] In the semiconductor structure 200, the infrared sensing material layer 111 is located within the first conductive via structure 211, covering and surrounding the sidewalls of the conductive material layer 112. The infrared sensing material layer 111 can serve as a buffer layer to alleviate the thermal expansion difference between the wafer and the conductive material layer 112, absorb or decompose the stress generated by temperature cycling, achieve stress adaptation, and improve the reliability of the semiconductor structure 200.
[0070] In some embodiments, the second conductive via structure 212 includes a conductive material layer 121 that extends along the thickness direction of the wafer 101.
[0071] In some embodiments, the sum of the dimensions of the first conductive via structure 211 along the thickness direction of the wafer 101 and the dimensions of the second conductive via structure 212 along the thickness direction of the wafer 101 is equal to the dimensions of the wafer 101 along the thickness direction of the wafer 101.
[0072] In some embodiments, the first conductive via structure 211 further includes a reflective material layer 113, which covers the sidewalls of the infrared sensing material layer 111 and surrounds the infrared sensing material layer 111.
[0073] In some embodiments, the infrared sensing material layer 111 and the reflective material layer 113 are conductive materials, and the infrared sensing material layer 111 and the reflective material layer 113 are also located between the conductive material layer 112 and the conductive material layer 121.
[0074] In some embodiments, the conductive material layer 121 is in contact with the conductive material layer 112, the external sensing material layer 111, and the reflective material layer 113.
[0075] In some embodiments, the infrared sensing material layer 111 includes at least one of the following: neodymium-doped titanium dioxide stacked material, ytterbium-doped titanium dioxide stacked material, silicon dioxide and nitrogen-doped titanium dioxide stacked material, tungsten-doped vanadium dioxide, gold core titanium dioxide shell structure, lead sulfide quantum dot modified titanium dioxide material, perovskite quantum dot modified titanium dioxide material, lead selenide quantum dot modified titanium dioxide material, ytterbium ion-doped silicon dioxide, ytterbium ion-doped silicon nitride, erbium ion-doped silicon dioxide, and erbium ion-doped silicon nitride.
[0076] In some embodiments, the thickness of the infrared sensing material layer 111 is less than 500 nm.
[0077] In some embodiments, the reflective material layer 113 includes at least one of titanium dioxide, silicon, silicon dioxide, indium tin oxide, zinc gallium oxide, tantalum nitride, tantalum oxide, gallium arsenide, aluminum arsenide, aluminum oxide, and gallium arsenide.
[0078] In some embodiments, the thickness of the reflective material layer 113 is less than 1000 nm.
[0079] In some embodiments, the conductive material layer 112 (121) includes at least one of copper, tungsten, and cobalt.
[0080] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
[0081] For further details regarding the methods for forming semiconductor structures, please refer to the relevant introduction on the semiconductor structure side above. For the sake of brevity, these details will not be repeated here.
[0082] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0083] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.
[0084] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A wafer is provided having a first surface and a second surface opposite each other along the thickness direction of the wafer; A first through-hole is formed in the wafer, the first through-hole extending from the first surface of the wafer toward the second surface but not penetrating the second surface of the wafer; An infrared sensing material layer is formed covering the sidewall and bottom wall of the first through hole; A conductive material layer is filled into the first through hole, and the conductive material layer covers the infrared sensing material layer. An incident light is provided to illuminate the second surface of the wafer, and the infrared sensing material layer generates infrared light under the illumination of the incident light; The infrared light generated from the second surface through the infrared sensing material layer is aligned to form a second through-hole in the wafer. The second through-hole extends from the second surface of the wafer toward the first surface, and the first through-hole communicates with the second through-hole.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The method further includes: Before forming the infrared sensing material layer covering the sidewall and bottom wall of the first through hole, a reflective material layer covering the sidewall and bottom wall of the first through hole is formed. The formation of the infrared sensing material layer covering the sidewall and bottom wall of the first through hole includes: forming the infrared sensing material layer on the sidewall and bottom wall of the first through hole where the reflective material layer is formed, and the infrared sensing material layer covering the reflective material layer.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The reflective material layer includes at least one of the following: titanium dioxide, silicon, silicon dioxide, indium tin oxide, zinc gallium oxide, tantalum nitride, tantalum oxide, gallium arsenide, aluminum arsenide, aluminum oxide, and aluminum gallium arsenide.
4. The method for forming a semiconductor structure according to claim 2, characterized in that, The thickness of the reflective material layer is less than 1000 nm.
5. The method for forming a semiconductor structure according to claim 2, characterized in that, After forming a second via in the wafer, the reflective material layer and infrared sensing material layer covering the bottom wall of the first via are removed through the second via.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, The infrared sensing material layer includes at least one of the following: neodymium-doped titanium dioxide stacked material, ytterbium-doped titanium dioxide stacked material, silicon dioxide and nitrogen-doped titanium dioxide stacked material, tungsten-doped vanadium dioxide, gold core titanium dioxide shell structure, lead sulfide quantum dot modified titanium dioxide material, perovskite quantum dot modified titanium dioxide material, lead selenide quantum dot modified titanium dioxide material, ytterbium ion-doped silicon dioxide, ytterbium ion-doped silicon nitride, erbium ion-doped silicon dioxide, and erbium ion-doped silicon nitride.
7. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness of the infrared sensing material layer is less than 500 nm.
8. The method for forming a semiconductor structure according to claim 1, characterized in that, The conductive material layer includes at least one of copper, tungsten, and cobalt.
9. The method for forming a semiconductor structure according to claim 1, characterized in that, The wavelength of the incident light is greater than 1 μm.
10. A semiconductor structure, characterized in that, include: A wafer having a first surface and a second surface disposed opposite to each other along the thickness direction of the wafer; A conductive via structure is provided, wherein the conductive via structure penetrates the wafer along the thickness direction of the wafer, and the conductive via structure includes a first conductive via structure and a second conductive via structure arranged and contacting each other along the thickness direction of the wafer; the first conductive via structure extends from a first surface of the wafer toward the second surface. The second conductive via structure extends from the second surface of the wafer toward the first surface; The first conductive via structure includes an infrared sensing material layer and a conductive material layer. The conductive material layer extends along the thickness direction of the wafer, and the infrared sensing material layer covers the sidewalls of the conductive material layer and surrounds the conductive material layer.
11. The semiconductor structure according to claim 10, characterized in that, The first conductive via structure further includes a reflective material layer, which covers the sidewalls of the infrared sensing material layer and surrounds the infrared sensing material layer.
12. The semiconductor structure according to claim 10, characterized in that, The infrared sensing material layer includes at least one of the following: neodymium-doped titanium dioxide stacked material, ytterbium-doped titanium dioxide stacked material, silicon dioxide and nitrogen-doped titanium dioxide stacked material, tungsten-doped vanadium dioxide, gold core titanium dioxide shell structure, lead sulfide quantum dot modified titanium dioxide material, perovskite quantum dot modified titanium dioxide material, lead selenide quantum dot modified titanium dioxide material, ytterbium ion-doped silicon dioxide, ytterbium ion-doped silicon nitride, erbium ion-doped silicon dioxide, and erbium ion-doped silicon nitride.
13. The semiconductor structure according to claim 11, characterized in that, The reflective material layer includes at least one of the following: titanium dioxide, silicon, silicon dioxide, indium tin oxide, zinc gallium oxide, tantalum nitride, tantalum oxide, gallium arsenide, aluminum arsenide, aluminum oxide, and aluminum gallium arsenide.